[PATCH] DRIVER MODEL: Get rid of the obsolete tri-level suspend/resume callbacks
[linux-2.6.git] / drivers / usb / gadget / omap_udc.c
1 /*
2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3  *
4  * Copyright (C) 2004 Texas Instruments, Inc.
5  * Copyright (C) 2004-2005 David Brownell
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20  */
21
22 #undef  DEBUG
23 #undef  VERBOSE
24
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/ioport.h>
29 #include <linux/types.h>
30 #include <linux/errno.h>
31 #include <linux/delay.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/init.h>
35 #include <linux/timer.h>
36 #include <linux/list.h>
37 #include <linux/interrupt.h>
38 #include <linux/proc_fs.h>
39 #include <linux/mm.h>
40 #include <linux/moduleparam.h>
41 #include <linux/device.h>
42 #include <linux/usb_ch9.h>
43 #include <linux/usb_gadget.h>
44 #include <linux/usb_otg.h>
45 #include <linux/dma-mapping.h>
46
47 #include <asm/byteorder.h>
48 #include <asm/io.h>
49 #include <asm/irq.h>
50 #include <asm/system.h>
51 #include <asm/unaligned.h>
52 #include <asm/mach-types.h>
53
54 #include <asm/arch/dma.h>
55 #include <asm/arch/usb.h>
56
57 #include "omap_udc.h"
58
59 #undef  USB_TRACE
60
61 /* bulk DMA seems to be behaving for both IN and OUT */
62 #define USE_DMA
63
64 /* ISO too */
65 #define USE_ISO
66
67 #define DRIVER_DESC     "OMAP UDC driver"
68 #define DRIVER_VERSION  "4 October 2004"
69
70 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
71
72
73 /*
74  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
75  * D+ pullup to allow enumeration.  That's too early for the gadget
76  * framework to use from usb_endpoint_enable(), which happens after
77  * enumeration as part of activating an interface.  (But if we add an
78  * optional new "UDC not yet running" state to the gadget driver model,
79  * even just during driver binding, the endpoint autoconfig logic is the
80  * natural spot to manufacture new endpoints.)
81  *
82  * So instead of using endpoint enable calls to control the hardware setup,
83  * this driver defines a "fifo mode" parameter.  It's used during driver
84  * initialization to choose among a set of pre-defined endpoint configs.
85  * See omap_udc_setup() for available modes, or to add others.  That code
86  * lives in an init section, so use this driver as a module if you need
87  * to change the fifo mode after the kernel boots.
88  *
89  * Gadget drivers normally ignore endpoints they don't care about, and
90  * won't include them in configuration descriptors.  That means only
91  * misbehaving hosts would even notice they exist.
92  */
93 #ifdef  USE_ISO
94 static unsigned fifo_mode = 3;
95 #else
96 static unsigned fifo_mode = 0;
97 #endif
98
99 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
100  * boot parameter "omap_udc:fifo_mode=42"
101  */
102 module_param (fifo_mode, uint, 0);
103 MODULE_PARM_DESC (fifo_mode, "endpoint setup (0 == default)");
104
105 #ifdef  USE_DMA
106 static unsigned use_dma = 1;
107
108 /* "modprobe omap_udc use_dma=y", or else as a kernel
109  * boot parameter "omap_udc:use_dma=y"
110  */
111 module_param (use_dma, bool, 0);
112 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
113 #else   /* !USE_DMA */
114
115 /* save a bit of code */
116 #define use_dma         0
117 #endif  /* !USE_DMA */
118
119
120 static const char driver_name [] = "omap_udc";
121 static const char driver_desc [] = DRIVER_DESC;
122
123 /*-------------------------------------------------------------------------*/
124
125 /* there's a notion of "current endpoint" for modifying endpoint
126  * state, and PIO access to its FIFO.  
127  */
128
129 static void use_ep(struct omap_ep *ep, u16 select)
130 {
131         u16     num = ep->bEndpointAddress & 0x0f;
132
133         if (ep->bEndpointAddress & USB_DIR_IN)
134                 num |= UDC_EP_DIR;
135         UDC_EP_NUM_REG = num | select;
136         /* when select, MUST deselect later !! */
137 }
138
139 static inline void deselect_ep(void)
140 {
141         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
142         /* 6 wait states before TX will happen */
143 }
144
145 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
146
147 /*-------------------------------------------------------------------------*/
148
149 static int omap_ep_enable(struct usb_ep *_ep,
150                 const struct usb_endpoint_descriptor *desc)
151 {
152         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
153         struct omap_udc *udc;
154         unsigned long   flags;
155         u16             maxp;
156
157         /* catch various bogus parameters */
158         if (!_ep || !desc || ep->desc
159                         || desc->bDescriptorType != USB_DT_ENDPOINT
160                         || ep->bEndpointAddress != desc->bEndpointAddress
161                         || ep->maxpacket < le16_to_cpu
162                                                 (desc->wMaxPacketSize)) {
163                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
164                 return -EINVAL;
165         }
166         maxp = le16_to_cpu (desc->wMaxPacketSize);
167         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
168                                 && maxp != ep->maxpacket)
169                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
170                         || !desc->wMaxPacketSize) {
171                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
172                 return -ERANGE;
173         }
174
175 #ifdef  USE_ISO
176         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
177                                 && desc->bInterval != 1)) {
178                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
179                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
180                                 1 << (desc->bInterval - 1));
181                 return -EDOM;
182         }
183 #else
184         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
185                 DBG("%s, ISO nyet\n", _ep->name);
186                 return -EDOM;
187         }
188 #endif
189
190         /* xfer types must match, except that interrupt ~= bulk */
191         if (ep->bmAttributes != desc->bmAttributes
192                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
193                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
194                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
195                 return -EINVAL;
196         }
197
198         udc = ep->udc;
199         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
200                 DBG("%s, bogus device state\n", __FUNCTION__);
201                 return -ESHUTDOWN;
202         }
203
204         spin_lock_irqsave(&udc->lock, flags);
205
206         ep->desc = desc;
207         ep->irqs = 0;
208         ep->stopped = 0;
209         ep->ep.maxpacket = maxp;
210
211         /* set endpoint to initial state */
212         ep->dma_channel = 0;
213         ep->has_dma = 0;
214         ep->lch = -1;
215         use_ep(ep, UDC_EP_SEL);
216         UDC_CTRL_REG = udc->clr_halt;
217         ep->ackwait = 0;
218         deselect_ep();
219
220         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
221                 list_add(&ep->iso, &udc->iso);
222
223         /* maybe assign a DMA channel to this endpoint */
224         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
225                 /* FIXME ISO can dma, but prefers first channel */
226                 dma_channel_claim(ep, 0);
227
228         /* PIO OUT may RX packets */
229         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
230                         && !ep->has_dma
231                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
232                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
233                 ep->ackwait = 1 + ep->double_buf;
234         }
235
236         spin_unlock_irqrestore(&udc->lock, flags);
237         VDBG("%s enabled\n", _ep->name);
238         return 0;
239 }
240
241 static void nuke(struct omap_ep *, int status);
242
243 static int omap_ep_disable(struct usb_ep *_ep)
244 {
245         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
246         unsigned long   flags;
247
248         if (!_ep || !ep->desc) {
249                 DBG("%s, %s not enabled\n", __FUNCTION__,
250                         _ep ? ep->ep.name : NULL);
251                 return -EINVAL;
252         }
253
254         spin_lock_irqsave(&ep->udc->lock, flags);
255         ep->desc = NULL;
256         nuke (ep, -ESHUTDOWN);
257         ep->ep.maxpacket = ep->maxpacket;
258         ep->has_dma = 0;
259         UDC_CTRL_REG = UDC_SET_HALT;
260         list_del_init(&ep->iso);
261         del_timer(&ep->timer);
262
263         spin_unlock_irqrestore(&ep->udc->lock, flags);
264
265         VDBG("%s disabled\n", _ep->name);
266         return 0;
267 }
268
269 /*-------------------------------------------------------------------------*/
270
271 static struct usb_request *
272 omap_alloc_request(struct usb_ep *ep, unsigned gfp_flags)
273 {
274         struct omap_req *req;
275
276         req = kmalloc(sizeof *req, gfp_flags);
277         if (req) {
278                 memset (req, 0, sizeof *req);
279                 req->req.dma = DMA_ADDR_INVALID;
280                 INIT_LIST_HEAD (&req->queue);
281         }
282         return &req->req;
283 }
284
285 static void
286 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
287 {
288         struct omap_req *req = container_of(_req, struct omap_req, req);
289
290         if (_req)
291                 kfree (req);
292 }
293
294 /*-------------------------------------------------------------------------*/
295
296 static void *
297 omap_alloc_buffer(
298         struct usb_ep   *_ep,
299         unsigned        bytes,
300         dma_addr_t      *dma,
301         unsigned        gfp_flags
302 )
303 {
304         void            *retval;
305         struct omap_ep  *ep;
306
307         ep = container_of(_ep, struct omap_ep, ep);
308         if (use_dma && ep->has_dma) {
309                 static int      warned;
310                 if (!warned && bytes < PAGE_SIZE) {
311                         dev_warn(ep->udc->gadget.dev.parent,
312                                 "using dma_alloc_coherent for "
313                                 "small allocations wastes memory\n");
314                         warned++;
315                 }
316                 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
317                                 bytes, dma, gfp_flags);
318         }
319
320         retval = kmalloc(bytes, gfp_flags);
321         if (retval)
322                 *dma = virt_to_phys(retval);
323         return retval;
324 }
325
326 static void omap_free_buffer(
327         struct usb_ep   *_ep,
328         void            *buf,
329         dma_addr_t      dma,
330         unsigned        bytes
331 )
332 {
333         struct omap_ep  *ep;
334
335         ep = container_of(_ep, struct omap_ep, ep);
336         if (use_dma && _ep && ep->has_dma)
337                 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
338         else
339                 kfree (buf);
340 }
341
342 /*-------------------------------------------------------------------------*/
343
344 static void
345 done(struct omap_ep *ep, struct omap_req *req, int status)
346 {
347         unsigned                stopped = ep->stopped;
348
349         list_del_init(&req->queue);
350
351         if (req->req.status == -EINPROGRESS)
352                 req->req.status = status;
353         else
354                 status = req->req.status;
355
356         if (use_dma && ep->has_dma) {
357                 if (req->mapped) {
358                         dma_unmap_single(ep->udc->gadget.dev.parent,
359                                 req->req.dma, req->req.length,
360                                 (ep->bEndpointAddress & USB_DIR_IN)
361                                         ? DMA_TO_DEVICE
362                                         : DMA_FROM_DEVICE);
363                         req->req.dma = DMA_ADDR_INVALID;
364                         req->mapped = 0;
365                 } else
366                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
367                                 req->req.dma, req->req.length,
368                                 (ep->bEndpointAddress & USB_DIR_IN)
369                                         ? DMA_TO_DEVICE
370                                         : DMA_FROM_DEVICE);
371         }
372
373 #ifndef USB_TRACE
374         if (status && status != -ESHUTDOWN)
375 #endif
376                 VDBG("complete %s req %p stat %d len %u/%u\n",
377                         ep->ep.name, &req->req, status,
378                         req->req.actual, req->req.length);
379
380         /* don't modify queue heads during completion callback */
381         ep->stopped = 1;
382         spin_unlock(&ep->udc->lock);
383         req->req.complete(&ep->ep, &req->req);
384         spin_lock(&ep->udc->lock);
385         ep->stopped = stopped;
386 }
387
388 /*-------------------------------------------------------------------------*/
389
390 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
391 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
392
393 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
394 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
395
396 static inline int 
397 write_packet(u8 *buf, struct omap_req *req, unsigned max)
398 {
399         unsigned        len;
400         u16             *wp;
401
402         len = min(req->req.length - req->req.actual, max);
403         req->req.actual += len;
404
405         max = len;
406         if (likely((((int)buf) & 1) == 0)) {
407                 wp = (u16 *)buf;
408                 while (max >= 2) {
409                         UDC_DATA_REG = *wp++;
410                         max -= 2;
411                 }
412                 buf = (u8 *)wp;
413         }
414         while (max--)
415                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
416         return len;
417 }
418
419 // FIXME change r/w fifo calling convention
420
421
422 // return:  0 = still running, 1 = completed, negative = errno
423 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
424 {
425         u8              *buf;
426         unsigned        count;
427         int             is_last;
428         u16             ep_stat;
429
430         buf = req->req.buf + req->req.actual;
431         prefetch(buf);
432
433         /* PIO-IN isn't double buffered except for iso */
434         ep_stat = UDC_STAT_FLG_REG;
435         if (ep_stat & UDC_FIFO_UNWRITABLE)
436                 return 0;
437
438         count = ep->ep.maxpacket;
439         count = write_packet(buf, req, count);
440         UDC_CTRL_REG = UDC_SET_FIFO_EN;
441         ep->ackwait = 1;
442
443         /* last packet is often short (sometimes a zlp) */
444         if (count != ep->ep.maxpacket)
445                 is_last = 1;
446         else if (req->req.length == req->req.actual
447                         && !req->req.zero)
448                 is_last = 1;
449         else
450                 is_last = 0;
451
452         /* NOTE:  requests complete when all IN data is in a
453          * FIFO (or sometimes later, if a zlp was needed).
454          * Use usb_ep_fifo_status() where needed.
455          */
456         if (is_last)
457                 done(ep, req, 0);
458         return is_last;
459 }
460
461 static inline int 
462 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
463 {
464         unsigned        len;
465         u16             *wp;
466
467         len = min(req->req.length - req->req.actual, avail);
468         req->req.actual += len;
469         avail = len;
470
471         if (likely((((int)buf) & 1) == 0)) {
472                 wp = (u16 *)buf;
473                 while (avail >= 2) {
474                         *wp++ = UDC_DATA_REG;
475                         avail -= 2;
476                 }
477                 buf = (u8 *)wp;
478         }
479         while (avail--)
480                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
481         return len;
482 }
483
484 // return:  0 = still running, 1 = queue empty, negative = errno
485 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
486 {
487         u8              *buf;
488         unsigned        count, avail;
489         int             is_last;
490
491         buf = req->req.buf + req->req.actual;
492         prefetchw(buf);
493
494         for (;;) {
495                 u16     ep_stat = UDC_STAT_FLG_REG;
496
497                 is_last = 0;
498                 if (ep_stat & FIFO_EMPTY) {
499                         if (!ep->double_buf)
500                                 break;
501                         ep->fnf = 1;
502                 }
503                 if (ep_stat & UDC_EP_HALTED)
504                         break;
505
506                 if (ep_stat & UDC_FIFO_FULL)
507                         avail = ep->ep.maxpacket;
508                 else  {
509                         avail = UDC_RXFSTAT_REG;
510                         ep->fnf = ep->double_buf;
511                 }
512                 count = read_packet(buf, req, avail);
513
514                 /* partial packet reads may not be errors */
515                 if (count < ep->ep.maxpacket) {
516                         is_last = 1;
517                         /* overflowed this request?  flush extra data */
518                         if (count != avail) {
519                                 req->req.status = -EOVERFLOW;
520                                 avail -= count;
521                                 while (avail--)
522                                         (void) *(volatile u8 *)&UDC_DATA_REG;
523                         }
524                 } else if (req->req.length == req->req.actual)
525                         is_last = 1;
526                 else
527                         is_last = 0;
528
529                 if (!ep->bEndpointAddress)
530                         break;
531                 if (is_last)
532                         done(ep, req, 0);
533                 break;
534         }
535         return is_last;
536 }
537
538 /*-------------------------------------------------------------------------*/
539
540 static inline dma_addr_t dma_csac(unsigned lch)
541 {
542         dma_addr_t      csac;
543
544         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
545          * read before the DMA controller finished disabling the channel.
546          */
547         csac = omap_readw(OMAP_DMA_CSAC(lch));
548         if (csac == 0)
549                 csac = omap_readw(OMAP_DMA_CSAC(lch));
550         return csac;
551 }
552
553 static inline dma_addr_t dma_cdac(unsigned lch)
554 {
555         dma_addr_t      cdac;
556
557         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
558          * read before the DMA controller finished disabling the channel.
559          */
560         cdac = omap_readw(OMAP_DMA_CDAC(lch));
561         if (cdac == 0)
562                 cdac = omap_readw(OMAP_DMA_CDAC(lch));
563         return cdac;
564 }
565
566 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
567 {
568         dma_addr_t      end;
569
570         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
571          * the last transfer's bytecount by more than a FIFO's worth.
572          */
573         if (cpu_is_omap15xx())
574                 return 0;
575
576         end = dma_csac(ep->lch);
577         if (end == ep->dma_counter)
578                 return 0;
579
580         end |= start & (0xffff << 16);
581         if (end < start)
582                 end += 0x10000;
583         return end - start;
584 }
585
586 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
587                 ? omap_readw(OMAP_DMA_CSAC(x)) /* really: CPC */ \
588                 : dma_cdac(x))
589
590 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
591 {
592         dma_addr_t      end;
593
594         end = DMA_DEST_LAST(ep->lch);
595         if (end == ep->dma_counter)
596                 return 0;
597
598         end |= start & (0xffff << 16);
599         if (cpu_is_omap15xx())
600                 end++;
601         if (end < start)
602                 end += 0x10000;
603         return end - start;
604 }
605
606
607 /* Each USB transfer request using DMA maps to one or more DMA transfers.
608  * When DMA completion isn't request completion, the UDC continues with
609  * the next DMA transfer for that USB transfer.
610  */
611
612 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
613 {
614         u16             txdma_ctrl;
615         unsigned        length = req->req.length - req->req.actual;
616         const int       sync_mode = cpu_is_omap15xx()
617                                 ? OMAP_DMA_SYNC_FRAME
618                                 : OMAP_DMA_SYNC_ELEMENT;
619
620         /* measure length in either bytes or packets */
621         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
622                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
623                 txdma_ctrl = UDC_TXN_EOT | length;
624                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
625                                 length, 1, sync_mode);
626         } else {
627                 length = min(length / ep->maxpacket,
628                                 (unsigned) UDC_TXN_TSC + 1);
629                 txdma_ctrl = length;
630                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
631                                 ep->ep.maxpacket >> 1, length, sync_mode);
632                 length *= ep->maxpacket;
633         }
634         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
635                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
636
637         omap_start_dma(ep->lch);
638         ep->dma_counter = dma_csac(ep->lch);
639         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
640         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
641         req->dma_bytes = length;
642 }
643
644 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
645 {
646         if (status == 0) {
647                 req->req.actual += req->dma_bytes;
648
649                 /* return if this request needs to send data or zlp */
650                 if (req->req.actual < req->req.length)
651                         return;
652                 if (req->req.zero
653                                 && req->dma_bytes != 0
654                                 && (req->req.actual % ep->maxpacket) == 0)
655                         return;
656         } else
657                 req->req.actual += dma_src_len(ep, req->req.dma
658                                                         + req->req.actual);
659
660         /* tx completion */
661         omap_stop_dma(ep->lch);
662         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
663         done(ep, req, status);
664 }
665
666 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
667 {
668         unsigned packets;
669
670         /* NOTE:  we filtered out "short reads" before, so we know
671          * the buffer has only whole numbers of packets.
672          */
673
674         /* set up this DMA transfer, enable the fifo, start */
675         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
676         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
677         req->dma_bytes = packets * ep->ep.maxpacket;
678         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
679                         ep->ep.maxpacket >> 1, packets,
680                         OMAP_DMA_SYNC_ELEMENT);
681         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
682                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual);
683         ep->dma_counter = DMA_DEST_LAST(ep->lch);
684
685         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
686         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
687         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
688         UDC_CTRL_REG = UDC_SET_FIFO_EN;
689
690         omap_start_dma(ep->lch);
691 }
692
693 static void
694 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status)
695 {
696         u16     count;
697
698         if (status == 0)
699                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
700         count = dma_dest_len(ep, req->req.dma + req->req.actual);
701         count += req->req.actual;
702         if (count <= req->req.length)
703                 req->req.actual = count;
704
705         if (count != req->dma_bytes || status)
706                 omap_stop_dma(ep->lch);
707
708         /* if this wasn't short, request may need another transfer */
709         else if (req->req.actual < req->req.length)
710                 return;
711
712         /* rx completion */
713         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
714         done(ep, req, status);
715 }
716
717 static void dma_irq(struct omap_udc *udc, u16 irq_src)
718 {
719         u16             dman_stat = UDC_DMAN_STAT_REG;
720         struct omap_ep  *ep;
721         struct omap_req *req;
722
723         /* IN dma: tx to host */
724         if (irq_src & UDC_TXN_DONE) {
725                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
726                 ep->irqs++;
727                 /* can see TXN_DONE after dma abort */
728                 if (!list_empty(&ep->queue)) {
729                         req = container_of(ep->queue.next,
730                                                 struct omap_req, queue);
731                         finish_in_dma(ep, req, 0);
732                 }
733                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
734
735                 if (!list_empty (&ep->queue)) {
736                         req = container_of(ep->queue.next,
737                                         struct omap_req, queue);
738                         next_in_dma(ep, req);
739                 }
740         }
741
742         /* OUT dma: rx from host */
743         if (irq_src & UDC_RXN_EOT) {
744                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
745                 ep->irqs++;
746                 /* can see RXN_EOT after dma abort */
747                 if (!list_empty(&ep->queue)) {
748                         req = container_of(ep->queue.next,
749                                         struct omap_req, queue);
750                         finish_out_dma(ep, req, 0);
751                 }
752                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
753
754                 if (!list_empty (&ep->queue)) {
755                         req = container_of(ep->queue.next,
756                                         struct omap_req, queue);
757                         next_out_dma(ep, req);
758                 }
759         }
760
761         if (irq_src & UDC_RXN_CNT) {
762                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
763                 ep->irqs++;
764                 /* omap15xx does this unasked... */
765                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
766                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
767         }
768 }
769
770 static void dma_error(int lch, u16 ch_status, void *data)
771 {
772         struct omap_ep  *ep = data;
773
774         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
775         /* if ch_status & OMAP_DMA_TOUT_IRQ ... */
776         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
777
778         /* complete current transfer ... */
779 }
780
781 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
782 {
783         u16     reg;
784         int     status, restart, is_in;
785
786         is_in = ep->bEndpointAddress & USB_DIR_IN;
787         if (is_in)
788                 reg = UDC_TXDMA_CFG_REG;
789         else
790                 reg = UDC_RXDMA_CFG_REG;
791         reg |= UDC_DMA_REQ;             /* "pulse" activated */
792
793         ep->dma_channel = 0;
794         ep->lch = -1;
795         if (channel == 0 || channel > 3) {
796                 if ((reg & 0x0f00) == 0)
797                         channel = 3;
798                 else if ((reg & 0x00f0) == 0)
799                         channel = 2;
800                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
801                         channel = 1;
802                 else {
803                         status = -EMLINK;
804                         goto just_restart;
805                 }
806         }
807         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
808         ep->dma_channel = channel;
809
810         if (is_in) {
811                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
812                         ep->ep.name, dma_error, ep, &ep->lch);
813                 if (status == 0) {
814                         UDC_TXDMA_CFG_REG = reg;
815                         /* EMIFF */
816                         omap_set_dma_src_burst_mode(ep->lch,
817                                                 OMAP_DMA_DATA_BURST_4);
818                         omap_set_dma_src_data_pack(ep->lch, 1);
819                         /* TIPB */
820                         omap_set_dma_dest_params(ep->lch,
821                                 OMAP_DMA_PORT_TIPB,
822                                 OMAP_DMA_AMODE_CONSTANT,
823                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
824                 }
825         } else {
826                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
827                         ep->ep.name, dma_error, ep, &ep->lch);
828                 if (status == 0) {
829                         UDC_RXDMA_CFG_REG = reg;
830                         /* TIPB */
831                         omap_set_dma_src_params(ep->lch,
832                                 OMAP_DMA_PORT_TIPB,
833                                 OMAP_DMA_AMODE_CONSTANT,
834                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG));
835                         /* EMIFF */
836                         omap_set_dma_dest_burst_mode(ep->lch,
837                                                 OMAP_DMA_DATA_BURST_4);
838                         omap_set_dma_dest_data_pack(ep->lch, 1);
839                 }
840         }
841         if (status)
842                 ep->dma_channel = 0;
843         else {
844                 ep->has_dma = 1;
845                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
846
847                 /* channel type P: hw synch (fifo) */
848                 if (!cpu_is_omap15xx())
849                         omap_writew(2, OMAP_DMA_LCH_CTRL(ep->lch));
850         }
851
852 just_restart:
853         /* restart any queue, even if the claim failed  */
854         restart = !ep->stopped && !list_empty(&ep->queue);
855
856         if (status)
857                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
858                         restart ? " (restart)" : "");
859         else
860                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
861                         is_in ? 't' : 'r',
862                         ep->dma_channel - 1, ep->lch,
863                         restart ? " (restart)" : "");
864
865         if (restart) {
866                 struct omap_req *req;
867                 req = container_of(ep->queue.next, struct omap_req, queue);
868                 if (ep->has_dma)
869                         (is_in ? next_in_dma : next_out_dma)(ep, req);
870                 else {
871                         use_ep(ep, UDC_EP_SEL);
872                         (is_in ? write_fifo : read_fifo)(ep, req);
873                         deselect_ep();
874                         if (!is_in) {
875                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
876                                 ep->ackwait = 1 + ep->double_buf;
877                         }
878                         /* IN: 6 wait states before it'll tx */
879                 }
880         }
881 }
882
883 static void dma_channel_release(struct omap_ep *ep)
884 {
885         int             shift = 4 * (ep->dma_channel - 1);
886         u16             mask = 0x0f << shift;
887         struct omap_req *req;
888         int             active;
889
890         /* abort any active usb transfer request */
891         if (!list_empty(&ep->queue))
892                 req = container_of(ep->queue.next, struct omap_req, queue);
893         else
894                 req = NULL;
895
896         active = ((1 << 7) & omap_readl(OMAP_DMA_CCR(ep->lch))) != 0;
897
898         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
899                         active ? "active" : "idle",
900                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
901                         ep->dma_channel - 1, req);
902
903         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
904          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
905          */
906
907         /* wait till current packet DMA finishes, and fifo empties */
908         if (ep->bEndpointAddress & USB_DIR_IN) {
909                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
910
911                 if (req) {
912                         finish_in_dma(ep, req, -ECONNRESET);
913
914                         /* clear FIFO; hosts probably won't empty it */
915                         use_ep(ep, UDC_EP_SEL);
916                         UDC_CTRL_REG = UDC_CLR_EP;
917                         deselect_ep();
918                 }
919                 while (UDC_TXDMA_CFG_REG & mask)
920                         udelay(10);
921         } else {
922                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
923
924                 /* dma empties the fifo */
925                 while (UDC_RXDMA_CFG_REG & mask)
926                         udelay(10);
927                 if (req)
928                         finish_out_dma(ep, req, -ECONNRESET);
929         }
930         omap_free_dma(ep->lch);
931         ep->dma_channel = 0;
932         ep->lch = -1;
933         /* has_dma still set, till endpoint is fully quiesced */
934 }
935
936
937 /*-------------------------------------------------------------------------*/
938
939 static int
940 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, unsigned gfp_flags)
941 {
942         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
943         struct omap_req *req = container_of(_req, struct omap_req, req);
944         struct omap_udc *udc;
945         unsigned long   flags;
946         int             is_iso = 0;
947
948         /* catch various bogus parameters */
949         if (!_req || !req->req.complete || !req->req.buf
950                         || !list_empty(&req->queue)) {
951                 DBG("%s, bad params\n", __FUNCTION__);
952                 return -EINVAL;
953         }
954         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
955                 DBG("%s, bad ep\n", __FUNCTION__);
956                 return -EINVAL;
957         }
958         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
959                 if (req->req.length > ep->ep.maxpacket)
960                         return -EMSGSIZE;
961                 is_iso = 1;
962         }
963
964         /* this isn't bogus, but OMAP DMA isn't the only hardware to
965          * have a hard time with partial packet reads...  reject it.
966          */
967         if (use_dma
968                         && ep->has_dma
969                         && ep->bEndpointAddress != 0
970                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
971                         && (req->req.length % ep->ep.maxpacket) != 0) {
972                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
973                 return -EMSGSIZE;
974         }
975
976         udc = ep->udc;
977         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
978                 return -ESHUTDOWN;
979
980         if (use_dma && ep->has_dma) {
981                 if (req->req.dma == DMA_ADDR_INVALID) {
982                         req->req.dma = dma_map_single(
983                                 ep->udc->gadget.dev.parent,
984                                 req->req.buf,
985                                 req->req.length,
986                                 (ep->bEndpointAddress & USB_DIR_IN)
987                                         ? DMA_TO_DEVICE
988                                         : DMA_FROM_DEVICE);
989                         req->mapped = 1;
990                 } else {
991                         dma_sync_single_for_device(
992                                 ep->udc->gadget.dev.parent,
993                                 req->req.dma, req->req.length,
994                                 (ep->bEndpointAddress & USB_DIR_IN)
995                                         ? DMA_TO_DEVICE
996                                         : DMA_FROM_DEVICE);
997                         req->mapped = 0;
998                 }
999         }
1000
1001         VDBG("%s queue req %p, len %d buf %p\n",
1002                 ep->ep.name, _req, _req->length, _req->buf);
1003
1004         spin_lock_irqsave(&udc->lock, flags);
1005
1006         req->req.status = -EINPROGRESS;
1007         req->req.actual = 0;
1008
1009         /* maybe kickstart non-iso i/o queues */
1010         if (is_iso)
1011                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1012         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1013                 int     is_in;
1014
1015                 if (ep->bEndpointAddress == 0) {
1016                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1017                                 spin_unlock_irqrestore(&udc->lock, flags);
1018                                 return -EL2HLT;
1019                         }
1020
1021                         /* empty DATA stage? */
1022                         is_in = udc->ep0_in;
1023                         if (!req->req.length) {
1024
1025                                 /* chip became CONFIGURED or ADDRESSED
1026                                  * earlier; drivers may already have queued
1027                                  * requests to non-control endpoints
1028                                  */
1029                                 if (udc->ep0_set_config) {
1030                                         u16     irq_en = UDC_IRQ_EN_REG;
1031
1032                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1033                                         if (!udc->ep0_reset_config)
1034                                                 irq_en |= UDC_EPN_RX_IE
1035                                                         | UDC_EPN_TX_IE;
1036                                         UDC_IRQ_EN_REG = irq_en;
1037                                 }
1038
1039                                 /* STATUS for zero length DATA stages is
1040                                  * always an IN ... even for IN transfers,
1041                                  * a wierd case which seem to stall OMAP.
1042                                  */
1043                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1044                                 UDC_CTRL_REG = UDC_CLR_EP;
1045                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1046                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1047
1048                                 /* cleanup */
1049                                 udc->ep0_pending = 0;
1050                                 done(ep, req, 0);
1051                                 req = NULL;
1052
1053                         /* non-empty DATA stage */
1054                         } else if (is_in) {
1055                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1056                         } else {
1057                                 if (udc->ep0_setup)
1058                                         goto irq_wait;
1059                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1060                         }
1061                 } else {
1062                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1063                         if (!ep->has_dma)
1064                                 use_ep(ep, UDC_EP_SEL);
1065                         /* if ISO: SOF IRQs must be enabled/disabled! */
1066                 }
1067
1068                 if (ep->has_dma)
1069                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1070                 else if (req) {
1071                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1072                                 req = NULL;
1073                         deselect_ep();
1074                         if (!is_in) {
1075                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1076                                 ep->ackwait = 1 + ep->double_buf;
1077                         }
1078                         /* IN: 6 wait states before it'll tx */
1079                 }
1080         }
1081
1082 irq_wait:
1083         /* irq handler advances the queue */
1084         if (req != NULL)
1085                 list_add_tail(&req->queue, &ep->queue);
1086         spin_unlock_irqrestore(&udc->lock, flags);
1087
1088         return 0;
1089 }
1090
1091 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1092 {
1093         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1094         struct omap_req *req;
1095         unsigned long   flags;
1096
1097         if (!_ep || !_req)
1098                 return -EINVAL;
1099
1100         spin_lock_irqsave(&ep->udc->lock, flags);
1101
1102         /* make sure it's actually queued on this endpoint */
1103         list_for_each_entry (req, &ep->queue, queue) {
1104                 if (&req->req == _req)
1105                         break;
1106         }
1107         if (&req->req != _req) {
1108                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1109                 return -EINVAL;
1110         }
1111
1112         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1113                 int channel = ep->dma_channel;
1114
1115                 /* releasing the channel cancels the request,
1116                  * reclaiming the channel restarts the queue
1117                  */
1118                 dma_channel_release(ep);
1119                 dma_channel_claim(ep, channel);
1120         } else 
1121                 done(ep, req, -ECONNRESET);
1122         spin_unlock_irqrestore(&ep->udc->lock, flags);
1123         return 0;
1124 }
1125
1126 /*-------------------------------------------------------------------------*/
1127
1128 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1129 {
1130         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1131         unsigned long   flags;
1132         int             status = -EOPNOTSUPP;
1133
1134         spin_lock_irqsave(&ep->udc->lock, flags);
1135
1136         /* just use protocol stalls for ep0; real halts are annoying */
1137         if (ep->bEndpointAddress == 0) {
1138                 if (!ep->udc->ep0_pending)
1139                         status = -EINVAL;
1140                 else if (value) {
1141                         if (ep->udc->ep0_set_config) {
1142                                 WARN("error changing config?\n");
1143                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1144                         }
1145                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1146                         ep->udc->ep0_pending = 0;
1147                         status = 0;
1148                 } else /* NOP */
1149                         status = 0;
1150
1151         /* otherwise, all active non-ISO endpoints can halt */
1152         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1153
1154                 /* IN endpoints must already be idle */
1155                 if ((ep->bEndpointAddress & USB_DIR_IN)
1156                                 && !list_empty(&ep->queue)) { 
1157                         status = -EAGAIN;
1158                         goto done;
1159                 }
1160
1161                 if (value) {
1162                         int     channel;
1163
1164                         if (use_dma && ep->dma_channel
1165                                         && !list_empty(&ep->queue)) {
1166                                 channel = ep->dma_channel;
1167                                 dma_channel_release(ep);
1168                         } else
1169                                 channel = 0;
1170
1171                         use_ep(ep, UDC_EP_SEL);
1172                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1173                                 UDC_CTRL_REG = UDC_SET_HALT;
1174                                 status = 0;
1175                         } else
1176                                 status = -EAGAIN;
1177                         deselect_ep();
1178
1179                         if (channel)
1180                                 dma_channel_claim(ep, channel);
1181                 } else {
1182                         use_ep(ep, 0);
1183                         UDC_CTRL_REG = ep->udc->clr_halt;
1184                         ep->ackwait = 0;
1185                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1186                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1187                                 ep->ackwait = 1 + ep->double_buf;
1188                         }
1189                 }
1190         }
1191 done:
1192         VDBG("%s %s halt stat %d\n", ep->ep.name,
1193                 value ? "set" : "clear", status);
1194
1195         spin_unlock_irqrestore(&ep->udc->lock, flags);
1196         return status;
1197 }
1198
1199 static struct usb_ep_ops omap_ep_ops = {
1200         .enable         = omap_ep_enable,
1201         .disable        = omap_ep_disable,
1202
1203         .alloc_request  = omap_alloc_request,
1204         .free_request   = omap_free_request,
1205
1206         .alloc_buffer   = omap_alloc_buffer,
1207         .free_buffer    = omap_free_buffer,
1208
1209         .queue          = omap_ep_queue,
1210         .dequeue        = omap_ep_dequeue,
1211
1212         .set_halt       = omap_ep_set_halt,
1213         // fifo_status ... report bytes in fifo
1214         // fifo_flush ... flush fifo
1215 };
1216
1217 /*-------------------------------------------------------------------------*/
1218
1219 static int omap_get_frame(struct usb_gadget *gadget)
1220 {
1221         u16     sof = UDC_SOF_REG;
1222         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1223 }
1224
1225 static int omap_wakeup(struct usb_gadget *gadget)
1226 {
1227         struct omap_udc *udc;
1228         unsigned long   flags;
1229         int             retval = -EHOSTUNREACH;
1230
1231         udc = container_of(gadget, struct omap_udc, gadget);
1232
1233         spin_lock_irqsave(&udc->lock, flags);
1234         if (udc->devstat & UDC_SUS) {
1235                 /* NOTE:  OTG spec erratum says that OTG devices may
1236                  * issue wakeups without host enable.
1237                  */
1238                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1239                         DBG("remote wakeup...\n");
1240                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1241                         retval = 0;
1242                 }
1243
1244         /* NOTE:  non-OTG systems may use SRP TOO... */
1245         } else if (!(udc->devstat & UDC_ATT)) {
1246                 if (udc->transceiver)
1247                         retval = otg_start_srp(udc->transceiver);
1248         }
1249         spin_unlock_irqrestore(&udc->lock, flags);
1250
1251         return retval;
1252 }
1253
1254 static int
1255 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1256 {
1257         struct omap_udc *udc;
1258         unsigned long   flags;
1259         u16             syscon1;
1260
1261         udc = container_of(gadget, struct omap_udc, gadget);
1262         spin_lock_irqsave(&udc->lock, flags);
1263         syscon1 = UDC_SYSCON1_REG;
1264         if (is_selfpowered)
1265                 syscon1 |= UDC_SELF_PWR;
1266         else
1267                 syscon1 &= ~UDC_SELF_PWR;
1268         UDC_SYSCON1_REG = syscon1;
1269         spin_unlock_irqrestore(&udc->lock, flags);
1270
1271         return 0;
1272 }
1273
1274 static int can_pullup(struct omap_udc *udc)
1275 {
1276         return udc->driver && udc->softconnect && udc->vbus_active;
1277 }
1278
1279 static void pullup_enable(struct omap_udc *udc)
1280 {
1281         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1282         udc->gadget.dev.power.power_state = PMSG_ON;
1283         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1284 #ifndef CONFIG_USB_OTG
1285         if (!cpu_is_omap15xx())
1286                 OTG_CTRL_REG |= OTG_BSESSVLD;
1287 #endif
1288         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1289 }
1290
1291 static void pullup_disable(struct omap_udc *udc)
1292 {
1293 #ifndef CONFIG_USB_OTG
1294         if (!cpu_is_omap15xx())
1295                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1296 #endif
1297         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1298         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1299 }
1300
1301 /*
1302  * Called by whatever detects VBUS sessions:  external transceiver
1303  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1304  */
1305 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1306 {
1307         struct omap_udc *udc;
1308         unsigned long   flags;
1309
1310         udc = container_of(gadget, struct omap_udc, gadget);
1311         spin_lock_irqsave(&udc->lock, flags);
1312         VDBG("VBUS %s\n", is_active ? "on" : "off");
1313         udc->vbus_active = (is_active != 0);
1314         if (cpu_is_omap15xx()) {
1315                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1316                 if (is_active)
1317                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1318                 else
1319                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1320         }
1321         if (can_pullup(udc))
1322                 pullup_enable(udc);
1323         else
1324                 pullup_disable(udc);
1325         spin_unlock_irqrestore(&udc->lock, flags);
1326         return 0;
1327 }
1328
1329 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1330 {
1331         struct omap_udc *udc;
1332
1333         udc = container_of(gadget, struct omap_udc, gadget);
1334         if (udc->transceiver)
1335                 return otg_set_power(udc->transceiver, mA);
1336         return -EOPNOTSUPP;
1337 }
1338
1339 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1340 {
1341         struct omap_udc *udc;
1342         unsigned long   flags;
1343
1344         udc = container_of(gadget, struct omap_udc, gadget);
1345         spin_lock_irqsave(&udc->lock, flags);
1346         udc->softconnect = (is_on != 0);
1347         if (can_pullup(udc))
1348                 pullup_enable(udc);
1349         else
1350                 pullup_disable(udc);
1351         spin_unlock_irqrestore(&udc->lock, flags);
1352         return 0;
1353 }
1354
1355 static struct usb_gadget_ops omap_gadget_ops = {
1356         .get_frame              = omap_get_frame,
1357         .wakeup                 = omap_wakeup,
1358         .set_selfpowered        = omap_set_selfpowered,
1359         .vbus_session           = omap_vbus_session,
1360         .vbus_draw              = omap_vbus_draw,
1361         .pullup                 = omap_pullup,
1362 };
1363
1364 /*-------------------------------------------------------------------------*/
1365
1366 /* dequeue ALL requests; caller holds udc->lock */
1367 static void nuke(struct omap_ep *ep, int status)
1368 {
1369         struct omap_req *req;
1370
1371         ep->stopped = 1;
1372
1373         if (use_dma && ep->dma_channel)
1374                 dma_channel_release(ep);
1375
1376         use_ep(ep, 0);
1377         UDC_CTRL_REG = UDC_CLR_EP;
1378         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1379                 UDC_CTRL_REG = UDC_SET_HALT;
1380
1381         while (!list_empty(&ep->queue)) {
1382                 req = list_entry(ep->queue.next, struct omap_req, queue);
1383                 done(ep, req, status);
1384         }
1385 }
1386
1387 /* caller holds udc->lock */
1388 static void udc_quiesce(struct omap_udc *udc)
1389 {
1390         struct omap_ep  *ep;
1391
1392         udc->gadget.speed = USB_SPEED_UNKNOWN;
1393         nuke(&udc->ep[0], -ESHUTDOWN);
1394         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1395                 nuke(ep, -ESHUTDOWN);
1396 }
1397
1398 /*-------------------------------------------------------------------------*/
1399
1400 static void update_otg(struct omap_udc *udc)
1401 {
1402         u16     devstat;
1403
1404         if (!udc->gadget.is_otg)
1405                 return;
1406
1407         if (OTG_CTRL_REG & OTG_ID)
1408                 devstat = UDC_DEVSTAT_REG;
1409         else
1410                 devstat = 0;
1411
1412         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1413         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1414         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1415
1416         /* Enable HNP early, avoiding races on suspend irq path.
1417          * ASSUMES OTG state machine B_BUS_REQ input is true.
1418          */
1419         if (udc->gadget.b_hnp_enable)
1420                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1421                                 & ~OTG_PULLUP;
1422 }
1423
1424 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1425 {
1426         struct omap_ep  *ep0 = &udc->ep[0];
1427         struct omap_req *req = NULL;
1428
1429         ep0->irqs++;
1430
1431         /* Clear any pending requests and then scrub any rx/tx state
1432          * before starting to handle the SETUP request.
1433          */
1434         if (irq_src & UDC_SETUP) {
1435                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1436
1437                 nuke(ep0, 0);
1438                 if (ack) {
1439                         UDC_IRQ_SRC_REG = ack;
1440                         irq_src = UDC_SETUP;
1441                 }
1442         }
1443
1444         /* IN/OUT packets mean we're in the DATA or STATUS stage.  
1445          * This driver uses only uses protocol stalls (ep0 never halts),
1446          * and if we got this far the gadget driver already had a
1447          * chance to stall.  Tries to be forgiving of host oddities.
1448          *
1449          * NOTE:  the last chance gadget drivers have to stall control
1450          * requests is during their request completion callback.
1451          */
1452         if (!list_empty(&ep0->queue))
1453                 req = container_of(ep0->queue.next, struct omap_req, queue);
1454
1455         /* IN == TX to host */
1456         if (irq_src & UDC_EP0_TX) {
1457                 int     stat;
1458
1459                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1460                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1461                 stat = UDC_STAT_FLG_REG;
1462                 if (stat & UDC_ACK) {
1463                         if (udc->ep0_in) {
1464                                 /* write next IN packet from response,
1465                                  * or set up the status stage.
1466                                  */
1467                                 if (req)
1468                                         stat = write_fifo(ep0, req);
1469                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1470                                 if (!req && udc->ep0_pending) {
1471                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1472                                         UDC_CTRL_REG = UDC_CLR_EP;
1473                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1474                                         UDC_EP_NUM_REG = 0;
1475                                         udc->ep0_pending = 0;
1476                                 } /* else:  6 wait states before it'll tx */
1477                         } else {
1478                                 /* ack status stage of OUT transfer */
1479                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1480                                 if (req)
1481                                         done(ep0, req, 0);
1482                         }
1483                         req = NULL;
1484                 } else if (stat & UDC_STALL) {
1485                         UDC_CTRL_REG = UDC_CLR_HALT;
1486                         UDC_EP_NUM_REG = UDC_EP_DIR;
1487                 } else {
1488                         UDC_EP_NUM_REG = UDC_EP_DIR;
1489                 }
1490         }
1491
1492         /* OUT == RX from host */
1493         if (irq_src & UDC_EP0_RX) {
1494                 int     stat;
1495
1496                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1497                 UDC_EP_NUM_REG = UDC_EP_SEL;
1498                 stat = UDC_STAT_FLG_REG;
1499                 if (stat & UDC_ACK) {
1500                         if (!udc->ep0_in) {
1501                                 stat = 0;
1502                                 /* read next OUT packet of request, maybe
1503                                  * reactiviting the fifo; stall on errors.
1504                                  */
1505                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1506                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1507                                         udc->ep0_pending = 0;
1508                                         stat = 0;
1509                                 } else if (stat == 0)
1510                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1511                                 UDC_EP_NUM_REG = 0;
1512                                 
1513                                 /* activate status stage */
1514                                 if (stat == 1) {
1515                                         done(ep0, req, 0);
1516                                         /* that may have STALLed ep0... */
1517                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1518                                         UDC_CTRL_REG = UDC_CLR_EP;
1519                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1520                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1521                                         udc->ep0_pending = 0;
1522                                 }
1523                         } else {
1524                                 /* ack status stage of IN transfer */
1525                                 UDC_EP_NUM_REG = 0;
1526                                 if (req)
1527                                         done(ep0, req, 0);
1528                         }
1529                 } else if (stat & UDC_STALL) {
1530                         UDC_CTRL_REG = UDC_CLR_HALT;
1531                         UDC_EP_NUM_REG = 0;
1532                 } else {
1533                         UDC_EP_NUM_REG = 0;
1534                 }
1535         }
1536
1537         /* SETUP starts all control transfers */
1538         if (irq_src & UDC_SETUP) {
1539                 union u {
1540                         u16                     word[4];
1541                         struct usb_ctrlrequest  r;
1542                 } u;
1543                 int                     status = -EINVAL;
1544                 struct omap_ep          *ep;
1545
1546                 /* read the (latest) SETUP message */
1547                 do {
1548                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1549                         /* two bytes at a time */
1550                         u.word[0] = UDC_DATA_REG;
1551                         u.word[1] = UDC_DATA_REG;
1552                         u.word[2] = UDC_DATA_REG;
1553                         u.word[3] = UDC_DATA_REG;
1554                         UDC_EP_NUM_REG = 0;
1555                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1556
1557 #define w_value         le16_to_cpup (&u.r.wValue)
1558 #define w_index         le16_to_cpup (&u.r.wIndex)
1559 #define w_length        le16_to_cpup (&u.r.wLength)
1560
1561                 /* Delegate almost all control requests to the gadget driver,
1562                  * except for a handful of ch9 status/feature requests that
1563                  * hardware doesn't autodecode _and_ the gadget API hides.
1564                  */
1565                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1566                 udc->ep0_set_config = 0;
1567                 udc->ep0_pending = 1;
1568                 ep0->stopped = 0;
1569                 ep0->ackwait = 0;
1570                 switch (u.r.bRequest) {
1571                 case USB_REQ_SET_CONFIGURATION:
1572                         /* udc needs to know when ep != 0 is valid */
1573                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1574                                 goto delegate;
1575                         if (w_length != 0)
1576                                 goto do_stall;
1577                         udc->ep0_set_config = 1;
1578                         udc->ep0_reset_config = (w_value == 0);
1579                         VDBG("set config %d\n", w_value);
1580
1581                         /* update udc NOW since gadget driver may start
1582                          * queueing requests immediately; clear config
1583                          * later if it fails the request.
1584                          */
1585                         if (udc->ep0_reset_config)
1586                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1587                         else
1588                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1589                         update_otg(udc);
1590                         goto delegate;
1591                 case USB_REQ_CLEAR_FEATURE:
1592                         /* clear endpoint halt */
1593                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1594                                 goto delegate;
1595                         if (w_value != USB_ENDPOINT_HALT
1596                                         || w_length != 0)
1597                                 goto do_stall;
1598                         ep = &udc->ep[w_index & 0xf];
1599                         if (ep != ep0) {
1600                                 if (w_index & USB_DIR_IN)
1601                                         ep += 16;
1602                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1603                                                 || !ep->desc)
1604                                         goto do_stall;
1605                                 use_ep(ep, 0);
1606                                 UDC_CTRL_REG = udc->clr_halt;
1607                                 ep->ackwait = 0;
1608                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1609                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1610                                         ep->ackwait = 1 + ep->double_buf;
1611                                 }
1612                                 /* NOTE:  assumes the host behaves sanely,
1613                                  * only clearing real halts.  Else we may
1614                                  * need to kill pending transfers and then
1615                                  * restart the queue... very messy for DMA!
1616                                  */
1617                         }
1618                         VDBG("%s halt cleared by host\n", ep->name);
1619                         goto ep0out_status_stage;
1620                 case USB_REQ_SET_FEATURE:
1621                         /* set endpoint halt */
1622                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1623                                 goto delegate;
1624                         if (w_value != USB_ENDPOINT_HALT
1625                                         || w_length != 0)
1626                                 goto do_stall;
1627                         ep = &udc->ep[w_index & 0xf];
1628                         if (w_index & USB_DIR_IN)
1629                                 ep += 16;
1630                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1631                                         || ep == ep0 || !ep->desc)
1632                                 goto do_stall;
1633                         if (use_dma && ep->has_dma) {
1634                                 /* this has rude side-effects (aborts) and
1635                                  * can't really work if DMA-IN is active
1636                                  */
1637                                 DBG("%s host set_halt, NYET \n", ep->name);
1638                                 goto do_stall;
1639                         }
1640                         use_ep(ep, 0);
1641                         /* can't halt if fifo isn't empty... */
1642                         UDC_CTRL_REG = UDC_CLR_EP;
1643                         UDC_CTRL_REG = UDC_SET_HALT;
1644                         VDBG("%s halted by host\n", ep->name);
1645 ep0out_status_stage:
1646                         status = 0;
1647                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1648                         UDC_CTRL_REG = UDC_CLR_EP;
1649                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1650                         UDC_EP_NUM_REG = UDC_EP_DIR;
1651                         udc->ep0_pending = 0;
1652                         break;
1653                 case USB_REQ_GET_STATUS:
1654                         /* return interface status.  if we were pedantic,
1655                          * we'd detect non-existent interfaces, and stall.
1656                          */
1657                         if (u.r.bRequestType
1658                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1659                                 goto delegate;
1660                         /* return two zero bytes */
1661                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1662                         UDC_DATA_REG = 0;
1663                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1664                         UDC_EP_NUM_REG = UDC_EP_DIR;
1665                         status = 0;
1666                         VDBG("GET_STATUS, interface %d\n", w_index);
1667                         /* next, status stage */
1668                         break;
1669                 default:
1670 delegate:
1671                         /* activate the ep0out fifo right away */
1672                         if (!udc->ep0_in && w_length) {
1673                                 UDC_EP_NUM_REG = 0;
1674                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1675                         }
1676
1677                         /* gadget drivers see class/vendor specific requests,
1678                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1679                          * and more
1680                          */
1681                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1682                                 u.r.bRequestType, u.r.bRequest,
1683                                 w_value, w_index, w_length);
1684
1685 #undef  w_value
1686 #undef  w_index
1687 #undef  w_length
1688
1689                         /* The gadget driver may return an error here,
1690                          * causing an immediate protocol stall.
1691                          *
1692                          * Else it must issue a response, either queueing a
1693                          * response buffer for the DATA stage, or halting ep0
1694                          * (causing a protocol stall, not a real halt).  A
1695                          * zero length buffer means no DATA stage.
1696                          *
1697                          * It's fine to issue that response after the setup()
1698                          * call returns, and this IRQ was handled.
1699                          */
1700                         udc->ep0_setup = 1;
1701                         spin_unlock(&udc->lock);
1702                         status = udc->driver->setup (&udc->gadget, &u.r);
1703                         spin_lock(&udc->lock);
1704                         udc->ep0_setup = 0;
1705                 }
1706
1707                 if (status < 0) {
1708 do_stall:
1709                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1710                                         u.r.bRequestType, u.r.bRequest, status);
1711                         if (udc->ep0_set_config) {
1712                                 if (udc->ep0_reset_config)
1713                                         WARN("error resetting config?\n");
1714                                 else
1715                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1716                         }
1717                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1718                         udc->ep0_pending = 0;
1719                 }
1720         }
1721 }
1722
1723 /*-------------------------------------------------------------------------*/
1724
1725 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1726
1727 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1728 {
1729         u16     devstat, change;
1730
1731         devstat = UDC_DEVSTAT_REG;
1732         change = devstat ^ udc->devstat;
1733         udc->devstat = devstat;
1734
1735         if (change & (UDC_USB_RESET|UDC_ATT)) {
1736                 udc_quiesce(udc);
1737
1738                 if (change & UDC_ATT) {
1739                         /* driver for any external transceiver will
1740                          * have called omap_vbus_session() already
1741                          */
1742                         if (devstat & UDC_ATT) {
1743                                 udc->gadget.speed = USB_SPEED_FULL;
1744                                 VDBG("connect\n");
1745                                 if (!udc->transceiver)
1746                                         pullup_enable(udc);
1747                                 // if (driver->connect) call it
1748                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1749                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1750                                 if (!udc->transceiver)
1751                                         pullup_disable(udc);
1752                                 DBG("disconnect, gadget %s\n",
1753                                         udc->driver->driver.name);
1754                                 if (udc->driver->disconnect) {
1755                                         spin_unlock(&udc->lock);
1756                                         udc->driver->disconnect(&udc->gadget);
1757                                         spin_lock(&udc->lock);
1758                                 }
1759                         }
1760                         change &= ~UDC_ATT;
1761                 }
1762
1763                 if (change & UDC_USB_RESET) {
1764                         if (devstat & UDC_USB_RESET) {
1765                                 VDBG("RESET=1\n");
1766                         } else {
1767                                 udc->gadget.speed = USB_SPEED_FULL;
1768                                 INFO("USB reset done, gadget %s\n",
1769                                         udc->driver->driver.name);
1770                                 /* ep0 traffic is legal from now on */
1771                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1772                         }
1773                         change &= ~UDC_USB_RESET;
1774                 }
1775         }
1776         if (change & UDC_SUS) {
1777                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1778                         // FIXME tell isp1301 to suspend/resume (?)
1779                         if (devstat & UDC_SUS) {
1780                                 VDBG("suspend\n");
1781                                 update_otg(udc);
1782                                 /* HNP could be under way already */
1783                                 if (udc->gadget.speed == USB_SPEED_FULL
1784                                                 && udc->driver->suspend) {
1785                                         spin_unlock(&udc->lock);
1786                                         udc->driver->suspend(&udc->gadget);
1787                                         spin_lock(&udc->lock);
1788                                 }
1789                         } else {
1790                                 VDBG("resume\n");
1791                                 if (udc->gadget.speed == USB_SPEED_FULL
1792                                                 && udc->driver->resume) {
1793                                         spin_unlock(&udc->lock);
1794                                         udc->driver->resume(&udc->gadget);
1795                                         spin_lock(&udc->lock);
1796                                 }
1797                         }
1798                 }
1799                 change &= ~UDC_SUS;
1800         }
1801         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1802                 update_otg(udc);
1803                 change &= ~OTG_FLAGS;
1804         }
1805
1806         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1807         if (change)
1808                 VDBG("devstat %03x, ignore change %03x\n",
1809                         devstat,  change);
1810
1811         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1812 }
1813
1814 static irqreturn_t
1815 omap_udc_irq(int irq, void *_udc, struct pt_regs *r)
1816 {
1817         struct omap_udc *udc = _udc;
1818         u16             irq_src;
1819         irqreturn_t     status = IRQ_NONE;
1820         unsigned long   flags;
1821
1822         spin_lock_irqsave(&udc->lock, flags);
1823         irq_src = UDC_IRQ_SRC_REG;
1824
1825         /* Device state change (usb ch9 stuff) */
1826         if (irq_src & UDC_DS_CHG) {
1827                 devstate_irq(_udc, irq_src);
1828                 status = IRQ_HANDLED;
1829                 irq_src &= ~UDC_DS_CHG;
1830         }
1831
1832         /* EP0 control transfers */
1833         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1834                 ep0_irq(_udc, irq_src);
1835                 status = IRQ_HANDLED;
1836                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1837         }
1838
1839         /* DMA transfer completion */
1840         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1841                 dma_irq(_udc, irq_src);
1842                 status = IRQ_HANDLED;
1843                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1844         }
1845
1846         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1847         if (irq_src)
1848                 DBG("udc_irq, unhandled %03x\n", irq_src);
1849         spin_unlock_irqrestore(&udc->lock, flags);
1850
1851         return status;
1852 }
1853
1854 /* workaround for seemingly-lost IRQs for RX ACKs... */
1855 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1856 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1857
1858 static void pio_out_timer(unsigned long _ep)
1859 {
1860         struct omap_ep  *ep = (void *) _ep;
1861         unsigned long   flags;
1862         u16             stat_flg;
1863
1864         spin_lock_irqsave(&ep->udc->lock, flags);
1865         if (!list_empty(&ep->queue) && ep->ackwait) {
1866                 use_ep(ep, 0);
1867                 stat_flg = UDC_STAT_FLG_REG;
1868
1869                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1870                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1871                         struct omap_req *req;
1872
1873                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1874                         req = container_of(ep->queue.next,
1875                                         struct omap_req, queue);
1876                         UDC_EP_NUM_REG = ep->bEndpointAddress | UDC_EP_SEL;
1877                         (void) read_fifo(ep, req);
1878                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1879                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1880                         ep->ackwait = 1 + ep->double_buf;
1881                 }
1882         }
1883         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1884         spin_unlock_irqrestore(&ep->udc->lock, flags);
1885 }
1886
1887 static irqreturn_t
1888 omap_udc_pio_irq(int irq, void *_dev, struct pt_regs *r)
1889 {
1890         u16             epn_stat, irq_src;
1891         irqreturn_t     status = IRQ_NONE;
1892         struct omap_ep  *ep;
1893         int             epnum;
1894         struct omap_udc *udc = _dev;
1895         struct omap_req *req;
1896         unsigned long   flags;
1897
1898         spin_lock_irqsave(&udc->lock, flags);
1899         epn_stat = UDC_EPN_STAT_REG;
1900         irq_src = UDC_IRQ_SRC_REG;
1901
1902         /* handle OUT first, to avoid some wasteful NAKs */
1903         if (irq_src & UDC_EPN_RX) {
1904                 epnum = (epn_stat >> 8) & 0x0f;
1905                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1906                 status = IRQ_HANDLED;
1907                 ep = &udc->ep[epnum];
1908                 ep->irqs++;
1909
1910                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1911                 ep->fnf = 0;
1912                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1913                         ep->ackwait--;
1914                         if (!list_empty(&ep->queue)) {
1915                                 int stat;
1916                                 req = container_of(ep->queue.next,
1917                                                 struct omap_req, queue);
1918                                 stat = read_fifo(ep, req);
1919                                 if (!ep->double_buf)
1920                                         ep->fnf = 1;
1921                         }
1922                 }
1923                 /* min 6 clock delay before clearing EP_SEL ... */
1924                 epn_stat = UDC_EPN_STAT_REG;
1925                 epn_stat = UDC_EPN_STAT_REG;
1926                 UDC_EP_NUM_REG = epnum;
1927
1928                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1929                  * reduces lossage; timer still needed though (sigh).
1930                  */
1931                 if (ep->fnf) {
1932                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1933                         ep->ackwait = 1 + ep->double_buf;
1934                 }
1935                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1936         }
1937
1938         /* then IN transfers */
1939         else if (irq_src & UDC_EPN_TX) {
1940                 epnum = epn_stat & 0x0f;
1941                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1942                 status = IRQ_HANDLED;
1943                 ep = &udc->ep[16 + epnum];
1944                 ep->irqs++;
1945
1946                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1947                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1948                         ep->ackwait = 0;
1949                         if (!list_empty(&ep->queue)) {
1950                                 req = container_of(ep->queue.next,
1951                                                 struct omap_req, queue);
1952                                 (void) write_fifo(ep, req);
1953                         }
1954                 }
1955                 /* min 6 clock delay before clearing EP_SEL ... */
1956                 epn_stat = UDC_EPN_STAT_REG;
1957                 epn_stat = UDC_EPN_STAT_REG;
1958                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1959                 /* then 6 clocks before it'd tx */
1960         }
1961
1962         spin_unlock_irqrestore(&udc->lock, flags);
1963         return status;
1964 }
1965
1966 #ifdef  USE_ISO
1967 static irqreturn_t
1968 omap_udc_iso_irq(int irq, void *_dev, struct pt_regs *r)
1969 {
1970         struct omap_udc *udc = _dev;
1971         struct omap_ep  *ep;
1972         int             pending = 0;
1973         unsigned long   flags;
1974
1975         spin_lock_irqsave(&udc->lock, flags);
1976
1977         /* handle all non-DMA ISO transfers */
1978         list_for_each_entry (ep, &udc->iso, iso) {
1979                 u16             stat;
1980                 struct omap_req *req;
1981
1982                 if (ep->has_dma || list_empty(&ep->queue))
1983                         continue;
1984                 req = list_entry(ep->queue.next, struct omap_req, queue);
1985
1986                 use_ep(ep, UDC_EP_SEL);
1987                 stat = UDC_STAT_FLG_REG;
1988
1989                 /* NOTE: like the other controller drivers, this isn't
1990                  * currently reporting lost or damaged frames.
1991                  */
1992                 if (ep->bEndpointAddress & USB_DIR_IN) {
1993                         if (stat & UDC_MISS_IN)
1994                                 /* done(ep, req, -EPROTO) */;
1995                         else
1996                                 write_fifo(ep, req);
1997                 } else {
1998                         int     status = 0;
1999
2000                         if (stat & UDC_NO_RXPACKET)
2001                                 status = -EREMOTEIO;
2002                         else if (stat & UDC_ISO_ERR)
2003                                 status = -EILSEQ;
2004                         else if (stat & UDC_DATA_FLUSH)
2005                                 status = -ENOSR;
2006
2007                         if (status)
2008                                 /* done(ep, req, status) */;
2009                         else
2010                                 read_fifo(ep, req);
2011                 }
2012                 deselect_ep();
2013                 /* 6 wait states before next EP */
2014
2015                 ep->irqs++;
2016                 if (!list_empty(&ep->queue))
2017                         pending = 1;
2018         }
2019         if (!pending)
2020                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2021         UDC_IRQ_SRC_REG = UDC_SOF;
2022
2023         spin_unlock_irqrestore(&udc->lock, flags);
2024         return IRQ_HANDLED;
2025 }
2026 #endif
2027
2028 /*-------------------------------------------------------------------------*/
2029
2030 static struct omap_udc *udc;
2031
2032 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2033 {
2034         int             status = -ENODEV;
2035         struct omap_ep  *ep;
2036         unsigned long   flags;
2037
2038         /* basic sanity tests */
2039         if (!udc)
2040                 return -ENODEV;
2041         if (!driver
2042                         // FIXME if otg, check:  driver->is_otg
2043                         || driver->speed < USB_SPEED_FULL
2044                         || !driver->bind
2045                         || !driver->unbind
2046                         || !driver->setup)
2047                 return -EINVAL;
2048
2049         spin_lock_irqsave(&udc->lock, flags);
2050         if (udc->driver) {
2051                 spin_unlock_irqrestore(&udc->lock, flags);
2052                 return -EBUSY;
2053         }
2054
2055         /* reset state */
2056         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2057                 ep->irqs = 0;
2058                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2059                         continue;
2060                 use_ep(ep, 0);
2061                 UDC_CTRL_REG = UDC_SET_HALT;
2062         }
2063         udc->ep0_pending = 0;
2064         udc->ep[0].irqs = 0;
2065         udc->softconnect = 1;
2066
2067         /* hook up the driver */
2068         driver->driver.bus = NULL;
2069         udc->driver = driver;
2070         udc->gadget.dev.driver = &driver->driver;
2071         spin_unlock_irqrestore(&udc->lock, flags);
2072
2073         status = driver->bind (&udc->gadget);
2074         if (status) {
2075                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2076                 udc->gadget.dev.driver = NULL;
2077                 udc->driver = NULL;
2078                 goto done;
2079         }
2080         DBG("bound to driver %s\n", driver->driver.name);
2081
2082         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2083
2084         /* connect to bus through transceiver */
2085         if (udc->transceiver) {
2086                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2087                 if (status < 0) {
2088                         ERR("can't bind to transceiver\n");
2089                         driver->unbind (&udc->gadget);
2090                         udc->gadget.dev.driver = NULL;
2091                         udc->driver = NULL;
2092                         goto done;
2093                 }
2094         } else {
2095                 if (can_pullup(udc))
2096                         pullup_enable (udc);
2097                 else
2098                         pullup_disable (udc);
2099         }
2100
2101         /* boards that don't have VBUS sensing can't autogate 48MHz;
2102          * can't enter deep sleep while a gadget driver is active.
2103          */
2104         if (machine_is_omap_innovator() || machine_is_omap_osk())
2105                 omap_vbus_session(&udc->gadget, 1);
2106
2107 done:
2108         return status;
2109 }
2110 EXPORT_SYMBOL(usb_gadget_register_driver);
2111
2112 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2113 {
2114         unsigned long   flags;
2115         int             status = -ENODEV;
2116
2117         if (!udc)
2118                 return -ENODEV;
2119         if (!driver || driver != udc->driver)
2120                 return -EINVAL;
2121
2122         if (machine_is_omap_innovator() || machine_is_omap_osk())
2123                 omap_vbus_session(&udc->gadget, 0);
2124
2125         if (udc->transceiver)
2126                 (void) otg_set_peripheral(udc->transceiver, NULL);
2127         else
2128                 pullup_disable(udc);
2129
2130         spin_lock_irqsave(&udc->lock, flags);
2131         udc_quiesce(udc);
2132         spin_unlock_irqrestore(&udc->lock, flags);
2133
2134         driver->unbind(&udc->gadget);
2135         udc->gadget.dev.driver = NULL;
2136         udc->driver = NULL;
2137
2138         DBG("unregistered driver '%s'\n", driver->driver.name);
2139         return status;
2140 }
2141 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2142
2143
2144 /*-------------------------------------------------------------------------*/
2145
2146 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2147
2148 #include <linux/seq_file.h>
2149
2150 static const char proc_filename[] = "driver/udc";
2151
2152 #define FOURBITS "%s%s%s%s"
2153 #define EIGHTBITS FOURBITS FOURBITS
2154
2155 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2156 {
2157         u16             stat_flg;
2158         struct omap_req *req;
2159         char            buf[20];
2160
2161         use_ep(ep, 0);
2162
2163         if (use_dma && ep->has_dma)
2164                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2165                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2166                         ep->dma_channel - 1, ep->lch);
2167         else
2168                 buf[0] = 0;
2169
2170         stat_flg = UDC_STAT_FLG_REG;
2171         seq_printf(s,
2172                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2173                 ep->name, buf,
2174                 ep->double_buf ? "dbuf " : "",
2175                 ({char *s; switch(ep->ackwait){
2176                 case 0: s = ""; break;
2177                 case 1: s = "(ackw) "; break;
2178                 case 2: s = "(ackw2) "; break;
2179                 default: s = "(?) "; break;
2180                 } s;}),
2181                 ep->irqs, stat_flg,
2182                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2183                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2184                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2185                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2186                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2187                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2188                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2189                 (stat_flg & UDC_STALL) ? "STALL " : "",
2190                 (stat_flg & UDC_NAK) ? "NAK " : "",
2191                 (stat_flg & UDC_ACK) ? "ACK " : "",
2192                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2193                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2194                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2195
2196         if (list_empty (&ep->queue))
2197                 seq_printf(s, "\t(queue empty)\n");
2198         else
2199                 list_for_each_entry (req, &ep->queue, queue) {
2200                         unsigned        length = req->req.actual;
2201
2202                         if (use_dma && buf[0]) {
2203                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2204                                                 ? dma_src_len : dma_dest_len)
2205                                         (ep, req->req.dma + length);
2206                                 buf[0] = 0;
2207                         }
2208                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2209                                         &req->req, length,
2210                                         req->req.length, req->req.buf);
2211                 }
2212 }
2213
2214 static char *trx_mode(unsigned m, int enabled)
2215 {
2216         switch (m) {
2217         case 0:         return enabled ? "*6wire" : "unused";
2218         case 1:         return "4wire";
2219         case 2:         return "3wire";
2220         case 3:         return "6wire";
2221         default:        return "unknown";
2222         }
2223 }
2224
2225 static int proc_otg_show(struct seq_file *s)
2226 {
2227         u32             tmp;
2228         u32             trans;
2229
2230         tmp = OTG_REV_REG;
2231         trans = USB_TRANSCEIVER_CTRL_REG;
2232         seq_printf(s, "\nOTG rev %d.%d, transceiver_ctrl %05x\n",
2233                 tmp >> 4, tmp & 0xf, trans);
2234         tmp = OTG_SYSCON_1_REG;
2235         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2236                         FOURBITS "\n", tmp,
2237                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2238                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2239                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2240                         ? "internal"
2241                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2242                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2243                 (tmp & HST_IDLE_EN) ? " !host" : "",
2244                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2245                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2246         tmp = OTG_SYSCON_2_REG;
2247         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2248                         " b_ase_brst=%d hmc=%d\n", tmp,
2249                 (tmp & OTG_EN) ? " otg_en" : "",
2250                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2251                 // much more SRP stuff
2252                 (tmp & SRP_DATA) ? " srp_data" : "",
2253                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2254                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2255                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2256                 (tmp & UHOST_EN) ? " uhost_en" : "",
2257                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2258                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2259                 B_ASE_BRST(tmp),
2260                 OTG_HMC(tmp));
2261         tmp = OTG_CTRL_REG;
2262         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2263                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2264                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2265                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2266                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2267                 (tmp & OTG_ID) ? " id" : "",
2268                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2269                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2270                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2271                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2272                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2273                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2274                 (tmp & OTG_PULLDOWN) ? " down" : "",
2275                 (tmp & OTG_PULLUP) ? " up" : "",
2276                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2277                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2278                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2279                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2280                 );
2281         tmp = OTG_IRQ_EN_REG;
2282         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2283         tmp = OTG_IRQ_SRC_REG;
2284         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2285         tmp = OTG_OUTCTRL_REG;
2286         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2287         tmp = OTG_TEST_REG;
2288         seq_printf(s, "otg_test    %04x" "\n", tmp);
2289         return 0;
2290 }
2291
2292 static int proc_udc_show(struct seq_file *s, void *_)
2293 {
2294         u32             tmp;
2295         struct omap_ep  *ep;
2296         unsigned long   flags;
2297
2298         spin_lock_irqsave(&udc->lock, flags);
2299
2300         seq_printf(s, "%s, version: " DRIVER_VERSION
2301 #ifdef  USE_ISO
2302                 " (iso)"
2303 #endif
2304                 "%s\n",
2305                 driver_desc,
2306                 use_dma ?  " (dma)" : "");
2307
2308         tmp = UDC_REV_REG & 0xff; 
2309         seq_printf(s,
2310                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2311                 "hmc %d, transceiver %s\n",
2312                 tmp >> 4, tmp & 0xf,
2313                 fifo_mode,
2314                 udc->driver ? udc->driver->driver.name : "(none)",
2315                 HMC,
2316                 udc->transceiver ? udc->transceiver->label : "(none)");
2317         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2318                 __REG16(ULPD_CLOCK_CTRL),
2319                 __REG16(ULPD_SOFT_REQ),
2320                 __REG16(ULPD_STATUS_REQ));
2321
2322         /* OTG controller registers */
2323         if (!cpu_is_omap15xx())
2324                 proc_otg_show(s);
2325
2326         tmp = UDC_SYSCON1_REG;
2327         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2328                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2329                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2330                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2331                 (tmp & UDC_NAK_EN) ? " nak" : "",
2332                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2333                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2334                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2335                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2336         // syscon2 is write-only
2337
2338         /* UDC controller registers */
2339         if (!(tmp & UDC_PULLUP_EN)) {
2340                 seq_printf(s, "(suspended)\n");
2341                 spin_unlock_irqrestore(&udc->lock, flags);
2342                 return 0;
2343         }
2344
2345         tmp = UDC_DEVSTAT_REG;
2346         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2347                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2348                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2349                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2350                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2351                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2352                 (tmp & UDC_SUS) ? " SUS" : "",
2353                 (tmp & UDC_CFG) ? " CFG" : "",
2354                 (tmp & UDC_ADD) ? " ADD" : "",
2355                 (tmp & UDC_DEF) ? " DEF" : "",
2356                 (tmp & UDC_ATT) ? " ATT" : "");
2357         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2358         tmp = UDC_IRQ_EN_REG;
2359         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2360                 (tmp & UDC_SOF_IE) ? " sof" : "",
2361                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2362                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2363                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2364                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2365         tmp = UDC_IRQ_SRC_REG;
2366         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2367                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2368                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2369                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2370                 (tmp & UDC_SOF) ? " sof" : "",
2371                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2372                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2373                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2374                 (tmp & UDC_SETUP) ? " setup" : "",
2375                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2376                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2377         if (use_dma) {
2378                 unsigned i;
2379
2380                 tmp = UDC_DMA_IRQ_EN_REG;
2381                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2382                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2383                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2384                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2385
2386                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2387                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2388                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2389
2390                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2391                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2392                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2393
2394                 tmp = UDC_RXDMA_CFG_REG;
2395                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2396                 if (tmp) {
2397                         for (i = 0; i < 3; i++) {
2398                                 if ((tmp & (0x0f << (i * 4))) == 0)
2399                                         continue;
2400                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2401                                                 UDC_RXDMA_REG(i + 1));
2402                         }
2403                 }
2404                 tmp = UDC_TXDMA_CFG_REG;
2405                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2406                 if (tmp) {
2407                         for (i = 0; i < 3; i++) {
2408                                 if (!(tmp & (0x0f << (i * 4))))
2409                                         continue;
2410                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2411                                                 UDC_TXDMA_REG(i + 1));
2412                         }
2413                 }
2414         }
2415
2416         tmp = UDC_DEVSTAT_REG;
2417         if (tmp & UDC_ATT) {
2418                 proc_ep_show(s, &udc->ep[0]);
2419                 if (tmp & UDC_ADD) {
2420                         list_for_each_entry (ep, &udc->gadget.ep_list,
2421                                         ep.ep_list) {
2422                                 if (ep->desc)
2423                                         proc_ep_show(s, ep);
2424                         }
2425                 }
2426         }
2427         spin_unlock_irqrestore(&udc->lock, flags);
2428         return 0;
2429 }
2430
2431 static int proc_udc_open(struct inode *inode, struct file *file)
2432 {
2433         return single_open(file, proc_udc_show, NULL);
2434 }
2435
2436 static struct file_operations proc_ops = {
2437         .open           = proc_udc_open,
2438         .read           = seq_read,
2439         .llseek         = seq_lseek,
2440         .release        = single_release,
2441 };
2442
2443 static void create_proc_file(void)
2444 {
2445         struct proc_dir_entry *pde;
2446
2447         pde = create_proc_entry (proc_filename, 0, NULL);
2448         if (pde)
2449                 pde->proc_fops = &proc_ops;
2450 }
2451
2452 static void remove_proc_file(void)
2453 {
2454         remove_proc_entry(proc_filename, NULL);
2455 }
2456
2457 #else
2458
2459 static inline void create_proc_file(void) {}
2460 static inline void remove_proc_file(void) {}
2461
2462 #endif
2463
2464 /*-------------------------------------------------------------------------*/
2465
2466 /* Before this controller can enumerate, we need to pick an endpoint
2467  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2468  * buffer space among the endpoints we'll be operating.
2469  *
2470  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2471  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2472  * capability yet though.
2473  */
2474 static unsigned __init
2475 omap_ep_setup(char *name, u8 addr, u8 type,
2476                 unsigned buf, unsigned maxp, int dbuf)
2477 {
2478         struct omap_ep  *ep;
2479         u16             epn_rxtx = 0;
2480
2481         /* OUT endpoints first, then IN */
2482         ep = &udc->ep[addr & 0xf];
2483         if (addr & USB_DIR_IN)
2484                 ep += 16;
2485
2486         /* in case of ep init table bugs */
2487         BUG_ON(ep->name[0]);
2488
2489         /* chip setup ... bit values are same for IN, OUT */
2490         if (type == USB_ENDPOINT_XFER_ISOC) {
2491                 switch (maxp) {
2492                 case 8:         epn_rxtx = 0 << 12; break;
2493                 case 16:        epn_rxtx = 1 << 12; break;
2494                 case 32:        epn_rxtx = 2 << 12; break;
2495                 case 64:        epn_rxtx = 3 << 12; break;
2496                 case 128:       epn_rxtx = 4 << 12; break;
2497                 case 256:       epn_rxtx = 5 << 12; break;
2498                 case 512:       epn_rxtx = 6 << 12; break;
2499                 default:        BUG();
2500                 }
2501                 epn_rxtx |= UDC_EPN_RX_ISO;
2502                 dbuf = 1;
2503         } else {
2504                 /* double-buffering "not supported" on 15xx,
2505                  * and ignored for PIO-IN on 16xx
2506                  */
2507                 if (!use_dma || cpu_is_omap15xx())
2508                         dbuf = 0;
2509
2510                 switch (maxp) {
2511                 case 8:         epn_rxtx = 0 << 12; break;
2512                 case 16:        epn_rxtx = 1 << 12; break;
2513                 case 32:        epn_rxtx = 2 << 12; break;
2514                 case 64:        epn_rxtx = 3 << 12; break;
2515                 default:        BUG();
2516                 }
2517                 if (dbuf && addr)
2518                         epn_rxtx |= UDC_EPN_RX_DB;
2519                 init_timer(&ep->timer);
2520                 ep->timer.function = pio_out_timer;
2521                 ep->timer.data = (unsigned long) ep;
2522         }
2523         if (addr)
2524                 epn_rxtx |= UDC_EPN_RX_VALID;
2525         BUG_ON(buf & 0x07);
2526         epn_rxtx |= buf >> 3;
2527
2528         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2529                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2530
2531         if (addr & USB_DIR_IN)
2532                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2533         else
2534                 UDC_EP_RX_REG(addr) = epn_rxtx;
2535
2536         /* next endpoint's buffer starts after this one's */
2537         buf += maxp;
2538         if (dbuf)
2539                 buf += maxp;
2540         BUG_ON(buf > 2048);
2541
2542         /* set up driver data structures */
2543         BUG_ON(strlen(name) >= sizeof ep->name);
2544         strlcpy(ep->name, name, sizeof ep->name);
2545         INIT_LIST_HEAD(&ep->queue);
2546         INIT_LIST_HEAD(&ep->iso);
2547         ep->bEndpointAddress = addr;
2548         ep->bmAttributes = type;
2549         ep->double_buf = dbuf;
2550         ep->udc = udc; 
2551
2552         ep->ep.name = ep->name;
2553         ep->ep.ops = &omap_ep_ops;
2554         ep->ep.maxpacket = ep->maxpacket = maxp;
2555         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2556
2557         return buf;
2558 }
2559
2560 static void omap_udc_release(struct device *dev)
2561 {
2562         complete(udc->done);
2563         kfree (udc);
2564         udc = NULL;
2565 }
2566
2567 static int __init
2568 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2569 {
2570         unsigned        tmp, buf;
2571
2572         /* abolish any previous hardware state */
2573         UDC_SYSCON1_REG = 0;
2574         UDC_IRQ_EN_REG = 0;
2575         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2576         UDC_DMA_IRQ_EN_REG = 0;
2577         UDC_RXDMA_CFG_REG = 0;
2578         UDC_TXDMA_CFG_REG = 0;
2579
2580         /* UDC_PULLUP_EN gates the chip clock */
2581         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2582
2583         udc = kmalloc (sizeof *udc, SLAB_KERNEL);
2584         if (!udc)
2585                 return -ENOMEM;
2586
2587         memset(udc, 0, sizeof *udc);
2588         spin_lock_init (&udc->lock);
2589
2590         udc->gadget.ops = &omap_gadget_ops;
2591         udc->gadget.ep0 = &udc->ep[0].ep;
2592         INIT_LIST_HEAD(&udc->gadget.ep_list);
2593         INIT_LIST_HEAD(&udc->iso);
2594         udc->gadget.speed = USB_SPEED_UNKNOWN;
2595         udc->gadget.name = driver_name;
2596
2597         device_initialize(&udc->gadget.dev);
2598         strcpy (udc->gadget.dev.bus_id, "gadget");
2599         udc->gadget.dev.release = omap_udc_release;
2600         udc->gadget.dev.parent = &odev->dev;
2601         if (use_dma)
2602                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2603
2604         udc->transceiver = xceiv;
2605
2606         /* ep0 is special; put it right after the SETUP buffer */
2607         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2608                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2609         list_del_init(&udc->ep[0].ep.ep_list);
2610
2611         /* initially disable all non-ep0 endpoints */
2612         for (tmp = 1; tmp < 15; tmp++) {
2613                 UDC_EP_RX_REG(tmp) = 0;
2614                 UDC_EP_TX_REG(tmp) = 0;
2615         }
2616
2617 #define OMAP_BULK_EP(name,addr) \
2618         buf = omap_ep_setup(name "-bulk", addr, \
2619                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2620 #define OMAP_INT_EP(name,addr, maxp) \
2621         buf = omap_ep_setup(name "-int", addr, \
2622                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2623 #define OMAP_ISO_EP(name,addr, maxp) \
2624         buf = omap_ep_setup(name "-iso", addr, \
2625                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2626
2627         switch (fifo_mode) {
2628         case 0:
2629                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2630                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2631                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2632                 break;
2633         case 1:
2634                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2635                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2636                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2637
2638                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2639                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2640                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2641
2642                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2643                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2644                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2645
2646                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2647                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2648                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2649
2650                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2651                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2652                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2653                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2654
2655                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2656                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2657                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2658                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2659
2660                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2661                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2662
2663                 break;
2664
2665 #ifdef  USE_ISO
2666         case 2:                 /* mixed iso/bulk */
2667                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2668                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2669                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2670                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2671
2672                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2673
2674                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2675                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2676                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2677                 break;
2678         case 3:                 /* mixed bulk/iso */
2679                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2680                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2681                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2682
2683                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2684                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2685                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2686
2687                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2688                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2689                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2690                 break;
2691 #endif
2692
2693         /* add more modes as needed */
2694
2695         default:
2696                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2697                 return -ENODEV;
2698         }
2699         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2700         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2701         return 0;
2702 }
2703
2704 static int __init omap_udc_probe(struct device *dev)
2705 {
2706         struct platform_device  *odev = to_platform_device(dev);
2707         int                     status = -ENODEV;
2708         int                     hmc;
2709         struct otg_transceiver  *xceiv = NULL;
2710         const char              *type = NULL;
2711         struct omap_usb_config  *config = dev->platform_data;
2712
2713         /* NOTE:  "knows" the order of the resources! */
2714         if (!request_mem_region(odev->resource[0].start, 
2715                         odev->resource[0].end - odev->resource[0].start + 1,
2716                         driver_name)) {
2717                 DBG("request_mem_region failed\n");
2718                 return -EBUSY;
2719         }
2720
2721         INFO("OMAP UDC rev %d.%d%s\n",
2722                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2723                 config->otg ? ", Mini-AB" : "");
2724
2725         /* use the mode given to us by board init code */
2726         if (cpu_is_omap15xx()) {
2727                 hmc = HMC_1510;
2728                 type = "(unknown)";
2729
2730                 if (machine_is_omap_innovator()) {
2731                         /* just set up software VBUS detect, and then
2732                          * later rig it so we always report VBUS.
2733                          * FIXME without really sensing VBUS, we can't
2734                          * know when to turn PULLUP_EN on/off; and that
2735                          * means we always "need" the 48MHz clock.
2736                          */
2737                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2738
2739                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2740                         tmp |= VBUS_MODE_1510;
2741                         tmp &= ~VBUS_CTRL_1510;
2742                         FUNC_MUX_CTRL_0_REG = tmp;
2743                 }
2744         } else {
2745                 /* The transceiver may package some GPIO logic or handle
2746                  * loopback and/or transceiverless setup; if we find one,
2747                  * use it.  Except for OTG, we don't _need_ to talk to one;
2748                  * but not having one probably means no VBUS detection.
2749                  */
2750                 xceiv = otg_get_transceiver();
2751                 if (xceiv)
2752                         type = xceiv->label;
2753                 else if (config->otg) {
2754                         DBG("OTG requires external transceiver!\n");
2755                         goto cleanup0;
2756                 }
2757
2758                 hmc = HMC_1610;
2759                 switch (hmc) {
2760                 case 0:                 /* POWERUP DEFAULT == 0 */
2761                 case 4:
2762                 case 12:
2763                 case 20:
2764                         if (!cpu_is_omap1710()) {
2765                                 type = "integrated";
2766                                 break;
2767                         }
2768                         /* FALL THROUGH */
2769                 case 3:
2770                 case 11:
2771                 case 16:
2772                 case 19:
2773                 case 25:
2774                         if (!xceiv) {
2775                                 DBG("external transceiver not registered!\n");
2776                                 type = "unknown";
2777                         }
2778                         break;
2779                 case 21:                        /* internal loopback */
2780                         type = "loopback";
2781                         break;
2782                 case 14:                        /* transceiverless */
2783                         if (cpu_is_omap1710())
2784                                 goto bad_on_1710;
2785                         /* FALL THROUGH */
2786                 case 13:
2787                 case 15:
2788                         type = "no";
2789                         break;
2790
2791                 default:
2792 bad_on_1710:
2793                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2794                         goto cleanup0;
2795                 }
2796         }
2797         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2798
2799         /* a "gadget" abstracts/virtualizes the controller */
2800         status = omap_udc_setup(odev, xceiv);
2801         if (status) {
2802                 goto cleanup0;
2803         }
2804         xceiv = NULL;
2805         // "udc" is now valid
2806         pullup_disable(udc);
2807 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2808         udc->gadget.is_otg = (config->otg != 0);
2809 #endif
2810
2811         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2812         if (UDC_REV_REG >= 0x61)
2813                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2814         else
2815                 udc->clr_halt = UDC_RESET_EP;
2816
2817         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2818         status = request_irq(odev->resource[1].start, omap_udc_irq,
2819                         SA_SAMPLE_RANDOM, driver_name, udc);
2820         if (status != 0) {
2821                 ERR( "can't get irq %ld, err %d\n",
2822                         odev->resource[1].start, status);
2823                 goto cleanup1;
2824         }
2825
2826         /* USB "non-iso" IRQ (PIO for all but ep0) */
2827         status = request_irq(odev->resource[2].start, omap_udc_pio_irq,
2828                         SA_SAMPLE_RANDOM, "omap_udc pio", udc);
2829         if (status != 0) {
2830                 ERR( "can't get irq %ld, err %d\n",
2831                         odev->resource[2].start, status);
2832                 goto cleanup2;
2833         }
2834 #ifdef  USE_ISO
2835         status = request_irq(odev->resource[3].start, omap_udc_iso_irq,
2836                         SA_INTERRUPT, "omap_udc iso", udc);
2837         if (status != 0) {
2838                 ERR("can't get irq %ld, err %d\n",
2839                         odev->resource[3].start, status);
2840                 goto cleanup3;
2841         }
2842 #endif
2843
2844         create_proc_file();
2845         device_add(&udc->gadget.dev);
2846         return 0;
2847
2848 #ifdef  USE_ISO
2849 cleanup3:
2850         free_irq(odev->resource[2].start, udc);
2851 #endif
2852
2853 cleanup2:
2854         free_irq(odev->resource[1].start, udc);
2855
2856 cleanup1:
2857         kfree (udc);
2858         udc = NULL;
2859
2860 cleanup0:
2861         if (xceiv)
2862                 put_device(xceiv->dev);
2863         release_mem_region(odev->resource[0].start,
2864                         odev->resource[0].end - odev->resource[0].start + 1);
2865         return status;
2866 }
2867
2868 static int __exit omap_udc_remove(struct device *dev)
2869 {
2870         struct platform_device  *odev = to_platform_device(dev);
2871         DECLARE_COMPLETION(done);
2872
2873         if (!udc)
2874                 return -ENODEV;
2875
2876         udc->done = &done;
2877
2878         pullup_disable(udc);
2879         if (udc->transceiver) {
2880                 put_device(udc->transceiver->dev);
2881                 udc->transceiver = NULL;
2882         }
2883         UDC_SYSCON1_REG = 0;
2884
2885         remove_proc_file();
2886
2887 #ifdef  USE_ISO
2888         free_irq(odev->resource[3].start, udc);
2889 #endif
2890         free_irq(odev->resource[2].start, udc);
2891         free_irq(odev->resource[1].start, udc);
2892
2893         release_mem_region(odev->resource[0].start,
2894                         odev->resource[0].end - odev->resource[0].start + 1);
2895
2896         device_unregister(&udc->gadget.dev);
2897         wait_for_completion(&done);
2898
2899         return 0;
2900 }
2901
2902 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2903  * system is forced into deep sleep
2904  *
2905  * REVISIT we should probably reject suspend requests when there's a host
2906  * session active, rather than disconnecting, at least on boards that can
2907  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
2908  * make host resumes and VBUS detection trigger OMAP wakeup events; that
2909  * may involve talking to an external transceiver (e.g. isp1301).
2910  */
2911
2912 static int omap_udc_suspend(struct device *dev, pm_message_t message)
2913 {
2914         u32     devstat;
2915
2916         devstat = UDC_DEVSTAT_REG;
2917
2918         /* we're requesting 48 MHz clock if the pullup is enabled
2919          * (== we're attached to the host) and we're not suspended,
2920          * which would prevent entry to deep sleep...
2921          */
2922         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
2923                 WARN("session active; suspend requires disconnect\n");
2924                 omap_pullup(&udc->gadget, 0);
2925         }
2926
2927         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
2928         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
2929         return 0;
2930 }
2931
2932 static int omap_udc_resume(struct device *dev)
2933 {
2934         DBG("resume + wakeup/SRP\n");
2935         omap_pullup(&udc->gadget, 1);
2936
2937         /* maybe the host would enumerate us if we nudged it */
2938         msleep(100);
2939         return omap_wakeup(&udc->gadget);
2940 }
2941
2942 /*-------------------------------------------------------------------------*/
2943
2944 static struct device_driver udc_driver = {
2945         .name           = (char *) driver_name,
2946         .bus            = &platform_bus_type,
2947         .probe          = omap_udc_probe,
2948         .remove         = __exit_p(omap_udc_remove),
2949         .suspend        = omap_udc_suspend,
2950         .resume         = omap_udc_resume,
2951 };
2952
2953 static int __init udc_init(void)
2954 {
2955         INFO("%s, version: " DRIVER_VERSION
2956 #ifdef  USE_ISO
2957                 " (iso)"
2958 #endif
2959                 "%s\n", driver_desc,
2960                 use_dma ?  " (dma)" : "");
2961         return driver_register(&udc_driver);
2962 }
2963 module_init(udc_init);
2964
2965 static void __exit udc_exit(void)
2966 {
2967         driver_unregister(&udc_driver);
2968 }
2969 module_exit(udc_exit);
2970
2971 MODULE_DESCRIPTION(DRIVER_DESC);
2972 MODULE_LICENSE("GPL");
2973