2 * Freescale USB device/endpoint management registers
4 #ifndef __FSL_USB2_UDC_H
5 #define __FSL_USB2_UDC_H
7 /* ### define USB registers here
9 #define USB_MAX_CTRL_PAYLOAD 64
10 #define USB_DR_SYS_OFFSET 0x400
12 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
13 /* USB DR device mode registers (Little Endian) */
14 struct usb_dr_device {
15 /* Capability register */
17 u16 caplength; /* Capability Register Length */
18 u16 hciversion; /* Host Controller Interface Version */
19 u32 hcsparams; /* Host Controller Structural Parameters */
20 u32 hccparams; /* Host Controller Capability Parameters */
22 u32 dciversion; /* Device Controller Interface Version */
23 u32 dccparams; /* Device Controller Capability Parameters */
25 /* Operation register */
26 u32 usbcmd; /* USB Command Register */
27 u32 usbsts; /* USB Status Register */
28 u32 usbintr; /* USB Interrupt Enable Register */
29 u32 frindex; /* Frame Index Register */
31 u32 deviceaddr; /* Device Address */
32 u32 endpointlistaddr; /* Endpoint List Address Register */
34 u32 burstsize; /* Master Interface Data Burst Size Register */
35 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
37 u32 configflag; /* Configure Flag Register */
38 u32 portsc1; /* Port 1 Status and Control Register */
40 u32 otgsc; /* On-The-Go Status and Control */
41 u32 usbmode; /* USB Mode Register */
42 u32 endptsetupstat; /* Endpoint Setup Status Register */
43 u32 endpointprime; /* Endpoint Initialization Register */
44 u32 endptflush; /* Endpoint Flush Register */
45 u32 endptstatus; /* Endpoint Status Register */
46 u32 endptcomplete; /* Endpoint Complete Register */
47 u32 endptctrl[6]; /* Endpoint Control Registers */
50 /* USB DR host mode registers (Little Endian) */
52 /* Capability register */
54 u16 caplength; /* Capability Register Length */
55 u16 hciversion; /* Host Controller Interface Version */
56 u32 hcsparams; /* Host Controller Structural Parameters */
57 u32 hccparams; /* Host Controller Capability Parameters */
59 u32 dciversion; /* Device Controller Interface Version */
60 u32 dccparams; /* Device Controller Capability Parameters */
62 /* Operation register */
63 u32 usbcmd; /* USB Command Register */
64 u32 usbsts; /* USB Status Register */
65 u32 usbintr; /* USB Interrupt Enable Register */
66 u32 frindex; /* Frame Index Register */
68 u32 periodiclistbase; /* Periodic Frame List Base Address Register */
69 u32 asynclistaddr; /* Current Asynchronous List Address Register */
71 u32 burstsize; /* Master Interface Data Burst Size Register */
72 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
74 u32 configflag; /* Configure Flag Register */
75 u32 portsc1; /* Port 1 Status and Control Register */
77 u32 otgsc; /* On-The-Go Status and Control */
78 u32 usbmode; /* USB Mode Register */
79 u32 endptsetupstat; /* Endpoint Setup Status Register */
80 u32 endpointprime; /* Endpoint Initialization Register */
81 u32 endptflush; /* Endpoint Flush Register */
82 u32 endptstatus; /* Endpoint Status Register */
83 u32 endptcomplete; /* Endpoint Complete Register */
84 u32 endptctrl[6]; /* Endpoint Control Registers */
88 * Following changes have been done in tegra3 USB regs:
89 * 1. Registers usbcmd to portsc1 have been shifted up by 16 bytes.
90 * 2. Registers otgsc and usbmode have been shifted down by 80 bytes.
91 * 3. hostpc1devlc register has been added at offset 0x1b4(436).
92 * 4. Registers endptsetupstat to endptctrl have shifted down by 92 bytes.
95 /* USB DR device mode registers (Little Endian) */
96 struct usb_dr_device {
97 /* Capability register */
99 u16 caplength; /* Capability Register Length */
100 u16 hciversion; /* Host Controller Interface Version */
101 u32 hcsparams; /* Host Controller Structual Parameters */
102 u32 hccparams; /* Host Controller Capability Parameters */
104 u32 dciversion; /* Device Controller Interface Version */
105 u32 dccparams; /* Device Controller Capability Parameters */
107 /* Operation register */
108 u32 usbcmd; /* USB Command Register */
109 u32 usbsts; /* USB Status Register */
110 u32 usbintr; /* USB Interrupt Enable Register */
111 u32 frindex; /* Frame Index Register */
113 u32 deviceaddr; /* Device Address */
114 u32 endpointlistaddr; /* Endpoint List Address Register */
116 u32 burstsize; /* Master Interface Data Burst Size Register */
117 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
119 u32 configflag; /* Configure Flag Register */
120 u32 portsc1; /* Port 1 Status and Control Register */
122 u32 hostpc1devlc; /* Usb LPM Behavior and Control Register */
124 u32 otgsc; /* On-The-Go Status and Control */
125 u32 usbmode; /* USB Mode Register */
127 u32 endptsetupstat; /* Endpoint Setup Status Register */
128 u32 endpointprime; /* Endpoint Initialization Register */
129 u32 endptflush; /* Endpoint Flush Register */
130 u32 endptstatus; /* Endpoint Status Register */
131 u32 endptcomplete; /* Endpoint Complete Register */
132 u32 endptctrl[6]; /* Endpoint Control Registers */
135 /* USB DR host mode registers (Little Endian) */
137 /* Capability register */
139 u16 caplength; /* Capability Register Length */
140 u16 hciversion; /* Host Controller Interface Version */
141 u32 hcsparams; /* Host Controller Structual Parameters */
142 u32 hccparams; /* Host Controller Capability Parameters */
144 u32 dciversion; /* Device Controller Interface Version */
145 u32 dccparams; /* Device Controller Capability Parameters */
147 /* Operation register */
148 u32 usbcmd; /* USB Command Register */
149 u32 usbsts; /* USB Status Register */
150 u32 usbintr; /* USB Interrupt Enable Register */
151 u32 frindex; /* Frame Index Register */
153 u32 periodiclistbase; /* Periodic Frame List Base Address Register */
154 u32 asynclistaddr; /* Current Asynchronous List Address Register */
156 u32 burstsize; /* Master Interface Data Burst Size Register */
157 u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
159 u32 configflag; /* Configure Flag Register */
160 u32 portsc1; /* Port 1 Status and Control Register */
162 u32 hostpc1devlc; /* Usb LPM Behavior and Control Register */
164 u32 otgsc; /* On-The-Go Status and Control */
165 u32 usbmode; /* USB Mode Register */
167 u32 endptsetupstat; /* Endpoint Setup Status Register */
168 u32 endpointprime; /* Endpoint Initialization Register */
169 u32 endptflush; /* Endpoint Flush Register */
170 u32 endptstatus; /* Endpoint Status Register */
171 u32 endptcomplete; /* Endpoint Complete Register */
172 u32 endptctrl[6]; /* Endpoint Control Registers */
174 #endif // ifdef CONFIG_ARCH_TEGRA_2x_SOC
176 /* non-EHCI USB system interface registers (Big Endian) */
177 #ifdef CONFIG_ARCH_TEGRA
178 struct usb_sys_interface {
186 struct usb_sys_interface {
189 u32 age_cnt_thresh; /* Age Count Threshold Register */
190 u32 pri_ctrl; /* Priority Control Register */
191 u32 si_ctrl; /* System Interface Control Register */
193 u32 control; /* General Purpose Control Register */
197 /* ep0 transfer state */
198 #define WAIT_FOR_SETUP 0
199 #define DATA_STATE_XMIT 1
200 #define DATA_STATE_NEED_ZLP 2
201 #define WAIT_FOR_OUT_STATUS 3
202 #define DATA_STATE_RECV 4
204 /* Device Controller Capability Parameter register */
205 #define DCCPARAMS_DC 0x00000080
206 #define DCCPARAMS_DEN_MASK 0x0000001f
208 /* Frame Index Register Bit Masks */
209 #define USB_FRINDEX_MASKS 0x3fff
210 /* USB CMD Register Bit Masks */
211 #define USB_CMD_RUN_STOP 0x00000001
212 #define USB_CMD_CTRL_RESET 0x00000002
213 #define USB_CMD_PERIODIC_SCHEDULE_EN 0x00000010
214 #define USB_CMD_ASYNC_SCHEDULE_EN 0x00000020
215 #define USB_CMD_INT_AA_DOORBELL 0x00000040
216 #define USB_CMD_ASP 0x00000300
217 #define USB_CMD_ASYNC_SCH_PARK_EN 0x00000800
218 #define USB_CMD_SUTW 0x00002000
219 #define USB_CMD_ATDTW 0x00004000
220 #define USB_CMD_ITC 0x00FF0000
222 /* bit 15,3,2 are frame list size */
223 #define USB_CMD_FRAME_SIZE_1024 0x00000000
224 #define USB_CMD_FRAME_SIZE_512 0x00000004
225 #define USB_CMD_FRAME_SIZE_256 0x00000008
226 #define USB_CMD_FRAME_SIZE_128 0x0000000C
227 #define USB_CMD_FRAME_SIZE_64 0x00008000
228 #define USB_CMD_FRAME_SIZE_32 0x00008004
229 #define USB_CMD_FRAME_SIZE_16 0x00008008
230 #define USB_CMD_FRAME_SIZE_8 0x0000800C
232 /* bit 9-8 are async schedule park mode count */
233 #define USB_CMD_ASP_00 0x00000000
234 #define USB_CMD_ASP_01 0x00000100
235 #define USB_CMD_ASP_10 0x00000200
236 #define USB_CMD_ASP_11 0x00000300
237 #define USB_CMD_ASP_BIT_POS 8
239 /* bit 23-16 are interrupt threshold control */
240 #define USB_CMD_ITC_NO_THRESHOLD 0x00000000
241 #define USB_CMD_ITC_1_MICRO_FRM 0x00010000
242 #define USB_CMD_ITC_2_MICRO_FRM 0x00020000
243 #define USB_CMD_ITC_4_MICRO_FRM 0x00040000
244 #define USB_CMD_ITC_8_MICRO_FRM 0x00080000
245 #define USB_CMD_ITC_16_MICRO_FRM 0x00100000
246 #define USB_CMD_ITC_32_MICRO_FRM 0x00200000
247 #define USB_CMD_ITC_64_MICRO_FRM 0x00400000
248 #define USB_CMD_ITC_BIT_POS 16
250 /* USB STS Register Bit Masks */
251 #define USB_STS_INT 0x00000001
252 #define USB_STS_ERR 0x00000002
253 #define USB_STS_PORT_CHANGE 0x00000004
254 #define USB_STS_FRM_LST_ROLL 0x00000008
255 #define USB_STS_SYS_ERR 0x00000010
256 #define USB_STS_IAA 0x00000020
257 #define USB_STS_RESET 0x00000040
258 #define USB_STS_SOF 0x00000080
259 #define USB_STS_SUSPEND 0x00000100
260 #define USB_STS_HC_HALTED 0x00001000
261 #define USB_STS_RCL 0x00002000
262 #define USB_STS_PERIODIC_SCHEDULE 0x00004000
263 #define USB_STS_ASYNC_SCHEDULE 0x00008000
265 /* USB INTR Register Bit Masks */
266 #define USB_INTR_INT_EN 0x00000001
267 #define USB_INTR_ERR_INT_EN 0x00000002
268 #define USB_INTR_PTC_DETECT_EN 0x00000004
269 #define USB_INTR_FRM_LST_ROLL_EN 0x00000008
270 #define USB_INTR_SYS_ERR_EN 0x00000010
271 #define USB_INTR_ASYN_ADV_EN 0x00000020
272 #define USB_INTR_RESET_EN 0x00000040
273 #define USB_INTR_SOF_EN 0x00000080
274 #define USB_INTR_DEVICE_SUSPEND 0x00000100
276 /* Device Address bit masks */
277 #define USB_DEVICE_ADDRESS_MASK 0xFE000000
278 #define USB_DEVICE_ADDRESS_BIT_POS 25
280 /* endpoint list address bit masks */
281 #define USB_EP_LIST_ADDRESS_MASK 0xfffff800
283 /* PORTSCX Register Bit Masks */
284 #define PORTSCX_CURRENT_CONNECT_STATUS 0x00000001
285 #define PORTSCX_CONNECT_STATUS_CHANGE 0x00000002
286 #define PORTSCX_PORT_ENABLE 0x00000004
287 #define PORTSCX_PORT_EN_DIS_CHANGE 0x00000008
288 #define PORTSCX_OVER_CURRENT_ACT 0x00000010
289 #define PORTSCX_OVER_CURRENT_CHG 0x00000020
290 #define PORTSCX_PORT_FORCE_RESUME 0x00000040
291 #define PORTSCX_PORT_SUSPEND 0x00000080
292 #define PORTSCX_PORT_RESET 0x00000100
293 #define PORTSCX_LINE_STATUS_BITS 0x00000C00
294 #define PORTSCX_PORT_POWER 0x00001000
295 #define PORTSCX_PORT_INDICTOR_CTRL 0x0000C000
296 #define PORTSCX_PORT_TEST_CTRL 0x000F0000
297 #define PORTSCX_WAKE_ON_CONNECT_EN 0x00100000
298 #define PORTSCX_WAKE_ON_CONNECT_DIS 0x00200000
299 #define PORTSCX_WAKE_ON_OVER_CURRENT 0x00400000
300 #define PORTSCX_PHY_LOW_POWER_SPD 0x00800000
302 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
303 #define PORTSCX_PORT_FORCE_FULL_SPEED 0x01000000
304 #define PORTSCX_PORT_SPEED_MASK 0x0C000000
305 #define PORTSCX_PORT_WIDTH 0x10000000
306 #define PORTSCX_PHY_TYPE_SEL 0xC0000000
308 /* bit 27-26 are port speed */
309 #define PORTSCX_PORT_SPEED_FULL 0x00000000
310 #define PORTSCX_PORT_SPEED_LOW 0x04000000
311 #define PORTSCX_PORT_SPEED_HIGH 0x08000000
312 #define PORTSCX_PORT_SPEED_UNDEF 0x0C000000
313 #define PORTSCX_SPEED_BIT_POS 26
315 /* bit 28 is parallel transceiver width for UTMI interface */
316 #define PORTSCX_PTW 0x10000000
317 #define PORTSCX_PTW_8BIT 0x00000000
318 #define PORTSCX_PTW_16BIT 0x10000000
320 /* bit 31-30 are port transceiver select */
321 #define PORTSCX_PTS_UTMI 0x00000000
322 #define PORTSCX_PTS_ULPI 0x80000000
323 #define PORTSCX_PTS_FSLS 0xC0000000
324 #define PORTSCX_PTS_BIT_POS 30
326 /* In tegra3 the following fields have moved to new HOSTPC1_DEVLC reg and
327 * their offsets have changed.
328 * Keeping the name of bit masks same as before (PORTSCX_*) to have
329 * minimum changes to code */
330 #define PORTSCX_PORT_FORCE_FULL_SPEED 0x00800000
331 #define PORTSCX_PORT_SPEED_MASK 0x06000000
332 #define PORTSCX_PORT_WIDTH 0x08000000
333 #define PORTSCX_PHY_TYPE_SEL 0xE0000000
335 /* bit 26-25 are port speed */
336 #define PORTSCX_PORT_SPEED_FULL 0x00000000
337 #define PORTSCX_PORT_SPEED_LOW 0x02000000
338 #define PORTSCX_PORT_SPEED_HIGH 0x04000000
339 #define PORTSCX_PORT_SPEED_UNDEF 0x06000000
340 #define PORTSCX_SPEED_BIT_POS 25
342 /* bit 27 is parallel transceiver width for UTMI interface */
343 #define PORTSCX_PTW 0x08000000
344 #define PORTSCX_PTW_8BIT 0x00000000
345 #define PORTSCX_PTW_16BIT 0x08000000
347 /* bit 31-29 are port transceiver select */
348 #define PORTSCX_PTS_UTMI 0x00000000
349 #define PORTSCX_PTS_ULPI 0x40000000
350 #define PORTSCX_PTS_FSLS 0x60000000
351 #define PORTSCX_PTS_BIT_POS 29
354 /* bit 11-10 are line status */
355 #define PORTSCX_LINE_STATUS_SE0 0x00000000
356 #define PORTSCX_LINE_STATUS_JSTATE 0x00000400
357 #define PORTSCX_LINE_STATUS_KSTATE 0x00000800
358 #define PORTSCX_LINE_STATUS_UNDEF 0x00000C00
359 #define PORTSCX_LINE_STATUS_BIT_POS 10
361 /* bit 15-14 are port indicator control */
362 #define PORTSCX_PIC_OFF 0x00000000
363 #define PORTSCX_PIC_AMBER 0x00004000
364 #define PORTSCX_PIC_GREEN 0x00008000
365 #define PORTSCX_PIC_UNDEF 0x0000C000
366 #define PORTSCX_PIC_BIT_POS 14
368 /* bit 19-16 are port test control */
369 #define PORTSCX_PTC_DISABLE 0x00000000
370 #define PORTSCX_PTC_JSTATE 0x00010000
371 #define PORTSCX_PTC_KSTATE 0x00020000
372 #define PORTSCX_PTC_SEQNAK 0x00030000
373 #define PORTSCX_PTC_PACKET 0x00040000
374 #define PORTSCX_PTC_FORCE_EN 0x00050000
375 #define PORTSCX_PTC_BIT_POS 16
377 /* otgsc Register Bit Masks */
378 #define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001
379 #define OTGSC_CTRL_VUSB_CHARGE 0x00000002
380 #define OTGSC_CTRL_OTG_TERM 0x00000008
381 #define OTGSC_CTRL_DATA_PULSING 0x00000010
382 #define OTGSC_STS_USB_ID 0x00000100
383 #define OTGSC_STS_A_VBUS_VALID 0x00000200
384 #define OTGSC_STS_A_SESSION_VALID 0x00000400
385 #define OTGSC_STS_B_SESSION_VALID 0x00000800
386 #define OTGSC_STS_B_SESSION_END 0x00001000
387 #define OTGSC_STS_1MS_TOGGLE 0x00002000
388 #define OTGSC_STS_DATA_PULSING 0x00004000
389 #define OTGSC_INTSTS_USB_ID 0x00010000
390 #define OTGSC_INTSTS_A_VBUS_VALID 0x00020000
391 #define OTGSC_INTSTS_A_SESSION_VALID 0x00040000
392 #define OTGSC_INTSTS_B_SESSION_VALID 0x00080000
393 #define OTGSC_INTSTS_B_SESSION_END 0x00100000
394 #define OTGSC_INTSTS_1MS 0x00200000
395 #define OTGSC_INTSTS_DATA_PULSING 0x00400000
396 #define OTGSC_INTR_USB_ID 0x01000000
397 #define OTGSC_INTR_A_VBUS_VALID 0x02000000
398 #define OTGSC_INTR_A_SESSION_VALID 0x04000000
399 #define OTGSC_INTR_B_SESSION_VALID 0x08000000
400 #define OTGSC_INTR_B_SESSION_END 0x10000000
401 #define OTGSC_INTR_1MS_TIMER 0x20000000
402 #define OTGSC_INTR_DATA_PULSING 0x40000000
404 /* USB MODE Register Bit Masks */
405 #define USB_MODE_CTRL_MODE_IDLE 0x00000000
406 #define USB_MODE_CTRL_MODE_DEVICE 0x00000002
407 #define USB_MODE_CTRL_MODE_HOST 0x00000003
408 #define USB_MODE_CTRL_MODE_MASK 0x00000003
409 #define USB_MODE_CTRL_MODE_RSV 0x00000001
410 #define USB_MODE_ES 0x00000004 /* Endian Select */
411 #define USB_MODE_SETUP_LOCK_OFF 0x00000008
412 #define USB_MODE_STREAM_DISABLE 0x00000010
413 /* Endpoint Flush Register */
414 #define EPFLUSH_TX_OFFSET 0x00010000
415 #define EPFLUSH_RX_OFFSET 0x00000000
417 /* Endpoint Setup Status bit masks */
418 #define EP_SETUP_STATUS_MASK 0x0000003F
419 #define EP_SETUP_STATUS_EP0 0x00000001
421 /* ENDPOINTCTRLx Register Bit Masks */
422 #define EPCTRL_TX_ENABLE 0x00800000
423 #define EPCTRL_TX_DATA_TOGGLE_RST 0x00400000 /* Not EP0 */
424 #define EPCTRL_TX_DATA_TOGGLE_INH 0x00200000 /* Not EP0 */
425 #define EPCTRL_TX_TYPE 0x000C0000
426 #define EPCTRL_TX_DATA_SOURCE 0x00020000 /* Not EP0 */
427 #define EPCTRL_TX_EP_STALL 0x00010000
428 #define EPCTRL_RX_ENABLE 0x00000080
429 #define EPCTRL_RX_DATA_TOGGLE_RST 0x00000040 /* Not EP0 */
430 #define EPCTRL_RX_DATA_TOGGLE_INH 0x00000020 /* Not EP0 */
431 #define EPCTRL_RX_TYPE 0x0000000C
432 #define EPCTRL_RX_DATA_SINK 0x00000002 /* Not EP0 */
433 #define EPCTRL_RX_EP_STALL 0x00000001
435 /* bit 19-18 and 3-2 are endpoint type */
436 #define EPCTRL_EP_TYPE_CONTROL 0
437 #define EPCTRL_EP_TYPE_ISO 1
438 #define EPCTRL_EP_TYPE_BULK 2
439 #define EPCTRL_EP_TYPE_INTERRUPT 3
440 #define EPCTRL_TX_EP_TYPE_SHIFT 18
441 #define EPCTRL_RX_EP_TYPE_SHIFT 2
443 /* SNOOPn Register Bit Masks */
444 #define SNOOP_ADDRESS_MASK 0xFFFFF000
445 #define SNOOP_SIZE_ZERO 0x00 /* snooping disable */
446 #define SNOOP_SIZE_4KB 0x0B /* 4KB snoop size */
447 #define SNOOP_SIZE_8KB 0x0C
448 #define SNOOP_SIZE_16KB 0x0D
449 #define SNOOP_SIZE_32KB 0x0E
450 #define SNOOP_SIZE_64KB 0x0F
451 #define SNOOP_SIZE_128KB 0x10
452 #define SNOOP_SIZE_256KB 0x11
453 #define SNOOP_SIZE_512KB 0x12
454 #define SNOOP_SIZE_1MB 0x13
455 #define SNOOP_SIZE_2MB 0x14
456 #define SNOOP_SIZE_4MB 0x15
457 #define SNOOP_SIZE_8MB 0x16
458 #define SNOOP_SIZE_16MB 0x17
459 #define SNOOP_SIZE_32MB 0x18
460 #define SNOOP_SIZE_64MB 0x19
461 #define SNOOP_SIZE_128MB 0x1A
462 #define SNOOP_SIZE_256MB 0x1B
463 #define SNOOP_SIZE_512MB 0x1C
464 #define SNOOP_SIZE_1GB 0x1D
465 #define SNOOP_SIZE_2GB 0x1E /* 2GB snoop size */
467 /* pri_ctrl Register Bit Masks */
468 #define PRI_CTRL_PRI_LVL1 0x0000000C
469 #define PRI_CTRL_PRI_LVL0 0x00000003
471 /* si_ctrl Register Bit Masks */
472 #define SI_CTRL_ERR_DISABLE 0x00000010
473 #define SI_CTRL_IDRC_DISABLE 0x00000008
474 #define SI_CTRL_RD_SAFE_EN 0x00000004
475 #define SI_CTRL_RD_PREFETCH_DISABLE 0x00000002
476 #define SI_CTRL_RD_PREFEFETCH_VAL 0x00000001
478 /* control Register Bit Masks */
479 #define USB_CTRL_IOENB 0x00000004
480 #define USB_CTRL_ULPI_INT0EN 0x00000001
482 /* Endpoint Queue Head data struct
483 * Rem: all the variables of qh are LittleEndian Mode
484 * and NEXT_POINTER_MASK should operate on a LittleEndian, Phy Addr
486 struct ep_queue_head {
487 u32 max_pkt_length; /* Mult(31-30) , Zlt(29) , Max Pkt len
489 u32 curr_dtd_ptr; /* Current dTD Pointer(31-5) */
490 u32 next_dtd_ptr; /* Next dTD Pointer(31-5), T(0) */
491 u32 size_ioc_int_sts; /* Total bytes (30-16), IOC (15),
492 MultO(11-10), STS (7-0) */
493 u32 buff_ptr0; /* Buffer pointer Page 0 (31-12) */
494 u32 buff_ptr1; /* Buffer pointer Page 1 (31-12) */
495 u32 buff_ptr2; /* Buffer pointer Page 2 (31-12) */
496 u32 buff_ptr3; /* Buffer pointer Page 3 (31-12) */
497 u32 buff_ptr4; /* Buffer pointer Page 4 (31-12) */
499 u8 setup_buffer[8]; /* Setup data 8 bytes */
503 /* Endpoint Queue Head Bit Masks */
504 #define EP_QUEUE_HEAD_MULT_POS 30
505 #define EP_QUEUE_HEAD_ZLT_SEL 0x20000000
506 #define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16
507 #define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff)
508 #define EP_QUEUE_HEAD_IOS 0x00008000
509 #define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001
510 #define EP_QUEUE_HEAD_IOC 0x00008000
511 #define EP_QUEUE_HEAD_MULTO 0x00000C00
512 #define EP_QUEUE_HEAD_STATUS_HALT 0x00000040
513 #define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080
514 #define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF
515 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0
516 #define EP_QUEUE_FRINDEX_MASK 0x000007FF
517 #define EP_MAX_LENGTH_TRANSFER 0x4000
519 /* Endpoint Transfer Descriptor data struct */
520 /* Rem: all the variables of td are LittleEndian Mode */
521 struct ep_td_struct {
522 u32 next_td_ptr; /* Next TD pointer(31-5), T(0) set
524 u32 size_ioc_sts; /* Total bytes (30-16), IOC (15),
525 MultO(11-10), STS (7-0) */
526 u32 buff_ptr0; /* Buffer pointer Page 0 */
527 u32 buff_ptr1; /* Buffer pointer Page 1 */
528 u32 buff_ptr2; /* Buffer pointer Page 2 */
529 u32 buff_ptr3; /* Buffer pointer Page 3 */
530 u32 buff_ptr4; /* Buffer pointer Page 4 */
533 dma_addr_t td_dma; /* dma address for this td */
534 /* virtual address of next td specified in next_td_ptr */
535 struct ep_td_struct *next_td_virt;
538 /* Endpoint Transfer Descriptor bit Masks */
539 #define DTD_NEXT_TERMINATE 0x00000001
540 #define DTD_IOC 0x00008000
541 #define DTD_STATUS_ACTIVE 0x00000080
542 #define DTD_STATUS_HALTED 0x00000040
543 #define DTD_STATUS_DATA_BUFF_ERR 0x00000020
544 #define DTD_STATUS_TRANSACTION_ERR 0x00000008
545 #define DTD_RESERVED_FIELDS 0x80007300
546 #define DTD_ADDR_MASK 0xFFFFFFE0
547 #define DTD_PACKET_SIZE 0x7FFF0000
548 #define DTD_LENGTH_BIT_POS 16
549 #define DTD_ERROR_MASK (DTD_STATUS_HALTED | \
550 DTD_STATUS_DATA_BUFF_ERR | \
551 DTD_STATUS_TRANSACTION_ERR)
552 /* Alignment requirements; must be a power of two */
553 #if defined(CONFIG_ARCH_TEGRA)
554 #define DTD_ALIGNMENT 0x80
556 #define DTD_ALIGNMENT 0x20
558 #define QH_ALIGNMENT 2048
559 #define QH_OFFSET 0x1000
561 /* Controller dma boundary */
562 #define UDC_DMA_BOUNDARY 0x1000
564 #define USB_SYS_VBUS_ASESSION_INT_EN 0x10000
565 #define USB_SYS_VBUS_ASESSION_CHANGED 0x20000
566 #define USB_SYS_VBUS_ASESSION 0x40000
567 #define USB_SYS_VBUS_WAKEUP_ENABLE 0x40000000
568 #define USB_SYS_VBUS_WAKEUP_INT_ENABLE 0x100
569 #define USB_SYS_VBUS_WAKEUP_INT_STATUS 0x200
570 #define USB_SYS_VBUS_STATUS 0x400
571 #define USB_SYS_ID_PIN_STATUS (0x4)
572 /*-------------------------------------------------------------------------*/
574 /* ### driver private data
577 struct usb_request req;
578 struct list_head queue;
579 /* ep_queue() func will add
580 a request->queue into a udc_ep->queue 'd tail */
584 struct ep_td_struct *head, *tail; /* For dTD List
585 cpu endian Virtual addr */
586 unsigned int dtd_count;
589 #define REQ_UNCOMPLETE 1
593 struct list_head queue;
595 struct ep_queue_head *qh;
596 const struct usb_endpoint_descriptor *desc;
597 struct usb_gadget *gadget;
607 struct usb_gadget gadget;
608 struct usb_gadget_driver *driver;
609 struct fsl_usb2_platform_data *pdata;
610 struct completion *done; /* to make sure release() is done */
615 struct usb_ctrlrequest local_setup_buff;
617 struct otg_transceiver *transceiver;
618 unsigned softconnect:1;
619 unsigned vbus_active:1;
621 unsigned remote_wakeup:1;
622 unsigned already_stopped:1;
623 unsigned big_endian_desc:1;
625 struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */
626 struct fsl_req *status_req; /* ep0 status request */
627 struct dma_pool *td_pool; /* dma pool for DTD */
628 enum fsl_usb2_phy_modes phy_mode;
630 size_t ep_qh_size; /* size after alignment adjustment*/
631 dma_addr_t ep_qh_dma; /* dma address of QH */
633 u32 max_pipes; /* Device max pipes */
634 u32 bus_reset; /* Device is bus resetting */
635 u32 resume_state; /* USB state to resume */
636 u32 usb_state; /* USB current state */
637 u32 ep0_state; /* Endpoint zero state */
638 u32 ep0_dir; /* Endpoint zero direction: can be
639 USB_DIR_IN or USB_DIR_OUT */
640 u8 device_address; /* Device USB address */
641 struct delayed_work work; /* delayed work for charger detection */
642 struct regulator *vbus_regulator; /* regulator for drawing VBUS */
645 /*-------------------------------------------------------------------------*/
648 #define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt "\n", \
651 #define DBG(fmt, args...) do{}while(0)
655 static void dump_msg(const char *label, const u8 * buf, unsigned int length)
657 unsigned int start, num, i;
662 DBG("%s, length %u:\n", label, length);
665 num = min(length, 16u);
667 for (i = 0; i < num; ++i) {
670 sprintf(p, " %02x", buf[i]);
674 printk(KERN_DEBUG "%6x: %s\n", start, line);
685 #define VDBG(stuff...) do{}while(0)
688 #define ERR(stuff...) pr_err("udc: " stuff)
689 #define WARNING(stuff...) pr_warning("udc: " stuff)
690 #define INFO(stuff...) pr_info("udc: " stuff)
692 /*-------------------------------------------------------------------------*/
694 /* ### Add board specific defines here
698 * ### pipe direction macro from device view
700 #define USB_RECV 0 /* OUT EP */
701 #define USB_SEND 1 /* IN EP */
704 * ### internal used help routines.
706 #define ep_index(EP) ((EP)->desc->bEndpointAddress&0xF)
707 #define ep_maxpacket(EP) ((EP)->ep.maxpacket)
708 #define ep_is_in(EP) ( (ep_index(EP) == 0) ? (EP->udc->ep0_dir == \
709 USB_DIR_IN ):((EP)->desc->bEndpointAddress \
710 & USB_DIR_IN)==USB_DIR_IN)
711 #define get_ep_by_pipe(udc, pipe) ((pipe == 1)? &udc->eps[0]: \
713 #define get_pipe_by_windex(windex) ((windex & USB_ENDPOINT_NUMBER_MASK) \
714 * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
715 #define get_pipe_by_ep(EP) (ep_index(EP) * 2 + ep_is_in(EP))
717 struct platform_device;
718 #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_ARCH_TEGRA)
719 int fsl_udc_clk_init(struct platform_device *pdev);
720 void fsl_udc_clk_finalize(struct platform_device *pdev);
721 void fsl_udc_clk_release(void);
722 void fsl_udc_clk_suspend(bool is_dpd);
723 void fsl_udc_clk_resume(bool is_dpd);
724 void fsl_udc_clk_enable(void);
725 void fsl_udc_clk_disable(void);
726 bool fsl_udc_charger_detect(void);
728 static inline int fsl_udc_clk_init(struct platform_device *pdev)
732 static inline void fsl_udc_clk_finalize(struct platform_device *pdev)
735 static inline void fsl_udc_clk_release(void)
738 static inline void fsl_udc_clk_suspend(bool is_dpd)
741 static inline void fsl_udc_clk_resume(bool is_dpd)
744 void fsl_udc_clk_enable(void)
747 void fsl_udc_clk_disable(void)
750 static inline bool fsl_udc_charger_detect(void)