usb: gadget: fsl_udc: avoid can_pullup function in vbus_session
[linux-2.6.git] / drivers / usb / gadget / fsl_udc_core.c
1 /*
2  * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
3  * All rights reserved.
4  *
5  * Author: Li Yang <leoli@freescale.com>
6  *         Jiang Bo <tanya.jiang@freescale.com>
7  *
8  * Copyright (C) 2010-2011 NVIDIA Corporation
9  *
10  * Description:
11  * Freescale high-speed USB SOC DR module device controller driver.
12  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
13  * The driver is previously named as mpc_udc.  Based on bare board
14  * code from Dave Liu and Shlomi Gridish.
15  *
16  * This program is free software; you can redistribute  it and/or modify it
17  * under  the terms of  the GNU General  Public License as published by the
18  * Free Software Foundation;  either version 2 of the  License, or (at your
19  * option) any later version.
20  */
21
22 #undef VERBOSE
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/ioport.h>
27 #include <linux/types.h>
28 #include <linux/errno.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/proc_fs.h>
34 #include <linux/mm.h>
35 #include <linux/moduleparam.h>
36 #include <linux/device.h>
37 #include <linux/usb/ch9.h>
38 #include <linux/usb/gadget.h>
39 #include <linux/usb/otg.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/platform_device.h>
42 #include <linux/fsl_devices.h>
43 #include <linux/dmapool.h>
44 #include <linux/delay.h>
45 #include <linux/regulator/consumer.h>
46 #include <linux/workqueue.h>
47
48 #include <asm/byteorder.h>
49 #include <asm/io.h>
50 #include <asm/system.h>
51 #include <asm/unaligned.h>
52 #include <asm/dma.h>
53
54 #include "fsl_usb2_udc.h"
55
56 #ifdef CONFIG_ARCH_TEGRA
57 #define DRIVER_DESC     "NVidia Tegra High-Speed USB SOC Device Controller driver"
58 #else
59 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
60 #endif
61 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
62 #define DRIVER_VERSION  "Apr 20, 2007"
63
64 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
65
66 #ifdef CONFIG_ARCH_TEGRA
67 static const char driver_name[] = "fsl-tegra-udc";
68 #else
69 static const char driver_name[] = "fsl-usb2-udc";
70 #endif
71 static const char driver_desc[] = DRIVER_DESC;
72
73 static struct usb_dr_device *dr_regs;
74 #ifndef CONFIG_ARCH_MXC
75 static struct usb_sys_interface *usb_sys_regs;
76 #endif
77
78 /* Charger current limit=1800mA, as per the USB charger spec */
79 #define USB_CHARGING_CURRENT_LIMIT_MA 1800
80 /* 1 sec wait time for charger detection after vbus is detected */
81 #define USB_CHARGER_DETECTION_WAIT_TIME_MS 1000
82
83 /* it is initialized in probe()  */
84 static struct fsl_udc *udc_controller = NULL;
85
86 static const struct usb_endpoint_descriptor
87 fsl_ep0_desc = {
88         .bLength =              USB_DT_ENDPOINT_SIZE,
89         .bDescriptorType =      USB_DT_ENDPOINT,
90         .bEndpointAddress =     0,
91         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
92         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
93 };
94
95 static u32 *control_reg = NULL;
96 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
97 static int reset_queues(struct fsl_udc *udc);
98
99 #ifdef CONFIG_PPC32
100 /*
101  * On some SoCs, the USB controller registers can be big or little endian,
102  * depending on the version of the chip. In order to be able to run the
103  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
104  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
105  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
106  * call through those pointers. Platform code for SoCs that have BE USB
107  * registers should set pdata->big_endian_mmio flag.
108  *
109  * This also applies to controller-to-cpu accessors for the USB descriptors,
110  * since their endianness is also SoC dependant. Platform code for SoCs that
111  * have BE USB descriptors should set pdata->big_endian_desc flag.
112  */
113 static u32 _fsl_readl_be(const unsigned __iomem *p)
114 {
115         return in_be32(p);
116 }
117
118 static u32 _fsl_readl_le(const unsigned __iomem *p)
119 {
120         return in_le32(p);
121 }
122
123 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
124 {
125         out_be32(p, v);
126 }
127
128 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
129 {
130         out_le32(p, v);
131 }
132
133 static u32 (*_fsl_readl)(const unsigned __iomem *p);
134 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
135
136 #define fsl_readl(p)            (*_fsl_readl)((p))
137 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
138
139 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
140 {
141         if (pdata->big_endian_mmio) {
142                 _fsl_readl = _fsl_readl_be;
143                 _fsl_writel = _fsl_writel_be;
144         } else {
145                 _fsl_readl = _fsl_readl_le;
146                 _fsl_writel = _fsl_writel_le;
147         }
148 }
149
150 static inline u32 cpu_to_hc32(const u32 x)
151 {
152         return udc_controller->pdata->big_endian_desc
153                 ? (__force u32)cpu_to_be32(x)
154                 : (__force u32)cpu_to_le32(x);
155 }
156
157 static inline u32 hc32_to_cpu(const u32 x)
158 {
159         return udc_controller->pdata->big_endian_desc
160                 ? be32_to_cpu((__force __be32)x)
161                 : le32_to_cpu((__force __le32)x);
162 }
163 #else /* !CONFIG_PPC32 */
164 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
165
166 #define fsl_readl(addr)         readl(addr)
167 #define fsl_writel(val32, addr) writel(val32, addr)
168 #define cpu_to_hc32(x)          cpu_to_le32(x)
169 #define hc32_to_cpu(x)          le32_to_cpu(x)
170 #endif /* CONFIG_PPC32 */
171
172 /*
173  * High speed test mode packet(53 bytes).
174  * See USB 2.0 spec, section 7.1.20.
175  */
176 static const u8 fsl_udc_test_packet[53] = {
177         /* JKJKJKJK x9 */
178         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
179         /* JJKKJJKK x8 */
180         0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
181         /* JJJJKKKK x8 */
182         0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
183         /* JJJJJJJKKKKKKK x8 */
184         0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
185         /* JJJJJJJK x8 */
186         0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
187         /* JKKKKKKK x10, JK */
188         0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
189 };
190
191 /********************************************************************
192  *      Internal Used Function
193 ********************************************************************/
194 /*-----------------------------------------------------------------
195  * vbus_enabled() - checks vbus status
196  *--------------------------------------------------------------*/
197 static inline bool vbus_enabled(void)
198 {
199         bool status = false;
200 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
201         status = (fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS);
202 #else
203         /*On FPGA VBUS is detected through VBUS A Session instead of VBUS status. */
204         status = (fsl_readl(&usb_sys_regs->vbus_sensors) & USB_SYS_VBUS_ASESSION);
205 #endif
206         return status;
207 }
208
209 /*-----------------------------------------------------------------
210  * done() - retire a request; caller blocked irqs
211  * @status : request status to be set, only works when
212  *      request is still in progress.
213  *--------------------------------------------------------------*/
214 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
215 {
216         struct fsl_udc *udc = NULL;
217         unsigned char stopped = ep->stopped;
218         struct ep_td_struct *curr_td, *next_td;
219         int j;
220
221         udc = (struct fsl_udc *)ep->udc;
222         /* Removed the req from fsl_ep->queue */
223         list_del_init(&req->queue);
224
225         /* req.status should be set as -EINPROGRESS in ep_queue() */
226         if (req->req.status == -EINPROGRESS)
227                 req->req.status = status;
228         else
229                 status = req->req.status;
230
231         /* Free dtd for the request */
232         next_td = req->head;
233         for (j = 0; j < req->dtd_count; j++) {
234                 curr_td = next_td;
235                 if (j != req->dtd_count - 1) {
236                         next_td = curr_td->next_td_virt;
237                 }
238                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
239         }
240
241         if (req->mapped) {
242                 dma_unmap_single(ep->udc->gadget.dev.parent,
243                         req->req.dma, req->req.length,
244                         ep_is_in(ep)
245                                 ? DMA_TO_DEVICE
246                                 : DMA_FROM_DEVICE);
247                 req->req.dma = DMA_ADDR_INVALID;
248                 req->mapped = 0;
249         } else
250                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
251                         req->req.dma, req->req.length,
252                         ep_is_in(ep)
253                                 ? DMA_TO_DEVICE
254                                 : DMA_FROM_DEVICE);
255
256         if (status && (status != -ESHUTDOWN))
257                 VDBG("complete %s req %p stat %d len %u/%u",
258                         ep->ep.name, &req->req, status,
259                         req->req.actual, req->req.length);
260
261         ep->stopped = 1;
262
263         spin_unlock(&ep->udc->lock);
264         /* complete() is from gadget layer,
265          * eg fsg->bulk_in_complete() */
266         if (req->req.complete)
267                 req->req.complete(&ep->ep, &req->req);
268
269         spin_lock(&ep->udc->lock);
270         ep->stopped = stopped;
271 }
272
273 /*-----------------------------------------------------------------
274  * nuke(): delete all requests related to this ep
275  * called with spinlock held
276  *--------------------------------------------------------------*/
277 static void nuke(struct fsl_ep *ep, int status)
278 {
279         ep->stopped = 1;
280
281         /* Flush fifo */
282         fsl_ep_fifo_flush(&ep->ep);
283
284         /* Whether this eq has request linked */
285         while (!list_empty(&ep->queue)) {
286                 struct fsl_req *req = NULL;
287
288                 req = list_entry(ep->queue.next, struct fsl_req, queue);
289                 done(ep, req, status);
290         }
291 }
292
293 /*------------------------------------------------------------------
294         Internal Hardware related function
295  ------------------------------------------------------------------*/
296
297 #define FSL_UDC_RESET_TIMEOUT 1000
298 static int dr_controller_reset(struct fsl_udc *udc)
299 {
300         unsigned int tmp;
301         unsigned long timeout;
302
303         /* Stop and reset the usb controller */
304         tmp = fsl_readl(&dr_regs->usbcmd);
305         tmp &= ~USB_CMD_RUN_STOP;
306         fsl_writel(tmp, &dr_regs->usbcmd);
307
308         tmp = fsl_readl(&dr_regs->usbcmd);
309         tmp |= USB_CMD_CTRL_RESET;
310         fsl_writel(tmp, &dr_regs->usbcmd);
311
312         /* Wait for reset to complete */
313         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
314         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
315                 if (time_after(jiffies, timeout)) {
316                         ERR("udc reset timeout!\n");
317                         return -ETIMEDOUT;
318                 }
319                 cpu_relax();
320         }
321         return 0;
322 }
323
324 static int dr_controller_setup(struct fsl_udc *udc)
325 {
326         unsigned int tmp, portctrl, ep_num;
327         unsigned int max_no_of_ep;
328 #if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
329         unsigned int ctrl;
330 #endif
331 #ifdef CONFIG_ARCH_TEGRA
332         unsigned long timeout;
333 #endif
334         int status;
335
336         /* Config PHY interface */
337         portctrl = fsl_readl(control_reg);
338         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
339         switch (udc->phy_mode) {
340         case FSL_USB2_PHY_ULPI:
341                 portctrl |= PORTSCX_PTS_ULPI;
342                 break;
343         case FSL_USB2_PHY_UTMI_WIDE:
344                 portctrl |= PORTSCX_PTW_16BIT;
345                 /* fall through */
346         case FSL_USB2_PHY_UTMI:
347                 portctrl |= PORTSCX_PTS_UTMI;
348                 break;
349         case FSL_USB2_PHY_SERIAL:
350                 portctrl |= PORTSCX_PTS_FSLS;
351                 break;
352         default:
353                 return -EINVAL;
354         }
355         fsl_writel(portctrl, control_reg);
356
357         status = dr_controller_reset(udc);
358         if (status)
359                 return status;
360
361         /* Set the controller as device mode */
362         tmp = fsl_readl(&dr_regs->usbmode);
363         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
364         tmp |= USB_MODE_CTRL_MODE_DEVICE;
365         /* Disable Setup Lockout */
366         tmp |= USB_MODE_SETUP_LOCK_OFF;
367         if (udc->pdata->es)
368                 tmp |= USB_MODE_ES;
369         fsl_writel(tmp, &dr_regs->usbmode);
370
371 #ifdef CONFIG_ARCH_TEGRA
372         /* Wait for controller to switch to device mode */
373         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
374         while ((fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_DEVICE) !=
375                USB_MODE_CTRL_MODE_DEVICE) {
376                 if (time_after(jiffies, timeout)) {
377                         ERR("udc device mode setup timeout!\n");
378                         return -ETIMEDOUT;
379                 }
380                 cpu_relax();
381         }
382 #endif
383
384         /* Clear the setup status */
385         fsl_writel(0, &dr_regs->usbsts);
386
387         tmp = udc->ep_qh_dma;
388         tmp &= USB_EP_LIST_ADDRESS_MASK;
389         fsl_writel(tmp, &dr_regs->endpointlistaddr);
390
391         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
392                 udc->ep_qh, (int)tmp,
393                 fsl_readl(&dr_regs->endpointlistaddr));
394
395         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
396         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
397                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
398                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
399                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
400                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
401                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
402         }
403         /* Config control enable i/o output, cpu endian register */
404 #if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
405         if (udc->pdata->have_sysif_regs) {
406                 ctrl = __raw_readl(&usb_sys_regs->control);
407                 ctrl |= USB_CTRL_IOENB;
408                 __raw_writel(ctrl, &usb_sys_regs->control);
409         }
410 #endif
411
412 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
413         /* Turn on cache snooping hardware, since some PowerPC platforms
414          * wholly rely on hardware to deal with cache coherent. */
415
416         if (udc->pdata->have_sysif_regs) {
417                 /* Setup Snooping for all the 4GB space */
418                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
419                 __raw_writel(tmp, &usb_sys_regs->snoop1);
420                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
421                 __raw_writel(tmp, &usb_sys_regs->snoop2);
422         }
423 #endif
424
425         return 0;
426 }
427
428 /* Enable DR irq and set controller to run state */
429 static void dr_controller_run(struct fsl_udc *udc)
430 {
431         u32 temp;
432 #ifdef CONFIG_ARCH_TEGRA
433         unsigned long timeout;
434 #define FSL_UDC_RUN_TIMEOUT 1000
435 #endif
436         /* Clear stopped bit */
437         udc->stopped = 0;
438
439 /* If OTG transceiver is available, then it handles the VBUS detection */
440         if (!udc_controller->transceiver) {
441 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
442                 /* Enable cable detection interrupt, without setting the
443                  * USB_SYS_VBUS_WAKEUP_INT bit. USB_SYS_VBUS_WAKEUP_INT is
444                  * clear on write */
445                 temp = fsl_readl(&usb_sys_regs->vbus_wakeup);
446                 temp |= (USB_SYS_VBUS_WAKEUP_INT_ENABLE | USB_SYS_VBUS_WAKEUP_ENABLE);
447                 temp &= ~USB_SYS_VBUS_WAKEUP_INT_STATUS;
448                 fsl_writel(temp, &usb_sys_regs->vbus_wakeup);
449 #else
450                 /*On FPGA VBUS is detected through VBUS A Session instead of VBUS
451                  * status. */
452                 temp = fsl_readl(&usb_sys_regs->vbus_sensors);
453                 temp |= USB_SYS_VBUS_ASESSION_INT_EN;
454                 temp &= ~USB_SYS_VBUS_ASESSION_CHANGED;
455                 fsl_writel(temp, &usb_sys_regs->vbus_sensors);
456 #endif
457         }
458         /* Enable DR irq reg */
459         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
460                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
461                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
462
463         fsl_writel(temp, &dr_regs->usbintr);
464
465         /* Set the controller as device mode */
466         temp = fsl_readl(&dr_regs->usbmode);
467         temp |= USB_MODE_CTRL_MODE_DEVICE;
468         fsl_writel(temp, &dr_regs->usbmode);
469
470         /* Set controller to Run */
471         temp = fsl_readl(&dr_regs->usbcmd);
472         temp |= USB_CMD_RUN_STOP;
473         fsl_writel(temp, &dr_regs->usbcmd);
474
475 #ifdef CONFIG_ARCH_TEGRA
476         /* Wait for controller to start */
477         timeout = jiffies + FSL_UDC_RUN_TIMEOUT;
478         while ((fsl_readl(&dr_regs->usbcmd) & USB_CMD_RUN_STOP) !=
479                USB_CMD_RUN_STOP) {
480                 if (time_after(jiffies, timeout)) {
481                         ERR("udc start timeout!\n");
482                         return;
483                 }
484                 cpu_relax();
485         }
486 #endif
487
488         return;
489 }
490
491 static void dr_controller_stop(struct fsl_udc *udc)
492 {
493         unsigned int tmp;
494
495         /* Clear pending interrupt status bits */
496         tmp = fsl_readl(&dr_regs->usbsts);
497         fsl_writel(tmp, &dr_regs->usbsts);
498
499         /* disable all INTR */
500         fsl_writel(0, &dr_regs->usbintr);
501
502         /* Set stopped bit for isr */
503         udc->stopped = 1;
504
505         /* disable IO output */
506 /*      usb_sys_regs->control = 0; */
507
508         /* set controller to Stop */
509         tmp = fsl_readl(&dr_regs->usbcmd);
510         tmp &= ~USB_CMD_RUN_STOP;
511         fsl_writel(tmp, &dr_regs->usbcmd);
512 }
513
514 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
515                         unsigned char ep_type)
516 {
517         unsigned int tmp_epctrl = 0;
518
519         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
520         if (dir) {
521                 if (ep_num)
522                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
523                 tmp_epctrl |= EPCTRL_TX_ENABLE;
524                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
525                 tmp_epctrl |= ((unsigned int)(ep_type)
526                                 << EPCTRL_TX_EP_TYPE_SHIFT);
527         } else {
528                 if (ep_num)
529                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
530                 tmp_epctrl |= EPCTRL_RX_ENABLE;
531                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
532                 tmp_epctrl |= ((unsigned int)(ep_type)
533                                 << EPCTRL_RX_EP_TYPE_SHIFT);
534         }
535
536         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
537 }
538
539 static void
540 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
541 {
542         u32 tmp_epctrl = 0;
543
544         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
545
546         if (value) {
547                 /* set the stall bit */
548                 if (dir)
549                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
550                 else
551                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
552         } else {
553                 /* clear the stall bit and reset data toggle */
554                 if (dir) {
555                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
556                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
557                 } else {
558                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
559                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
560                 }
561         }
562         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
563 }
564
565 /* Get stall status of a specific ep
566    Return: 0: not stalled; 1:stalled */
567 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
568 {
569         u32 epctrl;
570
571         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
572         if (dir)
573                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
574         else
575                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
576 }
577
578 /********************************************************************
579         Internal Structure Build up functions
580 ********************************************************************/
581
582 /*------------------------------------------------------------------
583 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
584  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
585  * @mult: Mult field
586  ------------------------------------------------------------------*/
587 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
588                 unsigned char dir, unsigned char ep_type,
589                 unsigned int max_pkt_len,
590                 unsigned int zlt, unsigned char mult)
591 {
592         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
593         unsigned int tmp = 0;
594
595         /* set the Endpoint Capabilites in QH */
596         switch (ep_type) {
597         case USB_ENDPOINT_XFER_CONTROL:
598                 /* Interrupt On Setup (IOS). for control ep  */
599                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
600                         | EP_QUEUE_HEAD_IOS;
601                 break;
602         case USB_ENDPOINT_XFER_ISOC:
603                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
604                         | (mult << EP_QUEUE_HEAD_MULT_POS);
605                 break;
606         case USB_ENDPOINT_XFER_BULK:
607         case USB_ENDPOINT_XFER_INT:
608                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
609                 break;
610         default:
611                 VDBG("error ep type is %d", ep_type);
612                 return;
613         }
614         if (zlt)
615                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
616
617         p_QH->max_pkt_length = cpu_to_hc32(tmp);
618         p_QH->next_dtd_ptr = 1;
619         p_QH->size_ioc_int_sts = 0;
620 }
621
622 /* Setup qh structure and ep register for ep0. */
623 static void ep0_setup(struct fsl_udc *udc)
624 {
625         /* the intialization of an ep includes: fields in QH, Regs,
626          * fsl_ep struct */
627         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
628                         USB_MAX_CTRL_PAYLOAD, 1, 0);
629         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
630                         USB_MAX_CTRL_PAYLOAD, 1, 0);
631         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
632         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
633
634         return;
635
636 }
637
638 /***********************************************************************
639                 Endpoint Management Functions
640 ***********************************************************************/
641
642 /*-------------------------------------------------------------------------
643  * when configurations are set, or when interface settings change
644  * for example the do_set_interface() in gadget layer,
645  * the driver will enable or disable the relevant endpoints
646  * ep0 doesn't use this routine. It is always enabled.
647 -------------------------------------------------------------------------*/
648 static int fsl_ep_enable(struct usb_ep *_ep,
649                 const struct usb_endpoint_descriptor *desc)
650 {
651         struct fsl_udc *udc = NULL;
652         struct fsl_ep *ep = NULL;
653         unsigned short max = 0;
654         unsigned char mult = 0, zlt;
655         int retval = -EINVAL;
656         unsigned long flags = 0;
657
658         ep = container_of(_ep, struct fsl_ep, ep);
659
660         /* catch various bogus parameters */
661         if (!_ep || !desc || ep->desc
662                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
663                 return -EINVAL;
664
665         udc = ep->udc;
666
667         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
668                 return -ESHUTDOWN;
669
670         max = le16_to_cpu(desc->wMaxPacketSize);
671
672         /* Disable automatic zlp generation.  Driver is responsible to indicate
673          * explicitly through req->req.zero.  This is needed to enable multi-td
674          * request. */
675         zlt = 1;
676
677         /* Assume the max packet size from gadget is always correct */
678         switch (desc->bmAttributes & 0x03) {
679         case USB_ENDPOINT_XFER_CONTROL:
680         case USB_ENDPOINT_XFER_BULK:
681         case USB_ENDPOINT_XFER_INT:
682                 /* mult = 0.  Execute N Transactions as demonstrated by
683                  * the USB variable length packet protocol where N is
684                  * computed using the Maximum Packet Length (dQH) and
685                  * the Total Bytes field (dTD) */
686                 mult = 0;
687                 break;
688         case USB_ENDPOINT_XFER_ISOC:
689                 /* Calculate transactions needed for high bandwidth iso */
690                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
691                 max = max & 0x7ff;      /* bit 0~10 */
692                 /* 3 transactions at most */
693                 if (mult > 3)
694                         goto en_done;
695                 break;
696         default:
697                 goto en_done;
698         }
699
700         spin_lock_irqsave(&udc->lock, flags);
701         ep->ep.maxpacket = max;
702         ep->desc = desc;
703         ep->stopped = 0;
704
705         /* Controller related setup */
706         /* Init EPx Queue Head (Ep Capabilites field in QH
707          * according to max, zlt, mult) */
708         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
709                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
710                                         ?  USB_SEND : USB_RECV),
711                         (unsigned char) (desc->bmAttributes
712                                         & USB_ENDPOINT_XFERTYPE_MASK),
713                         max, zlt, mult);
714
715         /* Init endpoint ctrl register */
716         dr_ep_setup((unsigned char) ep_index(ep),
717                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
718                                         ? USB_SEND : USB_RECV),
719                         (unsigned char) (desc->bmAttributes
720                                         & USB_ENDPOINT_XFERTYPE_MASK));
721
722         spin_unlock_irqrestore(&udc->lock, flags);
723         retval = 0;
724
725         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
726                         ep->desc->bEndpointAddress & 0x0f,
727                         (desc->bEndpointAddress & USB_DIR_IN)
728                                 ? "in" : "out", max);
729 en_done:
730         return retval;
731 }
732
733 /*---------------------------------------------------------------------
734  * @ep : the ep being unconfigured. May not be ep0
735  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
736 *---------------------------------------------------------------------*/
737 static int fsl_ep_disable(struct usb_ep *_ep)
738 {
739         struct fsl_udc *udc = NULL;
740         struct fsl_ep *ep = NULL;
741         unsigned long flags = 0;
742         u32 epctrl;
743         int ep_num;
744
745         ep = container_of(_ep, struct fsl_ep, ep);
746         if (!_ep || !ep->desc) {
747                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
748                 return -EINVAL;
749         }
750
751         /* disable ep on controller */
752         ep_num = ep_index(ep);
753 #if defined(CONFIG_ARCH_TEGRA)
754         /* Touch the registers if cable is connected and phy is on */
755         if (vbus_enabled())
756 #endif
757         {
758                 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
759                 if (ep_is_in(ep)) {
760                         epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
761                         epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
762                 } else {
763                         epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
764                         epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
765                 }
766                 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
767         }
768
769         udc = (struct fsl_udc *)ep->udc;
770         spin_lock_irqsave(&udc->lock, flags);
771
772         /* nuke all pending requests (does flush) */
773         nuke(ep, -ESHUTDOWN);
774
775         ep->desc = NULL;
776         ep->stopped = 1;
777         spin_unlock_irqrestore(&udc->lock, flags);
778
779         VDBG("disabled %s OK", _ep->name);
780         return 0;
781 }
782
783 /*---------------------------------------------------------------------
784  * allocate a request object used by this endpoint
785  * the main operation is to insert the req->queue to the eq->queue
786  * Returns the request, or null if one could not be allocated
787 *---------------------------------------------------------------------*/
788 static struct usb_request *
789 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
790 {
791         struct fsl_req *req = NULL;
792
793         req = kzalloc(sizeof *req, gfp_flags);
794         if (!req)
795                 return NULL;
796
797         req->req.dma = DMA_ADDR_INVALID;
798         INIT_LIST_HEAD(&req->queue);
799
800         return &req->req;
801 }
802
803 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
804 {
805         struct fsl_req *req = NULL;
806
807         req = container_of(_req, struct fsl_req, req);
808
809         if (_req)
810                 kfree(req);
811 }
812
813 /*-------------------------------------------------------------------------*/
814 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
815 {
816         int i = ep_index(ep) * 2 + ep_is_in(ep);
817         u32 temp, bitmask, tmp_stat;
818         struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
819
820         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
821         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
822
823         bitmask = ep_is_in(ep)
824                 ? (1 << (ep_index(ep) + 16))
825                 : (1 << (ep_index(ep)));
826
827         /* Flush all the dTD structs out to memory */
828         wmb();
829
830         /* check if the pipe is empty */
831         if (!(list_empty(&ep->queue))) {
832                 /* Add td to the end */
833                 struct fsl_req *lastreq;
834                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
835                 lastreq->tail->next_td_ptr =
836                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
837                 wmb();
838                 /* Read prime bit, if 1 goto done */
839                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
840                         goto out;
841
842                 do {
843                         /* Set ATDTW bit in USBCMD */
844                         temp = fsl_readl(&dr_regs->usbcmd);
845                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
846
847                         /* Read correct status bit */
848                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
849
850                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
851
852                 /* Write ATDTW bit to 0 */
853                 temp = fsl_readl(&dr_regs->usbcmd);
854                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
855
856                 if (tmp_stat)
857                         goto out;
858         }
859
860         /* Write dQH next pointer and terminate bit to 0 */
861         temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
862         dQH->next_dtd_ptr = cpu_to_hc32(temp);
863
864         /* Clear active and halt bit */
865         temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
866                         | EP_QUEUE_HEAD_STATUS_HALT));
867         dQH->size_ioc_int_sts &= temp;
868
869         /* Ensure that updates to the QH will occur before priming. */
870         wmb();
871
872         /* Prime endpoint by writing 1 to ENDPTPRIME */
873         temp = ep_is_in(ep)
874                 ? (1 << (ep_index(ep) + 16))
875                 : (1 << (ep_index(ep)));
876         fsl_writel(temp, &dr_regs->endpointprime);
877 out:
878         return;
879 }
880
881 /* Fill in the dTD structure
882  * @req: request that the transfer belongs to
883  * @length: return actually data length of the dTD
884  * @dma: return dma address of the dTD
885  * @is_last: return flag if it is the last dTD of the request
886  * return: pointer to the built dTD */
887 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
888                 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
889 {
890         u32 swap_temp;
891         struct ep_td_struct *dtd;
892
893         /* how big will this transfer be? */
894         *length = min(req->req.length - req->req.actual,
895                         (unsigned)EP_MAX_LENGTH_TRANSFER);
896
897         dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
898         if (dtd == NULL)
899                 return dtd;
900
901         dtd->td_dma = *dma;
902         /* Clear reserved field */
903         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
904         swap_temp &= ~DTD_RESERVED_FIELDS;
905         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
906
907         /* Init all of buffer page pointers */
908         swap_temp = (u32) (req->req.dma + req->req.actual);
909         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
910         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
911         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
912         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
913         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
914
915         req->req.actual += *length;
916
917         /* zlp is needed if req->req.zero is set */
918         if (req->req.zero) {
919                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
920                         *is_last = 1;
921                 else
922                         *is_last = 0;
923         } else if (req->req.length == req->req.actual)
924                 *is_last = 1;
925         else
926                 *is_last = 0;
927
928         if ((*is_last) == 0)
929                 VDBG("multi-dtd request!");
930         /* Fill in the transfer size; set active bit */
931         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
932
933         /* Enable interrupt for the last dtd of a request */
934         if (*is_last && !req->req.no_interrupt)
935                 swap_temp |= DTD_IOC;
936
937         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
938
939         mb();
940
941         VDBG("length = %d address= 0x%x", *length, (int)*dma);
942
943         return dtd;
944 }
945
946 /* Generate dtd chain for a request */
947 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
948 {
949         unsigned        count;
950         int             is_last;
951         int             is_first =1;
952         struct ep_td_struct     *last_dtd = NULL, *dtd;
953         dma_addr_t dma;
954
955         do {
956                 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
957                 if (dtd == NULL)
958                         return -ENOMEM;
959
960                 if (is_first) {
961                         is_first = 0;
962                         req->head = dtd;
963                 } else {
964                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
965                         last_dtd->next_td_virt = dtd;
966                 }
967                 last_dtd = dtd;
968
969                 req->dtd_count++;
970         } while (!is_last);
971
972         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
973
974         req->tail = dtd;
975
976         return 0;
977 }
978
979 /* queues (submits) an I/O request to an endpoint */
980 static int
981 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
982 {
983         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
984         struct fsl_req *req = container_of(_req, struct fsl_req, req);
985         struct fsl_udc *udc = ep->udc;
986         unsigned long flags;
987         enum dma_data_direction dir;
988         int status;
989
990         /* catch various bogus parameters */
991         if (!_req || !req->req.complete || !req->req.buf
992                         || !list_empty(&req->queue)) {
993                 VDBG("%s, bad params", __func__);
994                 return -EINVAL;
995         }
996
997         spin_lock_irqsave(&udc->lock, flags);
998
999         if (unlikely(!ep->desc)) {
1000                 VDBG("%s, bad ep", __func__);
1001                 spin_unlock_irqrestore(&udc->lock, flags);
1002                 return -EINVAL;
1003         }
1004
1005         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1006                 if (req->req.length > ep->ep.maxpacket) {
1007                         spin_unlock_irqrestore(&udc->lock, flags);
1008                         return -EMSGSIZE;
1009                 }
1010         }
1011
1012         dir = ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
1013
1014         spin_unlock_irqrestore(&udc->lock, flags);
1015
1016         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1017                 return -ESHUTDOWN;
1018
1019         req->ep = ep;
1020
1021         /* map virtual address to hardware */
1022         if (req->req.dma == DMA_ADDR_INVALID) {
1023                 req->req.dma = dma_map_single(udc->gadget.dev.parent,
1024                                         req->req.buf, req->req.length, dir);
1025                 req->mapped = 1;
1026         } else {
1027                 dma_sync_single_for_device(udc->gadget.dev.parent,
1028                                         req->req.dma, req->req.length, dir);
1029                 req->mapped = 0;
1030         }
1031
1032         req->req.status = -EINPROGRESS;
1033         req->req.actual = 0;
1034         req->dtd_count = 0;
1035
1036
1037         /* build dtds and push them to device queue */
1038         status = fsl_req_to_dtd(req, gfp_flags);
1039         if (status)
1040                 goto err_unmap;
1041
1042         spin_lock_irqsave(&udc->lock, flags);
1043
1044         /* re-check if the ep has not been disabled */
1045         if (unlikely(!ep->desc)) {
1046                 spin_unlock_irqrestore(&udc->lock, flags);
1047                 status = -EINVAL;
1048                 goto err_unmap;
1049         }
1050
1051         fsl_queue_td(ep, req);
1052
1053         /* Update ep0 state */
1054         if ((ep_index(ep) == 0))
1055                 udc->ep0_state = DATA_STATE_XMIT;
1056
1057         /* irq handler advances the queue */
1058         if (req != NULL)
1059                 list_add_tail(&req->queue, &ep->queue);
1060         spin_unlock_irqrestore(&udc->lock, flags);
1061
1062         return 0;
1063
1064 err_unmap:
1065         if (req->mapped) {
1066                 dma_unmap_single(udc->gadget.dev.parent,
1067                         req->req.dma, req->req.length, dir);
1068                 req->req.dma = DMA_ADDR_INVALID;
1069                 req->mapped = 0;
1070         }
1071         return status;
1072 }
1073
1074 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
1075 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1076 {
1077         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
1078         struct fsl_req *req;
1079         unsigned long flags;
1080         int ep_num, stopped, ret = 0;
1081         u32 epctrl;
1082
1083         if (!_ep || !_req)
1084                 return -EINVAL;
1085
1086         spin_lock_irqsave(&ep->udc->lock, flags);
1087         stopped = ep->stopped;
1088
1089         /* Stop the ep before we deal with the queue */
1090         ep->stopped = 1;
1091         ep_num = ep_index(ep);
1092
1093 #if defined(CONFIG_ARCH_TEGRA)
1094         /* Touch the registers if cable is connected and phy is on */
1095         if(vbus_enabled())
1096 #endif
1097         {
1098                 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1099                 if (ep_is_in(ep))
1100                         epctrl &= ~EPCTRL_TX_ENABLE;
1101                 else
1102                         epctrl &= ~EPCTRL_RX_ENABLE;
1103                 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1104         }
1105
1106         /* make sure it's actually queued on this endpoint */
1107         list_for_each_entry(req, &ep->queue, queue) {
1108                 if (&req->req == _req)
1109                         break;
1110         }
1111         if (&req->req != _req) {
1112                 ret = -EINVAL;
1113                 goto out;
1114         }
1115
1116         /* The request is in progress, or completed but not dequeued */
1117         if (ep->queue.next == &req->queue) {
1118                 _req->status = -ECONNRESET;
1119                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
1120
1121                 /* The request isn't the last request in this ep queue */
1122                 if (req->queue.next != &ep->queue) {
1123                         struct ep_queue_head *qh;
1124                         struct fsl_req *next_req;
1125
1126                         qh = ep->qh;
1127                         next_req = list_entry(req->queue.next, struct fsl_req,
1128                                         queue);
1129
1130                         /* Point the QH to the first TD of next request */
1131                         fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
1132                 }
1133
1134                 /* The request hasn't been processed, patch up the TD chain */
1135         } else {
1136                 struct fsl_req *prev_req;
1137
1138                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
1139                 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
1140                                 &prev_req->tail->next_td_ptr);
1141
1142         }
1143
1144         done(ep, req, -ECONNRESET);
1145
1146         /* Enable EP */
1147 out:
1148 #if defined(CONFIG_ARCH_TEGRA)
1149         /* Touch the registers if cable is connected and phy is on */
1150         if(vbus_enabled())
1151 #endif
1152         {
1153                 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1154                 if (ep_is_in(ep))
1155                         epctrl |= EPCTRL_TX_ENABLE;
1156                 else
1157                         epctrl |= EPCTRL_RX_ENABLE;
1158                 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1159         }
1160         ep->stopped = stopped;
1161
1162         spin_unlock_irqrestore(&ep->udc->lock, flags);
1163         return ret;
1164 }
1165
1166 /*-------------------------------------------------------------------------*/
1167
1168 /*-----------------------------------------------------------------
1169  * modify the endpoint halt feature
1170  * @ep: the non-isochronous endpoint being stalled
1171  * @value: 1--set halt  0--clear halt
1172  * Returns zero, or a negative error code.
1173 *----------------------------------------------------------------*/
1174 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1175 {
1176         struct fsl_ep *ep = NULL;
1177         unsigned long flags = 0;
1178         int status = -EOPNOTSUPP;       /* operation not supported */
1179         unsigned char ep_dir = 0, ep_num = 0;
1180         struct fsl_udc *udc = NULL;
1181
1182         ep = container_of(_ep, struct fsl_ep, ep);
1183         udc = ep->udc;
1184         if (!_ep || !ep->desc) {
1185                 status = -EINVAL;
1186                 goto out;
1187         }
1188
1189         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1190                 status = -EOPNOTSUPP;
1191                 goto out;
1192         }
1193
1194         /* Attempt to halt IN ep will fail if any transfer requests
1195          * are still queue */
1196         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1197                 status = -EAGAIN;
1198                 goto out;
1199         }
1200
1201         status = 0;
1202         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1203         ep_num = (unsigned char)(ep_index(ep));
1204         spin_lock_irqsave(&ep->udc->lock, flags);
1205         dr_ep_change_stall(ep_num, ep_dir, value);
1206         spin_unlock_irqrestore(&ep->udc->lock, flags);
1207
1208         if (ep_index(ep) == 0) {
1209                 udc->ep0_state = WAIT_FOR_SETUP;
1210                 udc->ep0_dir = 0;
1211         }
1212 out:
1213         VDBG(" %s %s halt stat %d", ep->ep.name,
1214                         value ?  "set" : "clear", status);
1215
1216         return status;
1217 }
1218
1219 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1220 {
1221         struct fsl_ep *ep;
1222         struct fsl_udc *udc;
1223         int size = 0;
1224         u32 bitmask;
1225         struct ep_queue_head *d_qh;
1226
1227         ep = container_of(_ep, struct fsl_ep, ep);
1228         if (!_ep || (!ep->desc && ep_index(ep) != 0))
1229                 return -ENODEV;
1230
1231         udc = (struct fsl_udc *)ep->udc;
1232
1233         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1234                 return -ESHUTDOWN;
1235
1236         d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
1237
1238         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1239             (1 << (ep_index(ep)));
1240
1241         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1242                 size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1243                     >> DTD_LENGTH_BIT_POS;
1244
1245         pr_debug("%s %u\n", __func__, size);
1246         return size;
1247 }
1248
1249 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1250 {
1251         struct fsl_ep *ep;
1252         int ep_num, ep_dir;
1253         u32 bits;
1254         unsigned long timeout;
1255 #define FSL_UDC_FLUSH_TIMEOUT 1000
1256
1257 #if defined(CONFIG_ARCH_TEGRA)
1258         /* Touch the registers if cable is connected and phy is on */
1259         if (!vbus_enabled())
1260                 return;
1261 #endif
1262
1263         if (!_ep) {
1264                 return;
1265         } else {
1266                 ep = container_of(_ep, struct fsl_ep, ep);
1267                 if (!ep->desc)
1268                         return;
1269         }
1270         ep_num = ep_index(ep);
1271         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1272
1273         if (ep_num == 0)
1274                 bits = (1 << 16) | 1;
1275         else if (ep_dir == USB_SEND)
1276                 bits = 1 << (16 + ep_num);
1277         else
1278                 bits = 1 << ep_num;
1279
1280         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1281         do {
1282                 fsl_writel(bits, &dr_regs->endptflush);
1283
1284                 /* Wait until flush complete */
1285                 while (fsl_readl(&dr_regs->endptflush)) {
1286                         if (time_after(jiffies, timeout)) {
1287                                 ERR("ep flush timeout\n");
1288                                 return;
1289                         }
1290                         cpu_relax();
1291                 }
1292                 /* See if we need to flush again */
1293         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1294 }
1295
1296 static struct usb_ep_ops fsl_ep_ops = {
1297         .enable = fsl_ep_enable,
1298         .disable = fsl_ep_disable,
1299
1300         .alloc_request = fsl_alloc_request,
1301         .free_request = fsl_free_request,
1302
1303         .queue = fsl_ep_queue,
1304         .dequeue = fsl_ep_dequeue,
1305
1306         .set_halt = fsl_ep_set_halt,
1307         .fifo_status = fsl_ep_fifo_status,
1308         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1309 };
1310
1311 /*-------------------------------------------------------------------------
1312                 Gadget Driver Layer Operations
1313 -------------------------------------------------------------------------*/
1314
1315 /*----------------------------------------------------------------------
1316  * Get the current frame number (from DR frame_index Reg )
1317  *----------------------------------------------------------------------*/
1318 static int fsl_get_frame(struct usb_gadget *gadget)
1319 {
1320         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1321 }
1322
1323 /*-----------------------------------------------------------------------
1324  * Tries to wake up the host connected to this gadget
1325  -----------------------------------------------------------------------*/
1326 #ifndef CONFIG_USB_ANDROID
1327 static int fsl_wakeup(struct usb_gadget *gadget)
1328 {
1329         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1330         u32 portsc;
1331
1332         /* Remote wakeup feature not enabled by host */
1333         if (!udc->remote_wakeup)
1334                 return -ENOTSUPP;
1335
1336         portsc = fsl_readl(&dr_regs->portsc1);
1337         /* not suspended? */
1338         if (!(portsc & PORTSCX_PORT_SUSPEND))
1339                 return 0;
1340         /* trigger force resume */
1341         portsc |= PORTSCX_PORT_FORCE_RESUME;
1342         fsl_writel(portsc, &dr_regs->portsc1);
1343         return 0;
1344 }
1345 #endif
1346
1347 static int can_pullup(struct fsl_udc *udc)
1348 {
1349         return udc->driver && udc->softconnect && udc->vbus_active;
1350 }
1351
1352 /* Notify controller that VBUS is powered, Called by whatever
1353    detects VBUS sessions */
1354 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1355 {
1356         struct fsl_udc  *udc;
1357         unsigned long   flags;
1358
1359         udc = container_of(gadget, struct fsl_udc, gadget);
1360
1361         VDBG("VBUS %s", is_active ? "on" : "off");
1362
1363         if (udc->transceiver) {
1364                 if (udc->vbus_active && !is_active) {
1365                         /* If cable disconnected, cancel any delayed work */
1366                         cancel_delayed_work(&udc->work);
1367                         spin_lock_irqsave(&udc->lock, flags);
1368                         /* reset all internal Queues and inform client driver */
1369                         reset_queues(udc);
1370                         /* stop the controller and turn off the clocks */
1371                         dr_controller_stop(udc);
1372                         dr_controller_reset(udc);
1373                         udc->vbus_active = 0;
1374                         udc->usb_state = USB_STATE_DEFAULT;
1375                         spin_unlock_irqrestore(&udc->lock, flags);
1376                         fsl_udc_clk_suspend(false);
1377                         if (udc->vbus_regulator) {
1378                                 /* set the current limit to 0mA */
1379                                 regulator_set_current_limit(
1380                                         udc->vbus_regulator, 0, 0);
1381                         }
1382                 } else if (!udc->vbus_active && is_active) {
1383                         fsl_udc_clk_resume(false);
1384                         /* setup the controller in the device mode */
1385                         dr_controller_setup(udc);
1386                         /* setup EP0 for setup packet */
1387                         ep0_setup(udc);
1388                         /* initialize the USB and EP states */
1389                         udc->usb_state = USB_STATE_ATTACHED;
1390                         udc->ep0_state = WAIT_FOR_SETUP;
1391                         udc->ep0_dir = 0;
1392                         udc->vbus_active = 1;
1393                         /* start the controller */
1394                         dr_controller_run(udc);
1395                         if (udc->vbus_regulator) {
1396                                 /* set the current limit to 100mA */
1397                                 regulator_set_current_limit(
1398                                         udc->vbus_regulator, 0, 100);
1399                         }
1400                         /* Schedule work to wait for 1000 msec and check for
1401                          * charger if setup packet is not received */
1402                         schedule_delayed_work(&udc->work,
1403                                 USB_CHARGER_DETECTION_WAIT_TIME_MS);
1404                 }
1405
1406 #ifndef CONFIG_USB_G_ANDROID
1407                 return 0;
1408 #endif
1409         }
1410
1411         spin_lock_irqsave(&udc->lock, flags);
1412         udc->vbus_active = (is_active != 0);
1413         if (can_pullup(udc))
1414                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1415                                 &dr_regs->usbcmd);
1416         else
1417                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1418                                 &dr_regs->usbcmd);
1419         spin_unlock_irqrestore(&udc->lock, flags);
1420         return 0;
1421 }
1422
1423 /* constrain controller's VBUS power usage
1424  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1425  * reporting how much power the device may consume.  For example, this
1426  * could affect how quickly batteries are recharged.
1427  *
1428  * Returns zero on success, else negative errno.
1429  */
1430 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1431 {
1432         struct fsl_udc *udc;
1433
1434         udc = container_of(gadget, struct fsl_udc, gadget);
1435         /* check udc regulator is available for drawing the vbus current */
1436         if (udc->vbus_regulator) {
1437                 udc->current_limit = mA;
1438                 schedule_work(&udc->charger_work);
1439         }
1440
1441         if (udc->transceiver)
1442                 return otg_set_power(udc->transceiver, mA);
1443         return -ENOTSUPP;
1444 }
1445
1446 /* Change Data+ pullup status
1447  * this func is used by usb_gadget_connect/disconnet
1448  */
1449 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1450 {
1451         struct fsl_udc *udc;
1452
1453         udc = container_of(gadget, struct fsl_udc, gadget);
1454         udc->softconnect = (is_on != 0);
1455         if (udc_controller->transceiver) {
1456                 if (udc_controller->transceiver->state == OTG_STATE_B_PERIPHERAL) {
1457                         if (can_pullup(udc))
1458                                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1459                                                 &dr_regs->usbcmd);
1460                         else
1461                                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1462                                                 &dr_regs->usbcmd);
1463                 }
1464         }
1465         return 0;
1466 }
1467
1468 static int fsl_start(struct usb_gadget_driver *driver,
1469                 int (*bind)(struct usb_gadget *));
1470 static int fsl_stop(struct usb_gadget_driver *driver);
1471 /* defined in gadget.h */
1472 static struct usb_gadget_ops fsl_gadget_ops = {
1473         .get_frame = fsl_get_frame,
1474 #ifndef CONFIG_USB_ANDROID
1475         .wakeup = fsl_wakeup,
1476 #endif
1477 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1478         .vbus_session = fsl_vbus_session,
1479         .vbus_draw = fsl_vbus_draw,
1480         .pullup = fsl_pullup,
1481         .start = fsl_start,
1482         .stop = fsl_stop,
1483 };
1484
1485 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1486    on new transaction */
1487 static void ep0stall(struct fsl_udc *udc)
1488 {
1489         u32 tmp;
1490
1491         /* must set tx and rx to stall at the same time */
1492         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1493         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1494         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1495         udc->ep0_state = WAIT_FOR_SETUP;
1496         udc->ep0_dir = 0;
1497 }
1498
1499 /* Prime a status phase for ep0 */
1500 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1501 {
1502         struct fsl_req *req = udc->status_req;
1503         struct fsl_ep *ep;
1504
1505         if (direction == EP_DIR_IN)
1506                 udc->ep0_dir = USB_DIR_IN;
1507         else
1508                 udc->ep0_dir = USB_DIR_OUT;
1509
1510         ep = &udc->eps[0];
1511         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1512
1513         req->ep = ep;
1514         req->req.length = 0;
1515         req->req.status = -EINPROGRESS;
1516         req->req.actual = 0;
1517         req->req.complete = NULL;
1518         req->dtd_count = 0;
1519
1520         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1521                         req->req.buf, req->req.length,
1522                         ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1523         req->mapped = 1;
1524
1525         if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1526                 fsl_queue_td(ep, req);
1527         else
1528                 return -ENOMEM;
1529
1530         list_add_tail(&req->queue, &ep->queue);
1531
1532         return 0;
1533 }
1534
1535 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1536 {
1537         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1538
1539         if (ep->name)
1540                 nuke(ep, -ESHUTDOWN);
1541 }
1542
1543 /*
1544  * ch9 Set address
1545  */
1546 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1547 {
1548         /* Save the new address to device struct */
1549         udc->device_address = (u8) value;
1550         /* Update usb state */
1551         udc->usb_state = USB_STATE_ADDRESS;
1552         /* Status phase */
1553         if (ep0_prime_status(udc, EP_DIR_IN))
1554                 ep0stall(udc);
1555 }
1556
1557 /*
1558  * ch9 Get status
1559  */
1560 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1561                 u16 index, u16 length)
1562 {
1563         u16 tmp = 0;            /* Status, cpu endian */
1564         struct fsl_req *req;
1565         struct fsl_ep *ep;
1566
1567         ep = &udc->eps[0];
1568
1569         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1570                 /* Get device status */
1571                 tmp = 1 << USB_DEVICE_SELF_POWERED;
1572                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1573         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1574                 /* Get interface status */
1575                 /* We don't have interface information in udc driver */
1576                 tmp = 0;
1577         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1578                 /* Get endpoint status */
1579                 struct fsl_ep *target_ep;
1580
1581                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1582
1583                 /* stall if endpoint doesn't exist */
1584                 if (!target_ep->desc)
1585                         goto stall;
1586                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1587                                 << USB_ENDPOINT_HALT;
1588         }
1589
1590         udc->ep0_dir = USB_DIR_IN;
1591         /* Borrow the per device status_req */
1592         req = udc->status_req;
1593         /* Fill in the reqest structure */
1594         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1595
1596         req->ep = ep;
1597         req->req.length = 2;
1598         req->req.status = -EINPROGRESS;
1599         req->req.actual = 0;
1600         req->req.complete = NULL;
1601         req->dtd_count = 0;
1602
1603         /* map virtual address to hardware */
1604         if (req->req.dma == DMA_ADDR_INVALID) {
1605                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1606                                         req->req.buf,
1607                                         req->req.length, ep_is_in(ep)
1608                                                 ? DMA_TO_DEVICE
1609                                                 : DMA_FROM_DEVICE);
1610                 req->mapped = 1;
1611         } else {
1612                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
1613                                         req->req.dma, req->req.length,
1614                                         ep_is_in(ep)
1615                                                 ? DMA_TO_DEVICE
1616                                                 : DMA_FROM_DEVICE);
1617                 req->mapped = 0;
1618         }
1619
1620         /* prime the data phase */
1621         if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1622                 fsl_queue_td(ep, req);
1623         else                    /* no mem */
1624                 goto stall;
1625
1626         list_add_tail(&req->queue, &ep->queue);
1627         udc->ep0_state = DATA_STATE_XMIT;
1628         return;
1629 stall:
1630         ep0stall(udc);
1631 }
1632
1633 static void udc_test_mode(struct fsl_udc *udc, u32 test_mode)
1634 {
1635         struct fsl_req *req;
1636         struct fsl_ep *ep;
1637         u32 portsc, bitmask;
1638         unsigned long timeout;
1639
1640         /* Ack the ep0 IN */
1641         if (ep0_prime_status(udc, EP_DIR_IN))
1642                 ep0stall(udc);
1643
1644         /* get the ep0 */
1645         ep = &udc->eps[0];
1646         bitmask = ep_is_in(ep)
1647                 ? (1 << (ep_index(ep) + 16))
1648                 : (1 << (ep_index(ep)));
1649
1650         timeout = jiffies + HZ;
1651         /* Wait until ep0 IN endpoint txfr is complete */
1652         while (!(fsl_readl(&dr_regs->endptcomplete) & bitmask)) {
1653                 if (time_after(jiffies, timeout)) {
1654                         pr_err("Timeout for Ep0 IN Ack\n");
1655                         break;
1656                 }
1657                 cpu_relax();
1658         }
1659
1660         switch (test_mode << PORTSCX_PTC_BIT_POS) {
1661         case PORTSCX_PTC_JSTATE:
1662                 VDBG("TEST_J\n");
1663                 break;
1664         case PORTSCX_PTC_KSTATE:
1665                 VDBG("TEST_K\n");
1666                 break;
1667         case PORTSCX_PTC_SEQNAK:
1668                 VDBG("TEST_SE0_NAK\n");
1669                 break;
1670         case PORTSCX_PTC_PACKET:
1671                 VDBG("TEST_PACKET\n");
1672
1673                 /* get the ep and configure for IN direction */
1674                 ep = &udc->eps[0];
1675                 udc->ep0_dir = USB_DIR_IN;
1676
1677                 /* Initialize ep0 status request structure */
1678                 req = container_of(fsl_alloc_request(NULL, GFP_ATOMIC),
1679                                 struct fsl_req, req);
1680                 /* allocate a small amount of memory to get valid address */
1681                 req->req.buf = kmalloc(sizeof(fsl_udc_test_packet), GFP_ATOMIC);
1682                 req->req.dma = virt_to_phys(req->req.buf);
1683
1684                 /* Fill in the reqest structure */
1685                 memcpy(req->req.buf, fsl_udc_test_packet, sizeof(fsl_udc_test_packet));
1686                 req->ep = ep;
1687                 req->req.length = sizeof(fsl_udc_test_packet);
1688                 req->req.status = -EINPROGRESS;
1689                 req->req.actual = 0;
1690                 req->req.complete = NULL;
1691                 req->dtd_count = 0;
1692                 req->mapped = 0;
1693
1694                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
1695                                         req->req.dma, req->req.length,
1696                                         ep_is_in(ep)
1697                                                 ? DMA_TO_DEVICE
1698                                                 : DMA_FROM_DEVICE);
1699
1700                 /* prime the data phase */
1701                 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1702                         fsl_queue_td(ep, req);
1703                 else                    /* no mem */
1704                         goto stall;
1705
1706                 list_add_tail(&req->queue, &ep->queue);
1707                 udc->ep0_state = DATA_STATE_XMIT;
1708                 break;
1709         case PORTSCX_PTC_FORCE_EN:
1710                 VDBG("TEST_FORCE_EN\n");
1711                 break;
1712         default:
1713                 ERR("udc unknown test mode[%d]!\n", test_mode);
1714                 goto stall;
1715         }
1716
1717         /* read the portsc register */
1718         portsc = fsl_readl(&dr_regs->portsc1);
1719         /* set the test mode selector */
1720         portsc |= test_mode << PORTSCX_PTC_BIT_POS;
1721         fsl_writel(portsc, &dr_regs->portsc1);
1722
1723         /*
1724          * The device must have its power cycled to exit test mode.
1725          * See USB 2.0 spec, section 9.4.9 for test modes operation in "Set Feature"
1726          * See USB 2.0 spec, section 7.1.20 for test modes.
1727          */
1728         pr_info("udc entering the test mode, power cycle to exit test mode\n");
1729         return;
1730 stall:
1731         ep0stall(udc);
1732 }
1733
1734 static void setup_received_irq(struct fsl_udc *udc,
1735                 struct usb_ctrlrequest *setup)
1736 {
1737         u16 wValue = le16_to_cpu(setup->wValue);
1738         u16 wIndex = le16_to_cpu(setup->wIndex);
1739         u16 wLength = le16_to_cpu(setup->wLength);
1740
1741         udc_reset_ep_queue(udc, 0);
1742
1743         /* We process some stardard setup requests here */
1744         switch (setup->bRequest) {
1745         case USB_REQ_GET_STATUS:
1746                 /* Data+Status phase from udc */
1747                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1748                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1749                         break;
1750                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1751                 return;
1752
1753         case USB_REQ_SET_ADDRESS:
1754                 /* Status phase from udc */
1755                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1756                                                 | USB_RECIP_DEVICE))
1757                         break;
1758 #ifdef CONFIG_ARCH_TEGRA
1759                 /* This delay is necessary for some windows drivers to
1760                  * properly recognize the device */
1761                 mdelay(1);
1762 #endif
1763                 ch9setaddress(udc, wValue, wIndex, wLength);
1764                 return;
1765
1766         case USB_REQ_CLEAR_FEATURE:
1767         case USB_REQ_SET_FEATURE:
1768                 /* Status phase from udc */
1769         {
1770                 int rc = -EOPNOTSUPP;
1771                 u16 ptc = 0;
1772
1773                 if (setup->bRequestType == USB_RECIP_DEVICE &&
1774                                  wValue == USB_DEVICE_TEST_MODE) {
1775                         /*
1776                          * If the feature selector is TEST_MODE, then the most
1777                          * significant byte of wIndex is used to specify the specific
1778                          * test mode and the lower byte of wIndex must be zero.
1779                          */
1780                         udc_test_mode(udc, wIndex >> 8);
1781                         return;
1782
1783                 } else if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1784                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1785                         int pipe = get_pipe_by_windex(wIndex);
1786                         struct fsl_ep *ep;
1787
1788                         if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1789                                 break;
1790                         ep = get_ep_by_pipe(udc, pipe);
1791
1792                         spin_unlock(&udc->lock);
1793                         rc = fsl_ep_set_halt(&ep->ep,
1794                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1795                                                 ? 1 : 0);
1796                         spin_lock(&udc->lock);
1797
1798                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1799                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1800                                 | USB_TYPE_STANDARD)) {
1801                         /* Note: The driver has not include OTG support yet.
1802                          * This will be set when OTG support is added */
1803                         if (wValue == USB_DEVICE_TEST_MODE)
1804                                 ptc = wIndex >> 8;
1805                         else if (gadget_is_otg(&udc->gadget)) {
1806                                 if (setup->bRequest ==
1807                                     USB_DEVICE_B_HNP_ENABLE)
1808                                         udc->gadget.b_hnp_enable = 1;
1809                                 else if (setup->bRequest ==
1810                                          USB_DEVICE_A_HNP_SUPPORT)
1811                                         udc->gadget.a_hnp_support = 1;
1812                                 else if (setup->bRequest ==
1813                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1814                                         udc->gadget.a_alt_hnp_support = 1;
1815                         }
1816                         rc = 0;
1817                 } else
1818                         break;
1819
1820                 if (rc == 0) {
1821                         if (ep0_prime_status(udc, EP_DIR_IN))
1822                                 ep0stall(udc);
1823                 }
1824                 if (ptc) {
1825                         u32 tmp;
1826
1827                         mdelay(10);
1828                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1829                         fsl_writel(tmp, &dr_regs->portsc1);
1830                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1831                 }
1832
1833                 return;
1834         }
1835
1836         default:
1837                 break;
1838         }
1839
1840         /* Requests handled by gadget */
1841         if (wLength) {
1842                 /* Data phase from gadget, status phase from udc */
1843                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1844                                 ?  USB_DIR_IN : USB_DIR_OUT;
1845                 spin_unlock(&udc->lock);
1846                 if (udc->driver && udc->driver->setup(&udc->gadget,
1847                                 &udc->local_setup_buff) < 0)
1848                         ep0stall(udc);
1849                 spin_lock(&udc->lock);
1850                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1851                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1852         } else {
1853                 /* No data phase, IN status from gadget */
1854                 udc->ep0_dir = USB_DIR_IN;
1855                 spin_unlock(&udc->lock);
1856                 if (udc->driver && udc->driver->setup(&udc->gadget,
1857                                 &udc->local_setup_buff) < 0)
1858                         ep0stall(udc);
1859                 spin_lock(&udc->lock);
1860                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1861         }
1862 }
1863
1864 /* Process request for Data or Status phase of ep0
1865  * prime status phase if needed */
1866 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1867                 struct fsl_req *req)
1868 {
1869         if (udc->usb_state == USB_STATE_ADDRESS) {
1870                 /* Set the new address */
1871                 u32 new_address = (u32) udc->device_address;
1872                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1873                                 &dr_regs->deviceaddr);
1874         }
1875
1876         done(ep0, req, 0);
1877
1878         switch (udc->ep0_state) {
1879         case DATA_STATE_XMIT:
1880                 /* receive status phase */
1881                 if (ep0_prime_status(udc, EP_DIR_OUT))
1882                         ep0stall(udc);
1883                 break;
1884         case DATA_STATE_RECV:
1885                 /* send status phase */
1886                 if (ep0_prime_status(udc, EP_DIR_IN))
1887                         ep0stall(udc);
1888                 break;
1889         case WAIT_FOR_OUT_STATUS:
1890                 udc->ep0_state = WAIT_FOR_SETUP;
1891                 break;
1892         case WAIT_FOR_SETUP:
1893                 ERR("Unexpect ep0 packets\n");
1894                 break;
1895         default:
1896                 ep0stall(udc);
1897                 break;
1898         }
1899 }
1900
1901 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1902  * being corrupted by another incoming setup packet */
1903 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1904 {
1905         u32 temp;
1906         struct ep_queue_head *qh;
1907         struct fsl_usb2_platform_data *pdata = udc->pdata;
1908
1909         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1910
1911         /* Clear bit in ENDPTSETUPSTAT */
1912         temp = fsl_readl(&dr_regs->endptsetupstat);
1913         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1914
1915         /* while a hazard exists when setup package arrives */
1916         do {
1917                 /* Set Setup Tripwire */
1918                 temp = fsl_readl(&dr_regs->usbcmd);
1919                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1920
1921                 /* Copy the setup packet to local buffer */
1922                 if (pdata->le_setup_buf) {
1923                         u32 *p = (u32 *)buffer_ptr;
1924                         u32 *s = (u32 *)qh->setup_buffer;
1925
1926                         /* Convert little endian setup buffer to CPU endian */
1927                         *p++ = le32_to_cpu(*s++);
1928                         *p = le32_to_cpu(*s);
1929                 } else {
1930                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1931                 }
1932         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1933
1934         /* Clear Setup Tripwire */
1935         temp = fsl_readl(&dr_regs->usbcmd);
1936         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1937 }
1938
1939 /* process-ep_req(): free the completed Tds for this req */
1940 static int process_ep_req(struct fsl_udc *udc, int pipe,
1941                 struct fsl_req *curr_req)
1942 {
1943         struct ep_td_struct *curr_td;
1944         int     td_complete, actual, remaining_length, j, tmp;
1945         int     status = 0;
1946         int     errors = 0;
1947         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1948         int direction = pipe % 2;
1949
1950         curr_td = curr_req->head;
1951         td_complete = 0;
1952         actual = curr_req->req.length;
1953
1954         for (j = 0; j < curr_req->dtd_count; j++) {
1955                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1956                                         & DTD_PACKET_SIZE)
1957                                 >> DTD_LENGTH_BIT_POS;
1958                 actual -= remaining_length;
1959
1960                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1961                 if (errors & DTD_ERROR_MASK) {
1962                         if (errors & DTD_STATUS_HALTED) {
1963                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1964                                 /* Clear the errors and Halt condition */
1965                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1966                                 tmp &= ~errors;
1967                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1968                                 status = -EPIPE;
1969                                 /* FIXME: continue with next queued TD? */
1970
1971                                 break;
1972                         }
1973                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1974                                 VDBG("Transfer overflow");
1975                                 status = -EPROTO;
1976                                 break;
1977                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1978                                 VDBG("ISO error");
1979                                 status = -EILSEQ;
1980                                 break;
1981                         } else
1982                                 ERR("Unknown error has occurred (0x%x)!\n",
1983                                         errors);
1984
1985                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1986                                 & DTD_STATUS_ACTIVE) {
1987                         VDBG("Request not complete");
1988                         status = REQ_UNCOMPLETE;
1989                         return status;
1990                 } else if (remaining_length) {
1991                         if (direction) {
1992                                 VDBG("Transmit dTD remaining length not zero");
1993                                 status = -EPROTO;
1994                                 break;
1995                         } else {
1996                                 td_complete++;
1997                                 break;
1998                         }
1999                 } else {
2000                         td_complete++;
2001                         VDBG("dTD transmitted successful");
2002                 }
2003
2004                 if (j != curr_req->dtd_count - 1)
2005                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
2006         }
2007
2008         if (status)
2009                 return status;
2010
2011         curr_req->req.actual = actual;
2012
2013         return 0;
2014 }
2015
2016 /* Process a DTD completion interrupt */
2017 static void dtd_complete_irq(struct fsl_udc *udc)
2018 {
2019         u32 bit_pos;
2020         int i, ep_num, direction, bit_mask, status;
2021         struct fsl_ep *curr_ep;
2022         struct fsl_req *curr_req, *temp_req;
2023
2024         /* Clear the bits in the register */
2025         bit_pos = fsl_readl(&dr_regs->endptcomplete);
2026         fsl_writel(bit_pos, &dr_regs->endptcomplete);
2027
2028         if (!bit_pos)
2029                 return;
2030
2031 #ifdef CONFIG_ARCH_TEGRA
2032         /* XXX what's going on here */
2033         for (i = 0; i < udc->max_ep; i++) {
2034 #else
2035         for (i = 0; i < udc->max_ep * 2; i++) {
2036 #endif
2037                 ep_num = i >> 1;
2038                 direction = i % 2;
2039
2040                 bit_mask = 1 << (ep_num + 16 * direction);
2041
2042                 if (!(bit_pos & bit_mask))
2043                         continue;
2044
2045                 curr_ep = get_ep_by_pipe(udc, i);
2046
2047                 /* If the ep is configured */
2048                 if (curr_ep->name == NULL) {
2049                         WARNING("Invalid EP?");
2050                         continue;
2051                 }
2052
2053                 /* process the req queue until an uncomplete request */
2054                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
2055                                 queue) {
2056                         status = process_ep_req(udc, i, curr_req);
2057
2058                         VDBG("status of process_ep_req= %d, ep = %d",
2059                                         status, ep_num);
2060                         if (status == REQ_UNCOMPLETE)
2061                                 break;
2062                         /* write back status to req */
2063                         curr_req->req.status = status;
2064
2065                         if (ep_num == 0) {
2066                                 ep0_req_complete(udc, curr_ep, curr_req);
2067                                 break;
2068                         } else
2069                                 done(curr_ep, curr_req, status);
2070                 }
2071         }
2072 }
2073
2074 /* Process a port change interrupt */
2075 static void port_change_irq(struct fsl_udc *udc)
2076 {
2077         u32 speed;
2078
2079         /* Bus resetting is finished */
2080         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
2081                 /* Get the speed */
2082                 speed = (fsl_readl(control_reg)
2083                                 & PORTSCX_PORT_SPEED_MASK);
2084                 switch (speed) {
2085                 case PORTSCX_PORT_SPEED_HIGH:
2086                         udc->gadget.speed = USB_SPEED_HIGH;
2087                         break;
2088                 case PORTSCX_PORT_SPEED_FULL:
2089                         udc->gadget.speed = USB_SPEED_FULL;
2090                         break;
2091                 case PORTSCX_PORT_SPEED_LOW:
2092                         udc->gadget.speed = USB_SPEED_LOW;
2093                         break;
2094                 default:
2095                         udc->gadget.speed = USB_SPEED_UNKNOWN;
2096                         break;
2097                 }
2098         }
2099
2100         /* Update USB state */
2101         if (!udc->resume_state)
2102                 udc->usb_state = USB_STATE_DEFAULT;
2103 }
2104
2105 /* Process suspend interrupt */
2106 static void suspend_irq(struct fsl_udc *udc)
2107 {
2108         udc->resume_state = udc->usb_state;
2109         udc->usb_state = USB_STATE_SUSPENDED;
2110
2111         /* report suspend to the driver, serial.c does not support this */
2112         if (udc->driver && udc->driver->suspend)
2113                 udc->driver->suspend(&udc->gadget);
2114 }
2115
2116 static void bus_resume(struct fsl_udc *udc)
2117 {
2118         udc->usb_state = udc->resume_state;
2119         udc->resume_state = 0;
2120
2121         /* report resume to the driver, serial.c does not support this */
2122         if (udc->driver && udc->driver->resume)
2123                 udc->driver->resume(&udc->gadget);
2124 }
2125
2126 /* Clear up all ep queues */
2127 static int reset_queues(struct fsl_udc *udc)
2128 {
2129         u8 pipe;
2130
2131         for (pipe = 0; pipe < udc->max_pipes; pipe++)
2132                 udc_reset_ep_queue(udc, pipe);
2133
2134         /* report disconnect; the driver is already quiesced */
2135         spin_unlock(&udc->lock);
2136         if (udc->driver && udc->driver->disconnect)
2137                 udc->driver->disconnect(&udc->gadget);
2138         spin_lock(&udc->lock);
2139
2140         return 0;
2141 }
2142
2143 /* Process reset interrupt */
2144 static void reset_irq(struct fsl_udc *udc)
2145 {
2146         u32 temp;
2147         unsigned long timeout;
2148
2149         /* Clear the device address */
2150         temp = fsl_readl(&dr_regs->deviceaddr);
2151         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
2152
2153         udc->device_address = 0;
2154
2155         /* Clear usb state */
2156         udc->resume_state = 0;
2157         udc->ep0_dir = 0;
2158         udc->ep0_state = WAIT_FOR_SETUP;
2159         udc->remote_wakeup = 0; /* default to 0 on reset */
2160         udc->gadget.b_hnp_enable = 0;
2161         udc->gadget.a_hnp_support = 0;
2162         udc->gadget.a_alt_hnp_support = 0;
2163
2164         /* Clear all the setup token semaphores */
2165         temp = fsl_readl(&dr_regs->endptsetupstat);
2166         fsl_writel(temp, &dr_regs->endptsetupstat);
2167
2168         /* Clear all the endpoint complete status bits */
2169         temp = fsl_readl(&dr_regs->endptcomplete);
2170         fsl_writel(temp, &dr_regs->endptcomplete);
2171
2172         timeout = jiffies + 100;
2173         while (fsl_readl(&dr_regs->endpointprime)) {
2174                 /* Wait until all endptprime bits cleared */
2175                 if (time_after(jiffies, timeout)) {
2176                         ERR("Timeout for reset\n");
2177                         break;
2178                 }
2179                 cpu_relax();
2180         }
2181
2182         /* Write 1s to the flush register */
2183         fsl_writel(0xffffffff, &dr_regs->endptflush);
2184
2185 #if defined(CONFIG_ARCH_TEGRA)
2186         /* When the bus reset is seen on Tegra, the PORTSCX_PORT_RESET bit
2187          * is not set */
2188         VDBG("Bus reset");
2189         /* Reset all the queues, include XD, dTD, EP queue
2190          * head and TR Queue */
2191         reset_queues(udc);
2192         udc->usb_state = USB_STATE_DEFAULT;
2193 #else
2194         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
2195                 VDBG("Bus reset");
2196                 /* Reset all the queues, include XD, dTD, EP queue
2197                  * head and TR Queue */
2198                 reset_queues(udc);
2199                 udc->usb_state = USB_STATE_DEFAULT;
2200         } else {
2201                 VDBG("Controller reset");
2202                 /* initialize usb hw reg except for regs for EP, not
2203                  * touch usbintr reg */
2204                 dr_controller_setup(udc);
2205
2206                 /* Reset all internal used Queues */
2207                 reset_queues(udc);
2208
2209                 ep0_setup(udc);
2210
2211                 /* Enable DR IRQ reg, Set Run bit, change udc state */
2212                 dr_controller_run(udc);
2213                 udc->usb_state = USB_STATE_ATTACHED;
2214         }
2215 #endif
2216 }
2217
2218 static void fsl_udc_set_current_limit_work(struct work_struct* work)
2219 {
2220         struct fsl_udc *udc = container_of (work, struct fsl_udc, charger_work);
2221
2222         /* check udc regulator is available for drawing vbus current*/
2223         if (udc->vbus_regulator) {
2224                 /* set the current limit in uA */
2225                 regulator_set_current_limit(
2226                         udc->vbus_regulator, 0,
2227                         udc->current_limit *1000);
2228         }
2229 }
2230
2231 /*
2232  * If VBUS is detected and setup packet is not received in 100ms then
2233  * work thread starts and checks for the USB charger detection.
2234  */
2235 static void fsl_udc_charger_detect_work(struct work_struct* work)
2236 {
2237         struct fsl_udc *udc = container_of (work, struct fsl_udc, work.work);
2238
2239         /* check for the platform charger detection */
2240         if (fsl_udc_charger_detect()) {
2241                 printk(KERN_INFO "USB compliant charger detected\n");
2242                 /* check udc regulator is available for drawing vbus current*/
2243                 if (udc->vbus_regulator) {
2244                         /* set the current limit in uA */
2245                         regulator_set_current_limit(
2246                                 udc->vbus_regulator, 0,
2247                                 USB_CHARGING_CURRENT_LIMIT_MA*1000);
2248                 }
2249         }
2250 }
2251
2252 #if defined(CONFIG_ARCH_TEGRA)
2253 /*
2254  * Restart device controller in the OTG mode on VBUS detection
2255  */
2256 static void fsl_udc_restart(struct fsl_udc *udc)
2257 {
2258         /* setup the controller in the device mode */
2259         dr_controller_setup(udc);
2260         /* setup EP0 for setup packet */
2261         ep0_setup(udc);
2262         /* start the controller */
2263         dr_controller_run(udc);
2264         /* initialize the USB and EP states */
2265         udc->usb_state = USB_STATE_ATTACHED;
2266         udc->ep0_state = WAIT_FOR_SETUP;
2267         udc->ep0_dir = 0;
2268         udc->vbus_active = 1;
2269 }
2270 #endif
2271
2272 /*
2273  * USB device controller interrupt handler
2274  */
2275 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
2276 {
2277         struct fsl_udc *udc = _udc;
2278         u32 irq_src;
2279         irqreturn_t status = IRQ_NONE;
2280         unsigned long flags;
2281
2282         spin_lock_irqsave(&udc->lock, flags);
2283
2284         /* Disable ISR for OTG host mode */
2285         if (udc->stopped) {
2286                 spin_unlock_irqrestore(&udc->lock, flags);
2287                 return IRQ_NONE;
2288         }
2289 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
2290         {
2291                 u32 temp = fsl_readl(&usb_sys_regs->vbus_sensors);
2292                 udc->vbus_active = (temp & USB_SYS_VBUS_ASESSION) ? true : false;
2293                 /* write back the register to clear the interrupt */
2294                 fsl_writel(temp, &usb_sys_regs->vbus_sensors);
2295         }
2296 #endif
2297         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
2298         /* Clear notification bits */
2299         fsl_writel(irq_src, &dr_regs->usbsts);
2300
2301         /* VDBG("irq_src [0x%8x]", irq_src); */
2302
2303         /* Need to resume? */
2304         if (udc->usb_state == USB_STATE_SUSPENDED)
2305                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
2306                         bus_resume(udc);
2307
2308         /* USB Interrupt */
2309         if (irq_src & USB_STS_INT) {
2310                 VDBG("Packet int");
2311                 /* Setup package, we only support ep0 as control ep */
2312                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
2313                         /* Setup packet received, we are connected to host and
2314                          * not charger. Cancel any delayed work */
2315                         __cancel_delayed_work(&udc->work);
2316                         tripwire_handler(udc, 0,
2317                                         (u8 *) (&udc->local_setup_buff));
2318                         setup_received_irq(udc, &udc->local_setup_buff);
2319                         status = IRQ_HANDLED;
2320                 }
2321
2322                 /* completion of dtd */
2323                 if (fsl_readl(&dr_regs->endptcomplete)) {
2324                         dtd_complete_irq(udc);
2325                         status = IRQ_HANDLED;
2326                 }
2327         }
2328
2329         /* SOF (for ISO transfer) */
2330         if (irq_src & USB_STS_SOF) {
2331                 status = IRQ_HANDLED;
2332         }
2333
2334         /* Port Change */
2335         if (irq_src & USB_STS_PORT_CHANGE) {
2336                 port_change_irq(udc);
2337                 status = IRQ_HANDLED;
2338         }
2339
2340         /* Reset Received */
2341         if (irq_src & USB_STS_RESET) {
2342                 reset_irq(udc);
2343                 status = IRQ_HANDLED;
2344         }
2345
2346         /* Sleep Enable (Suspend) */
2347         if (irq_src & USB_STS_SUSPEND) {
2348                 suspend_irq(udc);
2349                 status = IRQ_HANDLED;
2350         }
2351
2352         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
2353                 VDBG("Error IRQ %x", irq_src);
2354         }
2355
2356         spin_unlock_irqrestore(&udc->lock, flags);
2357         return status;
2358 }
2359
2360 /*----------------------------------------------------------------*
2361  * Hook to gadget drivers
2362  * Called by initialization code of gadget drivers
2363 *----------------------------------------------------------------*/
2364 static int fsl_start(struct usb_gadget_driver *driver,
2365                 int (*bind)(struct usb_gadget *))
2366 {
2367         int retval = -ENODEV;
2368         unsigned long flags = 0;
2369
2370         if (!udc_controller)
2371                 return -ENODEV;
2372
2373         if (!driver || (driver->speed != USB_SPEED_FULL
2374                                 && driver->speed != USB_SPEED_HIGH)
2375                         || !bind || !driver->disconnect || !driver->setup)
2376                 return -EINVAL;
2377
2378         if (udc_controller->driver)
2379                 return -EBUSY;
2380
2381         /* lock is needed but whether should use this lock or another */
2382         spin_lock_irqsave(&udc_controller->lock, flags);
2383
2384         driver->driver.bus = NULL;
2385         /* hook up the driver */
2386         udc_controller->driver = driver;
2387         udc_controller->gadget.dev.driver = &driver->driver;
2388         spin_unlock_irqrestore(&udc_controller->lock, flags);
2389
2390         /* bind udc driver to gadget driver */
2391         retval = bind(&udc_controller->gadget);
2392         if (retval) {
2393                 VDBG("bind to %s --> %d", driver->driver.name, retval);
2394                 udc_controller->gadget.dev.driver = NULL;
2395                 udc_controller->driver = NULL;
2396                 goto out;
2397         }
2398
2399         /* Enable DR IRQ reg and Set usbcmd reg  Run bit */
2400         if (!udc_controller->transceiver) {
2401                 dr_controller_run(udc_controller);
2402                 udc_controller->usb_state = USB_STATE_ATTACHED;
2403                 udc_controller->ep0_state = WAIT_FOR_SETUP;
2404                 udc_controller->ep0_dir = 0;
2405         }
2406
2407         printk(KERN_INFO "%s: bind to driver %s\n",
2408                         udc_controller->gadget.name, driver->driver.name);
2409
2410 out:
2411         if (retval)
2412                 printk(KERN_WARNING "gadget driver register failed %d\n",
2413                        retval);
2414         return retval;
2415 }
2416
2417 /* Disconnect from gadget driver */
2418 static int fsl_stop(struct usb_gadget_driver *driver)
2419 {
2420         struct fsl_ep *loop_ep;
2421         unsigned long flags;
2422
2423         if (!udc_controller)
2424                 return -ENODEV;
2425
2426         if (!driver || driver != udc_controller->driver || !driver->unbind)
2427                 return -EINVAL;
2428
2429         /* stop DR, disable intr */
2430         dr_controller_stop(udc_controller);
2431
2432         /* in fact, no needed */
2433         udc_controller->usb_state = USB_STATE_ATTACHED;
2434         udc_controller->ep0_state = WAIT_FOR_SETUP;
2435         udc_controller->ep0_dir = 0;
2436
2437         /* stand operation */
2438         spin_lock_irqsave(&udc_controller->lock, flags);
2439         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2440         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2441         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2442                         ep.ep_list)
2443                 nuke(loop_ep, -ESHUTDOWN);
2444         spin_unlock_irqrestore(&udc_controller->lock, flags);
2445
2446         /* report disconnect; the controller is already quiesced */
2447         driver->disconnect(&udc_controller->gadget);
2448
2449         /* unbind gadget and unhook driver. */
2450         driver->unbind(&udc_controller->gadget);
2451         udc_controller->gadget.dev.driver = NULL;
2452         udc_controller->driver = NULL;
2453
2454         printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2455                driver->driver.name);
2456         return 0;
2457 }
2458
2459 /*-------------------------------------------------------------------------
2460                 PROC File System Support
2461 -------------------------------------------------------------------------*/
2462 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2463
2464 #include <linux/seq_file.h>
2465
2466 #ifdef CONFIG_ARCH_TEGRA
2467 static const char proc_filename[] = "driver/fsl_tegra_udc";
2468 #else
2469 static const char proc_filename[] = "driver/fsl_usb2_udc";
2470 #endif
2471
2472 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2473                 int *eof, void *_dev)
2474 {
2475         char *buf = page;
2476         char *next = buf;
2477         unsigned size = count;
2478         unsigned long flags;
2479         int t, i;
2480         u32 tmp_reg;
2481         u32 tmp_reg2;
2482         struct fsl_ep *ep = NULL;
2483         struct fsl_req *req;
2484
2485         struct fsl_udc *udc = udc_controller;
2486         if (off != 0)
2487                 return 0;
2488
2489         spin_lock_irqsave(&udc->lock, flags);
2490
2491         /* ------basic driver information ---- */
2492         t = scnprintf(next, size,
2493                         DRIVER_DESC "\n"
2494                         "%s version: %s\n"
2495                         "Gadget driver: %s\n\n",
2496                         driver_name, DRIVER_VERSION,
2497                         udc->driver ? udc->driver->driver.name : "(none)");
2498         size -= t;
2499         next += t;
2500
2501         /* ------ DR Registers ----- */
2502         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2503         t = scnprintf(next, size,
2504                         "USBCMD reg:\n"
2505                         "SetupTW: %d\n"
2506                         "Run/Stop: %s\n\n",
2507                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2508                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2509         size -= t;
2510         next += t;
2511
2512         tmp_reg = fsl_readl(&dr_regs->usbsts);
2513         t = scnprintf(next, size,
2514                         "USB Status Reg:\n"
2515                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2516                         "USB Error Interrupt: %s\n\n",
2517                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2518                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2519                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2520                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2521         size -= t;
2522         next += t;
2523
2524         tmp_reg = fsl_readl(&dr_regs->usbintr);
2525         t = scnprintf(next, size,
2526                         "USB Intrrupt Enable Reg:\n"
2527                         "Sleep Enable: %d SOF Received Enable: %d "
2528                         "Reset Enable: %d\n"
2529                         "System Error Enable: %d "
2530                         "Port Change Dectected Enable: %d\n"
2531                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2532                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2533                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2534                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2535                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2536                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2537                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2538                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2539         size -= t;
2540         next += t;
2541
2542         tmp_reg = fsl_readl(&dr_regs->frindex);
2543         t = scnprintf(next, size,
2544                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2545                         (tmp_reg & USB_FRINDEX_MASKS));
2546         size -= t;
2547         next += t;
2548
2549         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2550         t = scnprintf(next, size,
2551                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2552                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2553         size -= t;
2554         next += t;
2555
2556         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2557         t = scnprintf(next, size,
2558                         "USB Endpoint List Address Reg: "
2559                         "Device Addr is 0x%x\n\n",
2560                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2561         size -= t;
2562         next += t;
2563
2564         tmp_reg = fsl_readl(&dr_regs->portsc1);
2565 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2566         tmp_reg2 = tmp_reg;
2567 #else
2568         /* In Tegra3 the Phy Type Select(PTS) and Port Speed fields are specified in
2569          * hostpc1devlc register instead of portsc1 register. */
2570         tmp_reg2 = fsl_readl(&dr_regs->hostpc1devlc);
2571 #endif
2572         t = scnprintf(next, size,
2573                 "USB Port Status&Control Reg:\n"
2574                 "Port Transceiver Type : %s Port Speed: %s\n"
2575                 "PHY Low Power Suspend: %s Port Reset: %s "
2576                 "Port Suspend Mode: %s\n"
2577                 "Over-current Change: %s "
2578                 "Port Enable/Disable Change: %s\n"
2579                 "Port Enabled/Disabled: %s "
2580                 "Current Connect Status: %s\n\n", ( {
2581                         char *s;
2582                         switch (tmp_reg2 & PORTSCX_PTS_FSLS) {
2583                         case PORTSCX_PTS_UTMI:
2584                                 s = "UTMI"; break;
2585                         case PORTSCX_PTS_ULPI:
2586                                 s = "ULPI "; break;
2587                         case PORTSCX_PTS_FSLS:
2588                                 s = "FS/LS Serial"; break;
2589                         default:
2590                                 s = "None"; break;
2591                         }
2592                         s;} ), ( {
2593                         char *s;
2594                         switch (tmp_reg2 & PORTSCX_PORT_SPEED_UNDEF) {
2595                         case PORTSCX_PORT_SPEED_FULL:
2596                                 s = "Full Speed"; break;
2597                         case PORTSCX_PORT_SPEED_LOW:
2598                                 s = "Low Speed"; break;
2599                         case PORTSCX_PORT_SPEED_HIGH:
2600                                 s = "High Speed"; break;
2601                         default:
2602                                 s = "Undefined"; break;
2603                         }
2604                         s;
2605                 } ),
2606                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2607                 "Normal PHY mode" : "Low power mode",
2608                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2609                 "Not in Reset",
2610                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2611                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2612                 "No",
2613                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2614                 "Not change",
2615                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2616                 "Not correct",
2617                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2618                 "Attached" : "Not-Att");
2619         size -= t;
2620         next += t;
2621
2622         tmp_reg = fsl_readl(&dr_regs->usbmode);
2623         t = scnprintf(next, size,
2624                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2625                                 char *s;
2626                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2627                                 case USB_MODE_CTRL_MODE_IDLE:
2628                                         s = "Idle"; break;
2629                                 case USB_MODE_CTRL_MODE_DEVICE:
2630                                         s = "Device Controller"; break;
2631                                 case USB_MODE_CTRL_MODE_HOST:
2632                                         s = "Host Controller"; break;
2633                                 default:
2634                                         s = "None"; break;
2635                                 }
2636                                 s;
2637                         } ));
2638         size -= t;
2639         next += t;
2640
2641         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2642         t = scnprintf(next, size,
2643                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2644                         (tmp_reg & EP_SETUP_STATUS_MASK));
2645         size -= t;
2646         next += t;
2647
2648         for (i = 0; i < udc->max_ep / 2; i++) {
2649                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2650                 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2651                                 i, tmp_reg);
2652                 size -= t;
2653                 next += t;
2654         }
2655         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2656         t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2657         size -= t;
2658         next += t;
2659
2660 #if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
2661         if (udc->pdata->have_sysif_regs) {
2662                 tmp_reg = usb_sys_regs->snoop1;
2663                 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2664                 size -= t;
2665                 next += t;
2666
2667                 tmp_reg = usb_sys_regs->control;
2668                 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2669                                 tmp_reg);
2670                 size -= t;
2671                 next += t;
2672         }
2673 #endif
2674
2675         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2676         ep = &udc->eps[0];
2677         t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2678                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2679         size -= t;
2680         next += t;
2681
2682         if (list_empty(&ep->queue)) {
2683                 t = scnprintf(next, size, "its req queue is empty\n\n");
2684                 size -= t;
2685                 next += t;
2686         } else {
2687                 list_for_each_entry(req, &ep->queue, queue) {
2688                         t = scnprintf(next, size,
2689                                 "req %p actual 0x%x length 0x%x buf %p\n",
2690                                 &req->req, req->req.actual,
2691                                 req->req.length, req->req.buf);
2692                         size -= t;
2693                         next += t;
2694                 }
2695         }
2696         /* other gadget->eplist ep */
2697         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2698                 if (ep->desc) {
2699                         t = scnprintf(next, size,
2700                                         "\nFor %s Maxpkt is 0x%x "
2701                                         "index is 0x%x\n",
2702                                         ep->ep.name, ep_maxpacket(ep),
2703                                         ep_index(ep));
2704                         size -= t;
2705                         next += t;
2706
2707                         if (list_empty(&ep->queue)) {
2708                                 t = scnprintf(next, size,
2709                                                 "its req queue is empty\n\n");
2710                                 size -= t;
2711                                 next += t;
2712                         } else {
2713                                 list_for_each_entry(req, &ep->queue, queue) {
2714                                         t = scnprintf(next, size,
2715                                                 "req %p actual 0x%x length "
2716                                                 "0x%x  buf %p\n",
2717                                                 &req->req, req->req.actual,
2718                                                 req->req.length, req->req.buf);
2719                                         size -= t;
2720                                         next += t;
2721                                         }       /* end for each_entry of ep req */
2722                                 }       /* end for else */
2723                         }       /* end for if(ep->queue) */
2724                 }               /* end (ep->desc) */
2725
2726         spin_unlock_irqrestore(&udc->lock, flags);
2727
2728         *eof = 1;
2729         return count - size;
2730 }
2731
2732 #define create_proc_file()      create_proc_read_entry(proc_filename, \
2733                                 0, NULL, fsl_proc_read, NULL)
2734
2735 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2736
2737 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2738
2739 #define create_proc_file()      do {} while (0)
2740 #define remove_proc_file()      do {} while (0)
2741
2742 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2743
2744 /*-------------------------------------------------------------------------*/
2745
2746 /* Release udc structures */
2747 static void fsl_udc_release(struct device *dev)
2748 {
2749         complete(udc_controller->done);
2750         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2751                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2752         kfree(udc_controller);
2753 }
2754
2755 /******************************************************************
2756         Internal structure setup functions
2757 *******************************************************************/
2758 /*------------------------------------------------------------------
2759  * init resource for globle controller
2760  * Return the udc handle on success or NULL on failure
2761  ------------------------------------------------------------------*/
2762 static int __init struct_udc_setup(struct fsl_udc *udc,
2763                 struct platform_device *pdev)
2764 {
2765         struct fsl_usb2_platform_data *pdata;
2766         size_t size;
2767
2768         pdata = pdev->dev.platform_data;
2769         udc->phy_mode = pdata->phy_mode;
2770
2771         udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2772         if (!udc->eps) {
2773                 ERR("malloc fsl_ep failed\n");
2774                 return -1;
2775         }
2776
2777 #ifdef CONFIG_ARCH_TEGRA
2778         /* Tegra uses hardware queue heads */
2779         size = udc->max_ep * sizeof(struct ep_queue_head);
2780         udc->ep_qh = (struct ep_queue_head *)((u8 *)dr_regs + QH_OFFSET);
2781         udc->ep_qh_dma = platform_get_resource(pdev, IORESOURCE_MEM, 0)->start +
2782                 QH_OFFSET;
2783 #else
2784         /* initialized QHs, take care of alignment */
2785         size = udc->max_ep * sizeof(struct ep_queue_head);
2786         if (size < QH_ALIGNMENT)
2787                 size = QH_ALIGNMENT;
2788         else if ((size % QH_ALIGNMENT) != 0) {
2789                 size += QH_ALIGNMENT + 1;
2790                 size &= ~(QH_ALIGNMENT - 1);
2791         }
2792         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2793                                         &udc->ep_qh_dma, GFP_KERNEL);
2794         if (!udc->ep_qh) {
2795                 ERR("malloc QHs for udc failed\n");
2796                 kfree(udc->eps);
2797                 return -1;
2798         }
2799 #endif
2800
2801         udc->ep_qh_size = size;
2802
2803         /* Initialize ep0 status request structure */
2804         /* FIXME: fsl_alloc_request() ignores ep argument */
2805         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2806                         struct fsl_req, req);
2807         /* allocate a small amount of memory to get valid address */
2808         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2809
2810         udc->resume_state = USB_STATE_NOTATTACHED;
2811         udc->usb_state = USB_STATE_POWERED;
2812         udc->ep0_dir = 0;
2813         udc->remote_wakeup = 0; /* default to 0 on reset */
2814
2815         return 0;
2816 }
2817
2818 /*----------------------------------------------------------------
2819  * Setup the fsl_ep struct for eps
2820  * Link fsl_ep->ep to gadget->ep_list
2821  * ep0out is not used so do nothing here
2822  * ep0in should be taken care
2823  *--------------------------------------------------------------*/
2824 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2825                 char *name, int link)
2826 {
2827         struct fsl_ep *ep = &udc->eps[index];
2828
2829         ep->udc = udc;
2830         strcpy(ep->name, name);
2831         ep->ep.name = ep->name;
2832
2833         ep->ep.ops = &fsl_ep_ops;
2834         ep->stopped = 0;
2835
2836         /* for ep0: maxP defined in desc
2837          * for other eps, maxP is set by epautoconfig() called by gadget layer
2838          */
2839         ep->ep.maxpacket = (unsigned short) ~0;
2840
2841         /* the queue lists any req for this ep */
2842         INIT_LIST_HEAD(&ep->queue);
2843
2844         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2845         if (link)
2846                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2847         ep->gadget = &udc->gadget;
2848         ep->qh = &udc->ep_qh[index];
2849
2850         return 0;
2851 }
2852
2853 /* Driver probe function
2854  * all intialization operations implemented here except enabling usb_intr reg
2855  * board setup should have been done in the platform code
2856  */
2857 static int __init fsl_udc_probe(struct platform_device *pdev)
2858 {
2859         struct fsl_usb2_platform_data *pdata;
2860         struct resource *res;
2861         int ret = -ENODEV;
2862         unsigned int i;
2863         u32 dccparams;
2864 #if defined(CONFIG_ARCH_TEGRA)
2865         struct resource *res_sys = NULL;
2866 #endif
2867
2868         if (strcmp(pdev->name, driver_name)) {
2869                 VDBG("Wrong device");
2870                 return -ENODEV;
2871         }
2872
2873         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2874         if (udc_controller == NULL) {
2875                 ERR("malloc udc failed\n");
2876                 return -ENOMEM;
2877         }
2878
2879         pdata = pdev->dev.platform_data;
2880         udc_controller->pdata = pdata;
2881         spin_lock_init(&udc_controller->lock);
2882         udc_controller->stopped = 1;
2883
2884         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2885         if (!res) {
2886                 ret = -ENXIO;
2887                 goto err_kfree;
2888         }
2889
2890         if (!request_mem_region(res->start, resource_size(res),
2891                                 driver_name)) {
2892                 ERR("request mem region for %s failed\n", pdev->name);
2893                 ret = -EBUSY;
2894                 goto err_kfree;
2895         }
2896
2897         dr_regs = ioremap(res->start, resource_size(res));
2898         if (!dr_regs) {
2899                 ret = -ENOMEM;
2900                 goto err_release_mem_region;
2901         }
2902
2903         pdata->regs = (void *)dr_regs;
2904
2905         /*
2906          * do platform specific init: check the clock, grab/config pins, etc.
2907          */
2908         if (pdata->init && pdata->init(pdev)) {
2909                 ret = -ENODEV;
2910                 goto err_iounmap_noclk;
2911         }
2912
2913         /* Set accessors only after pdata->init() ! */
2914         fsl_set_accessors(pdata);
2915
2916 #if defined(CONFIG_ARCH_TEGRA)
2917         /* If the PHY registers are NOT provided as a seperate aperture, then
2918          * we should be using the registers inside the controller aperture. */
2919         res_sys = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2920         if (res_sys)  {
2921                 usb_sys_regs = ioremap(res_sys->start, resource_size(res_sys));
2922                 if (!usb_sys_regs)
2923                         goto err_release_mem_region;
2924         } else {
2925                 usb_sys_regs = (struct usb_sys_interface *)
2926                         ((u32)dr_regs + USB_DR_SYS_OFFSET);
2927         }
2928 #endif
2929
2930 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2931         control_reg = &dr_regs->portsc1;
2932 #else
2933         control_reg = &dr_regs->hostpc1devlc;
2934 #endif
2935 #if !defined(CONFIG_ARCH_MXC) && !defined(CONFIG_ARCH_TEGRA)
2936         if (pdata->have_sysif_regs)
2937                 usb_sys_regs = (struct usb_sys_interface *)
2938                                 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2939 #endif
2940
2941         /* Initialize USB clocks */
2942         ret = fsl_udc_clk_init(pdev);
2943         if (ret < 0)
2944                 goto err_iounmap_noclk;
2945
2946         /* Read Device Controller Capability Parameters register */
2947         dccparams = fsl_readl(&dr_regs->dccparams);
2948         if (!(dccparams & DCCPARAMS_DC)) {
2949                 ERR("This SOC doesn't support device role\n");
2950                 ret = -ENODEV;
2951                 goto err_iounmap;
2952         }
2953         /* Get max device endpoints */
2954         /* DEN is bidirectional ep number, max_ep doubles the number */
2955         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2956
2957         udc_controller->irq = platform_get_irq(pdev, 0);
2958         if (!udc_controller->irq) {
2959                 ret = -ENODEV;
2960                 goto err_iounmap;
2961         }
2962
2963         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2964                         driver_name, udc_controller);
2965         if (ret != 0) {
2966                 ERR("cannot request irq %d err %d\n",
2967                                 udc_controller->irq, ret);
2968                 goto err_iounmap;
2969         }
2970
2971         /* Initialize the udc structure including QH member and other member */
2972         if (struct_udc_setup(udc_controller, pdev)) {
2973                 ERR("Can't initialize udc data structure\n");
2974                 ret = -ENOMEM;
2975                 goto err_free_irq;
2976         }
2977
2978         /* initialize usb hw reg except for regs for EP,
2979          * leave usbintr reg untouched */
2980         dr_controller_setup(udc_controller);
2981
2982         fsl_udc_clk_finalize(pdev);
2983
2984         /* Setup gadget structure */
2985         udc_controller->gadget.ops = &fsl_gadget_ops;
2986         udc_controller->gadget.is_dualspeed = 1;
2987         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2988         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2989         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2990         udc_controller->gadget.name = driver_name;
2991
2992         /* Setup gadget.dev and register with kernel */
2993         dev_set_name(&udc_controller->gadget.dev, "gadget");
2994         udc_controller->gadget.dev.release = fsl_udc_release;
2995         udc_controller->gadget.dev.parent = &pdev->dev;
2996         ret = device_register(&udc_controller->gadget.dev);
2997         if (ret < 0)
2998                 goto err_free_irq;
2999
3000         /* setup QH and epctrl for ep0 */
3001         ep0_setup(udc_controller);
3002
3003         /* setup udc->eps[] for ep0 */
3004         struct_ep_setup(udc_controller, 0, "ep0", 0);
3005         /* for ep0: the desc defined here;
3006          * for other eps, gadget layer called ep_enable with defined desc
3007          */
3008         udc_controller->eps[0].desc = &fsl_ep0_desc;
3009         udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
3010
3011         /* setup the udc->eps[] for non-control endpoints and link
3012          * to gadget.ep_list */
3013         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
3014                 char name[14];
3015
3016                 sprintf(name, "ep%dout", i);
3017                 struct_ep_setup(udc_controller, i * 2, name, 1);
3018                 sprintf(name, "ep%din", i);
3019                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
3020         }
3021
3022         /* use dma_pool for TD management */
3023         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
3024                         sizeof(struct ep_td_struct),
3025                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
3026         if (udc_controller->td_pool == NULL) {
3027                 ret = -ENOMEM;
3028                 goto err_unregister;
3029         }
3030
3031         ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
3032         if (ret)
3033                 goto err_del_udc;
3034
3035         create_proc_file();
3036
3037         /* create a delayed work for detecting the USB charger */
3038         INIT_DELAYED_WORK(&udc_controller->work, fsl_udc_charger_detect_work);
3039         INIT_WORK(&udc_controller->charger_work, fsl_udc_set_current_limit_work);
3040
3041         /* Get the regulator for drawing the vbus current in udc driver */
3042         udc_controller->vbus_regulator = regulator_get(NULL, "usb_bat_chg");
3043         if (IS_ERR(udc_controller->vbus_regulator)) {
3044                 dev_err(&pdev->dev,
3045                         "can't get charge regulator,err:%ld\n",
3046                         PTR_ERR(udc_controller->vbus_regulator));
3047                 udc_controller->vbus_regulator = NULL;
3048         }
3049
3050 #ifdef CONFIG_USB_OTG_UTILS
3051         udc_controller->transceiver = otg_get_transceiver();
3052         if (udc_controller->transceiver) {
3053                 dr_controller_stop(udc_controller);
3054                 dr_controller_reset(udc_controller);
3055                 fsl_udc_clk_suspend(false);
3056                 udc_controller->vbus_active = 0;
3057                 udc_controller->usb_state = USB_STATE_DEFAULT;
3058                 otg_set_peripheral(udc_controller->transceiver, &udc_controller->gadget);
3059         }
3060 #else
3061 #ifdef CONFIG_ARCH_TEGRA
3062         /* Power down the phy if cable is not connected */
3063         if(!vbus_enabled())
3064                 fsl_udc_clk_suspend(false);
3065 #endif
3066 #endif
3067
3068         return 0;
3069
3070 err_del_udc:
3071         dma_pool_destroy(udc_controller->td_pool);
3072 err_unregister:
3073         device_unregister(&udc_controller->gadget.dev);
3074 err_free_irq:
3075         free_irq(udc_controller->irq, udc_controller);
3076 err_iounmap:
3077         if (pdata->exit)
3078                 pdata->exit(pdev);
3079         fsl_udc_clk_release();
3080 err_iounmap_noclk:
3081         iounmap(dr_regs);
3082 err_release_mem_region:
3083         release_mem_region(res->start, resource_size(res));
3084 err_kfree:
3085         kfree(udc_controller);
3086         udc_controller = NULL;
3087         return ret;
3088 }
3089
3090 /* Driver removal function
3091  * Free resources and finish pending transactions
3092  */
3093 static int __exit fsl_udc_remove(struct platform_device *pdev)
3094 {
3095         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3096         struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
3097
3098         DECLARE_COMPLETION(done);
3099
3100         if (!udc_controller)
3101                 return -ENODEV;
3102
3103         usb_del_gadget_udc(&udc_controller->gadget);
3104         udc_controller->done = &done;
3105
3106         cancel_delayed_work(&udc_controller->work);
3107         if (udc_controller->vbus_regulator)
3108                 regulator_put(udc_controller->vbus_regulator);
3109
3110         if (udc_controller->transceiver)
3111                 otg_set_peripheral(udc_controller->transceiver, NULL);
3112
3113         fsl_udc_clk_release();
3114
3115         /* DR has been stopped in usb_gadget_unregister_driver() */
3116         remove_proc_file();
3117
3118         /* Free allocated memory */
3119         kfree(udc_controller->status_req->req.buf);
3120         kfree(udc_controller->status_req);
3121         kfree(udc_controller->eps);
3122
3123         dma_pool_destroy(udc_controller->td_pool);
3124         free_irq(udc_controller->irq, udc_controller);
3125         iounmap(dr_regs);
3126         release_mem_region(res->start, resource_size(res));
3127
3128         device_unregister(&udc_controller->gadget.dev);
3129         /* free udc --wait for the release() finished */
3130         wait_for_completion(&done);
3131
3132         /*
3133          * do platform specific un-initialization:
3134          * release iomux pins, etc.
3135          */
3136         if (pdata->exit)
3137                 pdata->exit(pdev);
3138
3139         return 0;
3140 }
3141
3142 /*-----------------------------------------------------------------
3143  * Modify Power management attributes
3144  * Used by OTG statemachine to disable gadget temporarily
3145  -----------------------------------------------------------------*/
3146 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
3147 {
3148     if (udc_controller->transceiver) {
3149         if (udc_controller->transceiver->state != OTG_STATE_B_PERIPHERAL) {
3150             /* we are not in device mode, return */
3151             return 0;
3152         }
3153     }
3154     if (udc_controller->vbus_active) {
3155         spin_lock(&udc_controller->lock);
3156         /* Reset all internal Queues and inform client driver */
3157         reset_queues(udc_controller);
3158         udc_controller->vbus_active = 0;
3159         udc_controller->usb_state = USB_STATE_DEFAULT;
3160         spin_unlock(&udc_controller->lock);
3161     }
3162     /* stop the controller and turn off the clocks */
3163     dr_controller_stop(udc_controller);
3164     if (udc_controller->transceiver) {
3165         udc_controller->transceiver->state = OTG_STATE_UNDEFINED;
3166     }
3167     fsl_udc_clk_suspend(true);
3168     return 0;
3169 }
3170
3171 /*-----------------------------------------------------------------
3172  * Invoked on USB resume. May be called in_interrupt.
3173  * Here we start the DR controller and enable the irq
3174  *-----------------------------------------------------------------*/
3175 static int fsl_udc_resume(struct platform_device *pdev)
3176 {
3177         if (udc_controller->transceiver) {
3178                 fsl_udc_clk_resume(true);
3179                 if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_ID_PIN_STATUS)) {
3180                         /* If ID status is low means host is connected, return */
3181                         fsl_udc_clk_suspend(false);
3182                         return 0;
3183                 }
3184                 /* check for VBUS */
3185                 if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS)) {
3186                         /* if there is no VBUS then power down the clocks and return */
3187                         fsl_udc_clk_suspend(false);
3188                         return 0;
3189                 } else {
3190                         fsl_udc_clk_suspend(false);
3191                         if (udc_controller->transceiver->state == OTG_STATE_A_HOST)
3192                                 return 0;
3193                         /* Detected VBUS set the transceiver state to device mode */
3194                         udc_controller->transceiver->state = OTG_STATE_B_PERIPHERAL;
3195                 }
3196         }
3197         fsl_udc_clk_resume(true);
3198 #if defined(CONFIG_ARCH_TEGRA)
3199         fsl_udc_restart(udc_controller);
3200 #else
3201         /* Enable DR irq reg and set controller Run */
3202         if (udc_controller->stopped) {
3203                 dr_controller_setup(udc_controller);
3204                 dr_controller_run(udc_controller);
3205         }
3206         udc_controller->usb_state = USB_STATE_ATTACHED;
3207         udc_controller->ep0_state = WAIT_FOR_SETUP;
3208         udc_controller->ep0_dir = 0;
3209 #endif
3210         /* Power down the phy if cable is not connected */
3211         if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS))
3212                 fsl_udc_clk_suspend(false);
3213
3214         return 0;
3215 }
3216
3217 /*-------------------------------------------------------------------------
3218         Register entry point for the peripheral controller driver
3219 --------------------------------------------------------------------------*/
3220
3221 static struct platform_driver udc_driver = {
3222         .remove  = __exit_p(fsl_udc_remove),
3223         /* these suspend and resume are not usb suspend and resume */
3224         .suspend = fsl_udc_suspend,
3225         .resume  = fsl_udc_resume,
3226         .driver  = {
3227                 .name = (char *)driver_name,
3228                 .owner = THIS_MODULE,
3229         },
3230 };
3231
3232 static int __init udc_init(void)
3233 {
3234         printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
3235         return platform_driver_probe(&udc_driver, fsl_udc_probe);
3236 }
3237
3238 module_init(udc_init);
3239
3240 static void __exit udc_exit(void)
3241 {
3242         platform_driver_unregister(&udc_driver);
3243         printk(KERN_WARNING "%s unregistered\n", driver_desc);
3244 }
3245
3246 module_exit(udc_exit);
3247
3248 MODULE_DESCRIPTION(DRIVER_DESC);
3249 MODULE_AUTHOR(DRIVER_AUTHOR);
3250 MODULE_LICENSE("GPL");
3251 MODULE_ALIAS("platform:fsl-usb2-udc");