Revert "ARM: tegra: tegratab: dummy change"
[linux-2.6.git] / drivers / tty / synclinkmp.c
1 /*
2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3  *
4  * Device driver for Microgate SyncLink Multiport
5  * high speed multiprotocol serial adapter.
6  *
7  * written by Paul Fulghum for Microgate Corporation
8  * paulkf@microgate.com
9  *
10  * Microgate and SyncLink are trademarks of Microgate Corporation
11  *
12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13  * This code is released under the GNU General Public License (GPL)
14  *
15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25  * OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 #  define BREAKPOINT() asm("   int $3");
31 #else
32 #  define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
60
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <asm/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85         MGSL_MODE_HDLC,                 /* unsigned long mode */
86         0,                              /* unsigned char loopback; */
87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
89         0,                              /* unsigned long clock_speed; */
90         0xff,                           /* unsigned char addr_filter; */
91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
94         9600,                           /* unsigned long data_rate; */
95         8,                              /* unsigned char data_bits; */
96         1,                              /* unsigned char stop_bits; */
97         ASYNC_PARITY_NONE               /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE      1024
102 #define SCA_MEM_SIZE    0x40000
103 #define SCA_BASE_SIZE   512
104 #define SCA_REG_SIZE    16
105 #define SCA_MAX_PORTS   4
106 #define SCAMAXDESC      128
107
108 #define BUFFERLISTSIZE  4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113         u16     next;           /* lower l6 bits of next descriptor addr */
114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
115         u8      buf_base;       /* upper 8 bits of buffer addr */
116         u8      pad1;
117         u16     length;         /* length of buffer */
118         u8      status;         /* status of buffer */
119         u8      pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124         /* device driver bookkeeping section */
125         char    *virt_addr;     /* virtual address of data buffer */
126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE  1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS   4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct  _input_signal_events {
138         int     ri_up;
139         int     ri_down;
140         int     dsr_up;
141         int     dsr_down;
142         int     dcd_up;
143         int     dcd_down;
144         int     cts_up;
145         int     cts_down;
146 };
147
148 /*
149  * Device instance data structure
150  */
151 typedef struct _synclinkmp_info {
152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
153         int                     magic;
154         struct tty_port         port;
155         int                     line;
156         unsigned short          close_delay;
157         unsigned short          closing_wait;   /* time to wait before closing */
158
159         struct mgsl_icount      icount;
160
161         int                     timeout;
162         int                     x_char;         /* xon/xoff character */
163         u16                     read_status_mask1;  /* break detection (SR1 indications) */
164         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
165         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
166         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
167         unsigned char           *tx_buf;
168         int                     tx_put;
169         int                     tx_get;
170         int                     tx_count;
171
172         wait_queue_head_t       status_event_wait_q;
173         wait_queue_head_t       event_wait_q;
174         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
175         struct _synclinkmp_info *next_device;   /* device list link */
176         struct timer_list       status_timer;   /* input signal status check timer */
177
178         spinlock_t lock;                /* spinlock for synchronizing with ISR */
179         struct work_struct task;                        /* task structure for scheduling bh */
180
181         u32 max_frame_size;                     /* as set by device config */
182
183         u32 pending_bh;
184
185         bool bh_running;                                /* Protection from multiple */
186         int isr_overflow;
187         bool bh_requested;
188
189         int dcd_chkcount;                       /* check counts to prevent */
190         int cts_chkcount;                       /* too many IRQs if a signal */
191         int dsr_chkcount;                       /* is floating */
192         int ri_chkcount;
193
194         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
195         unsigned long buffer_list_phys;
196
197         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
198         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
199         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200         unsigned int current_rx_buf;
201
202         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
203         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
204         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205         unsigned int last_tx_buf;
206
207         unsigned char *tmp_rx_buf;
208         unsigned int tmp_rx_buf_count;
209
210         bool rx_enabled;
211         bool rx_overflow;
212
213         bool tx_enabled;
214         bool tx_active;
215         u32 idle_mode;
216
217         unsigned char ie0_value;
218         unsigned char ie1_value;
219         unsigned char ie2_value;
220         unsigned char ctrlreg_value;
221         unsigned char old_signals;
222
223         char device_name[25];                   /* device instance name */
224
225         int port_count;
226         int adapter_num;
227         int port_num;
228
229         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
232
233         unsigned int irq_level;                 /* interrupt level */
234         unsigned long irq_flags;
235         bool irq_requested;                     /* true if IRQ requested */
236
237         MGSL_PARAMS params;                     /* communications parameters */
238
239         unsigned char serial_signals;           /* current serial signal states */
240
241         bool irq_occurred;                      /* for diagnostics use */
242         unsigned int init_error;                /* Initialization startup error */
243
244         u32 last_mem_alloc;
245         unsigned char* memory_base;             /* shared memory address (PCI only) */
246         u32 phys_memory_base;
247         int shared_mem_requested;
248
249         unsigned char* sca_base;                /* HD64570 SCA Memory address */
250         u32 phys_sca_base;
251         u32 sca_offset;
252         bool sca_base_requested;
253
254         unsigned char* lcr_base;                /* local config registers (PCI only) */
255         u32 phys_lcr_base;
256         u32 lcr_offset;
257         int lcr_mem_requested;
258
259         unsigned char* statctrl_base;           /* status/control register memory */
260         u32 phys_statctrl_base;
261         u32 statctrl_offset;
262         bool sca_statctrl_requested;
263
264         u32 misc_ctrl_value;
265         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
266         char char_buf[MAX_ASYNC_BUFFER_SIZE];
267         bool drop_rts_on_tx_done;
268
269         struct  _input_signal_events    input_signal_events;
270
271         /* SPPP/Cisco HDLC device parts */
272         int netcount;
273         spinlock_t netlock;
274
275 #if SYNCLINK_GENERIC_HDLC
276         struct net_device *netdev;
277 #endif
278
279 } SLMP_INFO;
280
281 #define MGSL_MAGIC 0x5401
282
283 /*
284  * define serial signal status change macros
285  */
286 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
287 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
288 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
289 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
290
291 /* Common Register macros */
292 #define LPR     0x00
293 #define PABR0   0x02
294 #define PABR1   0x03
295 #define WCRL    0x04
296 #define WCRM    0x05
297 #define WCRH    0x06
298 #define DPCR    0x08
299 #define DMER    0x09
300 #define ISR0    0x10
301 #define ISR1    0x11
302 #define ISR2    0x12
303 #define IER0    0x14
304 #define IER1    0x15
305 #define IER2    0x16
306 #define ITCR    0x18
307 #define INTVR   0x1a
308 #define IMVR    0x1c
309
310 /* MSCI Register macros */
311 #define TRB     0x20
312 #define TRBL    0x20
313 #define TRBH    0x21
314 #define SR0     0x22
315 #define SR1     0x23
316 #define SR2     0x24
317 #define SR3     0x25
318 #define FST     0x26
319 #define IE0     0x28
320 #define IE1     0x29
321 #define IE2     0x2a
322 #define FIE     0x2b
323 #define CMD     0x2c
324 #define MD0     0x2e
325 #define MD1     0x2f
326 #define MD2     0x30
327 #define CTL     0x31
328 #define SA0     0x32
329 #define SA1     0x33
330 #define IDL     0x34
331 #define TMC     0x35
332 #define RXS     0x36
333 #define TXS     0x37
334 #define TRC0    0x38
335 #define TRC1    0x39
336 #define RRC     0x3a
337 #define CST0    0x3c
338 #define CST1    0x3d
339
340 /* Timer Register Macros */
341 #define TCNT    0x60
342 #define TCNTL   0x60
343 #define TCNTH   0x61
344 #define TCONR   0x62
345 #define TCONRL  0x62
346 #define TCONRH  0x63
347 #define TMCS    0x64
348 #define TEPR    0x65
349
350 /* DMA Controller Register macros */
351 #define DARL    0x80
352 #define DARH    0x81
353 #define DARB    0x82
354 #define BAR     0x80
355 #define BARL    0x80
356 #define BARH    0x81
357 #define BARB    0x82
358 #define SAR     0x84
359 #define SARL    0x84
360 #define SARH    0x85
361 #define SARB    0x86
362 #define CPB     0x86
363 #define CDA     0x88
364 #define CDAL    0x88
365 #define CDAH    0x89
366 #define EDA     0x8a
367 #define EDAL    0x8a
368 #define EDAH    0x8b
369 #define BFL     0x8c
370 #define BFLL    0x8c
371 #define BFLH    0x8d
372 #define BCR     0x8e
373 #define BCRL    0x8e
374 #define BCRH    0x8f
375 #define DSR     0x90
376 #define DMR     0x91
377 #define FCT     0x93
378 #define DIR     0x94
379 #define DCMD    0x95
380
381 /* combine with timer or DMA register address */
382 #define TIMER0  0x00
383 #define TIMER1  0x08
384 #define TIMER2  0x10
385 #define TIMER3  0x18
386 #define RXDMA   0x00
387 #define TXDMA   0x20
388
389 /* SCA Command Codes */
390 #define NOOP            0x00
391 #define TXRESET         0x01
392 #define TXENABLE        0x02
393 #define TXDISABLE       0x03
394 #define TXCRCINIT       0x04
395 #define TXCRCEXCL       0x05
396 #define TXEOM           0x06
397 #define TXABORT         0x07
398 #define MPON            0x08
399 #define TXBUFCLR        0x09
400 #define RXRESET         0x11
401 #define RXENABLE        0x12
402 #define RXDISABLE       0x13
403 #define RXCRCINIT       0x14
404 #define RXREJECT        0x15
405 #define SEARCHMP        0x16
406 #define RXCRCEXCL       0x17
407 #define RXCRCCALC       0x18
408 #define CHRESET         0x21
409 #define HUNT            0x31
410
411 /* DMA command codes */
412 #define SWABORT         0x01
413 #define FEICLEAR        0x02
414
415 /* IE0 */
416 #define TXINTE          BIT7
417 #define RXINTE          BIT6
418 #define TXRDYE          BIT1
419 #define RXRDYE          BIT0
420
421 /* IE1 & SR1 */
422 #define UDRN    BIT7
423 #define IDLE    BIT6
424 #define SYNCD   BIT4
425 #define FLGD    BIT4
426 #define CCTS    BIT3
427 #define CDCD    BIT2
428 #define BRKD    BIT1
429 #define ABTD    BIT1
430 #define GAPD    BIT1
431 #define BRKE    BIT0
432 #define IDLD    BIT0
433
434 /* IE2 & SR2 */
435 #define EOM     BIT7
436 #define PMP     BIT6
437 #define SHRT    BIT6
438 #define PE      BIT5
439 #define ABT     BIT5
440 #define FRME    BIT4
441 #define RBIT    BIT4
442 #define OVRN    BIT3
443 #define CRCE    BIT2
444
445
446 /*
447  * Global linked list of SyncLink devices
448  */
449 static SLMP_INFO *synclinkmp_device_list = NULL;
450 static int synclinkmp_adapter_count = -1;
451 static int synclinkmp_device_count = 0;
452
453 /*
454  * Set this param to non-zero to load eax with the
455  * .text section address and breakpoint on module load.
456  * This is useful for use with gdb and add-symbol-file command.
457  */
458 static bool break_on_load = 0;
459
460 /*
461  * Driver major number, defaults to zero to get auto
462  * assigned major number. May be forced as module parameter.
463  */
464 static int ttymajor = 0;
465
466 /*
467  * Array of user specified options for ISA adapters.
468  */
469 static int debug_level = 0;
470 static int maxframe[MAX_DEVICES] = {0,};
471
472 module_param(break_on_load, bool, 0);
473 module_param(ttymajor, int, 0);
474 module_param(debug_level, int, 0);
475 module_param_array(maxframe, int, NULL, 0);
476
477 static char *driver_name = "SyncLink MultiPort driver";
478 static char *driver_version = "$Revision: 4.38 $";
479
480 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
481 static void synclinkmp_remove_one(struct pci_dev *dev);
482
483 static struct pci_device_id synclinkmp_pci_tbl[] = {
484         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
485         { 0, }, /* terminate list */
486 };
487 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
488
489 MODULE_LICENSE("GPL");
490
491 static struct pci_driver synclinkmp_pci_driver = {
492         .name           = "synclinkmp",
493         .id_table       = synclinkmp_pci_tbl,
494         .probe          = synclinkmp_init_one,
495         .remove         = __devexit_p(synclinkmp_remove_one),
496 };
497
498
499 static struct tty_driver *serial_driver;
500
501 /* number of characters left in xmit buffer before we ask for more */
502 #define WAKEUP_CHARS 256
503
504
505 /* tty callbacks */
506
507 static int  open(struct tty_struct *tty, struct file * filp);
508 static void close(struct tty_struct *tty, struct file * filp);
509 static void hangup(struct tty_struct *tty);
510 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
511
512 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
513 static int put_char(struct tty_struct *tty, unsigned char ch);
514 static void send_xchar(struct tty_struct *tty, char ch);
515 static void wait_until_sent(struct tty_struct *tty, int timeout);
516 static int  write_room(struct tty_struct *tty);
517 static void flush_chars(struct tty_struct *tty);
518 static void flush_buffer(struct tty_struct *tty);
519 static void tx_hold(struct tty_struct *tty);
520 static void tx_release(struct tty_struct *tty);
521
522 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
523 static int  chars_in_buffer(struct tty_struct *tty);
524 static void throttle(struct tty_struct * tty);
525 static void unthrottle(struct tty_struct * tty);
526 static int set_break(struct tty_struct *tty, int break_state);
527
528 #if SYNCLINK_GENERIC_HDLC
529 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
530 static void hdlcdev_tx_done(SLMP_INFO *info);
531 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
532 static int  hdlcdev_init(SLMP_INFO *info);
533 static void hdlcdev_exit(SLMP_INFO *info);
534 #endif
535
536 /* ioctl handlers */
537
538 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
539 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
541 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
542 static int  set_txidle(SLMP_INFO *info, int idle_mode);
543 static int  tx_enable(SLMP_INFO *info, int enable);
544 static int  tx_abort(SLMP_INFO *info);
545 static int  rx_enable(SLMP_INFO *info, int enable);
546 static int  modem_input_wait(SLMP_INFO *info,int arg);
547 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
548 static int  tiocmget(struct tty_struct *tty);
549 static int  tiocmset(struct tty_struct *tty,
550                         unsigned int set, unsigned int clear);
551 static int  set_break(struct tty_struct *tty, int break_state);
552
553 static void add_device(SLMP_INFO *info);
554 static void device_init(int adapter_num, struct pci_dev *pdev);
555 static int  claim_resources(SLMP_INFO *info);
556 static void release_resources(SLMP_INFO *info);
557
558 static int  startup(SLMP_INFO *info);
559 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
560 static int carrier_raised(struct tty_port *port);
561 static void shutdown(SLMP_INFO *info);
562 static void program_hw(SLMP_INFO *info);
563 static void change_params(SLMP_INFO *info);
564
565 static bool init_adapter(SLMP_INFO *info);
566 static bool register_test(SLMP_INFO *info);
567 static bool irq_test(SLMP_INFO *info);
568 static bool loopback_test(SLMP_INFO *info);
569 static int  adapter_test(SLMP_INFO *info);
570 static bool memory_test(SLMP_INFO *info);
571
572 static void reset_adapter(SLMP_INFO *info);
573 static void reset_port(SLMP_INFO *info);
574 static void async_mode(SLMP_INFO *info);
575 static void hdlc_mode(SLMP_INFO *info);
576
577 static void rx_stop(SLMP_INFO *info);
578 static void rx_start(SLMP_INFO *info);
579 static void rx_reset_buffers(SLMP_INFO *info);
580 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
581 static bool rx_get_frame(SLMP_INFO *info);
582
583 static void tx_start(SLMP_INFO *info);
584 static void tx_stop(SLMP_INFO *info);
585 static void tx_load_fifo(SLMP_INFO *info);
586 static void tx_set_idle(SLMP_INFO *info);
587 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
588
589 static void get_signals(SLMP_INFO *info);
590 static void set_signals(SLMP_INFO *info);
591 static void enable_loopback(SLMP_INFO *info, int enable);
592 static void set_rate(SLMP_INFO *info, u32 data_rate);
593
594 static int  bh_action(SLMP_INFO *info);
595 static void bh_handler(struct work_struct *work);
596 static void bh_receive(SLMP_INFO *info);
597 static void bh_transmit(SLMP_INFO *info);
598 static void bh_status(SLMP_INFO *info);
599 static void isr_timer(SLMP_INFO *info);
600 static void isr_rxint(SLMP_INFO *info);
601 static void isr_rxrdy(SLMP_INFO *info);
602 static void isr_txint(SLMP_INFO *info);
603 static void isr_txrdy(SLMP_INFO *info);
604 static void isr_rxdmaok(SLMP_INFO *info);
605 static void isr_rxdmaerror(SLMP_INFO *info);
606 static void isr_txdmaok(SLMP_INFO *info);
607 static void isr_txdmaerror(SLMP_INFO *info);
608 static void isr_io_pin(SLMP_INFO *info, u16 status);
609
610 static int  alloc_dma_bufs(SLMP_INFO *info);
611 static void free_dma_bufs(SLMP_INFO *info);
612 static int  alloc_buf_list(SLMP_INFO *info);
613 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
614 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
615 static void free_tmp_rx_buf(SLMP_INFO *info);
616
617 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
618 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
619 static void tx_timeout(unsigned long context);
620 static void status_timeout(unsigned long context);
621
622 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
623 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
624 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
625 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
626 static unsigned char read_status_reg(SLMP_INFO * info);
627 static void write_control_reg(SLMP_INFO * info);
628
629
630 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
631 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
632 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
633
634 static u32 misc_ctrl_value = 0x007e4040;
635 static u32 lcr1_brdr_value = 0x00800028;
636
637 static u32 read_ahead_count = 8;
638
639 /* DPCR, DMA Priority Control
640  *
641  * 07..05  Not used, must be 0
642  * 04      BRC, bus release condition: 0=all transfers complete
643  *              1=release after 1 xfer on all channels
644  * 03      CCC, channel change condition: 0=every cycle
645  *              1=after each channel completes all xfers
646  * 02..00  PR<2..0>, priority 100=round robin
647  *
648  * 00000100 = 0x00
649  */
650 static unsigned char dma_priority = 0x04;
651
652 // Number of bytes that can be written to shared RAM
653 // in a single write operation
654 static u32 sca_pci_load_interval = 64;
655
656 /*
657  * 1st function defined in .text section. Calling this function in
658  * init_module() followed by a breakpoint allows a remote debugger
659  * (gdb) to get the .text address for the add-symbol-file command.
660  * This allows remote debugging of dynamically loadable modules.
661  */
662 static void* synclinkmp_get_text_ptr(void);
663 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
664
665 static inline int sanity_check(SLMP_INFO *info,
666                                char *name, const char *routine)
667 {
668 #ifdef SANITY_CHECK
669         static const char *badmagic =
670                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
671         static const char *badinfo =
672                 "Warning: null synclinkmp_struct for (%s) in %s\n";
673
674         if (!info) {
675                 printk(badinfo, name, routine);
676                 return 1;
677         }
678         if (info->magic != MGSL_MAGIC) {
679                 printk(badmagic, name, routine);
680                 return 1;
681         }
682 #else
683         if (!info)
684                 return 1;
685 #endif
686         return 0;
687 }
688
689 /**
690  * line discipline callback wrappers
691  *
692  * The wrappers maintain line discipline references
693  * while calling into the line discipline.
694  *
695  * ldisc_receive_buf  - pass receive data to line discipline
696  */
697
698 static void ldisc_receive_buf(struct tty_struct *tty,
699                               const __u8 *data, char *flags, int count)
700 {
701         struct tty_ldisc *ld;
702         if (!tty)
703                 return;
704         ld = tty_ldisc_ref(tty);
705         if (ld) {
706                 if (ld->ops->receive_buf)
707                         ld->ops->receive_buf(tty, data, flags, count);
708                 tty_ldisc_deref(ld);
709         }
710 }
711
712 /* tty callbacks */
713
714 /* Called when a port is opened.  Init and enable port.
715  */
716 static int open(struct tty_struct *tty, struct file *filp)
717 {
718         SLMP_INFO *info;
719         int retval, line;
720         unsigned long flags;
721
722         line = tty->index;
723         if (line >= synclinkmp_device_count) {
724                 printk("%s(%d): open with invalid line #%d.\n",
725                         __FILE__,__LINE__,line);
726                 return -ENODEV;
727         }
728
729         info = synclinkmp_device_list;
730         while(info && info->line != line)
731                 info = info->next_device;
732         if (sanity_check(info, tty->name, "open"))
733                 return -ENODEV;
734         if ( info->init_error ) {
735                 printk("%s(%d):%s device is not allocated, init error=%d\n",
736                         __FILE__,__LINE__,info->device_name,info->init_error);
737                 return -ENODEV;
738         }
739
740         tty->driver_data = info;
741         info->port.tty = tty;
742
743         if (debug_level >= DEBUG_LEVEL_INFO)
744                 printk("%s(%d):%s open(), old ref count = %d\n",
745                          __FILE__,__LINE__,tty->driver->name, info->port.count);
746
747         /* If port is closing, signal caller to try again */
748         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
749                 if (info->port.flags & ASYNC_CLOSING)
750                         interruptible_sleep_on(&info->port.close_wait);
751                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
752                         -EAGAIN : -ERESTARTSYS);
753                 goto cleanup;
754         }
755
756         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
757
758         spin_lock_irqsave(&info->netlock, flags);
759         if (info->netcount) {
760                 retval = -EBUSY;
761                 spin_unlock_irqrestore(&info->netlock, flags);
762                 goto cleanup;
763         }
764         info->port.count++;
765         spin_unlock_irqrestore(&info->netlock, flags);
766
767         if (info->port.count == 1) {
768                 /* 1st open on this device, init hardware */
769                 retval = startup(info);
770                 if (retval < 0)
771                         goto cleanup;
772         }
773
774         retval = block_til_ready(tty, filp, info);
775         if (retval) {
776                 if (debug_level >= DEBUG_LEVEL_INFO)
777                         printk("%s(%d):%s block_til_ready() returned %d\n",
778                                  __FILE__,__LINE__, info->device_name, retval);
779                 goto cleanup;
780         }
781
782         if (debug_level >= DEBUG_LEVEL_INFO)
783                 printk("%s(%d):%s open() success\n",
784                          __FILE__,__LINE__, info->device_name);
785         retval = 0;
786
787 cleanup:
788         if (retval) {
789                 if (tty->count == 1)
790                         info->port.tty = NULL; /* tty layer will release tty struct */
791                 if(info->port.count)
792                         info->port.count--;
793         }
794
795         return retval;
796 }
797
798 /* Called when port is closed. Wait for remaining data to be
799  * sent. Disable port and free resources.
800  */
801 static void close(struct tty_struct *tty, struct file *filp)
802 {
803         SLMP_INFO * info = tty->driver_data;
804
805         if (sanity_check(info, tty->name, "close"))
806                 return;
807
808         if (debug_level >= DEBUG_LEVEL_INFO)
809                 printk("%s(%d):%s close() entry, count=%d\n",
810                          __FILE__,__LINE__, info->device_name, info->port.count);
811
812         if (tty_port_close_start(&info->port, tty, filp) == 0)
813                 goto cleanup;
814
815         mutex_lock(&info->port.mutex);
816         if (info->port.flags & ASYNC_INITIALIZED)
817                 wait_until_sent(tty, info->timeout);
818
819         flush_buffer(tty);
820         tty_ldisc_flush(tty);
821         shutdown(info);
822         mutex_unlock(&info->port.mutex);
823
824         tty_port_close_end(&info->port, tty);
825         info->port.tty = NULL;
826 cleanup:
827         if (debug_level >= DEBUG_LEVEL_INFO)
828                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
829                         tty->driver->name, info->port.count);
830 }
831
832 /* Called by tty_hangup() when a hangup is signaled.
833  * This is the same as closing all open descriptors for the port.
834  */
835 static void hangup(struct tty_struct *tty)
836 {
837         SLMP_INFO *info = tty->driver_data;
838         unsigned long flags;
839
840         if (debug_level >= DEBUG_LEVEL_INFO)
841                 printk("%s(%d):%s hangup()\n",
842                          __FILE__,__LINE__, info->device_name );
843
844         if (sanity_check(info, tty->name, "hangup"))
845                 return;
846
847         mutex_lock(&info->port.mutex);
848         flush_buffer(tty);
849         shutdown(info);
850
851         spin_lock_irqsave(&info->port.lock, flags);
852         info->port.count = 0;
853         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
854         info->port.tty = NULL;
855         spin_unlock_irqrestore(&info->port.lock, flags);
856         mutex_unlock(&info->port.mutex);
857
858         wake_up_interruptible(&info->port.open_wait);
859 }
860
861 /* Set new termios settings
862  */
863 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
864 {
865         SLMP_INFO *info = tty->driver_data;
866         unsigned long flags;
867
868         if (debug_level >= DEBUG_LEVEL_INFO)
869                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
870                         tty->driver->name );
871
872         change_params(info);
873
874         /* Handle transition to B0 status */
875         if (old_termios->c_cflag & CBAUD &&
876             !(tty->termios->c_cflag & CBAUD)) {
877                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
878                 spin_lock_irqsave(&info->lock,flags);
879                 set_signals(info);
880                 spin_unlock_irqrestore(&info->lock,flags);
881         }
882
883         /* Handle transition away from B0 status */
884         if (!(old_termios->c_cflag & CBAUD) &&
885             tty->termios->c_cflag & CBAUD) {
886                 info->serial_signals |= SerialSignal_DTR;
887                 if (!(tty->termios->c_cflag & CRTSCTS) ||
888                     !test_bit(TTY_THROTTLED, &tty->flags)) {
889                         info->serial_signals |= SerialSignal_RTS;
890                 }
891                 spin_lock_irqsave(&info->lock,flags);
892                 set_signals(info);
893                 spin_unlock_irqrestore(&info->lock,flags);
894         }
895
896         /* Handle turning off CRTSCTS */
897         if (old_termios->c_cflag & CRTSCTS &&
898             !(tty->termios->c_cflag & CRTSCTS)) {
899                 tty->hw_stopped = 0;
900                 tx_release(tty);
901         }
902 }
903
904 /* Send a block of data
905  *
906  * Arguments:
907  *
908  *      tty             pointer to tty information structure
909  *      buf             pointer to buffer containing send data
910  *      count           size of send data in bytes
911  *
912  * Return Value:        number of characters written
913  */
914 static int write(struct tty_struct *tty,
915                  const unsigned char *buf, int count)
916 {
917         int     c, ret = 0;
918         SLMP_INFO *info = tty->driver_data;
919         unsigned long flags;
920
921         if (debug_level >= DEBUG_LEVEL_INFO)
922                 printk("%s(%d):%s write() count=%d\n",
923                        __FILE__,__LINE__,info->device_name,count);
924
925         if (sanity_check(info, tty->name, "write"))
926                 goto cleanup;
927
928         if (!info->tx_buf)
929                 goto cleanup;
930
931         if (info->params.mode == MGSL_MODE_HDLC) {
932                 if (count > info->max_frame_size) {
933                         ret = -EIO;
934                         goto cleanup;
935                 }
936                 if (info->tx_active)
937                         goto cleanup;
938                 if (info->tx_count) {
939                         /* send accumulated data from send_char() calls */
940                         /* as frame and wait before accepting more data. */
941                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
942                         goto start;
943                 }
944                 ret = info->tx_count = count;
945                 tx_load_dma_buffer(info, buf, count);
946                 goto start;
947         }
948
949         for (;;) {
950                 c = min_t(int, count,
951                         min(info->max_frame_size - info->tx_count - 1,
952                             info->max_frame_size - info->tx_put));
953                 if (c <= 0)
954                         break;
955                         
956                 memcpy(info->tx_buf + info->tx_put, buf, c);
957
958                 spin_lock_irqsave(&info->lock,flags);
959                 info->tx_put += c;
960                 if (info->tx_put >= info->max_frame_size)
961                         info->tx_put -= info->max_frame_size;
962                 info->tx_count += c;
963                 spin_unlock_irqrestore(&info->lock,flags);
964
965                 buf += c;
966                 count -= c;
967                 ret += c;
968         }
969
970         if (info->params.mode == MGSL_MODE_HDLC) {
971                 if (count) {
972                         ret = info->tx_count = 0;
973                         goto cleanup;
974                 }
975                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
976         }
977 start:
978         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
979                 spin_lock_irqsave(&info->lock,flags);
980                 if (!info->tx_active)
981                         tx_start(info);
982                 spin_unlock_irqrestore(&info->lock,flags);
983         }
984
985 cleanup:
986         if (debug_level >= DEBUG_LEVEL_INFO)
987                 printk( "%s(%d):%s write() returning=%d\n",
988                         __FILE__,__LINE__,info->device_name,ret);
989         return ret;
990 }
991
992 /* Add a character to the transmit buffer.
993  */
994 static int put_char(struct tty_struct *tty, unsigned char ch)
995 {
996         SLMP_INFO *info = tty->driver_data;
997         unsigned long flags;
998         int ret = 0;
999
1000         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1001                 printk( "%s(%d):%s put_char(%d)\n",
1002                         __FILE__,__LINE__,info->device_name,ch);
1003         }
1004
1005         if (sanity_check(info, tty->name, "put_char"))
1006                 return 0;
1007
1008         if (!info->tx_buf)
1009                 return 0;
1010
1011         spin_lock_irqsave(&info->lock,flags);
1012
1013         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1014              !info->tx_active ) {
1015
1016                 if (info->tx_count < info->max_frame_size - 1) {
1017                         info->tx_buf[info->tx_put++] = ch;
1018                         if (info->tx_put >= info->max_frame_size)
1019                                 info->tx_put -= info->max_frame_size;
1020                         info->tx_count++;
1021                         ret = 1;
1022                 }
1023         }
1024
1025         spin_unlock_irqrestore(&info->lock,flags);
1026         return ret;
1027 }
1028
1029 /* Send a high-priority XON/XOFF character
1030  */
1031 static void send_xchar(struct tty_struct *tty, char ch)
1032 {
1033         SLMP_INFO *info = tty->driver_data;
1034         unsigned long flags;
1035
1036         if (debug_level >= DEBUG_LEVEL_INFO)
1037                 printk("%s(%d):%s send_xchar(%d)\n",
1038                          __FILE__,__LINE__, info->device_name, ch );
1039
1040         if (sanity_check(info, tty->name, "send_xchar"))
1041                 return;
1042
1043         info->x_char = ch;
1044         if (ch) {
1045                 /* Make sure transmit interrupts are on */
1046                 spin_lock_irqsave(&info->lock,flags);
1047                 if (!info->tx_enabled)
1048                         tx_start(info);
1049                 spin_unlock_irqrestore(&info->lock,flags);
1050         }
1051 }
1052
1053 /* Wait until the transmitter is empty.
1054  */
1055 static void wait_until_sent(struct tty_struct *tty, int timeout)
1056 {
1057         SLMP_INFO * info = tty->driver_data;
1058         unsigned long orig_jiffies, char_time;
1059
1060         if (!info )
1061                 return;
1062
1063         if (debug_level >= DEBUG_LEVEL_INFO)
1064                 printk("%s(%d):%s wait_until_sent() entry\n",
1065                          __FILE__,__LINE__, info->device_name );
1066
1067         if (sanity_check(info, tty->name, "wait_until_sent"))
1068                 return;
1069
1070         if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1071                 goto exit;
1072
1073         orig_jiffies = jiffies;
1074
1075         /* Set check interval to 1/5 of estimated time to
1076          * send a character, and make it at least 1. The check
1077          * interval should also be less than the timeout.
1078          * Note: use tight timings here to satisfy the NIST-PCTS.
1079          */
1080
1081         if ( info->params.data_rate ) {
1082                 char_time = info->timeout/(32 * 5);
1083                 if (!char_time)
1084                         char_time++;
1085         } else
1086                 char_time = 1;
1087
1088         if (timeout)
1089                 char_time = min_t(unsigned long, char_time, timeout);
1090
1091         if ( info->params.mode == MGSL_MODE_HDLC ) {
1092                 while (info->tx_active) {
1093                         msleep_interruptible(jiffies_to_msecs(char_time));
1094                         if (signal_pending(current))
1095                                 break;
1096                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1097                                 break;
1098                 }
1099         } else {
1100                 /*
1101                  * TODO: determine if there is something similar to USC16C32
1102                  *       TXSTATUS_ALL_SENT status
1103                  */
1104                 while ( info->tx_active && info->tx_enabled) {
1105                         msleep_interruptible(jiffies_to_msecs(char_time));
1106                         if (signal_pending(current))
1107                                 break;
1108                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1109                                 break;
1110                 }
1111         }
1112
1113 exit:
1114         if (debug_level >= DEBUG_LEVEL_INFO)
1115                 printk("%s(%d):%s wait_until_sent() exit\n",
1116                          __FILE__,__LINE__, info->device_name );
1117 }
1118
1119 /* Return the count of free bytes in transmit buffer
1120  */
1121 static int write_room(struct tty_struct *tty)
1122 {
1123         SLMP_INFO *info = tty->driver_data;
1124         int ret;
1125
1126         if (sanity_check(info, tty->name, "write_room"))
1127                 return 0;
1128
1129         if (info->params.mode == MGSL_MODE_HDLC) {
1130                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1131         } else {
1132                 ret = info->max_frame_size - info->tx_count - 1;
1133                 if (ret < 0)
1134                         ret = 0;
1135         }
1136
1137         if (debug_level >= DEBUG_LEVEL_INFO)
1138                 printk("%s(%d):%s write_room()=%d\n",
1139                        __FILE__, __LINE__, info->device_name, ret);
1140
1141         return ret;
1142 }
1143
1144 /* enable transmitter and send remaining buffered characters
1145  */
1146 static void flush_chars(struct tty_struct *tty)
1147 {
1148         SLMP_INFO *info = tty->driver_data;
1149         unsigned long flags;
1150
1151         if ( debug_level >= DEBUG_LEVEL_INFO )
1152                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1153                         __FILE__,__LINE__,info->device_name,info->tx_count);
1154
1155         if (sanity_check(info, tty->name, "flush_chars"))
1156                 return;
1157
1158         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1159             !info->tx_buf)
1160                 return;
1161
1162         if ( debug_level >= DEBUG_LEVEL_INFO )
1163                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1164                         __FILE__,__LINE__,info->device_name );
1165
1166         spin_lock_irqsave(&info->lock,flags);
1167
1168         if (!info->tx_active) {
1169                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1170                         info->tx_count ) {
1171                         /* operating in synchronous (frame oriented) mode */
1172                         /* copy data from circular tx_buf to */
1173                         /* transmit DMA buffer. */
1174                         tx_load_dma_buffer(info,
1175                                  info->tx_buf,info->tx_count);
1176                 }
1177                 tx_start(info);
1178         }
1179
1180         spin_unlock_irqrestore(&info->lock,flags);
1181 }
1182
1183 /* Discard all data in the send buffer
1184  */
1185 static void flush_buffer(struct tty_struct *tty)
1186 {
1187         SLMP_INFO *info = tty->driver_data;
1188         unsigned long flags;
1189
1190         if (debug_level >= DEBUG_LEVEL_INFO)
1191                 printk("%s(%d):%s flush_buffer() entry\n",
1192                          __FILE__,__LINE__, info->device_name );
1193
1194         if (sanity_check(info, tty->name, "flush_buffer"))
1195                 return;
1196
1197         spin_lock_irqsave(&info->lock,flags);
1198         info->tx_count = info->tx_put = info->tx_get = 0;
1199         del_timer(&info->tx_timer);
1200         spin_unlock_irqrestore(&info->lock,flags);
1201
1202         tty_wakeup(tty);
1203 }
1204
1205 /* throttle (stop) transmitter
1206  */
1207 static void tx_hold(struct tty_struct *tty)
1208 {
1209         SLMP_INFO *info = tty->driver_data;
1210         unsigned long flags;
1211
1212         if (sanity_check(info, tty->name, "tx_hold"))
1213                 return;
1214
1215         if ( debug_level >= DEBUG_LEVEL_INFO )
1216                 printk("%s(%d):%s tx_hold()\n",
1217                         __FILE__,__LINE__,info->device_name);
1218
1219         spin_lock_irqsave(&info->lock,flags);
1220         if (info->tx_enabled)
1221                 tx_stop(info);
1222         spin_unlock_irqrestore(&info->lock,flags);
1223 }
1224
1225 /* release (start) transmitter
1226  */
1227 static void tx_release(struct tty_struct *tty)
1228 {
1229         SLMP_INFO *info = tty->driver_data;
1230         unsigned long flags;
1231
1232         if (sanity_check(info, tty->name, "tx_release"))
1233                 return;
1234
1235         if ( debug_level >= DEBUG_LEVEL_INFO )
1236                 printk("%s(%d):%s tx_release()\n",
1237                         __FILE__,__LINE__,info->device_name);
1238
1239         spin_lock_irqsave(&info->lock,flags);
1240         if (!info->tx_enabled)
1241                 tx_start(info);
1242         spin_unlock_irqrestore(&info->lock,flags);
1243 }
1244
1245 /* Service an IOCTL request
1246  *
1247  * Arguments:
1248  *
1249  *      tty     pointer to tty instance data
1250  *      cmd     IOCTL command code
1251  *      arg     command argument/context
1252  *
1253  * Return Value:        0 if success, otherwise error code
1254  */
1255 static int ioctl(struct tty_struct *tty,
1256                  unsigned int cmd, unsigned long arg)
1257 {
1258         SLMP_INFO *info = tty->driver_data;
1259         void __user *argp = (void __user *)arg;
1260
1261         if (debug_level >= DEBUG_LEVEL_INFO)
1262                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1263                         info->device_name, cmd );
1264
1265         if (sanity_check(info, tty->name, "ioctl"))
1266                 return -ENODEV;
1267
1268         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1269             (cmd != TIOCMIWAIT)) {
1270                 if (tty->flags & (1 << TTY_IO_ERROR))
1271                     return -EIO;
1272         }
1273
1274         switch (cmd) {
1275         case MGSL_IOCGPARAMS:
1276                 return get_params(info, argp);
1277         case MGSL_IOCSPARAMS:
1278                 return set_params(info, argp);
1279         case MGSL_IOCGTXIDLE:
1280                 return get_txidle(info, argp);
1281         case MGSL_IOCSTXIDLE:
1282                 return set_txidle(info, (int)arg);
1283         case MGSL_IOCTXENABLE:
1284                 return tx_enable(info, (int)arg);
1285         case MGSL_IOCRXENABLE:
1286                 return rx_enable(info, (int)arg);
1287         case MGSL_IOCTXABORT:
1288                 return tx_abort(info);
1289         case MGSL_IOCGSTATS:
1290                 return get_stats(info, argp);
1291         case MGSL_IOCWAITEVENT:
1292                 return wait_mgsl_event(info, argp);
1293         case MGSL_IOCLOOPTXDONE:
1294                 return 0; // TODO: Not supported, need to document
1295                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1296                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1297                  */
1298         case TIOCMIWAIT:
1299                 return modem_input_wait(info,(int)arg);
1300                 
1301                 /*
1302                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1303                  * Return: write counters to the user passed counter struct
1304                  * NB: both 1->0 and 0->1 transitions are counted except for
1305                  *     RI where only 0->1 is counted.
1306                  */
1307         default:
1308                 return -ENOIOCTLCMD;
1309         }
1310         return 0;
1311 }
1312
1313 static int get_icount(struct tty_struct *tty,
1314                                 struct serial_icounter_struct *icount)
1315 {
1316         SLMP_INFO *info = tty->driver_data;
1317         struct mgsl_icount cnow;        /* kernel counter temps */
1318         unsigned long flags;
1319
1320         spin_lock_irqsave(&info->lock,flags);
1321         cnow = info->icount;
1322         spin_unlock_irqrestore(&info->lock,flags);
1323
1324         icount->cts = cnow.cts;
1325         icount->dsr = cnow.dsr;
1326         icount->rng = cnow.rng;
1327         icount->dcd = cnow.dcd;
1328         icount->rx = cnow.rx;
1329         icount->tx = cnow.tx;
1330         icount->frame = cnow.frame;
1331         icount->overrun = cnow.overrun;
1332         icount->parity = cnow.parity;
1333         icount->brk = cnow.brk;
1334         icount->buf_overrun = cnow.buf_overrun;
1335
1336         return 0;
1337 }
1338
1339 /*
1340  * /proc fs routines....
1341  */
1342
1343 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1344 {
1345         char    stat_buf[30];
1346         unsigned long flags;
1347
1348         seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1349                        "\tIRQ=%d MaxFrameSize=%u\n",
1350                 info->device_name,
1351                 info->phys_sca_base,
1352                 info->phys_memory_base,
1353                 info->phys_statctrl_base,
1354                 info->phys_lcr_base,
1355                 info->irq_level,
1356                 info->max_frame_size );
1357
1358         /* output current serial signal states */
1359         spin_lock_irqsave(&info->lock,flags);
1360         get_signals(info);
1361         spin_unlock_irqrestore(&info->lock,flags);
1362
1363         stat_buf[0] = 0;
1364         stat_buf[1] = 0;
1365         if (info->serial_signals & SerialSignal_RTS)
1366                 strcat(stat_buf, "|RTS");
1367         if (info->serial_signals & SerialSignal_CTS)
1368                 strcat(stat_buf, "|CTS");
1369         if (info->serial_signals & SerialSignal_DTR)
1370                 strcat(stat_buf, "|DTR");
1371         if (info->serial_signals & SerialSignal_DSR)
1372                 strcat(stat_buf, "|DSR");
1373         if (info->serial_signals & SerialSignal_DCD)
1374                 strcat(stat_buf, "|CD");
1375         if (info->serial_signals & SerialSignal_RI)
1376                 strcat(stat_buf, "|RI");
1377
1378         if (info->params.mode == MGSL_MODE_HDLC) {
1379                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1380                               info->icount.txok, info->icount.rxok);
1381                 if (info->icount.txunder)
1382                         seq_printf(m, " txunder:%d", info->icount.txunder);
1383                 if (info->icount.txabort)
1384                         seq_printf(m, " txabort:%d", info->icount.txabort);
1385                 if (info->icount.rxshort)
1386                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1387                 if (info->icount.rxlong)
1388                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1389                 if (info->icount.rxover)
1390                         seq_printf(m, " rxover:%d", info->icount.rxover);
1391                 if (info->icount.rxcrc)
1392                         seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1393         } else {
1394                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1395                               info->icount.tx, info->icount.rx);
1396                 if (info->icount.frame)
1397                         seq_printf(m, " fe:%d", info->icount.frame);
1398                 if (info->icount.parity)
1399                         seq_printf(m, " pe:%d", info->icount.parity);
1400                 if (info->icount.brk)
1401                         seq_printf(m, " brk:%d", info->icount.brk);
1402                 if (info->icount.overrun)
1403                         seq_printf(m, " oe:%d", info->icount.overrun);
1404         }
1405
1406         /* Append serial signal status to end */
1407         seq_printf(m, " %s\n", stat_buf+1);
1408
1409         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1410          info->tx_active,info->bh_requested,info->bh_running,
1411          info->pending_bh);
1412 }
1413
1414 /* Called to print information about devices
1415  */
1416 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1417 {
1418         SLMP_INFO *info;
1419
1420         seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1421
1422         info = synclinkmp_device_list;
1423         while( info ) {
1424                 line_info(m, info);
1425                 info = info->next_device;
1426         }
1427         return 0;
1428 }
1429
1430 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1431 {
1432         return single_open(file, synclinkmp_proc_show, NULL);
1433 }
1434
1435 static const struct file_operations synclinkmp_proc_fops = {
1436         .owner          = THIS_MODULE,
1437         .open           = synclinkmp_proc_open,
1438         .read           = seq_read,
1439         .llseek         = seq_lseek,
1440         .release        = single_release,
1441 };
1442
1443 /* Return the count of bytes in transmit buffer
1444  */
1445 static int chars_in_buffer(struct tty_struct *tty)
1446 {
1447         SLMP_INFO *info = tty->driver_data;
1448
1449         if (sanity_check(info, tty->name, "chars_in_buffer"))
1450                 return 0;
1451
1452         if (debug_level >= DEBUG_LEVEL_INFO)
1453                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1454                        __FILE__, __LINE__, info->device_name, info->tx_count);
1455
1456         return info->tx_count;
1457 }
1458
1459 /* Signal remote device to throttle send data (our receive data)
1460  */
1461 static void throttle(struct tty_struct * tty)
1462 {
1463         SLMP_INFO *info = tty->driver_data;
1464         unsigned long flags;
1465
1466         if (debug_level >= DEBUG_LEVEL_INFO)
1467                 printk("%s(%d):%s throttle() entry\n",
1468                          __FILE__,__LINE__, info->device_name );
1469
1470         if (sanity_check(info, tty->name, "throttle"))
1471                 return;
1472
1473         if (I_IXOFF(tty))
1474                 send_xchar(tty, STOP_CHAR(tty));
1475
1476         if (tty->termios->c_cflag & CRTSCTS) {
1477                 spin_lock_irqsave(&info->lock,flags);
1478                 info->serial_signals &= ~SerialSignal_RTS;
1479                 set_signals(info);
1480                 spin_unlock_irqrestore(&info->lock,flags);
1481         }
1482 }
1483
1484 /* Signal remote device to stop throttling send data (our receive data)
1485  */
1486 static void unthrottle(struct tty_struct * tty)
1487 {
1488         SLMP_INFO *info = tty->driver_data;
1489         unsigned long flags;
1490
1491         if (debug_level >= DEBUG_LEVEL_INFO)
1492                 printk("%s(%d):%s unthrottle() entry\n",
1493                          __FILE__,__LINE__, info->device_name );
1494
1495         if (sanity_check(info, tty->name, "unthrottle"))
1496                 return;
1497
1498         if (I_IXOFF(tty)) {
1499                 if (info->x_char)
1500                         info->x_char = 0;
1501                 else
1502                         send_xchar(tty, START_CHAR(tty));
1503         }
1504
1505         if (tty->termios->c_cflag & CRTSCTS) {
1506                 spin_lock_irqsave(&info->lock,flags);
1507                 info->serial_signals |= SerialSignal_RTS;
1508                 set_signals(info);
1509                 spin_unlock_irqrestore(&info->lock,flags);
1510         }
1511 }
1512
1513 /* set or clear transmit break condition
1514  * break_state  -1=set break condition, 0=clear
1515  */
1516 static int set_break(struct tty_struct *tty, int break_state)
1517 {
1518         unsigned char RegValue;
1519         SLMP_INFO * info = tty->driver_data;
1520         unsigned long flags;
1521
1522         if (debug_level >= DEBUG_LEVEL_INFO)
1523                 printk("%s(%d):%s set_break(%d)\n",
1524                          __FILE__,__LINE__, info->device_name, break_state);
1525
1526         if (sanity_check(info, tty->name, "set_break"))
1527                 return -EINVAL;
1528
1529         spin_lock_irqsave(&info->lock,flags);
1530         RegValue = read_reg(info, CTL);
1531         if (break_state == -1)
1532                 RegValue |= BIT3;
1533         else
1534                 RegValue &= ~BIT3;
1535         write_reg(info, CTL, RegValue);
1536         spin_unlock_irqrestore(&info->lock,flags);
1537         return 0;
1538 }
1539
1540 #if SYNCLINK_GENERIC_HDLC
1541
1542 /**
1543  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1544  * set encoding and frame check sequence (FCS) options
1545  *
1546  * dev       pointer to network device structure
1547  * encoding  serial encoding setting
1548  * parity    FCS setting
1549  *
1550  * returns 0 if success, otherwise error code
1551  */
1552 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1553                           unsigned short parity)
1554 {
1555         SLMP_INFO *info = dev_to_port(dev);
1556         unsigned char  new_encoding;
1557         unsigned short new_crctype;
1558
1559         /* return error if TTY interface open */
1560         if (info->port.count)
1561                 return -EBUSY;
1562
1563         switch (encoding)
1564         {
1565         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1566         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1567         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1568         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1569         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1570         default: return -EINVAL;
1571         }
1572
1573         switch (parity)
1574         {
1575         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1576         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1577         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1578         default: return -EINVAL;
1579         }
1580
1581         info->params.encoding = new_encoding;
1582         info->params.crc_type = new_crctype;
1583
1584         /* if network interface up, reprogram hardware */
1585         if (info->netcount)
1586                 program_hw(info);
1587
1588         return 0;
1589 }
1590
1591 /**
1592  * called by generic HDLC layer to send frame
1593  *
1594  * skb  socket buffer containing HDLC frame
1595  * dev  pointer to network device structure
1596  */
1597 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1598                                       struct net_device *dev)
1599 {
1600         SLMP_INFO *info = dev_to_port(dev);
1601         unsigned long flags;
1602
1603         if (debug_level >= DEBUG_LEVEL_INFO)
1604                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1605
1606         /* stop sending until this frame completes */
1607         netif_stop_queue(dev);
1608
1609         /* copy data to device buffers */
1610         info->tx_count = skb->len;
1611         tx_load_dma_buffer(info, skb->data, skb->len);
1612
1613         /* update network statistics */
1614         dev->stats.tx_packets++;
1615         dev->stats.tx_bytes += skb->len;
1616
1617         /* done with socket buffer, so free it */
1618         dev_kfree_skb(skb);
1619
1620         /* save start time for transmit timeout detection */
1621         dev->trans_start = jiffies;
1622
1623         /* start hardware transmitter if necessary */
1624         spin_lock_irqsave(&info->lock,flags);
1625         if (!info->tx_active)
1626                 tx_start(info);
1627         spin_unlock_irqrestore(&info->lock,flags);
1628
1629         return NETDEV_TX_OK;
1630 }
1631
1632 /**
1633  * called by network layer when interface enabled
1634  * claim resources and initialize hardware
1635  *
1636  * dev  pointer to network device structure
1637  *
1638  * returns 0 if success, otherwise error code
1639  */
1640 static int hdlcdev_open(struct net_device *dev)
1641 {
1642         SLMP_INFO *info = dev_to_port(dev);
1643         int rc;
1644         unsigned long flags;
1645
1646         if (debug_level >= DEBUG_LEVEL_INFO)
1647                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1648
1649         /* generic HDLC layer open processing */
1650         if ((rc = hdlc_open(dev)))
1651                 return rc;
1652
1653         /* arbitrate between network and tty opens */
1654         spin_lock_irqsave(&info->netlock, flags);
1655         if (info->port.count != 0 || info->netcount != 0) {
1656                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1657                 spin_unlock_irqrestore(&info->netlock, flags);
1658                 return -EBUSY;
1659         }
1660         info->netcount=1;
1661         spin_unlock_irqrestore(&info->netlock, flags);
1662
1663         /* claim resources and init adapter */
1664         if ((rc = startup(info)) != 0) {
1665                 spin_lock_irqsave(&info->netlock, flags);
1666                 info->netcount=0;
1667                 spin_unlock_irqrestore(&info->netlock, flags);
1668                 return rc;
1669         }
1670
1671         /* assert DTR and RTS, apply hardware settings */
1672         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1673         program_hw(info);
1674
1675         /* enable network layer transmit */
1676         dev->trans_start = jiffies;
1677         netif_start_queue(dev);
1678
1679         /* inform generic HDLC layer of current DCD status */
1680         spin_lock_irqsave(&info->lock, flags);
1681         get_signals(info);
1682         spin_unlock_irqrestore(&info->lock, flags);
1683         if (info->serial_signals & SerialSignal_DCD)
1684                 netif_carrier_on(dev);
1685         else
1686                 netif_carrier_off(dev);
1687         return 0;
1688 }
1689
1690 /**
1691  * called by network layer when interface is disabled
1692  * shutdown hardware and release resources
1693  *
1694  * dev  pointer to network device structure
1695  *
1696  * returns 0 if success, otherwise error code
1697  */
1698 static int hdlcdev_close(struct net_device *dev)
1699 {
1700         SLMP_INFO *info = dev_to_port(dev);
1701         unsigned long flags;
1702
1703         if (debug_level >= DEBUG_LEVEL_INFO)
1704                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1705
1706         netif_stop_queue(dev);
1707
1708         /* shutdown adapter and release resources */
1709         shutdown(info);
1710
1711         hdlc_close(dev);
1712
1713         spin_lock_irqsave(&info->netlock, flags);
1714         info->netcount=0;
1715         spin_unlock_irqrestore(&info->netlock, flags);
1716
1717         return 0;
1718 }
1719
1720 /**
1721  * called by network layer to process IOCTL call to network device
1722  *
1723  * dev  pointer to network device structure
1724  * ifr  pointer to network interface request structure
1725  * cmd  IOCTL command code
1726  *
1727  * returns 0 if success, otherwise error code
1728  */
1729 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1730 {
1731         const size_t size = sizeof(sync_serial_settings);
1732         sync_serial_settings new_line;
1733         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1734         SLMP_INFO *info = dev_to_port(dev);
1735         unsigned int flags;
1736
1737         if (debug_level >= DEBUG_LEVEL_INFO)
1738                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1739
1740         /* return error if TTY interface open */
1741         if (info->port.count)
1742                 return -EBUSY;
1743
1744         if (cmd != SIOCWANDEV)
1745                 return hdlc_ioctl(dev, ifr, cmd);
1746
1747         switch(ifr->ifr_settings.type) {
1748         case IF_GET_IFACE: /* return current sync_serial_settings */
1749
1750                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1751                 if (ifr->ifr_settings.size < size) {
1752                         ifr->ifr_settings.size = size; /* data size wanted */
1753                         return -ENOBUFS;
1754                 }
1755
1756                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1757                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1758                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1759                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1760
1761                 switch (flags){
1762                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1763                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1764                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1765                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1766                 default: new_line.clock_type = CLOCK_DEFAULT;
1767                 }
1768
1769                 new_line.clock_rate = info->params.clock_speed;
1770                 new_line.loopback   = info->params.loopback ? 1:0;
1771
1772                 if (copy_to_user(line, &new_line, size))
1773                         return -EFAULT;
1774                 return 0;
1775
1776         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1777
1778                 if(!capable(CAP_NET_ADMIN))
1779                         return -EPERM;
1780                 if (copy_from_user(&new_line, line, size))
1781                         return -EFAULT;
1782
1783                 switch (new_line.clock_type)
1784                 {
1785                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1786                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1787                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1788                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1789                 case CLOCK_DEFAULT:  flags = info->params.flags &
1790                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1791                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1792                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1793                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1794                 default: return -EINVAL;
1795                 }
1796
1797                 if (new_line.loopback != 0 && new_line.loopback != 1)
1798                         return -EINVAL;
1799
1800                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1801                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1802                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1803                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1804                 info->params.flags |= flags;
1805
1806                 info->params.loopback = new_line.loopback;
1807
1808                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1809                         info->params.clock_speed = new_line.clock_rate;
1810                 else
1811                         info->params.clock_speed = 0;
1812
1813                 /* if network interface up, reprogram hardware */
1814                 if (info->netcount)
1815                         program_hw(info);
1816                 return 0;
1817
1818         default:
1819                 return hdlc_ioctl(dev, ifr, cmd);
1820         }
1821 }
1822
1823 /**
1824  * called by network layer when transmit timeout is detected
1825  *
1826  * dev  pointer to network device structure
1827  */
1828 static void hdlcdev_tx_timeout(struct net_device *dev)
1829 {
1830         SLMP_INFO *info = dev_to_port(dev);
1831         unsigned long flags;
1832
1833         if (debug_level >= DEBUG_LEVEL_INFO)
1834                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1835
1836         dev->stats.tx_errors++;
1837         dev->stats.tx_aborted_errors++;
1838
1839         spin_lock_irqsave(&info->lock,flags);
1840         tx_stop(info);
1841         spin_unlock_irqrestore(&info->lock,flags);
1842
1843         netif_wake_queue(dev);
1844 }
1845
1846 /**
1847  * called by device driver when transmit completes
1848  * reenable network layer transmit if stopped
1849  *
1850  * info  pointer to device instance information
1851  */
1852 static void hdlcdev_tx_done(SLMP_INFO *info)
1853 {
1854         if (netif_queue_stopped(info->netdev))
1855                 netif_wake_queue(info->netdev);
1856 }
1857
1858 /**
1859  * called by device driver when frame received
1860  * pass frame to network layer
1861  *
1862  * info  pointer to device instance information
1863  * buf   pointer to buffer contianing frame data
1864  * size  count of data bytes in buf
1865  */
1866 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1867 {
1868         struct sk_buff *skb = dev_alloc_skb(size);
1869         struct net_device *dev = info->netdev;
1870
1871         if (debug_level >= DEBUG_LEVEL_INFO)
1872                 printk("hdlcdev_rx(%s)\n",dev->name);
1873
1874         if (skb == NULL) {
1875                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1876                        dev->name);
1877                 dev->stats.rx_dropped++;
1878                 return;
1879         }
1880
1881         memcpy(skb_put(skb, size), buf, size);
1882
1883         skb->protocol = hdlc_type_trans(skb, dev);
1884
1885         dev->stats.rx_packets++;
1886         dev->stats.rx_bytes += size;
1887
1888         netif_rx(skb);
1889 }
1890
1891 static const struct net_device_ops hdlcdev_ops = {
1892         .ndo_open       = hdlcdev_open,
1893         .ndo_stop       = hdlcdev_close,
1894         .ndo_change_mtu = hdlc_change_mtu,
1895         .ndo_start_xmit = hdlc_start_xmit,
1896         .ndo_do_ioctl   = hdlcdev_ioctl,
1897         .ndo_tx_timeout = hdlcdev_tx_timeout,
1898 };
1899
1900 /**
1901  * called by device driver when adding device instance
1902  * do generic HDLC initialization
1903  *
1904  * info  pointer to device instance information
1905  *
1906  * returns 0 if success, otherwise error code
1907  */
1908 static int hdlcdev_init(SLMP_INFO *info)
1909 {
1910         int rc;
1911         struct net_device *dev;
1912         hdlc_device *hdlc;
1913
1914         /* allocate and initialize network and HDLC layer objects */
1915
1916         if (!(dev = alloc_hdlcdev(info))) {
1917                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1918                 return -ENOMEM;
1919         }
1920
1921         /* for network layer reporting purposes only */
1922         dev->mem_start = info->phys_sca_base;
1923         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1924         dev->irq       = info->irq_level;
1925
1926         /* network layer callbacks and settings */
1927         dev->netdev_ops     = &hdlcdev_ops;
1928         dev->watchdog_timeo = 10 * HZ;
1929         dev->tx_queue_len   = 50;
1930
1931         /* generic HDLC layer callbacks and settings */
1932         hdlc         = dev_to_hdlc(dev);
1933         hdlc->attach = hdlcdev_attach;
1934         hdlc->xmit   = hdlcdev_xmit;
1935
1936         /* register objects with HDLC layer */
1937         if ((rc = register_hdlc_device(dev))) {
1938                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1939                 free_netdev(dev);
1940                 return rc;
1941         }
1942
1943         info->netdev = dev;
1944         return 0;
1945 }
1946
1947 /**
1948  * called by device driver when removing device instance
1949  * do generic HDLC cleanup
1950  *
1951  * info  pointer to device instance information
1952  */
1953 static void hdlcdev_exit(SLMP_INFO *info)
1954 {
1955         unregister_hdlc_device(info->netdev);
1956         free_netdev(info->netdev);
1957         info->netdev = NULL;
1958 }
1959
1960 #endif /* CONFIG_HDLC */
1961
1962
1963 /* Return next bottom half action to perform.
1964  * Return Value:        BH action code or 0 if nothing to do.
1965  */
1966 static int bh_action(SLMP_INFO *info)
1967 {
1968         unsigned long flags;
1969         int rc = 0;
1970
1971         spin_lock_irqsave(&info->lock,flags);
1972
1973         if (info->pending_bh & BH_RECEIVE) {
1974                 info->pending_bh &= ~BH_RECEIVE;
1975                 rc = BH_RECEIVE;
1976         } else if (info->pending_bh & BH_TRANSMIT) {
1977                 info->pending_bh &= ~BH_TRANSMIT;
1978                 rc = BH_TRANSMIT;
1979         } else if (info->pending_bh & BH_STATUS) {
1980                 info->pending_bh &= ~BH_STATUS;
1981                 rc = BH_STATUS;
1982         }
1983
1984         if (!rc) {
1985                 /* Mark BH routine as complete */
1986                 info->bh_running = false;
1987                 info->bh_requested = false;
1988         }
1989
1990         spin_unlock_irqrestore(&info->lock,flags);
1991
1992         return rc;
1993 }
1994
1995 /* Perform bottom half processing of work items queued by ISR.
1996  */
1997 static void bh_handler(struct work_struct *work)
1998 {
1999         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2000         int action;
2001
2002         if (!info)
2003                 return;
2004
2005         if ( debug_level >= DEBUG_LEVEL_BH )
2006                 printk( "%s(%d):%s bh_handler() entry\n",
2007                         __FILE__,__LINE__,info->device_name);
2008
2009         info->bh_running = true;
2010
2011         while((action = bh_action(info)) != 0) {
2012
2013                 /* Process work item */
2014                 if ( debug_level >= DEBUG_LEVEL_BH )
2015                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2016                                 __FILE__,__LINE__,info->device_name, action);
2017
2018                 switch (action) {
2019
2020                 case BH_RECEIVE:
2021                         bh_receive(info);
2022                         break;
2023                 case BH_TRANSMIT:
2024                         bh_transmit(info);
2025                         break;
2026                 case BH_STATUS:
2027                         bh_status(info);
2028                         break;
2029                 default:
2030                         /* unknown work item ID */
2031                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2032                                 __FILE__,__LINE__,info->device_name,action);
2033                         break;
2034                 }
2035         }
2036
2037         if ( debug_level >= DEBUG_LEVEL_BH )
2038                 printk( "%s(%d):%s bh_handler() exit\n",
2039                         __FILE__,__LINE__,info->device_name);
2040 }
2041
2042 static void bh_receive(SLMP_INFO *info)
2043 {
2044         if ( debug_level >= DEBUG_LEVEL_BH )
2045                 printk( "%s(%d):%s bh_receive()\n",
2046                         __FILE__,__LINE__,info->device_name);
2047
2048         while( rx_get_frame(info) );
2049 }
2050
2051 static void bh_transmit(SLMP_INFO *info)
2052 {
2053         struct tty_struct *tty = info->port.tty;
2054
2055         if ( debug_level >= DEBUG_LEVEL_BH )
2056                 printk( "%s(%d):%s bh_transmit() entry\n",
2057                         __FILE__,__LINE__,info->device_name);
2058
2059         if (tty)
2060                 tty_wakeup(tty);
2061 }
2062
2063 static void bh_status(SLMP_INFO *info)
2064 {
2065         if ( debug_level >= DEBUG_LEVEL_BH )
2066                 printk( "%s(%d):%s bh_status() entry\n",
2067                         __FILE__,__LINE__,info->device_name);
2068
2069         info->ri_chkcount = 0;
2070         info->dsr_chkcount = 0;
2071         info->dcd_chkcount = 0;
2072         info->cts_chkcount = 0;
2073 }
2074
2075 static void isr_timer(SLMP_INFO * info)
2076 {
2077         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2078
2079         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2080         write_reg(info, IER2, 0);
2081
2082         /* TMCS, Timer Control/Status Register
2083          *
2084          * 07      CMF, Compare match flag (read only) 1=match
2085          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2086          * 05      Reserved, must be 0
2087          * 04      TME, Timer Enable
2088          * 03..00  Reserved, must be 0
2089          *
2090          * 0000 0000
2091          */
2092         write_reg(info, (unsigned char)(timer + TMCS), 0);
2093
2094         info->irq_occurred = true;
2095
2096         if ( debug_level >= DEBUG_LEVEL_ISR )
2097                 printk("%s(%d):%s isr_timer()\n",
2098                         __FILE__,__LINE__,info->device_name);
2099 }
2100
2101 static void isr_rxint(SLMP_INFO * info)
2102 {
2103         struct tty_struct *tty = info->port.tty;
2104         struct  mgsl_icount *icount = &info->icount;
2105         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2106         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2107
2108         /* clear status bits */
2109         if (status)
2110                 write_reg(info, SR1, status);
2111
2112         if (status2)
2113                 write_reg(info, SR2, status2);
2114         
2115         if ( debug_level >= DEBUG_LEVEL_ISR )
2116                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2117                         __FILE__,__LINE__,info->device_name,status,status2);
2118
2119         if (info->params.mode == MGSL_MODE_ASYNC) {
2120                 if (status & BRKD) {
2121                         icount->brk++;
2122
2123                         /* process break detection if tty control
2124                          * is not set to ignore it
2125                          */
2126                         if ( tty ) {
2127                                 if (!(status & info->ignore_status_mask1)) {
2128                                         if (info->read_status_mask1 & BRKD) {
2129                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2130                                                 if (info->port.flags & ASYNC_SAK)
2131                                                         do_SAK(tty);
2132                                         }
2133                                 }
2134                         }
2135                 }
2136         }
2137         else {
2138                 if (status & (FLGD|IDLD)) {
2139                         if (status & FLGD)
2140                                 info->icount.exithunt++;
2141                         else if (status & IDLD)
2142                                 info->icount.rxidle++;
2143                         wake_up_interruptible(&info->event_wait_q);
2144                 }
2145         }
2146
2147         if (status & CDCD) {
2148                 /* simulate a common modem status change interrupt
2149                  * for our handler
2150                  */
2151                 get_signals( info );
2152                 isr_io_pin(info,
2153                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2154         }
2155 }
2156
2157 /*
2158  * handle async rx data interrupts
2159  */
2160 static void isr_rxrdy(SLMP_INFO * info)
2161 {
2162         u16 status;
2163         unsigned char DataByte;
2164         struct tty_struct *tty = info->port.tty;
2165         struct  mgsl_icount *icount = &info->icount;
2166
2167         if ( debug_level >= DEBUG_LEVEL_ISR )
2168                 printk("%s(%d):%s isr_rxrdy\n",
2169                         __FILE__,__LINE__,info->device_name);
2170
2171         while((status = read_reg(info,CST0)) & BIT0)
2172         {
2173                 int flag = 0;
2174                 bool over = false;
2175                 DataByte = read_reg(info,TRB);
2176
2177                 icount->rx++;
2178
2179                 if ( status & (PE + FRME + OVRN) ) {
2180                         printk("%s(%d):%s rxerr=%04X\n",
2181                                 __FILE__,__LINE__,info->device_name,status);
2182
2183                         /* update error statistics */
2184                         if (status & PE)
2185                                 icount->parity++;
2186                         else if (status & FRME)
2187                                 icount->frame++;
2188                         else if (status & OVRN)
2189                                 icount->overrun++;
2190
2191                         /* discard char if tty control flags say so */
2192                         if (status & info->ignore_status_mask2)
2193                                 continue;
2194
2195                         status &= info->read_status_mask2;
2196
2197                         if ( tty ) {
2198                                 if (status & PE)
2199                                         flag = TTY_PARITY;
2200                                 else if (status & FRME)
2201                                         flag = TTY_FRAME;
2202                                 if (status & OVRN) {
2203                                         /* Overrun is special, since it's
2204                                          * reported immediately, and doesn't
2205                                          * affect the current character
2206                                          */
2207                                         over = true;
2208                                 }
2209                         }
2210                 }       /* end of if (error) */
2211
2212                 if ( tty ) {
2213                         tty_insert_flip_char(tty, DataByte, flag);
2214                         if (over)
2215                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2216                 }
2217         }
2218
2219         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2220                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2221                         __FILE__,__LINE__,info->device_name,
2222                         icount->rx,icount->brk,icount->parity,
2223                         icount->frame,icount->overrun);
2224         }
2225
2226         if ( tty )
2227                 tty_flip_buffer_push(tty);
2228 }
2229
2230 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2231 {
2232         if ( debug_level >= DEBUG_LEVEL_ISR )
2233                 printk("%s(%d):%s isr_txeom status=%02x\n",
2234                         __FILE__,__LINE__,info->device_name,status);
2235
2236         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2237         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2238         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2239
2240         if (status & UDRN) {
2241                 write_reg(info, CMD, TXRESET);
2242                 write_reg(info, CMD, TXENABLE);
2243         } else
2244                 write_reg(info, CMD, TXBUFCLR);
2245
2246         /* disable and clear tx interrupts */
2247         info->ie0_value &= ~TXRDYE;
2248         info->ie1_value &= ~(IDLE + UDRN);
2249         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2250         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2251
2252         if ( info->tx_active ) {
2253                 if (info->params.mode != MGSL_MODE_ASYNC) {
2254                         if (status & UDRN)
2255                                 info->icount.txunder++;
2256                         else if (status & IDLE)
2257                                 info->icount.txok++;
2258                 }
2259
2260                 info->tx_active = false;
2261                 info->tx_count = info->tx_put = info->tx_get = 0;
2262
2263                 del_timer(&info->tx_timer);
2264
2265                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2266                         info->serial_signals &= ~SerialSignal_RTS;
2267                         info->drop_rts_on_tx_done = false;
2268                         set_signals(info);
2269                 }
2270
2271 #if SYNCLINK_GENERIC_HDLC
2272                 if (info->netcount)
2273                         hdlcdev_tx_done(info);
2274                 else
2275 #endif
2276                 {
2277                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2278                                 tx_stop(info);
2279                                 return;
2280                         }
2281                         info->pending_bh |= BH_TRANSMIT;
2282                 }
2283         }
2284 }
2285
2286
2287 /*
2288  * handle tx status interrupts
2289  */
2290 static void isr_txint(SLMP_INFO * info)
2291 {
2292         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2293
2294         /* clear status bits */
2295         write_reg(info, SR1, status);
2296
2297         if ( debug_level >= DEBUG_LEVEL_ISR )
2298                 printk("%s(%d):%s isr_txint status=%02x\n",
2299                         __FILE__,__LINE__,info->device_name,status);
2300
2301         if (status & (UDRN + IDLE))
2302                 isr_txeom(info, status);
2303
2304         if (status & CCTS) {
2305                 /* simulate a common modem status change interrupt
2306                  * for our handler
2307                  */
2308                 get_signals( info );
2309                 isr_io_pin(info,
2310                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2311
2312         }
2313 }
2314
2315 /*
2316  * handle async tx data interrupts
2317  */
2318 static void isr_txrdy(SLMP_INFO * info)
2319 {
2320         if ( debug_level >= DEBUG_LEVEL_ISR )
2321                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2322                         __FILE__,__LINE__,info->device_name,info->tx_count);
2323
2324         if (info->params.mode != MGSL_MODE_ASYNC) {
2325                 /* disable TXRDY IRQ, enable IDLE IRQ */
2326                 info->ie0_value &= ~TXRDYE;
2327                 info->ie1_value |= IDLE;
2328                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2329                 return;
2330         }
2331
2332         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2333                 tx_stop(info);
2334                 return;
2335         }
2336
2337         if ( info->tx_count )
2338                 tx_load_fifo( info );
2339         else {
2340                 info->tx_active = false;
2341                 info->ie0_value &= ~TXRDYE;
2342                 write_reg(info, IE0, info->ie0_value);
2343         }
2344
2345         if (info->tx_count < WAKEUP_CHARS)
2346                 info->pending_bh |= BH_TRANSMIT;
2347 }
2348
2349 static void isr_rxdmaok(SLMP_INFO * info)
2350 {
2351         /* BIT7 = EOT (end of transfer)
2352          * BIT6 = EOM (end of message/frame)
2353          */
2354         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2355
2356         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2357         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2358
2359         if ( debug_level >= DEBUG_LEVEL_ISR )
2360                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2361                         __FILE__,__LINE__,info->device_name,status);
2362
2363         info->pending_bh |= BH_RECEIVE;
2364 }
2365
2366 static void isr_rxdmaerror(SLMP_INFO * info)
2367 {
2368         /* BIT5 = BOF (buffer overflow)
2369          * BIT4 = COF (counter overflow)
2370          */
2371         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2372
2373         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2374         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2375
2376         if ( debug_level >= DEBUG_LEVEL_ISR )
2377                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2378                         __FILE__,__LINE__,info->device_name,status);
2379
2380         info->rx_overflow = true;
2381         info->pending_bh |= BH_RECEIVE;
2382 }
2383
2384 static void isr_txdmaok(SLMP_INFO * info)
2385 {
2386         unsigned char status_reg1 = read_reg(info, SR1);
2387
2388         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2389         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2390         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2391
2392         if ( debug_level >= DEBUG_LEVEL_ISR )
2393                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2394                         __FILE__,__LINE__,info->device_name,status_reg1);
2395
2396         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2397         write_reg16(info, TRC0, 0);
2398         info->ie0_value |= TXRDYE;
2399         write_reg(info, IE0, info->ie0_value);
2400 }
2401
2402 static void isr_txdmaerror(SLMP_INFO * info)
2403 {
2404         /* BIT5 = BOF (buffer overflow)
2405          * BIT4 = COF (counter overflow)
2406          */
2407         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2408
2409         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2410         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2411
2412         if ( debug_level >= DEBUG_LEVEL_ISR )
2413                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2414                         __FILE__,__LINE__,info->device_name,status);
2415 }
2416
2417 /* handle input serial signal changes
2418  */
2419 static void isr_io_pin( SLMP_INFO *info, u16 status )
2420 {
2421         struct  mgsl_icount *icount;
2422
2423         if ( debug_level >= DEBUG_LEVEL_ISR )
2424                 printk("%s(%d):isr_io_pin status=%04X\n",
2425                         __FILE__,__LINE__,status);
2426
2427         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2428                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2429                 icount = &info->icount;
2430                 /* update input line counters */
2431                 if (status & MISCSTATUS_RI_LATCHED) {
2432                         icount->rng++;
2433                         if ( status & SerialSignal_RI )
2434                                 info->input_signal_events.ri_up++;
2435                         else
2436                                 info->input_signal_events.ri_down++;
2437                 }
2438                 if (status & MISCSTATUS_DSR_LATCHED) {
2439                         icount->dsr++;
2440                         if ( status & SerialSignal_DSR )
2441                                 info->input_signal_events.dsr_up++;
2442                         else
2443                                 info->input_signal_events.dsr_down++;
2444                 }
2445                 if (status & MISCSTATUS_DCD_LATCHED) {
2446                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2447                                 info->ie1_value &= ~CDCD;
2448                                 write_reg(info, IE1, info->ie1_value);
2449                         }
2450                         icount->dcd++;
2451                         if (status & SerialSignal_DCD) {
2452                                 info->input_signal_events.dcd_up++;
2453                         } else
2454                                 info->input_signal_events.dcd_down++;
2455 #if SYNCLINK_GENERIC_HDLC
2456                         if (info->netcount) {
2457                                 if (status & SerialSignal_DCD)
2458                                         netif_carrier_on(info->netdev);
2459                                 else
2460                                         netif_carrier_off(info->netdev);
2461                         }
2462 #endif
2463                 }
2464                 if (status & MISCSTATUS_CTS_LATCHED)
2465                 {
2466                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2467                                 info->ie1_value &= ~CCTS;
2468                                 write_reg(info, IE1, info->ie1_value);
2469                         }
2470                         icount->cts++;
2471                         if ( status & SerialSignal_CTS )
2472                                 info->input_signal_events.cts_up++;
2473                         else
2474                                 info->input_signal_events.cts_down++;
2475                 }
2476                 wake_up_interruptible(&info->status_event_wait_q);
2477                 wake_up_interruptible(&info->event_wait_q);
2478
2479                 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2480                      (status & MISCSTATUS_DCD_LATCHED) ) {
2481                         if ( debug_level >= DEBUG_LEVEL_ISR )
2482                                 printk("%s CD now %s...", info->device_name,
2483                                        (status & SerialSignal_DCD) ? "on" : "off");
2484                         if (status & SerialSignal_DCD)
2485                                 wake_up_interruptible(&info->port.open_wait);
2486                         else {
2487                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2488                                         printk("doing serial hangup...");
2489                                 if (info->port.tty)
2490                                         tty_hangup(info->port.tty);
2491                         }
2492                 }
2493
2494                 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2495                      (status & MISCSTATUS_CTS_LATCHED) ) {
2496                         if ( info->port.tty ) {
2497                                 if (info->port.tty->hw_stopped) {
2498                                         if (status & SerialSignal_CTS) {
2499                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2500                                                         printk("CTS tx start...");
2501                                                 info->port.tty->hw_stopped = 0;
2502                                                 tx_start(info);
2503                                                 info->pending_bh |= BH_TRANSMIT;
2504                                                 return;
2505                                         }
2506                                 } else {
2507                                         if (!(status & SerialSignal_CTS)) {
2508                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2509                                                         printk("CTS tx stop...");
2510                                                 info->port.tty->hw_stopped = 1;
2511                                                 tx_stop(info);
2512                                         }
2513                                 }
2514                         }
2515                 }
2516         }
2517
2518         info->pending_bh |= BH_STATUS;
2519 }
2520
2521 /* Interrupt service routine entry point.
2522  *
2523  * Arguments:
2524  *      irq             interrupt number that caused interrupt
2525  *      dev_id          device ID supplied during interrupt registration
2526  *      regs            interrupted processor context
2527  */
2528 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2529 {
2530         SLMP_INFO *info = dev_id;
2531         unsigned char status, status0, status1=0;
2532         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2533         unsigned char timerstatus0, timerstatus1=0;
2534         unsigned char shift;
2535         unsigned int i;
2536         unsigned short tmp;
2537
2538         if ( debug_level >= DEBUG_LEVEL_ISR )
2539                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2540                         __FILE__, __LINE__, info->irq_level);
2541
2542         spin_lock(&info->lock);
2543
2544         for(;;) {
2545
2546                 /* get status for SCA0 (ports 0-1) */
2547                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2548                 status0 = (unsigned char)tmp;
2549                 dmastatus0 = (unsigned char)(tmp>>8);
2550                 timerstatus0 = read_reg(info, ISR2);
2551
2552                 if ( debug_level >= DEBUG_LEVEL_ISR )
2553                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2554                                 __FILE__, __LINE__, info->device_name,
2555                                 status0, dmastatus0, timerstatus0);
2556
2557                 if (info->port_count == 4) {
2558                         /* get status for SCA1 (ports 2-3) */
2559                         tmp = read_reg16(info->port_array[2], ISR0);
2560                         status1 = (unsigned char)tmp;
2561                         dmastatus1 = (unsigned char)(tmp>>8);
2562                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2563
2564                         if ( debug_level >= DEBUG_LEVEL_ISR )
2565                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2566                                         __FILE__,__LINE__,info->device_name,
2567                                         status1,dmastatus1,timerstatus1);
2568                 }
2569
2570                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2571                          !status1 && !dmastatus1 && !timerstatus1)
2572                         break;
2573
2574                 for(i=0; i < info->port_count ; i++) {
2575                         if (info->port_array[i] == NULL)
2576                                 continue;
2577                         if (i < 2) {
2578                                 status = status0;
2579                                 dmastatus = dmastatus0;
2580                         } else {
2581                                 status = status1;
2582                                 dmastatus = dmastatus1;
2583                         }
2584
2585                         shift = i & 1 ? 4 :0;
2586
2587                         if (status & BIT0 << shift)
2588                                 isr_rxrdy(info->port_array[i]);
2589                         if (status & BIT1 << shift)
2590                                 isr_txrdy(info->port_array[i]);
2591                         if (status & BIT2 << shift)
2592                                 isr_rxint(info->port_array[i]);
2593                         if (status & BIT3 << shift)
2594                                 isr_txint(info->port_array[i]);
2595
2596                         if (dmastatus & BIT0 << shift)
2597                                 isr_rxdmaerror(info->port_array[i]);
2598                         if (dmastatus & BIT1 << shift)
2599                                 isr_rxdmaok(info->port_array[i]);
2600                         if (dmastatus & BIT2 << shift)
2601                                 isr_txdmaerror(info->port_array[i]);
2602                         if (dmastatus & BIT3 << shift)
2603                                 isr_txdmaok(info->port_array[i]);
2604                 }
2605
2606                 if (timerstatus0 & (BIT5 | BIT4))
2607                         isr_timer(info->port_array[0]);
2608                 if (timerstatus0 & (BIT7 | BIT6))
2609                         isr_timer(info->port_array[1]);
2610                 if (timerstatus1 & (BIT5 | BIT4))
2611                         isr_timer(info->port_array[2]);
2612                 if (timerstatus1 & (BIT7 | BIT6))
2613                         isr_timer(info->port_array[3]);
2614         }
2615
2616         for(i=0; i < info->port_count ; i++) {
2617                 SLMP_INFO * port = info->port_array[i];
2618
2619                 /* Request bottom half processing if there's something
2620                  * for it to do and the bh is not already running.
2621                  *
2622                  * Note: startup adapter diags require interrupts.
2623                  * do not request bottom half processing if the
2624                  * device is not open in a normal mode.
2625                  */
2626                 if ( port && (port->port.count || port->netcount) &&
2627                      port->pending_bh && !port->bh_running &&
2628                      !port->bh_requested ) {
2629                         if ( debug_level >= DEBUG_LEVEL_ISR )
2630                                 printk("%s(%d):%s queueing bh task.\n",
2631                                         __FILE__,__LINE__,port->device_name);
2632                         schedule_work(&port->task);
2633                         port->bh_requested = true;
2634                 }
2635         }
2636
2637         spin_unlock(&info->lock);
2638
2639         if ( debug_level >= DEBUG_LEVEL_ISR )
2640                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2641                         __FILE__, __LINE__, info->irq_level);
2642         return IRQ_HANDLED;
2643 }
2644
2645 /* Initialize and start device.
2646  */
2647 static int startup(SLMP_INFO * info)
2648 {
2649         if ( debug_level >= DEBUG_LEVEL_INFO )
2650                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2651
2652         if (info->port.flags & ASYNC_INITIALIZED)
2653                 return 0;
2654
2655         if (!info->tx_buf) {
2656                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2657                 if (!info->tx_buf) {
2658                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2659                                 __FILE__,__LINE__,info->device_name);
2660                         return -ENOMEM;
2661                 }
2662         }
2663
2664         info->pending_bh = 0;
2665
2666         memset(&info->icount, 0, sizeof(info->icount));
2667
2668         /* program hardware for current parameters */
2669         reset_port(info);
2670
2671         change_params(info);
2672
2673         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2674
2675         if (info->port.tty)
2676                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2677
2678         info->port.flags |= ASYNC_INITIALIZED;
2679
2680         return 0;
2681 }
2682
2683 /* Called by close() and hangup() to shutdown hardware
2684  */
2685 static void shutdown(SLMP_INFO * info)
2686 {
2687         unsigned long flags;
2688
2689         if (!(info->port.flags & ASYNC_INITIALIZED))
2690                 return;
2691
2692         if (debug_level >= DEBUG_LEVEL_INFO)
2693                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2694                          __FILE__,__LINE__, info->device_name );
2695
2696         /* clear status wait queue because status changes */
2697         /* can't happen after shutting down the hardware */
2698         wake_up_interruptible(&info->status_event_wait_q);
2699         wake_up_interruptible(&info->event_wait_q);
2700
2701         del_timer(&info->tx_timer);
2702         del_timer(&info->status_timer);
2703
2704         kfree(info->tx_buf);
2705         info->tx_buf = NULL;
2706
2707         spin_lock_irqsave(&info->lock,flags);
2708
2709         reset_port(info);
2710
2711         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2712                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2713                 set_signals(info);
2714         }
2715
2716         spin_unlock_irqrestore(&info->lock,flags);
2717
2718         if (info->port.tty)
2719                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2720
2721         info->port.flags &= ~ASYNC_INITIALIZED;
2722 }
2723
2724 static void program_hw(SLMP_INFO *info)
2725 {
2726         unsigned long flags;
2727
2728         spin_lock_irqsave(&info->lock,flags);
2729
2730         rx_stop(info);
2731         tx_stop(info);
2732
2733         info->tx_count = info->tx_put = info->tx_get = 0;
2734
2735         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2736                 hdlc_mode(info);
2737         else
2738                 async_mode(info);
2739
2740         set_signals(info);
2741
2742         info->dcd_chkcount = 0;
2743         info->cts_chkcount = 0;
2744         info->ri_chkcount = 0;
2745         info->dsr_chkcount = 0;
2746
2747         info->ie1_value |= (CDCD|CCTS);
2748         write_reg(info, IE1, info->ie1_value);
2749
2750         get_signals(info);
2751
2752         if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2753                 rx_start(info);
2754
2755         spin_unlock_irqrestore(&info->lock,flags);
2756 }
2757
2758 /* Reconfigure adapter based on new parameters
2759  */
2760 static void change_params(SLMP_INFO *info)
2761 {
2762         unsigned cflag;
2763         int bits_per_char;
2764
2765         if (!info->port.tty || !info->port.tty->termios)
2766                 return;
2767
2768         if (debug_level >= DEBUG_LEVEL_INFO)
2769                 printk("%s(%d):%s change_params()\n",
2770                          __FILE__,__LINE__, info->device_name );
2771
2772         cflag = info->port.tty->termios->c_cflag;
2773
2774         /* if B0 rate (hangup) specified then negate DTR and RTS */
2775         /* otherwise assert DTR and RTS */
2776         if (cflag & CBAUD)
2777                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2778         else
2779                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2780
2781         /* byte size and parity */
2782
2783         switch (cflag & CSIZE) {
2784               case CS5: info->params.data_bits = 5; break;
2785               case CS6: info->params.data_bits = 6; break;
2786               case CS7: info->params.data_bits = 7; break;
2787               case CS8: info->params.data_bits = 8; break;
2788               /* Never happens, but GCC is too dumb to figure it out */
2789               default:  info->params.data_bits = 7; break;
2790               }
2791
2792         if (cflag & CSTOPB)
2793                 info->params.stop_bits = 2;
2794         else
2795                 info->params.stop_bits = 1;
2796
2797         info->params.parity = ASYNC_PARITY_NONE;
2798         if (cflag & PARENB) {
2799                 if (cflag & PARODD)
2800                         info->params.parity = ASYNC_PARITY_ODD;
2801                 else
2802                         info->params.parity = ASYNC_PARITY_EVEN;
2803 #ifdef CMSPAR
2804                 if (cflag & CMSPAR)
2805                         info->params.parity = ASYNC_PARITY_SPACE;
2806 #endif
2807         }
2808
2809         /* calculate number of jiffies to transmit a full
2810          * FIFO (32 bytes) at specified data rate
2811          */
2812         bits_per_char = info->params.data_bits +
2813                         info->params.stop_bits + 1;
2814
2815         /* if port data rate is set to 460800 or less then
2816          * allow tty settings to override, otherwise keep the
2817          * current data rate.
2818          */
2819         if (info->params.data_rate <= 460800) {
2820                 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2821         }
2822
2823         if ( info->params.data_rate ) {
2824                 info->timeout = (32*HZ*bits_per_char) /
2825                                 info->params.data_rate;
2826         }
2827         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2828
2829         if (cflag & CRTSCTS)
2830                 info->port.flags |= ASYNC_CTS_FLOW;
2831         else
2832                 info->port.flags &= ~ASYNC_CTS_FLOW;
2833
2834         if (cflag & CLOCAL)
2835                 info->port.flags &= ~ASYNC_CHECK_CD;
2836         else
2837                 info->port.flags |= ASYNC_CHECK_CD;
2838
2839         /* process tty input control flags */
2840
2841         info->read_status_mask2 = OVRN;
2842         if (I_INPCK(info->port.tty))
2843                 info->read_status_mask2 |= PE | FRME;
2844         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2845                 info->read_status_mask1 |= BRKD;
2846         if (I_IGNPAR(info->port.tty))
2847                 info->ignore_status_mask2 |= PE | FRME;
2848         if (I_IGNBRK(info->port.tty)) {
2849                 info->ignore_status_mask1 |= BRKD;
2850                 /* If ignoring parity and break indicators, ignore
2851                  * overruns too.  (For real raw support).
2852                  */
2853                 if (I_IGNPAR(info->port.tty))
2854                         info->ignore_status_mask2 |= OVRN;
2855         }
2856
2857         program_hw(info);
2858 }
2859
2860 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2861 {
2862         int err;
2863
2864         if (debug_level >= DEBUG_LEVEL_INFO)
2865                 printk("%s(%d):%s get_params()\n",
2866                          __FILE__,__LINE__, info->device_name);
2867
2868         if (!user_icount) {
2869                 memset(&info->icount, 0, sizeof(info->icount));
2870         } else {
2871                 mutex_lock(&info->port.mutex);
2872                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2873                 mutex_unlock(&info->port.mutex);
2874                 if (err)
2875                         return -EFAULT;
2876         }
2877
2878         return 0;
2879 }
2880
2881 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2882 {
2883         int err;
2884         if (debug_level >= DEBUG_LEVEL_INFO)
2885                 printk("%s(%d):%s get_params()\n",
2886                          __FILE__,__LINE__, info->device_name);
2887
2888         mutex_lock(&info->port.mutex);
2889         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2890         mutex_unlock(&info->port.mutex);
2891         if (err) {
2892                 if ( debug_level >= DEBUG_LEVEL_INFO )
2893                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2894                                 __FILE__,__LINE__,info->device_name);
2895                 return -EFAULT;
2896         }
2897
2898         return 0;
2899 }
2900
2901 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2902 {
2903         unsigned long flags;
2904         MGSL_PARAMS tmp_params;
2905         int err;
2906
2907         if (debug_level >= DEBUG_LEVEL_INFO)
2908                 printk("%s(%d):%s set_params\n",
2909                         __FILE__,__LINE__,info->device_name );
2910         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2911         if (err) {
2912                 if ( debug_level >= DEBUG_LEVEL_INFO )
2913                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2914                                 __FILE__,__LINE__,info->device_name);
2915                 return -EFAULT;
2916         }
2917
2918         mutex_lock(&info->port.mutex);
2919         spin_lock_irqsave(&info->lock,flags);
2920         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2921         spin_unlock_irqrestore(&info->lock,flags);
2922
2923         change_params(info);
2924         mutex_unlock(&info->port.mutex);
2925
2926         return 0;
2927 }
2928
2929 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2930 {
2931         int err;
2932
2933         if (debug_level >= DEBUG_LEVEL_INFO)
2934                 printk("%s(%d):%s get_txidle()=%d\n",
2935                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2936
2937         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2938         if (err) {
2939                 if ( debug_level >= DEBUG_LEVEL_INFO )
2940                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2941                                 __FILE__,__LINE__,info->device_name);
2942                 return -EFAULT;
2943         }
2944
2945         return 0;
2946 }
2947
2948 static int set_txidle(SLMP_INFO * info, int idle_mode)
2949 {
2950         unsigned long flags;
2951
2952         if (debug_level >= DEBUG_LEVEL_INFO)
2953                 printk("%s(%d):%s set_txidle(%d)\n",
2954                         __FILE__,__LINE__,info->device_name, idle_mode );
2955
2956         spin_lock_irqsave(&info->lock,flags);
2957         info->idle_mode = idle_mode;
2958         tx_set_idle( info );
2959         spin_unlock_irqrestore(&info->lock,flags);
2960         return 0;
2961 }
2962
2963 static int tx_enable(SLMP_INFO * info, int enable)
2964 {
2965         unsigned long flags;
2966
2967         if (debug_level >= DEBUG_LEVEL_INFO)
2968                 printk("%s(%d):%s tx_enable(%d)\n",
2969                         __FILE__,__LINE__,info->device_name, enable);
2970
2971         spin_lock_irqsave(&info->lock,flags);
2972         if ( enable ) {
2973                 if ( !info->tx_enabled ) {
2974                         tx_start(info);
2975                 }
2976         } else {
2977                 if ( info->tx_enabled )
2978                         tx_stop(info);
2979         }
2980         spin_unlock_irqrestore(&info->lock,flags);
2981         return 0;
2982 }
2983
2984 /* abort send HDLC frame
2985  */
2986 static int tx_abort(SLMP_INFO * info)
2987 {
2988         unsigned long flags;
2989
2990         if (debug_level >= DEBUG_LEVEL_INFO)
2991                 printk("%s(%d):%s tx_abort()\n",
2992                         __FILE__,__LINE__,info->device_name);
2993
2994         spin_lock_irqsave(&info->lock,flags);
2995         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2996                 info->ie1_value &= ~UDRN;
2997                 info->ie1_value |= IDLE;
2998                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
2999                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3000
3001                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3002                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3003
3004                 write_reg(info, CMD, TXABORT);
3005         }
3006         spin_unlock_irqrestore(&info->lock,flags);
3007         return 0;
3008 }
3009
3010 static int rx_enable(SLMP_INFO * info, int enable)
3011 {
3012         unsigned long flags;
3013
3014         if (debug_level >= DEBUG_LEVEL_INFO)
3015                 printk("%s(%d):%s rx_enable(%d)\n",
3016                         __FILE__,__LINE__,info->device_name,enable);
3017
3018         spin_lock_irqsave(&info->lock,flags);
3019         if ( enable ) {
3020                 if ( !info->rx_enabled )
3021                         rx_start(info);
3022         } else {
3023                 if ( info->rx_enabled )
3024                         rx_stop(info);
3025         }
3026         spin_unlock_irqrestore(&info->lock,flags);
3027         return 0;
3028 }
3029
3030 /* wait for specified event to occur
3031  */
3032 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3033 {
3034         unsigned long flags;
3035         int s;
3036         int rc=0;
3037         struct mgsl_icount cprev, cnow;
3038         int events;
3039         int mask;
3040         struct  _input_signal_events oldsigs, newsigs;
3041         DECLARE_WAITQUEUE(wait, current);
3042
3043         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3044         if (rc) {
3045                 return  -EFAULT;
3046         }
3047
3048         if (debug_level >= DEBUG_LEVEL_INFO)
3049                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3050                         __FILE__,__LINE__,info->device_name,mask);
3051
3052         spin_lock_irqsave(&info->lock,flags);
3053
3054         /* return immediately if state matches requested events */
3055         get_signals(info);
3056         s = info->serial_signals;
3057
3058         events = mask &
3059                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3060                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3061                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3062                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3063         if (events) {
3064                 spin_unlock_irqrestore(&info->lock,flags);
3065                 goto exit;
3066         }
3067
3068         /* save current irq counts */
3069         cprev = info->icount;
3070         oldsigs = info->input_signal_events;
3071
3072         /* enable hunt and idle irqs if needed */
3073         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3074                 unsigned char oldval = info->ie1_value;
3075                 unsigned char newval = oldval +
3076                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3077                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3078                 if ( oldval != newval ) {
3079                         info->ie1_value = newval;
3080                         write_reg(info, IE1, info->ie1_value);
3081                 }
3082         }
3083
3084         set_current_state(TASK_INTERRUPTIBLE);
3085         add_wait_queue(&info->event_wait_q, &wait);
3086
3087         spin_unlock_irqrestore(&info->lock,flags);
3088
3089         for(;;) {
3090                 schedule();
3091                 if (signal_pending(current)) {
3092                         rc = -ERESTARTSYS;
3093                         break;
3094                 }
3095
3096                 /* get current irq counts */
3097                 spin_lock_irqsave(&info->lock,flags);
3098                 cnow = info->icount;
3099                 newsigs = info->input_signal_events;
3100                 set_current_state(TASK_INTERRUPTIBLE);
3101                 spin_unlock_irqrestore(&info->lock,flags);
3102
3103                 /* if no change, wait aborted for some reason */
3104                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3105                     newsigs.dsr_down == oldsigs.dsr_down &&
3106                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3107                     newsigs.dcd_down == oldsigs.dcd_down &&
3108                     newsigs.cts_up   == oldsigs.cts_up   &&
3109                     newsigs.cts_down == oldsigs.cts_down &&
3110                     newsigs.ri_up    == oldsigs.ri_up    &&
3111                     newsigs.ri_down  == oldsigs.ri_down  &&
3112                     cnow.exithunt    == cprev.exithunt   &&
3113                     cnow.rxidle      == cprev.rxidle) {
3114                         rc = -EIO;
3115                         break;
3116                 }
3117
3118                 events = mask &
3119                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3120                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3121                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3122                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3123                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3124                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3125                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3126                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3127                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3128                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3129                 if (events)
3130                         break;
3131
3132                 cprev = cnow;
3133                 oldsigs = newsigs;
3134         }
3135
3136         remove_wait_queue(&info->event_wait_q, &wait);
3137         set_current_state(TASK_RUNNING);
3138
3139
3140         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3141                 spin_lock_irqsave(&info->lock,flags);
3142                 if (!waitqueue_active(&info->event_wait_q)) {
3143                         /* disable enable exit hunt mode/idle rcvd IRQs */
3144                         info->ie1_value &= ~(FLGD|IDLD);
3145                         write_reg(info, IE1, info->ie1_value);
3146                 }
3147                 spin_unlock_irqrestore(&info->lock,flags);
3148         }
3149 exit:
3150         if ( rc == 0 )
3151                 PUT_USER(rc, events, mask_ptr);
3152
3153         return rc;
3154 }
3155
3156 static int modem_input_wait(SLMP_INFO *info,int arg)
3157 {
3158         unsigned long flags;
3159         int rc;
3160         struct mgsl_icount cprev, cnow;
3161         DECLARE_WAITQUEUE(wait, current);
3162
3163         /* save current irq counts */
3164         spin_lock_irqsave(&info->lock,flags);
3165         cprev = info->icount;
3166         add_wait_queue(&info->status_event_wait_q, &wait);
3167         set_current_state(TASK_INTERRUPTIBLE);
3168         spin_unlock_irqrestore(&info->lock,flags);
3169
3170         for(;;) {
3171                 schedule();
3172                 if (signal_pending(current)) {
3173                         rc = -ERESTARTSYS;
3174                         break;
3175                 }
3176
3177                 /* get new irq counts */
3178                 spin_lock_irqsave(&info->lock,flags);
3179                 cnow = info->icount;
3180                 set_current_state(TASK_INTERRUPTIBLE);
3181                 spin_unlock_irqrestore(&info->lock,flags);
3182
3183                 /* if no change, wait aborted for some reason */
3184                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3185                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3186                         rc = -EIO;
3187                         break;
3188                 }
3189
3190                 /* check for change in caller specified modem input */
3191                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3192                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3193                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3194                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3195                         rc = 0;
3196                         break;
3197                 }
3198
3199                 cprev = cnow;
3200         }
3201         remove_wait_queue(&info->status_event_wait_q, &wait);
3202         set_current_state(TASK_RUNNING);
3203         return rc;
3204 }
3205
3206 /* return the state of the serial control and status signals
3207  */
3208 static int tiocmget(struct tty_struct *tty)
3209 {
3210         SLMP_INFO *info = tty->driver_data;
3211         unsigned int result;
3212         unsigned long flags;
3213
3214         spin_lock_irqsave(&info->lock,flags);
3215         get_signals(info);
3216         spin_unlock_irqrestore(&info->lock,flags);
3217
3218         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3219                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3220                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3221                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3222                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3223                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3224
3225         if (debug_level >= DEBUG_LEVEL_INFO)
3226                 printk("%s(%d):%s tiocmget() value=%08X\n",
3227                          __FILE__,__LINE__, info->device_name, result );
3228         return result;
3229 }
3230
3231 /* set modem control signals (DTR/RTS)
3232  */
3233 static int tiocmset(struct tty_struct *tty,
3234                                         unsigned int set, unsigned int clear)
3235 {
3236         SLMP_INFO *info = tty->driver_data;
3237         unsigned long flags;
3238
3239         if (debug_level >= DEBUG_LEVEL_INFO)
3240                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3241                         __FILE__,__LINE__,info->device_name, set, clear);
3242
3243         if (set & TIOCM_RTS)
3244                 info->serial_signals |= SerialSignal_RTS;
3245         if (set & TIOCM_DTR)
3246                 info->serial_signals |= SerialSignal_DTR;
3247         if (clear & TIOCM_RTS)
3248                 info->serial_signals &= ~SerialSignal_RTS;
3249         if (clear & TIOCM_DTR)
3250                 info->serial_signals &= ~SerialSignal_DTR;
3251
3252         spin_lock_irqsave(&info->lock,flags);
3253         set_signals(info);
3254         spin_unlock_irqrestore(&info->lock,flags);
3255
3256         return 0;
3257 }
3258
3259 static int carrier_raised(struct tty_port *port)
3260 {
3261         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3262         unsigned long flags;
3263
3264         spin_lock_irqsave(&info->lock,flags);
3265         get_signals(info);
3266         spin_unlock_irqrestore(&info->lock,flags);
3267
3268         return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3269 }
3270
3271 static void dtr_rts(struct tty_port *port, int on)
3272 {
3273         SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3274         unsigned long flags;
3275
3276         spin_lock_irqsave(&info->lock,flags);
3277         if (on)
3278                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3279         else
3280                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3281         set_signals(info);
3282         spin_unlock_irqrestore(&info->lock,flags);
3283 }
3284
3285 /* Block the current process until the specified port is ready to open.
3286  */
3287 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3288                            SLMP_INFO *info)
3289 {
3290         DECLARE_WAITQUEUE(wait, current);
3291         int             retval;
3292         bool            do_clocal = false;
3293         bool            extra_count = false;
3294         unsigned long   flags;
3295         int             cd;
3296         struct tty_port *port = &info->port;
3297
3298         if (debug_level >= DEBUG_LEVEL_INFO)
3299                 printk("%s(%d):%s block_til_ready()\n",
3300                          __FILE__,__LINE__, tty->driver->name );
3301
3302         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3303                 /* nonblock mode is set or port is not enabled */
3304                 /* just verify that callout device is not active */
3305                 port->flags |= ASYNC_NORMAL_ACTIVE;
3306                 return 0;
3307         }
3308
3309         if (tty->termios->c_cflag & CLOCAL)
3310                 do_clocal = true;
3311
3312         /* Wait for carrier detect and the line to become
3313          * free (i.e., not in use by the callout).  While we are in
3314          * this loop, port->count is dropped by one, so that
3315          * close() knows when to free things.  We restore it upon
3316          * exit, either normal or abnormal.
3317          */
3318
3319         retval = 0;
3320         add_wait_queue(&port->open_wait, &wait);
3321
3322         if (debug_level >= DEBUG_LEVEL_INFO)
3323                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3324                          __FILE__,__LINE__, tty->driver->name, port->count );
3325
3326         spin_lock_irqsave(&info->lock, flags);
3327         if (!tty_hung_up_p(filp)) {
3328                 extra_count = true;
3329                 port->count--;
3330         }
3331         spin_unlock_irqrestore(&info->lock, flags);
3332         port->blocked_open++;
3333
3334         while (1) {
3335                 if (tty->termios->c_cflag & CBAUD)
3336                         tty_port_raise_dtr_rts(port);
3337
3338                 set_current_state(TASK_INTERRUPTIBLE);
3339
3340                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3341                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3342                                         -EAGAIN : -ERESTARTSYS;
3343                         break;
3344                 }
3345
3346                 cd = tty_port_carrier_raised(port);
3347
3348                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3349                         break;
3350
3351                 if (signal_pending(current)) {
3352                         retval = -ERESTARTSYS;
3353                         break;
3354                 }
3355
3356                 if (debug_level >= DEBUG_LEVEL_INFO)
3357                         printk("%s(%d):%s block_til_ready() count=%d\n",
3358                                  __FILE__,__LINE__, tty->driver->name, port->count );
3359
3360                 tty_unlock();
3361                 schedule();
3362                 tty_lock();
3363         }
3364
3365         set_current_state(TASK_RUNNING);
3366         remove_wait_queue(&port->open_wait, &wait);
3367
3368         if (extra_count)
3369                 port->count++;
3370         port->blocked_open--;
3371
3372         if (debug_level >= DEBUG_LEVEL_INFO)
3373                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3374                          __FILE__,__LINE__, tty->driver->name, port->count );
3375
3376         if (!retval)
3377                 port->flags |= ASYNC_NORMAL_ACTIVE;
3378
3379         return retval;
3380 }
3381
3382 static int alloc_dma_bufs(SLMP_INFO *info)
3383 {
3384         unsigned short BuffersPerFrame;
3385         unsigned short BufferCount;
3386
3387         // Force allocation to start at 64K boundary for each port.
3388         // This is necessary because *all* buffer descriptors for a port
3389         // *must* be in the same 64K block. All descriptors on a port
3390         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3391         // into the CBP register.
3392         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3393
3394         /* Calculate the number of DMA buffers necessary to hold the */
3395         /* largest allowable frame size. Note: If the max frame size is */
3396         /* not an even multiple of the DMA buffer size then we need to */
3397         /* round the buffer count per frame up one. */
3398
3399         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3400         if ( info->max_frame_size % SCABUFSIZE )
3401                 BuffersPerFrame++;
3402
3403         /* calculate total number of data buffers (SCABUFSIZE) possible
3404          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3405          * for the descriptor list (BUFFERLISTSIZE).
3406          */
3407         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3408
3409         /* limit number of buffers to maximum amount of descriptors */
3410         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3411                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3412
3413         /* use enough buffers to transmit one max size frame */
3414         info->tx_buf_count = BuffersPerFrame + 1;
3415
3416         /* never use more than half the available buffers for transmit */
3417         if (info->tx_buf_count > (BufferCount/2))
3418                 info->tx_buf_count = BufferCount/2;
3419
3420         if (info->tx_buf_count > SCAMAXDESC)
3421                 info->tx_buf_count = SCAMAXDESC;
3422
3423         /* use remaining buffers for receive */
3424         info->rx_buf_count = BufferCount - info->tx_buf_count;
3425
3426         if (info->rx_buf_count > SCAMAXDESC)
3427                 info->rx_buf_count = SCAMAXDESC;
3428
3429         if ( debug_level >= DEBUG_LEVEL_INFO )
3430                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3431                         __FILE__,__LINE__, info->device_name,
3432                         info->tx_buf_count,info->rx_buf_count);
3433
3434         if ( alloc_buf_list( info ) < 0 ||
3435                 alloc_frame_bufs(info,
3436                                         info->rx_buf_list,
3437                                         info->rx_buf_list_ex,
3438                                         info->rx_buf_count) < 0 ||
3439                 alloc_frame_bufs(info,
3440                                         info->tx_buf_list,
3441                                         info->tx_buf_list_ex,
3442                                         info->tx_buf_count) < 0 ||
3443                 alloc_tmp_rx_buf(info) < 0 ) {
3444                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3445                         __FILE__,__LINE__, info->device_name);
3446                 return -ENOMEM;
3447         }
3448
3449         rx_reset_buffers( info );
3450
3451         return 0;
3452 }
3453
3454 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3455  */
3456 static int alloc_buf_list(SLMP_INFO *info)
3457 {
3458         unsigned int i;
3459
3460         /* build list in adapter shared memory */
3461         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3462         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3463         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3464
3465         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3466
3467         /* Save virtual address pointers to the receive and */
3468         /* transmit buffer lists. (Receive 1st). These pointers will */
3469         /* be used by the processor to access the lists. */
3470         info->rx_buf_list = (SCADESC *)info->buffer_list;
3471
3472         info->tx_buf_list = (SCADESC *)info->buffer_list;
3473         info->tx_buf_list += info->rx_buf_count;
3474
3475         /* Build links for circular buffer entry lists (tx and rx)
3476          *
3477          * Note: links are physical addresses read by the SCA device
3478          * to determine the next buffer entry to use.
3479          */
3480
3481         for ( i = 0; i < info->rx_buf_count; i++ ) {
3482                 /* calculate and store physical address of this buffer entry */
3483                 info->rx_buf_list_ex[i].phys_entry =
3484                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3485
3486                 /* calculate and store physical address of */
3487                 /* next entry in cirular list of entries */
3488                 info->rx_buf_list[i].next = info->buffer_list_phys;
3489                 if ( i < info->rx_buf_count - 1 )
3490                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3491
3492                 info->rx_buf_list[i].length = SCABUFSIZE;
3493         }
3494
3495         for ( i = 0; i < info->tx_buf_count; i++ ) {
3496                 /* calculate and store physical address of this buffer entry */
3497                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3498                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3499
3500                 /* calculate and store physical address of */
3501                 /* next entry in cirular list of entries */
3502
3503                 info->tx_buf_list[i].next = info->buffer_list_phys +
3504                         info->rx_buf_count * sizeof(SCADESC);
3505
3506                 if ( i < info->tx_buf_count - 1 )
3507                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3508         }
3509
3510         return 0;
3511 }
3512
3513 /* Allocate the frame DMA buffers used by the specified buffer list.
3514  */
3515 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3516 {
3517         int i;
3518         unsigned long phys_addr;
3519
3520         for ( i = 0; i < count; i++ ) {
3521                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3522                 phys_addr = info->port_array[0]->last_mem_alloc;
3523                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3524
3525                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3526                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3527         }
3528
3529         return 0;
3530 }
3531
3532 static void free_dma_bufs(SLMP_INFO *info)
3533 {
3534         info->buffer_list = NULL;
3535         info->rx_buf_list = NULL;
3536         info->tx_buf_list = NULL;
3537 }
3538
3539 /* allocate buffer large enough to hold max_frame_size.
3540  * This buffer is used to pass an assembled frame to the line discipline.
3541  */
3542 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3543 {
3544         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3545         if (info->tmp_rx_buf == NULL)
3546                 return -ENOMEM;
3547         return 0;
3548 }
3549
3550 static void free_tmp_rx_buf(SLMP_INFO *info)
3551 {
3552         kfree(info->tmp_rx_buf);
3553         info->tmp_rx_buf = NULL;
3554 }
3555
3556 static int claim_resources(SLMP_INFO *info)
3557 {
3558         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3559                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3560                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3561                 info->init_error = DiagStatus_AddressConflict;
3562                 goto errout;
3563         }
3564         else
3565                 info->shared_mem_requested = true;
3566
3567         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3568                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3569                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3570                 info->init_error = DiagStatus_AddressConflict;
3571                 goto errout;
3572         }
3573         else
3574                 info->lcr_mem_requested = true;
3575
3576         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3577                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3578                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3579                 info->init_error = DiagStatus_AddressConflict;
3580                 goto errout;
3581         }
3582         else
3583                 info->sca_base_requested = true;
3584
3585         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3586                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3587                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3588                 info->init_error = DiagStatus_AddressConflict;
3589                 goto errout;
3590         }
3591         else
3592                 info->sca_statctrl_requested = true;
3593
3594         info->memory_base = ioremap_nocache(info->phys_memory_base,
3595                                                                 SCA_MEM_SIZE);
3596         if (!info->memory_base) {
3597                 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3598                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3599                 info->init_error = DiagStatus_CantAssignPciResources;
3600                 goto errout;
3601         }
3602
3603         info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3604         if (!info->lcr_base) {
3605                 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3606                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3607                 info->init_error = DiagStatus_CantAssignPciResources;
3608                 goto errout;
3609         }
3610         info->lcr_base += info->lcr_offset;
3611
3612         info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3613         if (!info->sca_base) {
3614                 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3615                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3616                 info->init_error = DiagStatus_CantAssignPciResources;
3617                 goto errout;
3618         }
3619         info->sca_base += info->sca_offset;
3620
3621         info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3622                                                                 PAGE_SIZE);
3623         if (!info->statctrl_base) {
3624                 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3625                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3626                 info->init_error = DiagStatus_CantAssignPciResources;
3627                 goto errout;
3628         }
3629         info->statctrl_base += info->statctrl_offset;
3630
3631         if ( !memory_test(info) ) {
3632                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3633                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3634                 info->init_error = DiagStatus_MemoryError;
3635                 goto errout;
3636         }
3637
3638         return 0;
3639
3640 errout:
3641         release_resources( info );
3642         return -ENODEV;
3643 }
3644
3645 static void release_resources(SLMP_INFO *info)
3646 {
3647         if ( debug_level >= DEBUG_LEVEL_INFO )
3648                 printk( "%s(%d):%s release_resources() entry\n",
3649                         __FILE__,__LINE__,info->device_name );
3650
3651         if ( info->irq_requested ) {
3652                 free_irq(info->irq_level, info);
3653                 info->irq_requested = false;
3654         }
3655
3656         if ( info->shared_mem_requested ) {
3657                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3658                 info->shared_mem_requested = false;
3659         }
3660         if ( info->lcr_mem_requested ) {
3661                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3662                 info->lcr_mem_requested = false;
3663         }
3664         if ( info->sca_base_requested ) {
3665                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3666                 info->sca_base_requested = false;
3667         }
3668         if ( info->sca_statctrl_requested ) {
3669                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3670                 info->sca_statctrl_requested = false;
3671         }
3672
3673         if (info->memory_base){
3674                 iounmap(info->memory_base);
3675                 info->memory_base = NULL;
3676         }
3677
3678         if (info->sca_base) {
3679                 iounmap(info->sca_base - info->sca_offset);
3680                 info->sca_base=NULL;
3681         }
3682
3683         if (info->statctrl_base) {
3684                 iounmap(info->statctrl_base - info->statctrl_offset);
3685                 info->statctrl_base=NULL;
3686         }
3687
3688         if (info->lcr_base){
3689                 iounmap(info->lcr_base - info->lcr_offset);
3690                 info->lcr_base = NULL;
3691         }
3692
3693         if ( debug_level >= DEBUG_LEVEL_INFO )
3694                 printk( "%s(%d):%s release_resources() exit\n",
3695                         __FILE__,__LINE__,info->device_name );
3696 }
3697
3698 /* Add the specified device instance data structure to the
3699  * global linked list of devices and increment the device count.
3700  */
3701 static void add_device(SLMP_INFO *info)
3702 {
3703         info->next_device = NULL;
3704         info->line = synclinkmp_device_count;
3705         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3706
3707         if (info->line < MAX_DEVICES) {
3708                 if (maxframe[info->line])
3709                         info->max_frame_size = maxframe[info->line];
3710         }
3711
3712         synclinkmp_device_count++;
3713
3714         if ( !synclinkmp_device_list )
3715                 synclinkmp_device_list = info;
3716         else {
3717                 SLMP_INFO *current_dev = synclinkmp_device_list;
3718                 while( current_dev->next_device )
3719                         current_dev = current_dev->next_device;
3720                 current_dev->next_device = info;
3721         }
3722
3723         if ( info->max_frame_size < 4096 )
3724                 info->max_frame_size = 4096;
3725         else if ( info->max_frame_size > 65535 )
3726                 info->max_frame_size = 65535;
3727
3728         printk( "SyncLink MultiPort %s: "
3729                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3730                 info->device_name,
3731                 info->phys_sca_base,
3732                 info->phys_memory_base,
3733                 info->phys_statctrl_base,
3734                 info->phys_lcr_base,
3735                 info->irq_level,
3736                 info->max_frame_size );
3737
3738 #if SYNCLINK_GENERIC_HDLC
3739         hdlcdev_init(info);
3740 #endif
3741 }
3742
3743 static const struct tty_port_operations port_ops = {
3744         .carrier_raised = carrier_raised,
3745         .dtr_rts = dtr_rts,
3746 };
3747
3748 /* Allocate and initialize a device instance structure
3749  *
3750  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3751  */
3752 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3753 {
3754         SLMP_INFO *info;
3755
3756         info = kzalloc(sizeof(SLMP_INFO),
3757                  GFP_KERNEL);
3758
3759         if (!info) {
3760                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3761                         __FILE__,__LINE__, adapter_num, port_num);
3762         } else {
3763                 tty_port_init(&info->port);
3764                 info->port.ops = &port_ops;
3765                 info->magic = MGSL_MAGIC;
3766                 INIT_WORK(&info->task, bh_handler);
3767                 info->max_frame_size = 4096;
3768                 info->port.close_delay = 5*HZ/10;
3769                 info->port.closing_wait = 30*HZ;
3770                 init_waitqueue_head(&info->status_event_wait_q);
3771                 init_waitqueue_head(&info->event_wait_q);
3772                 spin_lock_init(&info->netlock);
3773                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3774                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3775                 info->adapter_num = adapter_num;
3776                 info->port_num = port_num;
3777
3778                 /* Copy configuration info to device instance data */
3779                 info->irq_level = pdev->irq;
3780                 info->phys_lcr_base = pci_resource_start(pdev,0);
3781                 info->phys_sca_base = pci_resource_start(pdev,2);
3782                 info->phys_memory_base = pci_resource_start(pdev,3);
3783                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3784
3785                 /* Because veremap only works on page boundaries we must map
3786                  * a larger area than is actually implemented for the LCR
3787                  * memory range. We map a full page starting at the page boundary.
3788                  */
3789                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3790                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3791
3792                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3793                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3794
3795                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3796                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3797
3798                 info->bus_type = MGSL_BUS_TYPE_PCI;
3799                 info->irq_flags = IRQF_SHARED;
3800
3801                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3802                 setup_timer(&info->status_timer, status_timeout,
3803                                 (unsigned long)info);
3804
3805                 /* Store the PCI9050 misc control register value because a flaw
3806                  * in the PCI9050 prevents LCR registers from being read if
3807                  * BIOS assigns an LCR base address with bit 7 set.
3808                  *
3809                  * Only the misc control register is accessed for which only
3810                  * write access is needed, so set an initial value and change
3811                  * bits to the device instance data as we write the value
3812                  * to the actual misc control register.
3813                  */
3814                 info->misc_ctrl_value = 0x087e4546;
3815
3816                 /* initial port state is unknown - if startup errors
3817                  * occur, init_error will be set to indicate the
3818                  * problem. Once the port is fully initialized,
3819                  * this value will be set to 0 to indicate the
3820                  * port is available.
3821                  */
3822                 info->init_error = -1;
3823         }
3824
3825         return info;
3826 }
3827
3828 static void device_init(int adapter_num, struct pci_dev *pdev)
3829 {
3830         SLMP_INFO *port_array[SCA_MAX_PORTS];
3831         int port;
3832
3833         /* allocate device instances for up to SCA_MAX_PORTS devices */
3834         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3835                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3836                 if( port_array[port] == NULL ) {
3837                         for ( --port; port >= 0; --port )
3838                                 kfree(port_array[port]);
3839                         return;
3840                 }
3841         }
3842
3843         /* give copy of port_array to all ports and add to device list  */
3844         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3845                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3846                 add_device( port_array[port] );
3847                 spin_lock_init(&port_array[port]->lock);
3848         }
3849
3850         /* Allocate and claim adapter resources */
3851         if ( !claim_resources(port_array[0]) ) {
3852
3853                 alloc_dma_bufs(port_array[0]);
3854
3855                 /* copy resource information from first port to others */
3856                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3857                         port_array[port]->lock  = port_array[0]->lock;
3858                         port_array[port]->irq_level     = port_array[0]->irq_level;
3859                         port_array[port]->memory_base   = port_array[0]->memory_base;
3860                         port_array[port]->sca_base      = port_array[0]->sca_base;
3861                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3862                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3863                         alloc_dma_bufs(port_array[port]);
3864                 }
3865
3866                 if ( request_irq(port_array[0]->irq_level,
3867                                         synclinkmp_interrupt,
3868                                         port_array[0]->irq_flags,
3869                                         port_array[0]->device_name,
3870                                         port_array[0]) < 0 ) {
3871                         printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3872                                 __FILE__,__LINE__,
3873                                 port_array[0]->device_name,
3874                                 port_array[0]->irq_level );
3875                 }
3876                 else {
3877                         port_array[0]->irq_requested = true;
3878                         adapter_test(port_array[0]);
3879                 }
3880         }
3881 }
3882
3883 static const struct tty_operations ops = {
3884         .open = open,
3885         .close = close,
3886         .write = write,
3887         .put_char = put_char,
3888         .flush_chars = flush_chars,
3889         .write_room = write_room,
3890         .chars_in_buffer = chars_in_buffer,
3891         .flush_buffer = flush_buffer,
3892         .ioctl = ioctl,
3893         .throttle = throttle,
3894         .unthrottle = unthrottle,
3895         .send_xchar = send_xchar,
3896         .break_ctl = set_break,
3897         .wait_until_sent = wait_until_sent,
3898         .set_termios = set_termios,
3899         .stop = tx_hold,
3900         .start = tx_release,
3901         .hangup = hangup,
3902         .tiocmget = tiocmget,
3903         .tiocmset = tiocmset,
3904         .get_icount = get_icount,
3905         .proc_fops = &synclinkmp_proc_fops,
3906 };
3907
3908
3909 static void synclinkmp_cleanup(void)
3910 {
3911         int rc;
3912         SLMP_INFO *info;
3913         SLMP_INFO *tmp;
3914
3915         printk("Unloading %s %s\n", driver_name, driver_version);
3916
3917         if (serial_driver) {
3918                 if ((rc = tty_unregister_driver(serial_driver)))
3919                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3920                                __FILE__,__LINE__,rc);
3921                 put_tty_driver(serial_driver);
3922         }
3923
3924         /* reset devices */
3925         info = synclinkmp_device_list;
3926         while(info) {
3927                 reset_port(info);
3928                 info = info->next_device;
3929         }
3930
3931         /* release devices */
3932         info = synclinkmp_device_list;
3933         while(info) {
3934 #if SYNCLINK_GENERIC_HDLC
3935                 hdlcdev_exit(info);
3936 #endif
3937                 free_dma_bufs(info);
3938                 free_tmp_rx_buf(info);
3939                 if ( info->port_num == 0 ) {
3940                         if (info->sca_base)
3941                                 write_reg(info, LPR, 1); /* set low power mode */
3942                         release_resources(info);
3943                 }
3944                 tmp = info;
3945                 info = info->next_device;
3946                 kfree(tmp);
3947         }
3948
3949         pci_unregister_driver(&synclinkmp_pci_driver);
3950 }
3951
3952 /* Driver initialization entry point.
3953  */
3954
3955 static int __init synclinkmp_init(void)
3956 {
3957         int rc;
3958
3959         if (break_on_load) {
3960                 synclinkmp_get_text_ptr();
3961                 BREAKPOINT();
3962         }
3963
3964         printk("%s %s\n", driver_name, driver_version);
3965
3966         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3967                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3968                 return rc;
3969         }
3970
3971         serial_driver = alloc_tty_driver(128);
3972         if (!serial_driver) {
3973                 rc = -ENOMEM;
3974                 goto error;
3975         }
3976
3977         /* Initialize the tty_driver structure */
3978
3979         serial_driver->driver_name = "synclinkmp";
3980         serial_driver->name = "ttySLM";
3981         serial_driver->major = ttymajor;
3982         serial_driver->minor_start = 64;
3983         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3984         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3985         serial_driver->init_termios = tty_std_termios;
3986         serial_driver->init_termios.c_cflag =
3987                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3988         serial_driver->init_termios.c_ispeed = 9600;
3989         serial_driver->init_termios.c_ospeed = 9600;
3990         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3991         tty_set_operations(serial_driver, &ops);
3992         if ((rc = tty_register_driver(serial_driver)) < 0) {
3993                 printk("%s(%d):Couldn't register serial driver\n",
3994                         __FILE__,__LINE__);
3995                 put_tty_driver(serial_driver);
3996                 serial_driver = NULL;
3997                 goto error;
3998         }
3999
4000         printk("%s %s, tty major#%d\n",
4001                 driver_name, driver_version,
4002                 serial_driver->major);
4003
4004         return 0;
4005
4006 error:
4007         synclinkmp_cleanup();
4008         return rc;
4009 }
4010
4011 static void __exit synclinkmp_exit(void)
4012 {
4013         synclinkmp_cleanup();
4014 }
4015
4016 module_init(synclinkmp_init);
4017 module_exit(synclinkmp_exit);
4018
4019 /* Set the port for internal loopback mode.
4020  * The TxCLK and RxCLK signals are generated from the BRG and
4021  * the TxD is looped back to the RxD internally.
4022  */
4023 static void enable_loopback(SLMP_INFO *info, int enable)
4024 {
4025         if (enable) {
4026                 /* MD2 (Mode Register 2)
4027                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4028                  */
4029                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4030
4031                 /* degate external TxC clock source */
4032                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4033                 write_control_reg(info);
4034
4035                 /* RXS/TXS (Rx/Tx clock source)
4036                  * 07      Reserved, must be 0
4037                  * 06..04  Clock Source, 100=BRG
4038                  * 03..00  Clock Divisor, 0000=1
4039                  */
4040                 write_reg(info, RXS, 0x40);
4041                 write_reg(info, TXS, 0x40);
4042
4043         } else {
4044                 /* MD2 (Mode Register 2)
4045                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4046                  */
4047                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4048
4049                 /* RXS/TXS (Rx/Tx clock source)
4050                  * 07      Reserved, must be 0
4051                  * 06..04  Clock Source, 000=RxC/TxC Pin
4052                  * 03..00  Clock Divisor, 0000=1
4053                  */
4054                 write_reg(info, RXS, 0x00);
4055                 write_reg(info, TXS, 0x00);
4056         }
4057
4058         /* set LinkSpeed if available, otherwise default to 2Mbps */
4059         if (info->params.clock_speed)
4060                 set_rate(info, info->params.clock_speed);
4061         else
4062                 set_rate(info, 3686400);
4063 }
4064
4065 /* Set the baud rate register to the desired speed
4066  *
4067  *      data_rate       data rate of clock in bits per second
4068  *                      A data rate of 0 disables the AUX clock.
4069  */
4070 static void set_rate( SLMP_INFO *info, u32 data_rate )
4071 {
4072         u32 TMCValue;
4073         unsigned char BRValue;
4074         u32 Divisor=0;
4075
4076         /* fBRG = fCLK/(TMC * 2^BR)
4077          */
4078         if (data_rate != 0) {
4079                 Divisor = 14745600/data_rate;
4080                 if (!Divisor)
4081                         Divisor = 1;
4082
4083                 TMCValue = Divisor;
4084
4085                 BRValue = 0;
4086                 if (TMCValue != 1 && TMCValue != 2) {
4087                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4088                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4089                          * 50/50 duty cycle.
4090                          */
4091                         BRValue = 1;
4092                         TMCValue >>= 1;
4093                 }
4094
4095                 /* while TMCValue is too big for TMC register, divide
4096                  * by 2 and increment BR exponent.
4097                  */
4098                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4099                         TMCValue >>= 1;
4100
4101                 write_reg(info, TXS,
4102                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4103                 write_reg(info, RXS,
4104                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4105                 write_reg(info, TMC, (unsigned char)TMCValue);
4106         }
4107         else {
4108                 write_reg(info, TXS,0);
4109                 write_reg(info, RXS,0);
4110                 write_reg(info, TMC, 0);
4111         }
4112 }
4113
4114 /* Disable receiver
4115  */
4116 static void rx_stop(SLMP_INFO *info)
4117 {
4118         if (debug_level >= DEBUG_LEVEL_ISR)
4119                 printk("%s(%d):%s rx_stop()\n",
4120                          __FILE__,__LINE__, info->device_name );
4121
4122         write_reg(info, CMD, RXRESET);
4123
4124         info->ie0_value &= ~RXRDYE;
4125         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4126
4127         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4128         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4129         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4130
4131         info->rx_enabled = false;
4132         info->rx_overflow = false;
4133 }
4134
4135 /* enable the receiver
4136  */
4137 static void rx_start(SLMP_INFO *info)
4138 {
4139         int i;
4140
4141         if (debug_level >= DEBUG_LEVEL_ISR)
4142                 printk("%s(%d):%s rx_start()\n",
4143                          __FILE__,__LINE__, info->device_name );
4144
4145         write_reg(info, CMD, RXRESET);
4146
4147         if ( info->params.mode == MGSL_MODE_HDLC ) {
4148                 /* HDLC, disabe IRQ on rxdata */
4149                 info->ie0_value &= ~RXRDYE;
4150                 write_reg(info, IE0, info->ie0_value);
4151
4152                 /* Reset all Rx DMA buffers and program rx dma */
4153                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4154                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4155
4156                 for (i = 0; i < info->rx_buf_count; i++) {
4157                         info->rx_buf_list[i].status = 0xff;
4158
4159                         // throttle to 4 shared memory writes at a time to prevent
4160                         // hogging local bus (keep latency time for DMA requests low).
4161                         if (!(i % 4))
4162                                 read_status_reg(info);
4163                 }
4164                 info->current_rx_buf = 0;
4165
4166                 /* set current/1st descriptor address */
4167                 write_reg16(info, RXDMA + CDA,
4168                         info->rx_buf_list_ex[0].phys_entry);
4169
4170                 /* set new last rx descriptor address */
4171                 write_reg16(info, RXDMA + EDA,
4172                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4173
4174                 /* set buffer length (shared by all rx dma data buffers) */
4175                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4176
4177                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4178                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4179         } else {
4180                 /* async, enable IRQ on rxdata */
4181                 info->ie0_value |= RXRDYE;
4182                 write_reg(info, IE0, info->ie0_value);
4183         }
4184
4185         write_reg(info, CMD, RXENABLE);
4186
4187         info->rx_overflow = false;
4188         info->rx_enabled = true;
4189 }
4190
4191 /* Enable the transmitter and send a transmit frame if
4192  * one is loaded in the DMA buffers.
4193  */
4194 static void tx_start(SLMP_INFO *info)
4195 {
4196         if (debug_level >= DEBUG_LEVEL_ISR)
4197                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4198                          __FILE__,__LINE__, info->device_name,info->tx_count );
4199
4200         if (!info->tx_enabled ) {
4201                 write_reg(info, CMD, TXRESET);
4202                 write_reg(info, CMD, TXENABLE);
4203                 info->tx_enabled = true;
4204         }
4205
4206         if ( info->tx_count ) {
4207
4208                 /* If auto RTS enabled and RTS is inactive, then assert */
4209                 /* RTS and set a flag indicating that the driver should */
4210                 /* negate RTS when the transmission completes. */
4211
4212                 info->drop_rts_on_tx_done = false;
4213
4214                 if (info->params.mode != MGSL_MODE_ASYNC) {
4215
4216                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4217                                 get_signals( info );
4218                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4219                                         info->serial_signals |= SerialSignal_RTS;
4220                                         set_signals( info );
4221                                         info->drop_rts_on_tx_done = true;
4222                                 }
4223                         }
4224
4225                         write_reg16(info, TRC0,
4226                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4227
4228                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4229                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4230         
4231                         /* set TX CDA (current descriptor address) */
4232                         write_reg16(info, TXDMA + CDA,
4233                                 info->tx_buf_list_ex[0].phys_entry);
4234         
4235                         /* set TX EDA (last descriptor address) */
4236                         write_reg16(info, TXDMA + EDA,
4237                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4238         
4239                         /* enable underrun IRQ */
4240                         info->ie1_value &= ~IDLE;
4241                         info->ie1_value |= UDRN;
4242                         write_reg(info, IE1, info->ie1_value);
4243                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4244         
4245                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4246                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4247         
4248                         mod_timer(&info->tx_timer, jiffies +
4249                                         msecs_to_jiffies(5000));
4250                 }
4251                 else {
4252                         tx_load_fifo(info);
4253                         /* async, enable IRQ on txdata */
4254                         info->ie0_value |= TXRDYE;
4255                         write_reg(info, IE0, info->ie0_value);
4256                 }
4257
4258                 info->tx_active = true;
4259         }
4260 }
4261
4262 /* stop the transmitter and DMA
4263  */
4264 static void tx_stop( SLMP_INFO *info )
4265 {
4266         if (debug_level >= DEBUG_LEVEL_ISR)
4267                 printk("%s(%d):%s tx_stop()\n",
4268                          __FILE__,__LINE__, info->device_name );
4269
4270         del_timer(&info->tx_timer);
4271
4272         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4273         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4274
4275         write_reg(info, CMD, TXRESET);
4276
4277         info->ie1_value &= ~(UDRN + IDLE);
4278         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4279         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4280
4281         info->ie0_value &= ~TXRDYE;
4282         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4283
4284         info->tx_enabled = false;
4285         info->tx_active = false;
4286 }
4287
4288 /* Fill the transmit FIFO until the FIFO is full or
4289  * there is no more data to load.
4290  */
4291 static void tx_load_fifo(SLMP_INFO *info)
4292 {
4293         u8 TwoBytes[2];
4294
4295         /* do nothing is now tx data available and no XON/XOFF pending */
4296
4297         if ( !info->tx_count && !info->x_char )
4298                 return;
4299
4300         /* load the Transmit FIFO until FIFOs full or all data sent */
4301
4302         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4303
4304                 /* there is more space in the transmit FIFO and */
4305                 /* there is more data in transmit buffer */
4306
4307                 if ( (info->tx_count > 1) && !info->x_char ) {
4308                         /* write 16-bits */
4309                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4310                         if (info->tx_get >= info->max_frame_size)
4311                                 info->tx_get -= info->max_frame_size;
4312                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4313                         if (info->tx_get >= info->max_frame_size)
4314                                 info->tx_get -= info->max_frame_size;
4315
4316                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4317
4318                         info->tx_count -= 2;
4319                         info->icount.tx += 2;
4320                 } else {
4321                         /* only 1 byte left to transmit or 1 FIFO slot left */
4322
4323                         if (info->x_char) {
4324                                 /* transmit pending high priority char */
4325                                 write_reg(info, TRB, info->x_char);
4326                                 info->x_char = 0;
4327                         } else {
4328                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4329                                 if (info->tx_get >= info->max_frame_size)
4330                                         info->tx_get -= info->max_frame_size;
4331                                 info->tx_count--;
4332                         }
4333                         info->icount.tx++;
4334                 }
4335         }
4336 }
4337
4338 /* Reset a port to a known state
4339  */
4340 static void reset_port(SLMP_INFO *info)
4341 {
4342         if (info->sca_base) {
4343
4344                 tx_stop(info);
4345                 rx_stop(info);
4346
4347                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4348                 set_signals(info);
4349
4350                 /* disable all port interrupts */
4351                 info->ie0_value = 0;
4352                 info->ie1_value = 0;
4353                 info->ie2_value = 0;
4354                 write_reg(info, IE0, info->ie0_value);
4355                 write_reg(info, IE1, info->ie1_value);
4356                 write_reg(info, IE2, info->ie2_value);
4357
4358                 write_reg(info, CMD, CHRESET);
4359         }
4360 }
4361
4362 /* Reset all the ports to a known state.
4363  */
4364 static void reset_adapter(SLMP_INFO *info)
4365 {
4366         int i;
4367
4368         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4369                 if (info->port_array[i])
4370                         reset_port(info->port_array[i]);
4371         }
4372 }
4373
4374 /* Program port for asynchronous communications.
4375  */
4376 static void async_mode(SLMP_INFO *info)
4377 {
4378
4379         unsigned char RegValue;
4380
4381         tx_stop(info);
4382         rx_stop(info);
4383
4384         /* MD0, Mode Register 0
4385          *
4386          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4387          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4388          * 03      Reserved, must be 0
4389          * 02      CRCCC, CRC Calculation, 0=disabled
4390          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4391          *
4392          * 0000 0000
4393          */
4394         RegValue = 0x00;
4395         if (info->params.stop_bits != 1)
4396                 RegValue |= BIT1;
4397         write_reg(info, MD0, RegValue);
4398
4399         /* MD1, Mode Register 1
4400          *
4401          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4402          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4403          * 03..02  RXCHR<1..0>, rx char size
4404          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4405          *
4406          * 0100 0000
4407          */
4408         RegValue = 0x40;
4409         switch (info->params.data_bits) {
4410         case 7: RegValue |= BIT4 + BIT2; break;
4411         case 6: RegValue |= BIT5 + BIT3; break;
4412         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4413         }
4414         if (info->params.parity != ASYNC_PARITY_NONE) {
4415                 RegValue |= BIT1;
4416                 if (info->params.parity == ASYNC_PARITY_ODD)
4417                         RegValue |= BIT0;
4418         }
4419         write_reg(info, MD1, RegValue);
4420
4421         /* MD2, Mode Register 2
4422          *
4423          * 07..02  Reserved, must be 0
4424          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4425          *
4426          * 0000 0000
4427          */
4428         RegValue = 0x00;
4429         if (info->params.loopback)
4430                 RegValue |= (BIT1 + BIT0);
4431         write_reg(info, MD2, RegValue);
4432
4433         /* RXS, Receive clock source
4434          *
4435          * 07      Reserved, must be 0
4436          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4437          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4438          */
4439         RegValue=BIT6;
4440         write_reg(info, RXS, RegValue);
4441
4442         /* TXS, Transmit clock source
4443          *
4444          * 07      Reserved, must be 0
4445          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4446          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4447          */
4448         RegValue=BIT6;
4449         write_reg(info, TXS, RegValue);
4450
4451         /* Control Register
4452          *
4453          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4454          */
4455         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4456         write_control_reg(info);
4457
4458         tx_set_idle(info);
4459
4460         /* RRC Receive Ready Control 0
4461          *
4462          * 07..05  Reserved, must be 0
4463          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4464          */
4465         write_reg(info, RRC, 0x00);
4466
4467         /* TRC0 Transmit Ready Control 0
4468          *
4469          * 07..05  Reserved, must be 0
4470          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4471          */
4472         write_reg(info, TRC0, 0x10);
4473
4474         /* TRC1 Transmit Ready Control 1
4475          *
4476          * 07..05  Reserved, must be 0
4477          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4478          */
4479         write_reg(info, TRC1, 0x1e);
4480
4481         /* CTL, MSCI control register
4482          *
4483          * 07..06  Reserved, set to 0
4484          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4485          * 04      IDLC, idle control, 0=mark 1=idle register
4486          * 03      BRK, break, 0=off 1 =on (async)
4487          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4488          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4489          * 00      RTS, RTS output control, 0=active 1=inactive
4490          *
4491          * 0001 0001
4492          */
4493         RegValue = 0x10;
4494         if (!(info->serial_signals & SerialSignal_RTS))
4495                 RegValue |= 0x01;
4496         write_reg(info, CTL, RegValue);
4497
4498         /* enable status interrupts */
4499         info->ie0_value |= TXINTE + RXINTE;
4500         write_reg(info, IE0, info->ie0_value);
4501
4502         /* enable break detect interrupt */
4503         info->ie1_value = BRKD;
4504         write_reg(info, IE1, info->ie1_value);
4505
4506         /* enable rx overrun interrupt */
4507         info->ie2_value = OVRN;
4508         write_reg(info, IE2, info->ie2_value);
4509
4510         set_rate( info, info->params.data_rate * 16 );
4511 }
4512
4513 /* Program the SCA for HDLC communications.
4514  */
4515 static void hdlc_mode(SLMP_INFO *info)
4516 {
4517         unsigned char RegValue;
4518         u32 DpllDivisor;
4519
4520         // Can't use DPLL because SCA outputs recovered clock on RxC when
4521         // DPLL mode selected. This causes output contention with RxC receiver.
4522         // Use of DPLL would require external hardware to disable RxC receiver
4523         // when DPLL mode selected.
4524         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4525
4526         /* disable DMA interrupts */
4527         write_reg(info, TXDMA + DIR, 0);
4528         write_reg(info, RXDMA + DIR, 0);
4529
4530         /* MD0, Mode Register 0
4531          *
4532          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4533          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4534          * 03      Reserved, must be 0
4535          * 02      CRCCC, CRC Calculation, 1=enabled
4536          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4537          * 00      CRC0, CRC initial value, 1 = all 1s
4538          *
4539          * 1000 0001
4540          */
4541         RegValue = 0x81;
4542         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4543                 RegValue |= BIT4;
4544         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4545                 RegValue |= BIT4;
4546         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4547                 RegValue |= BIT2 + BIT1;
4548         write_reg(info, MD0, RegValue);
4549
4550         /* MD1, Mode Register 1
4551          *
4552          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4553          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4554          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4555          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4556          *
4557          * 0000 0000
4558          */
4559         RegValue = 0x00;
4560         write_reg(info, MD1, RegValue);
4561
4562         /* MD2, Mode Register 2
4563          *
4564          * 07      NRZFM, 0=NRZ, 1=FM
4565          * 06..05  CODE<1..0> Encoding, 00=NRZ
4566          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4567          * 02      Reserved, must be 0
4568          * 01..00  CNCT<1..0> Channel connection, 0=normal
4569          *
4570          * 0000 0000
4571          */
4572         RegValue = 0x00;
4573         switch(info->params.encoding) {
4574         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4575         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4576         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4577         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4578 #if 0
4579         case HDLC_ENCODING_NRZB:                                        /* not supported */
4580         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4581         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4582 #endif
4583         }
4584         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4585                 DpllDivisor = 16;
4586                 RegValue |= BIT3;
4587         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4588                 DpllDivisor = 8;
4589         } else {
4590                 DpllDivisor = 32;
4591                 RegValue |= BIT4;
4592         }
4593         write_reg(info, MD2, RegValue);
4594
4595
4596         /* RXS, Receive clock source
4597          *
4598          * 07      Reserved, must be 0
4599          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4600          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4601          */
4602         RegValue=0;
4603         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4604                 RegValue |= BIT6;
4605         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4606                 RegValue |= BIT6 + BIT5;
4607         write_reg(info, RXS, RegValue);
4608
4609         /* TXS, Transmit clock source
4610          *
4611          * 07      Reserved, must be 0
4612          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4613          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4614          */
4615         RegValue=0;
4616         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4617                 RegValue |= BIT6;
4618         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4619                 RegValue |= BIT6 + BIT5;
4620         write_reg(info, TXS, RegValue);
4621
4622         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4623                 set_rate(info, info->params.clock_speed * DpllDivisor);
4624         else
4625                 set_rate(info, info->params.clock_speed);
4626
4627         /* GPDATA (General Purpose I/O Data Register)
4628          *
4629          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4630          */
4631         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4632                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4633         else
4634                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4635         write_control_reg(info);
4636
4637         /* RRC Receive Ready Control 0
4638          *
4639          * 07..05  Reserved, must be 0
4640          * 04..00  RRC<4..0> Rx FIFO trigger active
4641          */
4642         write_reg(info, RRC, rx_active_fifo_level);
4643
4644         /* TRC0 Transmit Ready Control 0
4645          *
4646          * 07..05  Reserved, must be 0
4647          * 04..00  TRC<4..0> Tx FIFO trigger active
4648          */
4649         write_reg(info, TRC0, tx_active_fifo_level);
4650
4651         /* TRC1 Transmit Ready Control 1
4652          *
4653          * 07..05  Reserved, must be 0
4654          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4655          */
4656         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4657
4658         /* DMR, DMA Mode Register
4659          *
4660          * 07..05  Reserved, must be 0
4661          * 04      TMOD, Transfer Mode: 1=chained-block
4662          * 03      Reserved, must be 0
4663          * 02      NF, Number of Frames: 1=multi-frame
4664          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4665          * 00      Reserved, must be 0
4666          *
4667          * 0001 0100
4668          */
4669         write_reg(info, TXDMA + DMR, 0x14);
4670         write_reg(info, RXDMA + DMR, 0x14);
4671
4672         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4673         write_reg(info, RXDMA + CPB,
4674                 (unsigned char)(info->buffer_list_phys >> 16));
4675
4676         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4677         write_reg(info, TXDMA + CPB,
4678                 (unsigned char)(info->buffer_list_phys >> 16));
4679
4680         /* enable status interrupts. other code enables/disables
4681          * the individual sources for these two interrupt classes.
4682          */
4683         info->ie0_value |= TXINTE + RXINTE;
4684         write_reg(info, IE0, info->ie0_value);
4685
4686         /* CTL, MSCI control register
4687          *
4688          * 07..06  Reserved, set to 0
4689          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4690          * 04      IDLC, idle control, 0=mark 1=idle register
4691          * 03      BRK, break, 0=off 1 =on (async)
4692          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4693          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4694          * 00      RTS, RTS output control, 0=active 1=inactive
4695          *
4696          * 0001 0001
4697          */
4698         RegValue = 0x10;
4699         if (!(info->serial_signals & SerialSignal_RTS))
4700                 RegValue |= 0x01;
4701         write_reg(info, CTL, RegValue);
4702
4703         /* preamble not supported ! */
4704
4705         tx_set_idle(info);
4706         tx_stop(info);
4707         rx_stop(info);
4708
4709         set_rate(info, info->params.clock_speed);
4710
4711         if (info->params.loopback)
4712                 enable_loopback(info,1);
4713 }
4714
4715 /* Set the transmit HDLC idle mode
4716  */
4717 static void tx_set_idle(SLMP_INFO *info)
4718 {
4719         unsigned char RegValue = 0xff;
4720
4721         /* Map API idle mode to SCA register bits */
4722         switch(info->idle_mode) {
4723         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4724         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4725         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4726         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4727         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4728         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4729         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4730         }
4731
4732         write_reg(info, IDL, RegValue);
4733 }
4734
4735 /* Query the adapter for the state of the V24 status (input) signals.
4736  */
4737 static void get_signals(SLMP_INFO *info)
4738 {
4739         u16 status = read_reg(info, SR3);
4740         u16 gpstatus = read_status_reg(info);
4741         u16 testbit;
4742
4743         /* clear all serial signals except DTR and RTS */
4744         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4745
4746         /* set serial signal bits to reflect MISR */
4747
4748         if (!(status & BIT3))
4749                 info->serial_signals |= SerialSignal_CTS;
4750
4751         if ( !(status & BIT2))
4752                 info->serial_signals |= SerialSignal_DCD;
4753
4754         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4755         if (!(gpstatus & testbit))
4756                 info->serial_signals |= SerialSignal_RI;
4757
4758         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4759         if (!(gpstatus & testbit))
4760                 info->serial_signals |= SerialSignal_DSR;
4761 }
4762
4763 /* Set the state of DTR and RTS based on contents of
4764  * serial_signals member of device context.
4765  */
4766 static void set_signals(SLMP_INFO *info)
4767 {
4768         unsigned char RegValue;
4769         u16 EnableBit;
4770
4771         RegValue = read_reg(info, CTL);
4772         if (info->serial_signals & SerialSignal_RTS)
4773                 RegValue &= ~BIT0;
4774         else
4775                 RegValue |= BIT0;
4776         write_reg(info, CTL, RegValue);
4777
4778         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4779         EnableBit = BIT1 << (info->port_num*2);
4780         if (info->serial_signals & SerialSignal_DTR)
4781                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4782         else
4783                 info->port_array[0]->ctrlreg_value |= EnableBit;
4784         write_control_reg(info);
4785 }
4786
4787 /*******************/
4788 /* DMA Buffer Code */
4789 /*******************/
4790
4791 /* Set the count for all receive buffers to SCABUFSIZE
4792  * and set the current buffer to the first buffer. This effectively
4793  * makes all buffers free and discards any data in buffers.
4794  */
4795 static void rx_reset_buffers(SLMP_INFO *info)
4796 {
4797         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4798 }
4799
4800 /* Free the buffers used by a received frame
4801  *
4802  * info   pointer to device instance data
4803  * first  index of 1st receive buffer of frame
4804  * last   index of last receive buffer of frame
4805  */
4806 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4807 {
4808         bool done = false;
4809
4810         while(!done) {
4811                 /* reset current buffer for reuse */
4812                 info->rx_buf_list[first].status = 0xff;
4813
4814                 if (first == last) {
4815                         done = true;
4816                         /* set new last rx descriptor address */
4817                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4818                 }
4819
4820                 first++;
4821                 if (first == info->rx_buf_count)
4822                         first = 0;
4823         }
4824
4825         /* set current buffer to next buffer after last buffer of frame */
4826         info->current_rx_buf = first;
4827 }
4828
4829 /* Return a received frame from the receive DMA buffers.
4830  * Only frames received without errors are returned.
4831  *
4832  * Return Value:        true if frame returned, otherwise false
4833  */
4834 static bool rx_get_frame(SLMP_INFO *info)
4835 {
4836         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4837         unsigned short status;
4838         unsigned int framesize = 0;
4839         bool ReturnCode = false;
4840         unsigned long flags;
4841         struct tty_struct *tty = info->port.tty;
4842         unsigned char addr_field = 0xff;
4843         SCADESC *desc;
4844         SCADESC_EX *desc_ex;
4845
4846 CheckAgain:
4847         /* assume no frame returned, set zero length */
4848         framesize = 0;
4849         addr_field = 0xff;
4850
4851         /*
4852          * current_rx_buf points to the 1st buffer of the next available
4853          * receive frame. To find the last buffer of the frame look for
4854          * a non-zero status field in the buffer entries. (The status
4855          * field is set by the 16C32 after completing a receive frame.
4856          */
4857         StartIndex = EndIndex = info->current_rx_buf;
4858
4859         for ( ;; ) {
4860                 desc = &info->rx_buf_list[EndIndex];
4861                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4862
4863                 if (desc->status == 0xff)
4864                         goto Cleanup;   /* current desc still in use, no frames available */
4865
4866                 if (framesize == 0 && info->params.addr_filter != 0xff)
4867                         addr_field = desc_ex->virt_addr[0];
4868
4869                 framesize += desc->length;
4870
4871                 /* Status != 0 means last buffer of frame */
4872                 if (desc->status)
4873                         break;
4874
4875                 EndIndex++;
4876                 if (EndIndex == info->rx_buf_count)
4877                         EndIndex = 0;
4878
4879                 if (EndIndex == info->current_rx_buf) {
4880                         /* all buffers have been 'used' but none mark      */
4881                         /* the end of a frame. Reset buffers and receiver. */
4882                         if ( info->rx_enabled ){
4883                                 spin_lock_irqsave(&info->lock,flags);
4884                                 rx_start(info);
4885                                 spin_unlock_irqrestore(&info->lock,flags);
4886                         }
4887                         goto Cleanup;
4888                 }
4889
4890         }
4891
4892         /* check status of receive frame */
4893
4894         /* frame status is byte stored after frame data
4895          *
4896          * 7 EOM (end of msg), 1 = last buffer of frame
4897          * 6 Short Frame, 1 = short frame
4898          * 5 Abort, 1 = frame aborted
4899          * 4 Residue, 1 = last byte is partial
4900          * 3 Overrun, 1 = overrun occurred during frame reception
4901          * 2 CRC,     1 = CRC error detected
4902          *
4903          */
4904         status = desc->status;
4905
4906         /* ignore CRC bit if not using CRC (bit is undefined) */
4907         /* Note:CRC is not save to data buffer */
4908         if (info->params.crc_type == HDLC_CRC_NONE)
4909                 status &= ~BIT2;
4910
4911         if (framesize == 0 ||
4912                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4913                 /* discard 0 byte frames, this seems to occur sometime
4914                  * when remote is idling flags.
4915                  */
4916                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4917                 goto CheckAgain;
4918         }
4919
4920         if (framesize < 2)
4921                 status |= BIT6;
4922
4923         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4924                 /* received frame has errors,
4925                  * update counts and mark frame size as 0
4926                  */
4927                 if (status & BIT6)
4928                         info->icount.rxshort++;
4929                 else if (status & BIT5)
4930                         info->icount.rxabort++;
4931                 else if (status & BIT3)
4932                         info->icount.rxover++;
4933                 else
4934                         info->icount.rxcrc++;
4935
4936                 framesize = 0;
4937 #if SYNCLINK_GENERIC_HDLC
4938                 {
4939                         info->netdev->stats.rx_errors++;
4940                         info->netdev->stats.rx_frame_errors++;
4941                 }
4942 #endif
4943         }
4944
4945         if ( debug_level >= DEBUG_LEVEL_BH )
4946                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4947                         __FILE__,__LINE__,info->device_name,status,framesize);
4948
4949         if ( debug_level >= DEBUG_LEVEL_DATA )
4950                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4951                         min_t(unsigned int, framesize, SCABUFSIZE), 0);
4952
4953         if (framesize) {
4954                 if (framesize > info->max_frame_size)
4955                         info->icount.rxlong++;
4956                 else {
4957                         /* copy dma buffer(s) to contiguous intermediate buffer */
4958                         int copy_count = framesize;
4959                         int index = StartIndex;
4960                         unsigned char *ptmp = info->tmp_rx_buf;
4961                         info->tmp_rx_buf_count = framesize;
4962
4963                         info->icount.rxok++;
4964
4965                         while(copy_count) {
4966                                 int partial_count = min(copy_count,SCABUFSIZE);
4967                                 memcpy( ptmp,
4968                                         info->rx_buf_list_ex[index].virt_addr,
4969                                         partial_count );
4970                                 ptmp += partial_count;
4971                                 copy_count -= partial_count;
4972
4973                                 if ( ++index == info->rx_buf_count )
4974                                         index = 0;
4975                         }
4976
4977 #if SYNCLINK_GENERIC_HDLC
4978                         if (info->netcount)
4979                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4980                         else
4981 #endif
4982                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
4983                                                   info->flag_buf, framesize);
4984                 }
4985         }
4986         /* Free the buffers used by this frame. */
4987         rx_free_frame_buffers( info, StartIndex, EndIndex );
4988
4989         ReturnCode = true;
4990
4991 Cleanup:
4992         if ( info->rx_enabled && info->rx_overflow ) {
4993                 /* Receiver is enabled, but needs to restarted due to
4994                  * rx buffer overflow. If buffers are empty, restart receiver.
4995                  */
4996                 if (info->rx_buf_list[EndIndex].status == 0xff) {
4997                         spin_lock_irqsave(&info->lock,flags);
4998                         rx_start(info);
4999                         spin_unlock_irqrestore(&info->lock,flags);
5000                 }
5001         }
5002
5003         return ReturnCode;
5004 }
5005
5006 /* load the transmit DMA buffer with data
5007  */
5008 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5009 {
5010         unsigned short copy_count;
5011         unsigned int i = 0;
5012         SCADESC *desc;
5013         SCADESC_EX *desc_ex;
5014
5015         if ( debug_level >= DEBUG_LEVEL_DATA )
5016                 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5017
5018         /* Copy source buffer to one or more DMA buffers, starting with
5019          * the first transmit dma buffer.
5020          */
5021         for(i=0;;)
5022         {
5023                 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5024
5025                 desc = &info->tx_buf_list[i];
5026                 desc_ex = &info->tx_buf_list_ex[i];
5027
5028                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5029
5030                 desc->length = copy_count;
5031                 desc->status = 0;
5032
5033                 buf += copy_count;
5034                 count -= copy_count;
5035
5036                 if (!count)
5037                         break;
5038
5039                 i++;
5040                 if (i >= info->tx_buf_count)
5041                         i = 0;
5042         }
5043
5044         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5045         info->last_tx_buf = ++i;
5046 }
5047
5048 static bool register_test(SLMP_INFO *info)
5049 {
5050         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5051         static unsigned int count = ARRAY_SIZE(testval);
5052         unsigned int i;
5053         bool rc = true;
5054         unsigned long flags;
5055
5056         spin_lock_irqsave(&info->lock,flags);
5057         reset_port(info);
5058
5059         /* assume failure */
5060         info->init_error = DiagStatus_AddressFailure;
5061
5062         /* Write bit patterns to various registers but do it out of */
5063         /* sync, then read back and verify values. */
5064
5065         for (i = 0 ; i < count ; i++) {
5066                 write_reg(info, TMC, testval[i]);
5067                 write_reg(info, IDL, testval[(i+1)%count]);
5068                 write_reg(info, SA0, testval[(i+2)%count]);
5069                 write_reg(info, SA1, testval[(i+3)%count]);
5070
5071                 if ( (read_reg(info, TMC) != testval[i]) ||
5072                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5073                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5074                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5075                 {
5076                         rc = false;
5077                         break;
5078                 }
5079         }
5080
5081         reset_port(info);
5082         spin_unlock_irqrestore(&info->lock,flags);
5083
5084         return rc;
5085 }
5086
5087 static bool irq_test(SLMP_INFO *info)
5088 {
5089         unsigned long timeout;
5090         unsigned long flags;
5091
5092         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5093
5094         spin_lock_irqsave(&info->lock,flags);
5095         reset_port(info);
5096
5097         /* assume failure */
5098         info->init_error = DiagStatus_IrqFailure;
5099         info->irq_occurred = false;
5100
5101         /* setup timer0 on SCA0 to interrupt */
5102
5103         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5104         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5105
5106         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5107         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5108
5109
5110         /* TMCS, Timer Control/Status Register
5111          *
5112          * 07      CMF, Compare match flag (read only) 1=match
5113          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5114          * 05      Reserved, must be 0
5115          * 04      TME, Timer Enable
5116          * 03..00  Reserved, must be 0
5117          *
5118          * 0101 0000
5119          */
5120         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5121
5122         spin_unlock_irqrestore(&info->lock,flags);
5123
5124         timeout=100;
5125         while( timeout-- && !info->irq_occurred ) {
5126                 msleep_interruptible(10);
5127         }
5128
5129         spin_lock_irqsave(&info->lock,flags);
5130         reset_port(info);
5131         spin_unlock_irqrestore(&info->lock,flags);
5132
5133         return info->irq_occurred;
5134 }
5135
5136 /* initialize individual SCA device (2 ports)
5137  */
5138 static bool sca_init(SLMP_INFO *info)
5139 {
5140         /* set wait controller to single mem partition (low), no wait states */
5141         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5142         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5143         write_reg(info, WCRL, 0);       /* wait controller low range */
5144         write_reg(info, WCRM, 0);       /* wait controller mid range */
5145         write_reg(info, WCRH, 0);       /* wait controller high range */
5146
5147         /* DPCR, DMA Priority Control
5148          *
5149          * 07..05  Not used, must be 0
5150          * 04      BRC, bus release condition: 0=all transfers complete
5151          * 03      CCC, channel change condition: 0=every cycle
5152          * 02..00  PR<2..0>, priority 100=round robin
5153          *
5154          * 00000100 = 0x04
5155          */
5156         write_reg(info, DPCR, dma_priority);
5157
5158         /* DMA Master Enable, BIT7: 1=enable all channels */
5159         write_reg(info, DMER, 0x80);
5160
5161         /* enable all interrupt classes */
5162         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5163         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5164         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5165
5166         /* ITCR, interrupt control register
5167          * 07      IPC, interrupt priority, 0=MSCI->DMA
5168          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5169          * 04      VOS, Vector Output, 0=unmodified vector
5170          * 03..00  Reserved, must be 0
5171          */
5172         write_reg(info, ITCR, 0);
5173
5174         return true;
5175 }
5176
5177 /* initialize adapter hardware
5178  */
5179 static bool init_adapter(SLMP_INFO *info)
5180 {
5181         int i;
5182
5183         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5184         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5185         u32 readval;
5186
5187         info->misc_ctrl_value |= BIT30;
5188         *MiscCtrl = info->misc_ctrl_value;
5189
5190         /*
5191          * Force at least 170ns delay before clearing
5192          * reset bit. Each read from LCR takes at least
5193          * 30ns so 10 times for 300ns to be safe.
5194          */
5195         for(i=0;i<10;i++)
5196                 readval = *MiscCtrl;
5197
5198         info->misc_ctrl_value &= ~BIT30;
5199         *MiscCtrl = info->misc_ctrl_value;
5200
5201         /* init control reg (all DTRs off, all clksel=input) */
5202         info->ctrlreg_value = 0xaa;
5203         write_control_reg(info);
5204
5205         {
5206                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5207                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5208
5209                 switch(read_ahead_count)
5210                 {
5211                 case 16:
5212                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5213                         break;
5214                 case 8:
5215                         lcr1_brdr_value |= BIT5 + BIT4;
5216                         break;
5217                 case 4:
5218                         lcr1_brdr_value |= BIT5 + BIT3;
5219                         break;
5220                 case 0:
5221                         lcr1_brdr_value |= BIT5;
5222                         break;
5223                 }
5224
5225                 *LCR1BRDR = lcr1_brdr_value;
5226                 *MiscCtrl = misc_ctrl_value;
5227         }
5228
5229         sca_init(info->port_array[0]);
5230         sca_init(info->port_array[2]);
5231
5232         return true;
5233 }
5234
5235 /* Loopback an HDLC frame to test the hardware
5236  * interrupt and DMA functions.
5237  */
5238 static bool loopback_test(SLMP_INFO *info)
5239 {
5240 #define TESTFRAMESIZE 20
5241
5242         unsigned long timeout;
5243         u16 count = TESTFRAMESIZE;
5244         unsigned char buf[TESTFRAMESIZE];
5245         bool rc = false;
5246         unsigned long flags;
5247
5248         struct tty_struct *oldtty = info->port.tty;
5249         u32 speed = info->params.clock_speed;
5250
5251         info->params.clock_speed = 3686400;
5252         info->port.tty = NULL;
5253
5254         /* assume failure */
5255         info->init_error = DiagStatus_DmaFailure;
5256
5257         /* build and send transmit frame */
5258         for (count = 0; count < TESTFRAMESIZE;++count)
5259                 buf[count] = (unsigned char)count;
5260
5261         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5262
5263         /* program hardware for HDLC and enabled receiver */
5264         spin_lock_irqsave(&info->lock,flags);
5265         hdlc_mode(info);
5266         enable_loopback(info,1);
5267         rx_start(info);
5268         info->tx_count = count;
5269         tx_load_dma_buffer(info,buf,count);
5270         tx_start(info);
5271         spin_unlock_irqrestore(&info->lock,flags);
5272
5273         /* wait for receive complete */
5274         /* Set a timeout for waiting for interrupt. */
5275         for ( timeout = 100; timeout; --timeout ) {
5276                 msleep_interruptible(10);
5277
5278                 if (rx_get_frame(info)) {
5279                         rc = true;
5280                         break;
5281                 }
5282         }
5283
5284         /* verify received frame length and contents */
5285         if (rc &&
5286             ( info->tmp_rx_buf_count != count ||
5287               memcmp(buf, info->tmp_rx_buf,count))) {
5288                 rc = false;
5289         }
5290
5291         spin_lock_irqsave(&info->lock,flags);
5292         reset_adapter(info);
5293         spin_unlock_irqrestore(&info->lock,flags);
5294
5295         info->params.clock_speed = speed;
5296         info->port.tty = oldtty;
5297
5298         return rc;
5299 }
5300
5301 /* Perform diagnostics on hardware
5302  */
5303 static int adapter_test( SLMP_INFO *info )
5304 {
5305         unsigned long flags;
5306         if ( debug_level >= DEBUG_LEVEL_INFO )
5307                 printk( "%s(%d):Testing device %s\n",
5308                         __FILE__,__LINE__,info->device_name );
5309
5310         spin_lock_irqsave(&info->lock,flags);
5311         init_adapter(info);
5312         spin_unlock_irqrestore(&info->lock,flags);
5313
5314         info->port_array[0]->port_count = 0;
5315
5316         if ( register_test(info->port_array[0]) &&
5317                 register_test(info->port_array[1])) {
5318
5319                 info->port_array[0]->port_count = 2;
5320
5321                 if ( register_test(info->port_array[2]) &&
5322                         register_test(info->port_array[3]) )
5323                         info->port_array[0]->port_count += 2;
5324         }
5325         else {
5326                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5327                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5328                 return -ENODEV;
5329         }
5330
5331         if ( !irq_test(info->port_array[0]) ||
5332                 !irq_test(info->port_array[1]) ||
5333                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5334                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5335                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5336                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5337                 return -ENODEV;
5338         }
5339
5340         if (!loopback_test(info->port_array[0]) ||
5341                 !loopback_test(info->port_array[1]) ||
5342                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5343                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5344                 printk( "%s(%d):DMA test failure for device %s\n",
5345                         __FILE__,__LINE__,info->device_name);
5346                 return -ENODEV;
5347         }
5348
5349         if ( debug_level >= DEBUG_LEVEL_INFO )
5350                 printk( "%s(%d):device %s passed diagnostics\n",
5351                         __FILE__,__LINE__,info->device_name );
5352
5353         info->port_array[0]->init_error = 0;
5354         info->port_array[1]->init_error = 0;
5355         if ( info->port_count > 2 ) {
5356                 info->port_array[2]->init_error = 0;
5357                 info->port_array[3]->init_error = 0;
5358         }
5359
5360         return 0;
5361 }
5362
5363 /* Test the shared memory on a PCI adapter.
5364  */
5365 static bool memory_test(SLMP_INFO *info)
5366 {
5367         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5368                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5369         unsigned long count = ARRAY_SIZE(testval);
5370         unsigned long i;
5371         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5372         unsigned long * addr = (unsigned long *)info->memory_base;
5373
5374         /* Test data lines with test pattern at one location. */
5375
5376         for ( i = 0 ; i < count ; i++ ) {
5377                 *addr = testval[i];
5378                 if ( *addr != testval[i] )
5379                         return false;
5380         }
5381
5382         /* Test address lines with incrementing pattern over */
5383         /* entire address range. */
5384
5385         for ( i = 0 ; i < limit ; i++ ) {
5386                 *addr = i * 4;
5387                 addr++;
5388         }
5389
5390         addr = (unsigned long *)info->memory_base;
5391
5392         for ( i = 0 ; i < limit ; i++ ) {
5393                 if ( *addr != i * 4 )
5394                         return false;
5395                 addr++;
5396         }
5397
5398         memset( info->memory_base, 0, SCA_MEM_SIZE );
5399         return true;
5400 }
5401
5402 /* Load data into PCI adapter shared memory.
5403  *
5404  * The PCI9050 releases control of the local bus
5405  * after completing the current read or write operation.
5406  *
5407  * While the PCI9050 write FIFO not empty, the
5408  * PCI9050 treats all of the writes as a single transaction
5409  * and does not release the bus. This causes DMA latency problems
5410  * at high speeds when copying large data blocks to the shared memory.
5411  *
5412  * This function breaks a write into multiple transations by
5413  * interleaving a read which flushes the write FIFO and 'completes'
5414  * the write transation. This allows any pending DMA request to gain control
5415  * of the local bus in a timely fasion.
5416  */
5417 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5418 {
5419         /* A load interval of 16 allows for 4 32-bit writes at */
5420         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5421
5422         unsigned short interval = count / sca_pci_load_interval;
5423         unsigned short i;
5424
5425         for ( i = 0 ; i < interval ; i++ )
5426         {
5427                 memcpy(dest, src, sca_pci_load_interval);
5428                 read_status_reg(info);
5429                 dest += sca_pci_load_interval;
5430                 src += sca_pci_load_interval;
5431         }
5432
5433         memcpy(dest, src, count % sca_pci_load_interval);
5434 }
5435
5436 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5437 {
5438         int i;
5439         int linecount;
5440         if (xmit)
5441                 printk("%s tx data:\n",info->device_name);
5442         else
5443                 printk("%s rx data:\n",info->device_name);
5444
5445         while(count) {
5446                 if (count > 16)
5447                         linecount = 16;
5448                 else
5449                         linecount = count;
5450
5451                 for(i=0;i<linecount;i++)
5452                         printk("%02X ",(unsigned char)data[i]);
5453                 for(;i<17;i++)
5454                         printk("   ");
5455                 for(i=0;i<linecount;i++) {
5456                         if (data[i]>=040 && data[i]<=0176)
5457                                 printk("%c",data[i]);
5458                         else
5459                                 printk(".");
5460                 }
5461                 printk("\n");
5462
5463                 data  += linecount;
5464                 count -= linecount;
5465         }
5466 }       /* end of trace_block() */
5467
5468 /* called when HDLC frame times out
5469  * update stats and do tx completion processing
5470  */
5471 static void tx_timeout(unsigned long context)
5472 {
5473         SLMP_INFO *info = (SLMP_INFO*)context;
5474         unsigned long flags;
5475
5476         if ( debug_level >= DEBUG_LEVEL_INFO )
5477                 printk( "%s(%d):%s tx_timeout()\n",
5478                         __FILE__,__LINE__,info->device_name);
5479         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5480                 info->icount.txtimeout++;
5481         }
5482         spin_lock_irqsave(&info->lock,flags);
5483         info->tx_active = false;
5484         info->tx_count = info->tx_put = info->tx_get = 0;
5485
5486         spin_unlock_irqrestore(&info->lock,flags);
5487
5488 #if SYNCLINK_GENERIC_HDLC
5489         if (info->netcount)
5490                 hdlcdev_tx_done(info);
5491         else
5492 #endif
5493                 bh_transmit(info);
5494 }
5495
5496 /* called to periodically check the DSR/RI modem signal input status
5497  */
5498 static void status_timeout(unsigned long context)
5499 {
5500         u16 status = 0;
5501         SLMP_INFO *info = (SLMP_INFO*)context;
5502         unsigned long flags;
5503         unsigned char delta;
5504
5505
5506         spin_lock_irqsave(&info->lock,flags);
5507         get_signals(info);
5508         spin_unlock_irqrestore(&info->lock,flags);
5509
5510         /* check for DSR/RI state change */
5511
5512         delta = info->old_signals ^ info->serial_signals;
5513         info->old_signals = info->serial_signals;
5514
5515         if (delta & SerialSignal_DSR)
5516                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5517
5518         if (delta & SerialSignal_RI)
5519                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5520
5521         if (delta & SerialSignal_DCD)
5522                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5523
5524         if (delta & SerialSignal_CTS)
5525                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5526
5527         if (status)
5528                 isr_io_pin(info,status);
5529
5530         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5531 }
5532
5533
5534 /* Register Access Routines -
5535  * All registers are memory mapped
5536  */
5537 #define CALC_REGADDR() \
5538         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5539         if (info->port_num > 1) \
5540                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5541         if ( info->port_num & 1) { \
5542                 if (Addr > 0x7f) \
5543                         RegAddr += 0x40;        /* DMA access */ \
5544                 else if (Addr > 0x1f && Addr < 0x60) \
5545                         RegAddr += 0x20;        /* MSCI access */ \
5546         }
5547
5548
5549 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5550 {
5551         CALC_REGADDR();
5552         return *RegAddr;
5553 }
5554 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5555 {
5556         CALC_REGADDR();
5557         *RegAddr = Value;
5558 }
5559
5560 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5561 {
5562         CALC_REGADDR();
5563         return *((u16 *)RegAddr);
5564 }
5565
5566 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5567 {
5568         CALC_REGADDR();
5569         *((u16 *)RegAddr) = Value;
5570 }
5571
5572 static unsigned char read_status_reg(SLMP_INFO * info)
5573 {
5574         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5575         return *RegAddr;
5576 }
5577
5578 static void write_control_reg(SLMP_INFO * info)
5579 {
5580         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5581         *RegAddr = info->port_array[0]->ctrlreg_value;
5582 }
5583
5584
5585 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5586                                           const struct pci_device_id *ent)
5587 {
5588         if (pci_enable_device(dev)) {
5589                 printk("error enabling pci device %p\n", dev);
5590                 return -EIO;
5591         }
5592         device_init( ++synclinkmp_adapter_count, dev );
5593         return 0;
5594 }
5595
5596 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5597 {
5598 }