2 * drivers/serial/tegra_hsuart.c
4 * High-speed serial driver for NVIDIA Tegra SoCs
6 * Copyright (C) 2009-2011 NVIDIA Corporation
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
24 /*#define VERBOSE_DEBUG 1*/
26 #include <linux/module.h>
27 #include <linux/serial.h>
28 #include <linux/serial_core.h>
29 #include <linux/platform_device.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/dmapool.h>
33 #include <linux/termios.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <linux/clk.h>
37 #include <linux/string.h>
38 #include <linux/pagemap.h>
39 #include <linux/serial_reg.h>
40 #include <linux/serial_8250.h>
41 #include <linux/debugfs.h>
42 #include <linux/slab.h>
43 #include <linux/workqueue.h>
44 #include <linux/tegra_uart.h>
49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
51 #define BYTES_TO_ALIGN(x) ((unsigned long)(ALIGN((x), sizeof(u32))) - \
54 #define UART_RX_DMA_BUFFER_SIZE (2048*4)
56 #define UART_LSR_FIFOE 0x80
57 #define UART_IER_EORD 0x20
58 #define UART_MCR_RTS_EN 0x40
59 #define UART_MCR_CTS_EN 0x20
60 #define UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
61 UART_LSR_PE | UART_LSR_FE)
63 #define TX_FORCE_PIO 0
64 #define RX_FORCE_PIO 0
66 const int dma_req_sel[] = {
67 TEGRA_DMA_REQ_SEL_UARTA,
68 TEGRA_DMA_REQ_SEL_UARTB,
69 TEGRA_DMA_REQ_SEL_UARTC,
70 TEGRA_DMA_REQ_SEL_UARTD,
71 TEGRA_DMA_REQ_SEL_UARTE,
74 #define TEGRA_TX_PIO 1
75 #define TEGRA_TX_DMA 2
77 #define TEGRA_UART_MIN_DMA 16
78 #define TEGRA_UART_FIFO_SIZE 8
80 #define TEGRA_UART_CLOSED 0
81 #define TEGRA_UART_OPENED 1
82 #define TEGRA_UART_CLOCK_OFF 2
83 #define TEGRA_UART_SUSPEND 3
85 /* Tx fifo trigger level setting in tegra uart is in
86 * reverse way then conventional uart */
87 #define TEGRA_UART_TX_TRIG_16B 0x00
88 #define TEGRA_UART_TX_TRIG_8B 0x10
89 #define TEGRA_UART_TX_TRIG_4B 0x20
90 #define TEGRA_UART_TX_TRIG_1B 0x30
92 struct tegra_uart_port {
93 struct uart_port uport;
101 /* Register shadow */
102 unsigned char fcr_shadow;
103 unsigned char mcr_shadow;
104 unsigned char lcr_shadow;
105 unsigned char ier_shadow;
106 bool use_cts_control;
110 unsigned int tx_bytes;
112 dma_addr_t xmit_dma_addr;
115 struct tegra_dma_req tx_dma_req;
116 struct tegra_dma_channel *tx_dma;
119 struct tegra_dma_req rx_dma_req;
120 struct tegra_dma_channel *rx_dma;
129 static inline u8 uart_readb(struct tegra_uart_port *t, unsigned long reg)
131 u8 val = readb(t->uport.membase + (reg << t->uport.regshift));
132 dev_vdbg(t->uport.dev, "%s: %p %03lx = %02x\n", __func__,
133 t->uport.membase, reg << t->uport.regshift, val);
137 static inline void uart_writeb(struct tegra_uart_port *t, u8 val,
140 dev_vdbg(t->uport.dev, "%s: %p %03lx %02x\n",
141 __func__, t->uport.membase, reg << t->uport.regshift, val);
142 writeb(val, t->uport.membase + (reg << t->uport.regshift));
145 static inline void uart_writel(struct tegra_uart_port *t, u32 val,
148 dev_vdbg(t->uport.dev, "%s: %p %03lx %08x\n",
149 __func__, t->uport.membase, reg << t->uport.regshift, val);
150 writel(val, t->uport.membase + (reg << t->uport.regshift));
153 static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud);
154 static void tegra_set_mctrl(struct uart_port *u, unsigned int mctrl);
155 static void do_handle_rx_pio(struct tegra_uart_port *t);
156 static void do_handle_rx_dma(struct tegra_uart_port *t);
157 static void set_rts(struct tegra_uart_port *t, bool active);
158 static void set_dtr(struct tegra_uart_port *t, bool active);
160 static void fill_tx_fifo(struct tegra_uart_port *t, int max_bytes)
163 struct circ_buf *xmit = &t->uport.state->xmit;
165 for (i = 0; i < max_bytes; i++) {
166 BUG_ON(uart_circ_empty(xmit));
167 uart_writeb(t, xmit->buf[xmit->tail], UART_TX);
168 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
169 t->uport.icount.tx++;
173 static void tegra_start_pio_tx(struct tegra_uart_port *t, unsigned int bytes)
175 if (bytes > TEGRA_UART_FIFO_SIZE)
176 bytes = TEGRA_UART_FIFO_SIZE;
178 t->fcr_shadow &= ~UART_FCR_T_TRIG_11;
179 t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
180 uart_writeb(t, t->fcr_shadow, UART_FCR);
181 t->tx_in_progress = TEGRA_TX_PIO;
183 t->ier_shadow |= UART_IER_THRI;
184 uart_writeb(t, t->ier_shadow, UART_IER);
187 static void tegra_start_dma_tx(struct tegra_uart_port *t, unsigned long bytes)
189 struct circ_buf *xmit;
190 xmit = &t->uport.state->xmit;
192 dma_sync_single_for_device(t->uport.dev, t->xmit_dma_addr,
193 UART_XMIT_SIZE, DMA_TO_DEVICE);
195 t->fcr_shadow &= ~UART_FCR_T_TRIG_11;
196 t->fcr_shadow |= TEGRA_UART_TX_TRIG_4B;
197 uart_writeb(t, t->fcr_shadow, UART_FCR);
199 t->tx_bytes = bytes & ~(sizeof(u32)-1);
200 t->tx_dma_req.source_addr = t->xmit_dma_addr + xmit->tail;
201 t->tx_dma_req.size = t->tx_bytes;
203 t->tx_in_progress = TEGRA_TX_DMA;
205 tegra_dma_enqueue_req(t->tx_dma, &t->tx_dma_req);
208 /* Called with u->lock taken */
209 static void tegra_start_next_tx(struct tegra_uart_port *t)
214 struct circ_buf *xmit;
216 xmit = &t->uport.state->xmit;
217 tail = (unsigned long)&xmit->buf[xmit->tail];
218 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
221 dev_vdbg(t->uport.dev, "+%s %lu %d\n", __func__, count,
227 if (!t->use_tx_dma || count < TEGRA_UART_MIN_DMA)
228 tegra_start_pio_tx(t, count);
229 else if (BYTES_TO_ALIGN(tail) > 0)
230 tegra_start_pio_tx(t, BYTES_TO_ALIGN(tail));
232 tegra_start_dma_tx(t, count);
235 dev_vdbg(t->uport.dev, "-%s", __func__);
238 /* Called by serial core driver with u->lock taken. */
239 static void tegra_start_tx(struct uart_port *u)
241 struct tegra_uart_port *t;
242 struct circ_buf *xmit;
244 t = container_of(u, struct tegra_uart_port, uport);
245 xmit = &u->state->xmit;
247 if (!uart_circ_empty(xmit) && !t->tx_in_progress)
248 tegra_start_next_tx(t);
251 static int tegra_start_dma_rx(struct tegra_uart_port *t)
254 if (tegra_dma_enqueue_req(t->rx_dma, &t->rx_dma_req)) {
255 dev_err(t->uport.dev, "Could not enqueue Rx DMA req\n");
261 static void tegra_rx_dma_threshold_callback(struct tegra_dma_req *req)
263 struct tegra_uart_port *t = req->dev;
264 struct uart_port *u = &t->uport;
267 spin_lock_irqsave(&u->lock, flags);
271 spin_unlock_irqrestore(&u->lock, flags);
274 /* It is expected that the callers take the UART lock when this API is called.
276 * There are 2 contexts when this function is called:
278 * 1. DMA ISR - DMA ISR triggers the threshold complete calback, which calls the
279 * dequue API which in-turn calls this callback. UART lock is taken during
280 * the call to the threshold callback.
282 * 2. UART ISR - UART calls the dequue API which in-turn will call this API.
283 * In this case, UART ISR takes the UART lock.
285 static void tegra_rx_dma_complete_callback(struct tegra_dma_req *req)
287 struct tegra_uart_port *t = req->dev;
288 struct uart_port *u = &t->uport;
289 struct tty_struct *tty = u->state->port.tty;
291 /* If we are here, DMA is stopped */
293 dev_dbg(t->uport.dev, "%s: %d %d\n", __func__, req->bytes_transferred,
295 if (req->bytes_transferred) {
296 t->uport.icount.rx += req->bytes_transferred;
297 tty_insert_flip_string(tty,
298 ((unsigned char *)(req->virt_addr)),
299 req->bytes_transferred);
304 /* Push the read data later in caller place. */
305 if (req->status == -TEGRA_DMA_REQ_ERROR_ABORTED)
308 spin_unlock(&u->lock);
309 tty_flip_buffer_push(u->state->port.tty);
313 /* Lock already taken */
314 static void do_handle_rx_dma(struct tegra_uart_port *t)
316 struct uart_port *u = &t->uport;
319 tegra_dma_dequeue(t->rx_dma);
320 tty_flip_buffer_push(u->state->port.tty);
321 /* enqueue the request again */
322 tegra_start_dma_rx(t);
327 /* Wait for a symbol-time. */
328 static void wait_sym_time(struct tegra_uart_port *t, unsigned int syms)
331 /* Definitely have a start bit. */
332 unsigned int bits = 1;
333 switch (t->lcr_shadow & 3) {
348 /* Technically 5 bits gets 1.5 bits of stop... */
349 if (t->lcr_shadow & UART_LCR_STOP) {
355 if (t->lcr_shadow & UART_LCR_PARITY)
359 udelay(DIV_ROUND_UP(syms * bits * 1000000, t->baud));
362 /* Flush desired FIFO. */
363 static void tegra_fifo_reset(struct tegra_uart_port *t, u8 fcr_bits)
365 unsigned char fcr = t->fcr_shadow;
366 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
367 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
368 uart_writeb(t, fcr, UART_FCR);
370 /*Hw issue: Resetting tx fifo with non-fifo
371 mode to avoid any extra character to be sent*/
372 fcr &= ~UART_FCR_ENABLE_FIFO;
373 uart_writeb(t, fcr, UART_FCR);
375 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
376 uart_writeb(t, fcr, UART_FCR);
377 fcr |= UART_FCR_ENABLE_FIFO;
378 uart_writeb(t, fcr, UART_FCR);
380 uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */
381 wait_sym_time(t, 1); /* Wait for the flush to propagate. */
384 static char do_decode_rx_error(struct tegra_uart_port *t, u8 lsr)
386 char flag = TTY_NORMAL;
388 if (unlikely(lsr & UART_LSR_ANY)) {
389 if (lsr & UART_LSR_OE) {
392 t->uport.icount.overrun++;
393 dev_err(t->uport.dev, "Got overrun errors\n");
394 } else if (lsr & UART_LSR_PE) {
397 t->uport.icount.parity++;
398 dev_err(t->uport.dev, "Got Parity errors\n");
399 } else if (lsr & UART_LSR_FE) {
401 t->uport.icount.frame++;
402 dev_err(t->uport.dev, "Got frame errors\n");
403 } else if (lsr & UART_LSR_BI) {
404 dev_err(t->uport.dev, "Got Break\n");
405 t->uport.icount.brk++;
406 /* If FIFO read error without any data, reset Rx FIFO */
407 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
408 tegra_fifo_reset(t, UART_FCR_CLEAR_RCVR);
414 static void do_handle_rx_pio(struct tegra_uart_port *t)
418 char flag = TTY_NORMAL;
419 unsigned char lsr = 0;
423 lsr = uart_readb(t, UART_LSR);
424 if (!(lsr & UART_LSR_DR))
427 flag = do_decode_rx_error(t, lsr);
428 ch = uart_readb(t, UART_RX);
429 t->uport.icount.rx++;
432 if (!uart_handle_sysrq_char(&t->uport, c))
433 uart_insert_char(&t->uport, lsr, UART_LSR_OE, ch, flag);
436 dev_dbg(t->uport.dev, "PIO received %d bytes\n", count);
441 static void do_handle_modem_signal(struct uart_port *u)
444 struct tegra_uart_port *t;
446 t = container_of(u, struct tegra_uart_port, uport);
447 msr = uart_readb(t, UART_MSR);
448 if (msr & UART_MSR_CTS)
449 dev_dbg(u->dev, "CTS triggered\n");
450 if (msr & UART_MSR_DSR)
451 dev_dbg(u->dev, "DSR enabled\n");
452 if (msr & UART_MSR_DCD)
453 dev_dbg(u->dev, "CD enabled\n");
454 if (msr & UART_MSR_RI)
455 dev_dbg(u->dev, "RI enabled\n");
459 static void do_handle_tx_pio(struct tegra_uart_port *t)
461 struct circ_buf *xmit = &t->uport.state->xmit;
463 fill_tx_fifo(t, t->tx_bytes);
465 t->tx_in_progress = 0;
467 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
468 uart_write_wakeup(&t->uport);
470 tegra_start_next_tx(t);
474 static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req)
476 struct tegra_uart_port *t = req->dev;
477 struct circ_buf *xmit = &t->uport.state->xmit;
478 int count = req->bytes_transferred;
481 dev_vdbg(t->uport.dev, "%s: %d\n", __func__, count);
483 spin_lock_irqsave(&t->uport.lock, flags);
484 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
485 t->tx_in_progress = 0;
487 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
488 uart_write_wakeup(&t->uport);
490 if (req->status != -TEGRA_DMA_REQ_ERROR_ABORTED)
491 tegra_start_next_tx(t);
493 spin_unlock_irqrestore(&t->uport.lock, flags);
496 static irqreturn_t tegra_uart_isr(int irq, void *data)
498 struct tegra_uart_port *t = data;
499 struct uart_port *u = &t->uport;
502 bool is_rx_int = false;
505 spin_lock_irqsave(&u->lock, flags);
506 t = container_of(u, struct tegra_uart_port, uport);
508 iir = uart_readb(t, UART_IIR);
509 if (iir & UART_IIR_NO_INT) {
510 if (likely(t->use_rx_dma) && is_rx_int) {
513 if (t->rx_in_progress) {
515 ier |= (UART_IER_RLSI | UART_IER_RTOIE | UART_IER_EORD);
517 uart_writeb(t, ier, UART_IER);
520 spin_unlock_irqrestore(&u->lock, flags);
524 dev_dbg(u->dev, "tegra_uart_isr iir = 0x%x (%d)\n", iir,
526 switch ((iir >> 1) & 0x7) {
527 case 0: /* Modem signal change interrupt */
528 do_handle_modem_signal(u);
530 case 1: /* Transmit interrupt only triggered when using PIO */
531 t->ier_shadow &= ~UART_IER_THRI;
532 uart_writeb(t, t->ier_shadow, UART_IER);
535 case 4: /* End of data */
536 case 6: /* Rx timeout */
537 case 2: /* Receive */
538 if (likely(t->use_rx_dma)) {
541 /* Disable interrups */
544 uart_writeb(t, ier, UART_IER);
545 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | UART_IER_EORD);
547 uart_writeb(t, ier, UART_IER);
552 spin_unlock_irqrestore(&u->lock, flags);
553 tty_flip_buffer_push(u->state->port.tty);
554 spin_lock_irqsave(&u->lock, flags);
557 case 3: /* Receive error */
558 /* FIXME how to handle this? Why do we get here */
559 do_decode_rx_error(t, uart_readb(t, UART_LSR));
561 case 5: /* break nothing to handle */
562 case 7: /* break nothing to handle */
568 static void tegra_stop_rx(struct uart_port *u)
570 struct tegra_uart_port *t;
573 t = container_of(u, struct tegra_uart_port, uport);
578 if (t->rx_in_progress) {
579 wait_sym_time(t, 1); /* wait a character interval */
582 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE | UART_IER_EORD);
584 uart_writeb(t, ier, UART_IER);
585 t->rx_in_progress = 0;
587 if (t->use_rx_dma && t->rx_dma)
588 tegra_dma_dequeue(t->rx_dma);
592 tty_flip_buffer_push(u->state->port.tty);
598 static void tegra_uart_hw_deinit(struct tegra_uart_port *t)
602 /* Disable interrupts */
603 uart_writeb(t, 0, UART_IER);
605 while ((uart_readb(t, UART_LSR) & UART_LSR_TEMT) != UART_LSR_TEMT);
608 spin_lock_irqsave(&t->uport.lock, flags);
610 /* Reset the Rx and Tx FIFOs */
611 tegra_fifo_reset(t, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
615 t->uart_state = TEGRA_UART_CLOSED;
617 spin_unlock_irqrestore(&t->uport.lock, flags);
620 static void tegra_uart_free_rx_dma(struct tegra_uart_port *t)
625 tegra_dma_free_channel(t->rx_dma);
628 if (likely(t->rx_dma_req.dest_addr))
629 dma_free_coherent(t->uport.dev, t->rx_dma_req.size,
630 t->rx_dma_req.virt_addr, t->rx_dma_req.dest_addr);
631 t->rx_dma_req.dest_addr = 0;
632 t->rx_dma_req.virt_addr = NULL;
634 t->use_rx_dma = false;
637 static int tegra_uart_hw_init(struct tegra_uart_port *t)
641 dev_vdbg(t->uport.dev, "+tegra_uart_hw_init\n");
651 /* Reset the UART controller to clear all previous status.*/
652 tegra_periph_reset_assert(t->clk);
654 tegra_periph_reset_deassert(t->clk);
657 t->rx_in_progress = 0;
659 /* Set the trigger level
663 * For receive, this will interrupt the CPU after that many number of
664 * bytes are received, for the remaining bytes the receive timeout
665 * interrupt is received.
667 * Rx high watermark is set to 4.
669 * For transmit, if the trasnmit interrupt is enabled, this will
670 * interrupt the CPU when the number of entries in the FIFO reaches the
673 * Tx low watermark is set to 8.
677 * Set the Tx trigger to 4. This should match the DMA burst size that
678 * programmed in the DMA registers.
680 t->fcr_shadow = UART_FCR_ENABLE_FIFO;
681 t->fcr_shadow |= UART_FCR_R_TRIG_01;
682 t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
683 uart_writeb(t, t->fcr_shadow, UART_FCR);
686 /* initialize the UART for a simple default configuration
687 * so that the receive DMA buffer may be enqueued */
688 t->lcr_shadow = 3; /* no parity, stop, 8 data bits */
689 tegra_set_baudrate(t, 115200);
690 t->fcr_shadow |= UART_FCR_DMA_SELECT;
691 uart_writeb(t, t->fcr_shadow, UART_FCR);
692 if (tegra_start_dma_rx(t)) {
693 dev_err(t->uport.dev, "Rx DMA enqueue failed\n");
694 tegra_uart_free_rx_dma(t);
695 t->fcr_shadow &= ~UART_FCR_DMA_SELECT;
696 uart_writeb(t, t->fcr_shadow, UART_FCR);
700 uart_writeb(t, t->fcr_shadow, UART_FCR);
702 t->rx_in_progress = 1;
705 * Enable IE_RXS for the receive status interrupts like line errros.
706 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
708 * If using DMA mode, enable EORD instead of receive interrupt which
709 * will interrupt after the UART is done with the receive instead of
710 * the interrupt when the FIFO "threshold" is reached.
712 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
713 * the DATA is sitting in the FIFO and couldn't be transferred to the
714 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
715 * triggered when there is a pause of the incomming data stream for 4
718 * For pauses in the data which is not aligned to 4 bytes, we get
719 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
722 * Don't get confused, believe in the magic of nvidia hw...:-)
725 ier |= UART_IER_RLSI | UART_IER_RTOIE;
727 ier |= UART_IER_EORD;
731 uart_writeb(t, ier, UART_IER);
733 t->uart_state = TEGRA_UART_OPENED;
734 dev_vdbg(t->uport.dev, "-tegra_uart_hw_init\n");
738 static int tegra_uart_init_rx_dma(struct tegra_uart_port *t)
740 dma_addr_t rx_dma_phys;
743 t->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_CONTINUOUS,
744 "uart_rx_%d", t->uport.line);
746 dev_err(t->uport.dev, "%s: failed to allocate RX DMA.\n", __func__);
750 t->rx_dma_req.size = UART_RX_DMA_BUFFER_SIZE;
751 rx_dma_virt = dma_alloc_coherent(t->uport.dev,
752 t->rx_dma_req.size, &rx_dma_phys, GFP_KERNEL);
754 dev_err(t->uport.dev, "DMA buffers allocate failed\n");
757 t->rx_dma_req.dest_addr = rx_dma_phys;
758 t->rx_dma_req.virt_addr = rx_dma_virt;
760 t->rx_dma_req.source_addr = (unsigned long)t->uport.mapbase;
761 t->rx_dma_req.source_wrap = 4;
762 t->rx_dma_req.dest_wrap = 0;
763 t->rx_dma_req.to_memory = 1;
764 t->rx_dma_req.source_bus_width = 8;
765 t->rx_dma_req.dest_bus_width = 32;
766 t->rx_dma_req.req_sel = dma_req_sel[t->uport.line];
767 t->rx_dma_req.complete = tegra_rx_dma_complete_callback;
768 t->rx_dma_req.threshold = tegra_rx_dma_threshold_callback;
769 t->rx_dma_req.dev = t;
773 tegra_uart_free_rx_dma(t);
777 static int tegra_startup(struct uart_port *u)
779 struct tegra_uart_port *t = container_of(u,
780 struct tegra_uart_port, uport);
783 t = container_of(u, struct tegra_uart_port, uport);
784 sprintf(t->port_name, "tegra_uart_%d", u->line);
786 t->use_tx_dma = false;
788 t->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT,
789 "uart_tx_%d", u->line);
791 t->use_tx_dma = true;
793 pr_err("%s: failed to allocate TX DMA.\n", __func__);
796 t->tx_dma_req.instance = u->line;
797 t->tx_dma_req.complete = tegra_tx_dma_complete_callback;
798 t->tx_dma_req.to_memory = 0;
800 t->tx_dma_req.dest_addr = (unsigned long)t->uport.mapbase;
801 t->tx_dma_req.dest_wrap = 4;
802 t->tx_dma_req.source_wrap = 0;
803 t->tx_dma_req.source_bus_width = 32;
804 t->tx_dma_req.dest_bus_width = 8;
805 t->tx_dma_req.req_sel = dma_req_sel[t->uport.line];
806 t->tx_dma_req.dev = t;
807 t->tx_dma_req.size = 0;
808 t->xmit_dma_addr = dma_map_single(t->uport.dev,
809 t->uport.state->xmit.buf, UART_XMIT_SIZE,
812 t->tx_in_progress = 0;
814 t->use_rx_dma = false;
816 if (!tegra_uart_init_rx_dma(t))
817 t->use_rx_dma = true;
820 ret = tegra_uart_hw_init(t);
824 dev_dbg(u->dev, "Requesting IRQ %d\n", u->irq);
827 ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED,
830 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
833 dev_dbg(u->dev,"Started UART port %d\n", u->line);
837 dev_err(u->dev, "Tegra UART startup failed\n");
841 static void tegra_shutdown(struct uart_port *u)
843 struct tegra_uart_port *t;
845 t = container_of(u, struct tegra_uart_port, uport);
846 dev_vdbg(u->dev, "+tegra_shutdown\n");
848 tegra_uart_hw_deinit(t);
850 t->rx_in_progress = 0;
851 t->tx_in_progress = 0;
853 tegra_uart_free_rx_dma(t);
855 tegra_dma_free_channel(t->tx_dma);
857 t->use_tx_dma = false;
858 dma_unmap_single(t->uport.dev, t->xmit_dma_addr, UART_XMIT_SIZE,
860 t->xmit_dma_addr = 0;
864 dev_vdbg(u->dev, "-tegra_shutdown\n");
867 static unsigned int tegra_get_mctrl(struct uart_port *u)
869 /* RI - Ring detector is active
870 * CD/DCD/CAR - Carrier detect is always active. For some reason
871 * linux has different names for carrier detect.
872 * DSR - Data Set ready is active as the hardware doesn't support it.
873 * Don't know if the linux support this yet?
874 * CTS - Clear to send. Always set to active, as the hardware handles
877 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
880 static void set_rts(struct tegra_uart_port *t, bool active)
885 mcr |= UART_MCR_RTS_EN;
887 mcr &= ~UART_MCR_RTS_EN;
888 if (mcr != t->mcr_shadow) {
889 uart_writeb(t, mcr, UART_MCR);
895 static void set_dtr(struct tegra_uart_port *t, bool active)
902 mcr &= ~UART_MCR_DTR;
903 if (mcr != t->mcr_shadow) {
904 uart_writeb(t, mcr, UART_MCR);
910 static void tegra_set_mctrl(struct uart_port *u, unsigned int mctrl)
913 struct tegra_uart_port *t;
915 dev_dbg(u->dev, "tegra_set_mctrl called with %d\n", mctrl);
916 t = container_of(u, struct tegra_uart_port, uport);
919 if (mctrl & TIOCM_RTS) {
920 t->rts_active = true;
923 t->rts_active = false;
927 if (mctrl & TIOCM_DTR)
934 static void tegra_break_ctl(struct uart_port *u, int break_ctl)
936 struct tegra_uart_port *t;
939 t = container_of(u, struct tegra_uart_port, uport);
944 lcr &= ~UART_LCR_SBC;
945 uart_writeb(t, lcr, UART_LCR);
949 static int tegra_request_port(struct uart_port *u)
954 static void tegra_release_port(struct uart_port *u)
959 static unsigned int tegra_tx_empty(struct uart_port *u)
961 struct tegra_uart_port *t;
962 unsigned int ret = 0;
966 t = container_of(u, struct tegra_uart_port, uport);
967 dev_vdbg(u->dev, "+tegra_tx_empty\n");
969 spin_lock_irqsave(&u->lock, flags);
970 if (!t->tx_in_progress) {
971 lsr = uart_readb(t, UART_LSR);
972 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
975 spin_unlock_irqrestore(&u->lock, flags);
977 dev_vdbg(u->dev, "-tegra_tx_empty\n");
981 static void tegra_stop_tx(struct uart_port *u)
983 struct tegra_uart_port *t;
985 t = container_of(u, struct tegra_uart_port, uport);
988 tegra_dma_dequeue_req(t->tx_dma, &t->tx_dma_req);
993 static void tegra_enable_ms(struct uart_port *u)
997 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
998 static int clk_div71_get_divider(unsigned long parent_rate,
1001 s64 divider_u71 = parent_rate;
1006 divider_u71 += rate - 1;
1007 do_div(divider_u71, rate);
1009 if ((divider_u71 - 2) < 0)
1012 if ((divider_u71 - 2) > 255)
1015 return divider_u71 - 2;
1019 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
1023 divider_u16 = parent_rate;
1026 divider_u16 += rate - 1;
1027 do_div(divider_u16, rate);
1029 if (divider_u16 > 0xFFFF)
1035 static unsigned long find_best_clock_source(struct tegra_uart_port *t,
1038 struct uart_port *u = &t->uport;
1039 struct tegra_uart_platform_data *pdata;
1042 unsigned long parent_rate;
1043 unsigned long new_rate;
1044 unsigned long err_rate;
1045 unsigned int fin_err = rate;
1046 unsigned long fin_rate = rate;
1047 int final_index = -1;
1050 pdata = u->dev->platform_data;
1051 if (!pdata || !pdata->parent_clk_count)
1054 for (count = 0; count < pdata->parent_clk_count; ++count) {
1055 parent_rate = pdata->parent_clk_list[count].fixed_clk_rate;
1057 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
1058 divider = clk_div71_get_divider(parent_rate, rate);
1060 /* Get the best divider around calculated value */
1062 for (i = divider - 2; i < (divider + 2); ++i) {
1063 new_rate = ((parent_rate << 1) + i + 1) /
1065 err_rate = abs(new_rate - rate);
1066 if (err_rate < fin_err) {
1067 final_index = count;
1069 fin_rate = new_rate;
1074 /* Get the divisor by uart controller dll/dlm */
1075 divider = clk_div16_get_divider(parent_rate, rate);
1077 /* Get the best divider around calculated value */
1079 for (i = divider - 2; i < (divider + 2); ++i) {
1080 new_rate = parent_rate/i;
1081 err_rate = abs(new_rate - rate);
1082 if (err_rate < fin_err) {
1083 final_index = count;
1085 fin_rate = parent_rate;
1091 if (final_index >= 0) {
1092 dev_info(t->uport.dev, "Setting clk_src %s\n",
1093 pdata->parent_clk_list[final_index].name);
1094 clk_set_parent(t->clk,
1095 pdata->parent_clk_list[final_index].parent_clk);
1100 #define UART_CLOCK_ACCURACY 5
1101 static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud)
1104 unsigned int divisor;
1106 unsigned int baud_actual;
1107 unsigned int baud_delta;
1108 unsigned long best_rate;
1110 if (t->baud == baud)
1114 best_rate = find_best_clock_source(t, rate);
1115 clk_set_rate(t->clk, best_rate);
1117 rate = clk_get_rate(t->clk);
1120 do_div(divisor, 16);
1122 do_div(divisor, baud);
1124 /* The allowable baudrate error from desired baudrate is 5% */
1125 baud_actual = divisor ? rate / (16 * divisor) : 0;
1126 baud_delta = abs(baud_actual - baud);
1127 if (WARN_ON(baud_delta * 20 > baud)) {
1128 dev_err(t->uport.dev, "requested baud %u, actual %u\n",
1132 lcr = t->lcr_shadow;
1133 lcr |= UART_LCR_DLAB;
1134 uart_writeb(t, lcr, UART_LCR);
1136 uart_writel(t, divisor & 0xFF, UART_TX);
1137 uart_writel(t, ((divisor >> 8) & 0xFF), UART_IER);
1139 lcr &= ~UART_LCR_DLAB;
1140 uart_writeb(t, lcr, UART_LCR);
1141 uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */
1144 wait_sym_time(t, 2); /* wait two character intervals at new rate */
1145 dev_dbg(t->uport.dev, "Baud %u clock freq %lu and divisor of %u\n",
1146 baud, rate, divisor);
1149 static void tegra_set_termios(struct uart_port *u, struct ktermios *termios,
1150 struct ktermios *oldtermios)
1152 struct tegra_uart_port *t;
1154 unsigned long flags;
1156 unsigned int c_cflag = termios->c_cflag;
1159 t = container_of(u, struct tegra_uart_port, uport);
1160 dev_vdbg(t->uport.dev, "+tegra_set_termios\n");
1162 spin_lock_irqsave(&u->lock, flags);
1164 /* Changing configuration, it is safe to stop any rx now */
1169 lcr = t->lcr_shadow;
1170 lcr &= ~UART_LCR_PARITY;
1171 if (PARENB == (c_cflag & PARENB)) {
1172 if (CMSPAR == (c_cflag & CMSPAR)) {
1173 /* FIXME What is space parity? */
1174 /* data |= SPACE_PARITY; */
1175 } else if (c_cflag & PARODD) {
1176 lcr |= UART_LCR_PARITY;
1177 lcr &= ~UART_LCR_EPAR;
1178 lcr &= ~UART_LCR_SPAR;
1180 lcr |= UART_LCR_PARITY;
1181 lcr |= UART_LCR_EPAR;
1182 lcr &= ~UART_LCR_SPAR;
1186 lcr &= ~UART_LCR_WLEN8;
1187 switch (c_cflag & CSIZE) {
1189 lcr |= UART_LCR_WLEN5;
1192 lcr |= UART_LCR_WLEN6;
1195 lcr |= UART_LCR_WLEN7;
1198 lcr |= UART_LCR_WLEN8;
1203 if (termios->c_cflag & CSTOPB)
1204 lcr |= UART_LCR_STOP;
1206 lcr &= ~UART_LCR_STOP;
1208 uart_writeb(t, lcr, UART_LCR);
1209 t->lcr_shadow = lcr;
1212 baud = uart_get_baud_rate(u, termios, oldtermios, 200, 4000000);
1213 tegra_set_baudrate(t, baud);
1216 if (termios->c_cflag & CRTSCTS) {
1217 mcr = t->mcr_shadow;
1218 mcr |= UART_MCR_CTS_EN;
1219 mcr &= ~UART_MCR_RTS_EN;
1220 t->mcr_shadow = mcr;
1221 uart_writeb(t, mcr, UART_MCR);
1222 t->use_cts_control = true;
1223 /* if top layer has asked to set rts active then do so here */
1227 mcr = t->mcr_shadow;
1228 mcr &= ~UART_MCR_CTS_EN;
1229 mcr &= ~UART_MCR_RTS_EN;
1230 t->mcr_shadow = mcr;
1231 uart_writeb(t, mcr, UART_MCR);
1232 t->use_cts_control = false;
1235 /* update the port timeout based on new settings */
1236 uart_update_timeout(u, termios->c_cflag, baud);
1238 spin_unlock_irqrestore(&u->lock, flags);
1239 dev_vdbg(t->uport.dev, "-tegra_set_termios\n");
1244 * Flush any TX data submitted for DMA and PIO. Called when the
1245 * TX circular buffer is reset.
1247 static void tegra_flush_buffer(struct uart_port *u)
1249 struct tegra_uart_port *t;
1251 dev_vdbg(u->dev, "%s called", __func__);
1253 t = container_of(u, struct tegra_uart_port, uport);
1257 if (t->use_tx_dma) {
1258 tegra_dma_dequeue_req(t->tx_dma, &t->tx_dma_req);
1259 t->tx_dma_req.size = 0;
1265 static void tegra_pm(struct uart_port *u, unsigned int state,
1266 unsigned int oldstate)
1271 static const char *tegra_type(struct uart_port *u)
1276 static struct uart_ops tegra_uart_ops = {
1277 .tx_empty = tegra_tx_empty,
1278 .set_mctrl = tegra_set_mctrl,
1279 .get_mctrl = tegra_get_mctrl,
1280 .stop_tx = tegra_stop_tx,
1281 .start_tx = tegra_start_tx,
1282 .stop_rx = tegra_stop_rx,
1283 .flush_buffer = tegra_flush_buffer,
1284 .enable_ms = tegra_enable_ms,
1285 .break_ctl = tegra_break_ctl,
1286 .startup = tegra_startup,
1287 .shutdown = tegra_shutdown,
1288 .set_termios = tegra_set_termios,
1291 .request_port = tegra_request_port,
1292 .release_port = tegra_release_port,
1295 static int tegra_uart_probe(struct platform_device *pdev);
1296 static int __devexit tegra_uart_remove(struct platform_device *pdev);
1297 static int tegra_uart_suspend(struct platform_device *pdev, pm_message_t state);
1298 static int tegra_uart_resume(struct platform_device *pdev);
1300 static struct platform_driver tegra_uart_platform_driver = {
1301 .remove = tegra_uart_remove,
1302 .probe = tegra_uart_probe,
1303 .suspend = tegra_uart_suspend,
1304 .resume = tegra_uart_resume,
1306 .name = "tegra_uart"
1310 static struct uart_driver tegra_uart_driver =
1312 .owner = THIS_MODULE,
1313 .driver_name = "tegra_uart",
1314 .dev_name = "ttyHS",
1319 static int tegra_uart_suspend(struct platform_device *pdev, pm_message_t state)
1321 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1322 struct uart_port *u;
1324 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1325 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1328 dev_dbg(t->uport.dev, "tegra_uart_suspend called\n");
1330 /* enable clock before calling suspend so that controller
1331 register can be accessible */
1332 if (t->uart_state == TEGRA_UART_CLOCK_OFF) {
1334 t->uart_state = TEGRA_UART_OPENED;
1337 uart_suspend_port(&tegra_uart_driver, u);
1338 t->uart_state = TEGRA_UART_SUSPEND;
1343 static int tegra_uart_resume(struct platform_device *pdev)
1345 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1346 struct uart_port *u;
1348 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1349 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1352 dev_dbg(t->uport.dev, "tegra_uart_resume called\n");
1354 if (t->uart_state == TEGRA_UART_SUSPEND) {
1355 uart_resume_port(&tegra_uart_driver, u);
1362 static int __devexit tegra_uart_remove(struct platform_device *pdev)
1364 struct tegra_uart_port *t = platform_get_drvdata(pdev);
1365 struct uart_port *u;
1367 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
1368 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1371 uart_remove_one_port(&tegra_uart_driver, u);
1373 platform_set_drvdata(pdev, NULL);
1375 pr_info("Unregistered UART port %s%d\n",
1376 tegra_uart_driver.dev_name, u->line);
1381 static int tegra_uart_probe(struct platform_device *pdev)
1383 struct tegra_uart_port *t;
1384 struct uart_port *u;
1385 struct resource *resource;
1388 if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr) {
1389 pr_err("Invalid Uart instance (%d)\n", pdev->id);
1393 t = kzalloc(sizeof(struct tegra_uart_port), GFP_KERNEL);
1395 pr_err("%s: Failed to allocate memory\n", __func__);
1399 u->dev = &pdev->dev;
1400 platform_set_drvdata(pdev, u);
1402 u->ops = &tegra_uart_ops;
1403 u->type = ~PORT_UNKNOWN;
1406 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1407 if (unlikely(!resource))
1410 u->mapbase = resource->start;
1411 u->membase = IO_ADDRESS(u->mapbase);
1412 if (unlikely(!u->membase))
1415 u->irq = platform_get_irq(pdev, 0);
1416 if (unlikely(u->irq < 0))
1421 t->clk = clk_get(&pdev->dev, NULL);
1422 if (IS_ERR_OR_NULL(t->clk)) {
1423 dev_err(&pdev->dev, "Couldn't get the clock\n");
1427 ret = uart_add_one_port(&tegra_uart_driver, u);
1429 pr_err("%s: Failed(%d) to add uart port %s%d\n",
1430 __func__, ret, tegra_uart_driver.dev_name, u->line);
1432 platform_set_drvdata(pdev, NULL);
1436 snprintf(name, sizeof(name), "tegra_hsuart_%d", u->line);
1437 pr_info("Registered UART port %s%d\n",
1438 tegra_uart_driver.dev_name, u->line);
1439 t->uart_state = TEGRA_UART_CLOSED;
1446 /* Switch off the clock of the uart controller. */
1447 void tegra_uart_request_clock_off(struct uart_port *uport)
1449 unsigned long flags;
1450 struct tegra_uart_port *t;
1452 if (IS_ERR_OR_NULL(uport))
1455 dev_vdbg(uport->dev, "tegra_uart_request_clock_off");
1457 t = container_of(uport, struct tegra_uart_port, uport);
1458 spin_lock_irqsave(&uport->lock, flags);
1459 if (t->uart_state == TEGRA_UART_OPENED) {
1460 clk_disable(t->clk);
1461 t->uart_state = TEGRA_UART_CLOCK_OFF;
1463 spin_unlock_irqrestore(&uport->lock, flags);
1467 /* Switch on the clock of the uart controller */
1468 void tegra_uart_request_clock_on(struct uart_port *uport)
1470 unsigned long flags;
1471 struct tegra_uart_port *t;
1473 if (IS_ERR_OR_NULL(uport))
1476 t = container_of(uport, struct tegra_uart_port, uport);
1477 spin_lock_irqsave(&uport->lock, flags);
1478 if (t->uart_state == TEGRA_UART_CLOCK_OFF) {
1480 t->uart_state = TEGRA_UART_OPENED;
1482 spin_unlock_irqrestore(&uport->lock, flags);
1486 /* Set the modem control signals state of uart controller. */
1487 void tegra_uart_set_mctrl(struct uart_port *uport, unsigned int mctrl)
1489 unsigned long flags;
1490 struct tegra_uart_port *t;
1492 t = container_of(uport, struct tegra_uart_port, uport);
1493 spin_lock_irqsave(&uport->lock, flags);
1494 if (mctrl & TIOCM_RTS) {
1495 t->rts_active = true;
1498 t->rts_active = false;
1502 if (mctrl & TIOCM_DTR)
1506 spin_unlock_irqrestore(&uport->lock, flags);
1510 /* Return the status of the transmit fifo whether empty or not.
1511 * Return 0 if tx fifo is not empty.
1512 * Return TIOCSER_TEMT if tx fifo is empty.
1514 int tegra_uart_is_tx_empty(struct uart_port *uport)
1516 return tegra_tx_empty(uport);
1519 static int __init tegra_uart_init(void)
1523 ret = uart_register_driver(&tegra_uart_driver);
1524 if (unlikely(ret)) {
1525 pr_err("Could not register %s driver\n",
1526 tegra_uart_driver.driver_name);
1530 ret = platform_driver_register(&tegra_uart_platform_driver);
1531 if (unlikely(ret)) {
1532 pr_err("Could not register the UART platfrom "
1534 uart_unregister_driver(&tegra_uart_driver);
1538 pr_info("Initialized tegra uart driver\n");
1542 static void __exit tegra_uart_exit(void)
1544 pr_info("Unloading tegra uart driver\n");
1545 platform_driver_unregister(&tegra_uart_platform_driver);
1546 uart_unregister_driver(&tegra_uart_driver);
1549 module_init(tegra_uart_init);
1550 module_exit(tegra_uart_exit);
1551 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");