pcmcia: do not use io_req_t after call to pcmcia_request_io()
[linux-2.6.git] / drivers / staging / rtl8192su / r8192S_phy.h
1 /*****************************************************************************
2  *      Copyright(c) 2008,  RealTEK Technology Inc. All Right Reserved.
3  *
4  * Module:      __INC_HAL8192SPHYCFG_H
5  *
6  *
7  * Note:
8  *
9  *
10  * Export:      Constants, macro, functions(API), global variables(None).
11  *
12  * Abbrev:
13  *
14  * History:
15  *              Data            Who             Remark
16  *      08/07/2007  MHC         1. Porting from 9x series PHYCFG.h.
17  *                                                      2. Reorganize code architecture.
18  *
19  *****************************************************************************/
20  /* Check to see if the file has been included already.  */
21 #ifndef _R8192S_PHY_H
22 #define _R8192S_PHY_H
23
24
25 /*--------------------------Define Parameters-------------------------------*/
26 #define LOOP_LIMIT                              5
27 #define MAX_STALL_TIME                  50              //us
28 #define AntennaDiversityValue           0x80    //(dev->bSoftwareAntennaDiversity ? 0x00:0x80)
29 #define MAX_TXPWR_IDX_NMODE_92S 63
30
31 //#define delay_ms(_t)                  PlatformStallExecution(1000*(_t))
32 //#define delay_us(_t)                  PlatformStallExecution(_t)
33
34 /* Channel switch:The size of command tables for switch channel*/
35 #define MAX_PRECMD_CNT                  16
36 #define MAX_RFDEPENDCMD_CNT     16
37 #define MAX_POSTCMD_CNT                 16
38
39
40 /*------------------------------Define structure----------------------------*/
41 typedef enum _SwChnlCmdID{
42         CmdID_End,
43         CmdID_SetTxPowerLevel,
44         CmdID_BBRegWrite10,
45         CmdID_WritePortUlong,
46         CmdID_WritePortUshort,
47         CmdID_WritePortUchar,
48         CmdID_RF_WriteReg,
49 }SwChnlCmdID;
50
51
52 /* 1. Switch channel related */
53 typedef struct _SwChnlCmd{
54         SwChnlCmdID     CmdID;
55         u32                     Para1;
56         u32                     Para2;
57         u32                     msDelay;
58 }__attribute__ ((packed)) SwChnlCmd;
59
60 extern u32 rtl819XMACPHY_Array_PG[];
61 extern u32 rtl819XPHY_REG_1T2RArray[];
62 extern u32 rtl819XAGCTAB_Array[];
63 extern u32 rtl819XRadioA_Array[];
64 extern u32 rtl819XRadioB_Array[];
65 extern u32 rtl819XRadioC_Array[];
66 extern u32 rtl819XRadioD_Array[];
67
68 typedef enum _HW90_BLOCK{
69         HW90_BLOCK_MAC = 0,
70         HW90_BLOCK_PHY0 = 1,
71         HW90_BLOCK_PHY1 = 2,
72         HW90_BLOCK_RF = 3,
73         HW90_BLOCK_MAXIMUM = 4, // Never use this
74 }HW90_BLOCK_E, *PHW90_BLOCK_E;
75
76 typedef enum _RF90_RADIO_PATH{
77         RF90_PATH_A = 0,                        //Radio Path A
78         RF90_PATH_B = 1,                        //Radio Path B
79         RF90_PATH_C = 2,                        //Radio Path C
80         RF90_PATH_D = 3,                        //Radio Path D
81         RF90_PATH_MAX   = 4,                    //Max RF number 90 support
82 }RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
83
84 #define bMaskByte0                0xff
85 #define bMaskByte1                0xff00
86 #define bMaskByte2                0xff0000
87 #define bMaskByte3                0xff000000
88 #define bMaskHWord                0xffff0000
89 #define bMaskLWord                0x0000ffff
90 #define bMaskDWord                0xffffffff
91
92 typedef enum _VERSION_8190{
93         // RTL8190
94         VERSION_8190_BD=0x3,
95         VERSION_8190_BE
96 }VERSION_8190,*PVERSION_8190;
97
98 //
99 // BB and RF register read/write
100 //
101
102 extern  u32     rtl8192_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask);
103 extern  void    rtl8192_setBBreg(struct net_device* dev,u32 RegAddr, u32 BitMask,u32 Data);
104 extern  u32     rtl8192_phy_QueryRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
105 extern  void    rtl8192_phy_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr,u32 BitMask,u32 Data);
106
107 bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
108
109
110 /* MAC/BB/RF HAL config */
111 extern  bool    PHY_MACConfig8192S(struct net_device* dev);
112 extern  bool    PHY_BBConfig8192S(struct net_device* dev);
113 extern  bool    PHY_RFConfig8192S(struct net_device* dev);
114
115 extern  u8      rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath);
116 extern  void    rtl8192_SetBWMode(struct net_device* dev,HT_CHANNEL_WIDTH ChnlWidth,HT_EXTCHNL_OFFSET Offset    );
117 extern  u8      rtl8192_phy_SwChnl(struct net_device* dev,u8 channel);
118 extern  u8      rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev,u32 eRFPath       );
119 extern  void    rtl8192_BBConfig(struct net_device* dev);
120 extern  void    PHY_IQCalibrateBcut(struct net_device* dev);
121 extern  void    PHY_IQCalibrate(struct net_device* dev);
122 extern  void    PHY_GetHWRegOriginalValue(struct net_device* dev);
123
124 extern void     InitialGainOperateWorkItemCallBack(struct work_struct *work);
125
126 void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8  channel);
127 void PHY_InitialGain8192S(struct net_device* dev,u8 Operation   );
128
129 /*--------------------------Exported Function prototype---------------------*/
130 bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE                FwCmdIO);
131 extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval);
132 void ChkFwCmdIoDone(struct net_device* dev);
133
134 #endif  // __INC_HAL8192SPHYCFG_H
135