staging: Move media drivers to staging/media
[linux-2.6.git] / drivers / staging / media / dt3155v4l / dt3155v4l.c
1 /***************************************************************************
2  *   Copyright (C) 2006-2010 by Marin Mitov                                *
3  *   mitov@issp.bas.bg                                                     *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20
21 #include <linux/module.h>
22 #include <linux/version.h>
23 #include <linux/stringify.h>
24 #include <linux/delay.h>
25 #include <linux/kthread.h>
26 #include <linux/slab.h>
27 #include <media/v4l2-dev.h>
28 #include <media/v4l2-ioctl.h>
29 #include <media/videobuf2-dma-contig.h>
30
31 #include "dt3155v4l.h"
32
33 #define DT3155_VENDOR_ID 0x8086
34 #define DT3155_DEVICE_ID 0x1223
35
36 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
37 #define DT3155_CHUNK_SIZE (1U << 22)
38
39 #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
40
41 #define DT3155_BUF_SIZE (768 * 576)
42
43 #ifdef CONFIG_DT3155_STREAMING
44 #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
45 #else
46 #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
47 #endif
48
49 /*  global initializers (for all boards)  */
50 #ifdef CONFIG_DT3155_CCIR
51 static const u8 csr2_init = VT_50HZ;
52 #define DT3155_CURRENT_NORM V4L2_STD_625_50
53 static const unsigned int img_width = 768;
54 static const unsigned int img_height = 576;
55 static const unsigned int frames_per_sec = 25;
56 static const struct v4l2_fmtdesc frame_std[] = {
57         {
58         .index = 0,
59         .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
60         .flags = 0,
61         .description = "CCIR/50Hz 8 bits gray",
62         .pixelformat = V4L2_PIX_FMT_GREY,
63         },
64 };
65 #else
66 static const u8 csr2_init = VT_60HZ;
67 #define DT3155_CURRENT_NORM V4L2_STD_525_60
68 static const unsigned int img_width = 640;
69 static const unsigned int img_height = 480;
70 static const unsigned int frames_per_sec = 30;
71 static const struct v4l2_fmtdesc frame_std[] = {
72         {
73         .index = 0,
74         .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
75         .flags = 0,
76         .description = "RS-170/60Hz 8 bits gray",
77         .pixelformat = V4L2_PIX_FMT_GREY,
78         },
79 };
80 #endif
81
82 #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
83
84 static u8 config_init = ACQ_MODE_EVEN;
85
86 /**
87  * read_i2c_reg - reads an internal i2c register
88  *
89  * @addr:       dt3155 mmio base address
90  * @index:      index (internal address) of register to read
91  * @data:       pointer to byte the read data will be placed in
92  *
93  * returns:     zero on success or error code
94  *
95  * This function starts reading the specified (by index) register
96  * and busy waits for the process to finish. The result is placed
97  * in a byte pointed by data.
98  */
99 static int
100 read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
101 {
102         u32 tmp = index;
103
104         iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
105         mmiowb();
106         udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
107         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
108                 return -EIO; /* error: NEW_CYCLE not cleared */
109         tmp = ioread32(addr + IIC_CSR1);
110         if (tmp & DIRECT_ABORT) {
111                 /* reset DIRECT_ABORT bit */
112                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
113                 return -EIO; /* error: DIRECT_ABORT set */
114         }
115         *data = tmp>>24;
116         return 0;
117 }
118
119 /**
120  * write_i2c_reg - writes to an internal i2c register
121  *
122  * @addr:       dt3155 mmio base address
123  * @index:      index (internal address) of register to read
124  * @data:       data to be written
125  *
126  * returns:     zero on success or error code
127  *
128  * This function starts writting the specified (by index) register
129  * and busy waits for the process to finish.
130  */
131 static int
132 write_i2c_reg(void __iomem *addr, u8 index, u8 data)
133 {
134         u32 tmp = index;
135
136         iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
137         mmiowb();
138         udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
139         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
140                 return -EIO; /* error: NEW_CYCLE not cleared */
141         if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
142                 /* reset DIRECT_ABORT bit */
143                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
144                 return -EIO; /* error: DIRECT_ABORT set */
145         }
146         return 0;
147 }
148
149 /**
150  * write_i2c_reg_nowait - writes to an internal i2c register
151  *
152  * @addr:       dt3155 mmio base address
153  * @index:      index (internal address) of register to read
154  * @data:       data to be written
155  *
156  * This function starts writting the specified (by index) register
157  * and then returns.
158  */
159 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
160 {
161         u32 tmp = index;
162
163         iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
164         mmiowb();
165 }
166
167 /**
168  * wait_i2c_reg - waits the read/write to finish
169  *
170  * @addr:       dt3155 mmio base address
171  *
172  * returns:     zero on success or error code
173  *
174  * This function waits reading/writting to finish.
175  */
176 static int wait_i2c_reg(void __iomem *addr)
177 {
178         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
179                 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
180         if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
181                 return -EIO; /* error: NEW_CYCLE not cleared */
182         if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
183                 /* reset DIRECT_ABORT bit */
184                 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
185                 return -EIO; /* error: DIRECT_ABORT set */
186         }
187         return 0;
188 }
189
190 static int
191 dt3155_start_acq(struct dt3155_priv *pd)
192 {
193         struct vb2_buffer *vb = pd->curr_buf;
194         dma_addr_t dma_addr;
195
196         dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
197         iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
198         iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);
199         iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);
200         iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);
201         /* enable interrupts, clear all irq flags */
202         iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
203                         FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
204         iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
205                   FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
206                                                         pd->regs + CSR1);
207         wait_i2c_reg(pd->regs);
208         write_i2c_reg(pd->regs, CONFIG, pd->config);
209         write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
210         write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
211
212         /*  start the board  */
213         write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
214         return 0; /* success  */
215 }
216
217 /*
218  *      driver-specific callbacks (vb2_ops)
219  */
220 static int
221 dt3155_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
222                         unsigned int *num_planes, unsigned long sizes[],
223                                                 void *alloc_ctxs[])
224 {
225         struct dt3155_priv *pd = vb2_get_drv_priv(q);
226         void *ret;
227
228         if (*num_buffers == 0)
229                 *num_buffers = 1;
230         *num_planes = 1;
231         sizes[0] = img_width * img_height;
232         if (pd->q->alloc_ctx[0])
233                 return 0;
234         ret = vb2_dma_contig_init_ctx(&pd->pdev->dev);
235         if (IS_ERR(ret))
236                 return PTR_ERR(ret);
237         pd->q->alloc_ctx[0] = ret;
238         return 0;
239 }
240
241 static void
242 dt3155_wait_prepare(struct vb2_queue *q)
243 {
244         struct dt3155_priv *pd = vb2_get_drv_priv(q);
245
246         mutex_unlock(pd->vdev->lock);
247 }
248
249 static void
250 dt3155_wait_finish(struct vb2_queue *q)
251 {
252         struct dt3155_priv *pd = vb2_get_drv_priv(q);
253
254         mutex_lock(pd->vdev->lock);
255 }
256
257 static int
258 dt3155_buf_prepare(struct vb2_buffer *vb)
259 {
260         vb2_set_plane_payload(vb, 0, img_width * img_height);
261         return 0;
262 }
263
264 static int
265 dt3155_start_streaming(struct vb2_queue *q)
266 {
267         return 0;
268 }
269
270 static int
271 dt3155_stop_streaming(struct vb2_queue *q)
272 {
273         struct dt3155_priv *pd = vb2_get_drv_priv(q);
274         struct vb2_buffer *vb;
275
276         spin_lock_irq(&pd->lock);
277         while (!list_empty(&pd->dmaq)) {
278                 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
279                 list_del(&vb->done_entry);
280                 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
281         }
282         spin_unlock_irq(&pd->lock);
283         msleep(45); /* irq hendler will stop the hardware */
284         return 0;
285 }
286
287 static void
288 dt3155_buf_queue(struct vb2_buffer *vb)
289 {
290         struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
291
292         /*  pd->q->streaming = 1 when dt3155_buf_queue() is invoked  */
293         spin_lock_irq(&pd->lock);
294         if (pd->curr_buf)
295                 list_add_tail(&vb->done_entry, &pd->dmaq);
296         else {
297                 pd->curr_buf = vb;
298                 dt3155_start_acq(pd);
299         }
300         spin_unlock_irq(&pd->lock);
301 }
302 /*
303  *      end driver-specific callbacks
304  */
305
306 const struct vb2_ops q_ops = {
307         .queue_setup = dt3155_queue_setup,
308         .wait_prepare = dt3155_wait_prepare,
309         .wait_finish = dt3155_wait_finish,
310         .buf_prepare = dt3155_buf_prepare,
311         .start_streaming = dt3155_start_streaming,
312         .stop_streaming = dt3155_stop_streaming,
313         .buf_queue = dt3155_buf_queue,
314 };
315
316 static irqreturn_t
317 dt3155_irq_handler_even(int irq, void *dev_id)
318 {
319         struct dt3155_priv *ipd = dev_id;
320         struct vb2_buffer *ivb;
321         dma_addr_t dma_addr;
322         u32 tmp;
323
324         tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
325         if (!tmp)
326                 return IRQ_NONE;  /* not our irq */
327         if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
328                 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
329                                                         ipd->regs + INT_CSR);
330                 ipd->field_count++;
331                 return IRQ_HANDLED; /* start of field irq */
332         }
333         if ((tmp & FLD_START) && (tmp & FLD_END_ODD))
334                 ipd->stats.start_before_end++;
335         /*      check for corrupted fields     */
336 /*      write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);       */
337 /*      write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);        */
338         tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
339         if (tmp) {
340                 ipd->stats.corrupted_fields++;
341                 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
342                                                 FLD_DN_ODD | FLD_DN_EVEN |
343                                                 CAP_CONT_EVEN | CAP_CONT_ODD,
344                                                         ipd->regs + CSR1);
345                 mmiowb();
346         }
347
348         spin_lock(&ipd->lock);
349         if (ipd->curr_buf) {
350                 do_gettimeofday(&ipd->curr_buf->v4l2_buf.timestamp);
351                 ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1;
352                 vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
353         }
354
355         if (!ipd->q->streaming || list_empty(&ipd->dmaq))
356                 goto stop_dma;
357         ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
358         list_del(&ivb->done_entry);
359         ipd->curr_buf = ivb;
360         dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
361         iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
362         iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START);
363         iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE);
364         iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE);
365         mmiowb();
366         /* enable interrupts, clear all irq flags */
367         iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
368                         FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
369         spin_unlock(&ipd->lock);
370         return IRQ_HANDLED;
371
372 stop_dma:
373         ipd->curr_buf = NULL;
374         /* stop the board */
375         write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
376         iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
377                   FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
378         /* disable interrupts, clear all irq flags */
379         iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
380         spin_unlock(&ipd->lock);
381         return IRQ_HANDLED;
382 }
383
384 static int
385 dt3155_open(struct file *filp)
386 {
387         int ret = 0;
388         struct dt3155_priv *pd = video_drvdata(filp);
389
390         if (!pd->users) {
391                 pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL);
392                 if (!pd->q) {
393                         ret = -ENOMEM;
394                         goto err_alloc_queue;
395                 }
396                 pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
397                 pd->q->io_modes = VB2_READ | VB2_MMAP;
398                 pd->q->ops = &q_ops;
399                 pd->q->mem_ops = &vb2_dma_contig_memops;
400                 pd->q->drv_priv = pd;
401                 pd->curr_buf = NULL;
402                 pd->field_count = 0;
403                 vb2_queue_init(pd->q); /* cannot fail */
404                 INIT_LIST_HEAD(&pd->dmaq);
405                 spin_lock_init(&pd->lock);
406                 /* disable all irqs, clear all irq flags */
407                 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
408                                                 pd->regs + INT_CSR);
409                 ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
410                                                 IRQF_SHARED, DT3155_NAME, pd);
411                 if (ret)
412                         goto err_request_irq;
413         }
414         pd->users++;
415         return 0; /* success */
416 err_request_irq:
417         kfree(pd->q);
418         pd->q = NULL;
419 err_alloc_queue:
420         return ret;
421 }
422
423 static int
424 dt3155_release(struct file *filp)
425 {
426         struct dt3155_priv *pd = video_drvdata(filp);
427
428         pd->users--;
429         BUG_ON(pd->users < 0);
430         if (!pd->users) {
431                 vb2_queue_release(pd->q);
432                 free_irq(pd->pdev->irq, pd);
433                 if (pd->q->alloc_ctx[0])
434                         vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]);
435                 kfree(pd->q);
436                 pd->q = NULL;
437         }
438         return 0;
439 }
440
441 static ssize_t
442 dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
443 {
444         struct dt3155_priv *pd = video_drvdata(filp);
445
446         return vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK);
447 }
448
449 static unsigned int
450 dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
451 {
452         struct dt3155_priv *pd = video_drvdata(filp);
453
454         return vb2_poll(pd->q, filp, polltbl);
455 }
456
457 static int
458 dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
459 {
460         struct dt3155_priv *pd = video_drvdata(filp);
461
462         return vb2_mmap(pd->q, vma);
463 }
464
465 static const struct v4l2_file_operations dt3155_fops = {
466         .owner = THIS_MODULE,
467         .open = dt3155_open,
468         .release = dt3155_release,
469         .read = dt3155_read,
470         .poll = dt3155_poll,
471         .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
472         .mmap = dt3155_mmap,
473 };
474
475 static int
476 dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
477 {
478         struct dt3155_priv *pd = video_drvdata(filp);
479
480         return vb2_streamon(pd->q, type);
481 }
482
483 static int
484 dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
485 {
486         struct dt3155_priv *pd = video_drvdata(filp);
487
488         return vb2_streamoff(pd->q, type);
489 }
490
491 static int
492 dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
493 {
494         struct dt3155_priv *pd = video_drvdata(filp);
495
496         strcpy(cap->driver, DT3155_NAME);
497         strcpy(cap->card, DT3155_NAME " frame grabber");
498         sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
499         cap->version =
500                KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT);
501         cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
502                                 DT3155_CAPTURE_METHOD;
503         return 0;
504 }
505
506 static int
507 dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
508 {
509         if (f->index >= NUM_OF_FORMATS)
510                 return -EINVAL;
511         *f = frame_std[f->index];
512         return 0;
513 }
514
515 static int
516 dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
517 {
518         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
519                 return -EINVAL;
520         f->fmt.pix.width = img_width;
521         f->fmt.pix.height = img_height;
522         f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
523         f->fmt.pix.field = V4L2_FIELD_NONE;
524         f->fmt.pix.bytesperline = f->fmt.pix.width;
525         f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
526         f->fmt.pix.colorspace = 0;
527         f->fmt.pix.priv = 0;
528         return 0;
529 }
530
531 static int
532 dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
533 {
534         if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
535                 return -EINVAL;
536         if (f->fmt.pix.width == img_width &&
537                 f->fmt.pix.height == img_height &&
538                 f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
539                 f->fmt.pix.field == V4L2_FIELD_NONE &&
540                 f->fmt.pix.bytesperline == f->fmt.pix.width &&
541                 f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
542                         return 0;
543         else
544                 return -EINVAL;
545 }
546
547 static int
548 dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
549 {
550         return dt3155_ioc_g_fmt_vid_cap(filp, p, f);
551 }
552
553 static int
554 dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
555 {
556         struct dt3155_priv *pd = video_drvdata(filp);
557
558         return vb2_reqbufs(pd->q, b);
559 }
560
561 static int
562 dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
563 {
564         struct dt3155_priv *pd = video_drvdata(filp);
565
566         return vb2_querybuf(pd->q, b);
567 }
568
569 static int
570 dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
571 {
572         struct dt3155_priv *pd = video_drvdata(filp);
573
574         return vb2_qbuf(pd->q, b);
575 }
576
577 static int
578 dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
579 {
580         struct dt3155_priv *pd = video_drvdata(filp);
581
582         return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK);
583 }
584
585 static int
586 dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
587 {
588         *norm = DT3155_CURRENT_NORM;
589         return 0;
590 }
591
592 static int
593 dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
594 {
595         *norm = DT3155_CURRENT_NORM;
596         return 0;
597 }
598
599 static int
600 dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id *norm)
601 {
602         if (*norm & DT3155_CURRENT_NORM)
603                 return 0;
604         return -EINVAL;
605 }
606
607 static int
608 dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
609 {
610         if (input->index)
611                 return -EINVAL;
612         strcpy(input->name, "Coax in");
613         input->type = V4L2_INPUT_TYPE_CAMERA;
614         /*
615          * FIXME: input->std = 0 according to v4l2 API
616          * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
617          * should return -EINVAL
618          */
619         input->std = DT3155_CURRENT_NORM;
620         input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
621         return 0;
622 }
623
624 static int
625 dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
626 {
627         *i = 0;
628         return 0;
629 }
630
631 static int
632 dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
633 {
634         if (i)
635                 return -EINVAL;
636         return 0;
637 }
638
639 static int
640 dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
641 {
642         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
643                 return -EINVAL;
644         parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
645         parms->parm.capture.capturemode = 0;
646         parms->parm.capture.timeperframe.numerator = 1001;
647         parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
648         parms->parm.capture.extendedmode = 0;
649         parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
650         return 0;
651 }
652
653 static int
654 dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
655 {
656         if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
657                 return -EINVAL;
658         parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
659         parms->parm.capture.capturemode = 0;
660         parms->parm.capture.timeperframe.numerator = 1001;
661         parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
662         parms->parm.capture.extendedmode = 0;
663         parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
664         return 0;
665 }
666
667 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
668         .vidioc_streamon = dt3155_ioc_streamon,
669         .vidioc_streamoff = dt3155_ioc_streamoff,
670         .vidioc_querycap = dt3155_ioc_querycap,
671 /*
672         .vidioc_g_priority = dt3155_ioc_g_priority,
673         .vidioc_s_priority = dt3155_ioc_s_priority,
674 */
675         .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
676         .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
677         .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
678         .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
679         .vidioc_reqbufs = dt3155_ioc_reqbufs,
680         .vidioc_querybuf = dt3155_ioc_querybuf,
681         .vidioc_qbuf = dt3155_ioc_qbuf,
682         .vidioc_dqbuf = dt3155_ioc_dqbuf,
683         .vidioc_querystd = dt3155_ioc_querystd,
684         .vidioc_g_std = dt3155_ioc_g_std,
685         .vidioc_s_std = dt3155_ioc_s_std,
686         .vidioc_enum_input = dt3155_ioc_enum_input,
687         .vidioc_g_input = dt3155_ioc_g_input,
688         .vidioc_s_input = dt3155_ioc_s_input,
689 /*
690         .vidioc_queryctrl = dt3155_ioc_queryctrl,
691         .vidioc_g_ctrl = dt3155_ioc_g_ctrl,
692         .vidioc_s_ctrl = dt3155_ioc_s_ctrl,
693         .vidioc_querymenu = dt3155_ioc_querymenu,
694         .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
695         .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
696 */
697         .vidioc_g_parm = dt3155_ioc_g_parm,
698         .vidioc_s_parm = dt3155_ioc_s_parm,
699 /*
700         .vidioc_cropcap = dt3155_ioc_cropcap,
701         .vidioc_g_crop = dt3155_ioc_g_crop,
702         .vidioc_s_crop = dt3155_ioc_s_crop,
703         .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
704         .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
705 */
706 };
707
708 static int __devinit
709 dt3155_init_board(struct pci_dev *pdev)
710 {
711         struct dt3155_priv *pd = pci_get_drvdata(pdev);
712         void *buf_cpu;
713         dma_addr_t buf_dma;
714         int i;
715         u8 tmp;
716
717         pci_set_master(pdev); /* dt3155 needs it */
718
719         /*  resetting the adapter  */
720         iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
721                                                         pd->regs + CSR1);
722         mmiowb();
723         msleep(20);
724
725         /*  initializing adaper registers  */
726         iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
727         mmiowb();
728         iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
729         iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
730         iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
731         iowrite32(0x00000103, pd->regs + XFER_MODE);
732         iowrite32(0, pd->regs + RETRY_WAIT_CNT);
733         iowrite32(0, pd->regs + INT_CSR);
734         iowrite32(1, pd->regs + EVEN_FLD_MASK);
735         iowrite32(1, pd->regs + ODD_FLD_MASK);
736         iowrite32(0, pd->regs + MASK_LENGTH);
737         iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
738         iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
739         mmiowb();
740
741         /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
742         read_i2c_reg(pd->regs, DT_ID, &tmp);
743         if (tmp != DT3155_ID)
744                 return -ENODEV;
745
746         /* initialize AD LUT */
747         write_i2c_reg(pd->regs, AD_ADDR, 0);
748         for (i = 0; i < 256; i++)
749                 write_i2c_reg(pd->regs, AD_LUT, i);
750
751         /* initialize ADC references */
752         /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
753         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
754         write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
755         write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
756         write_i2c_reg(pd->regs, AD_CMD, 34);
757         write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
758         write_i2c_reg(pd->regs, AD_CMD, 0);
759
760         /* initialize PM LUT */
761         write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
762         for (i = 0; i < 256; i++) {
763                 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
764                 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
765         }
766         write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
767         for (i = 0; i < 256; i++) {
768                 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
769                 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
770         }
771         write_i2c_reg(pd->regs, CONFIG, pd->config); /*  ACQ_MODE_EVEN  */
772
773         /* select chanel 1 for input and set sync level */
774         write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
775         write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
776
777         /* allocate memory, and initialize the DMA machine */
778         buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma,
779                                                                 GFP_KERNEL);
780         if (!buf_cpu)
781                 return -ENOMEM;
782         iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
783         iowrite32(buf_dma, pd->regs + ODD_DMA_START);
784         iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
785         iowrite32(0, pd->regs + ODD_DMA_STRIDE);
786
787         /*  Perform a pseudo even field acquire    */
788         iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
789         write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
790         write_i2c_reg(pd->regs, CONFIG, pd->config);
791         write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
792         write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
793         msleep(100);
794         read_i2c_reg(pd->regs, CSR2, &tmp);
795         write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
796         write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
797         write_i2c_reg(pd->regs, CSR2, pd->csr2);
798         iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
799
800         /*  deallocate memory  */
801         dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
802         if (tmp & BUSY_EVEN)
803                 return -EIO;
804         return 0;
805 }
806
807 static struct video_device dt3155_vdev = {
808         .name = DT3155_NAME,
809         .fops = &dt3155_fops,
810         .ioctl_ops = &dt3155_ioctl_ops,
811         .minor = -1,
812         .release = video_device_release,
813         .tvnorms = DT3155_CURRENT_NORM,
814         .current_norm = DT3155_CURRENT_NORM,
815 };
816
817 /* same as in drivers/base/dma-coherent.c */
818 struct dma_coherent_mem {
819         void            *virt_base;
820         dma_addr_t      device_base;
821         int             size;
822         int             flags;
823         unsigned long   *bitmap;
824 };
825
826 static int __devinit
827 dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
828 {
829         struct dma_coherent_mem *mem;
830         dma_addr_t dev_base;
831         int pages = size >> PAGE_SHIFT;
832         int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
833
834         if ((flags & DMA_MEMORY_MAP) == 0)
835                 goto out;
836         if (!size)
837                 goto out;
838         if (dev->dma_mem)
839                 goto out;
840
841         mem = kzalloc(sizeof(*mem), GFP_KERNEL);
842         if (!mem)
843                 goto out;
844         mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
845                                                         DT3155_COH_FLAGS);
846         if (!mem->virt_base)
847                 goto err_alloc_coherent;
848         mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
849         if (!mem->bitmap)
850                 goto err_bitmap;
851
852         /* coherent_dma_mask is already set to 32 bits */
853         mem->device_base = dev_base;
854         mem->size = pages;
855         mem->flags = flags;
856         dev->dma_mem = mem;
857         return DMA_MEMORY_MAP;
858
859 err_bitmap:
860         dma_free_coherent(dev, size, mem->virt_base, dev_base);
861 err_alloc_coherent:
862         kfree(mem);
863 out:
864         return 0;
865 }
866
867 static void __devexit
868 dt3155_free_coherent(struct device *dev)
869 {
870         struct dma_coherent_mem *mem = dev->dma_mem;
871
872         if (!mem)
873                 return;
874         dev->dma_mem = NULL;
875         dma_free_coherent(dev, mem->size << PAGE_SHIFT,
876                                         mem->virt_base, mem->device_base);
877         kfree(mem->bitmap);
878         kfree(mem);
879 }
880
881 static int __devinit
882 dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
883 {
884         int err;
885         struct dt3155_priv *pd;
886
887         err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
888         if (err)
889                 return -ENODEV;
890         err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
891         if (err)
892                 return -ENODEV;
893         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
894         if (!pd)
895                 return -ENOMEM;
896         pd->vdev = video_device_alloc();
897         if (!pd->vdev)
898                 goto err_video_device_alloc;
899         *pd->vdev = dt3155_vdev;
900         pci_set_drvdata(pdev, pd);    /* for use in dt3155_remove() */
901         video_set_drvdata(pd->vdev, pd);  /* for use in video_fops */
902         pd->users = 0;
903         pd->pdev = pdev;
904         INIT_LIST_HEAD(&pd->dmaq);
905         mutex_init(&pd->mux);
906         pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */
907         spin_lock_init(&pd->lock);
908         pd->csr2 = csr2_init;
909         pd->config = config_init;
910         err = pci_enable_device(pdev);
911         if (err)
912                 goto err_enable_dev;
913         err = pci_request_region(pdev, 0, pci_name(pdev));
914         if (err)
915                 goto err_req_region;
916         pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
917         if (!pd->regs)
918                 err = -ENOMEM;
919                 goto err_pci_iomap;
920         err = dt3155_init_board(pdev);
921         if (err)
922                 goto err_init_board;
923         err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1);
924         if (err)
925                 goto err_init_board;
926         if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE,
927                                                         DMA_MEMORY_MAP))
928                 dev_info(&pdev->dev, "preallocated 8 buffers\n");
929         dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev->minor);
930         return 0;  /*   success   */
931
932 err_init_board:
933         pci_iounmap(pdev, pd->regs);
934 err_pci_iomap:
935         pci_release_region(pdev, 0);
936 err_req_region:
937         pci_disable_device(pdev);
938 err_enable_dev:
939         video_device_release(pd->vdev);
940 err_video_device_alloc:
941         kfree(pd);
942         return err;
943 }
944
945 static void __devexit
946 dt3155_remove(struct pci_dev *pdev)
947 {
948         struct dt3155_priv *pd = pci_get_drvdata(pdev);
949
950         dt3155_free_coherent(&pdev->dev);
951         video_unregister_device(pd->vdev);
952         pci_iounmap(pdev, pd->regs);
953         pci_release_region(pdev, 0);
954         pci_disable_device(pdev);
955         /*
956          * video_device_release() is invoked automatically
957          * see: struct video_device dt3155_vdev
958          */
959         kfree(pd);
960 }
961
962 static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
963         { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) },
964         { 0, /* zero marks the end */ },
965 };
966 MODULE_DEVICE_TABLE(pci, pci_ids);
967
968 static struct pci_driver pci_driver = {
969         .name = DT3155_NAME,
970         .id_table = pci_ids,
971         .probe = dt3155_probe,
972         .remove = __devexit_p(dt3155_remove),
973 };
974
975 static int __init
976 dt3155_init_module(void)
977 {
978         return pci_register_driver(&pci_driver);
979 }
980
981 static void __exit
982 dt3155_exit_module(void)
983 {
984         pci_unregister_driver(&pci_driver);
985 }
986
987 module_init(dt3155_init_module);
988 module_exit(dt3155_exit_module);
989
990 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
991 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
992 MODULE_VERSION(DT3155_VERSION);
993 MODULE_LICENSE("GPL");