iio: staging: adc: palmas: Support for auto conversion shutdown
[linux-2.6.git] / drivers / staging / iio / adc / palmas_gpadc.c
1 /*
2  * palmas-adc.c -- TI PALMAS GPADC.
3  *
4  * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
5  *
6  * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation version 2.
11  *
12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
13  * whether express or implied; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20  * 02111-1307, USA
21  */
22 #include <linux/module.h>
23 #include <linux/err.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/pm.h>
31 #include <linux/mfd/palmas.h>
32 #include <linux/completion.h>
33
34 #include "../iio.h"
35 #include "../driver.h"
36
37 #define MOD_NAME "palmas-gpadc"
38 #define ADC_CONVERTION_TIMEOUT  (msecs_to_jiffies(5000))
39 #define TO_BE_CALCULATED        0
40 #define PRECISION_MULTIPLIER    1000000LL
41
42 struct palmas_gpadc_info {
43 /* calibration codes and regs */
44         int x1;
45         int x2;
46         u8 trim1_reg;
47         u8 trim2_reg;
48         s64 gain;
49         s64 offset;
50         bool is_correct_code;
51 };
52
53 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _t1, _t2, _is_correct_code)    \
54 [PALMAS_ADC_CH_##_chan] = {                                             \
55                 .x1 = _x1,                                              \
56                 .x2 = _x2,                                              \
57                 .gain = TO_BE_CALCULATED,                               \
58                 .offset = TO_BE_CALCULATED,                             \
59                 .trim1_reg = PALMAS_GPADC_TRIM##_t1,                    \
60                 .trim2_reg = PALMAS_GPADC_TRIM##_t2,                    \
61                 .is_correct_code = _is_correct_code                     \
62         }
63
64 static struct palmas_gpadc_info palmas_gpadc_info[] = {
65         PALMAS_ADC_INFO(IN0, 2064, 3112, 1, 2, false),
66         PALMAS_ADC_INFO(IN1, 2064, 3112, 1, 2, false),
67         PALMAS_ADC_INFO(IN2, 2064, 3112, 3, 4, false),
68         PALMAS_ADC_INFO(IN3, 2064, 3112, 1, 2, false),
69         PALMAS_ADC_INFO(IN4, 2064, 3112, 1, 2, false),
70         PALMAS_ADC_INFO(IN5, 2064, 3112, 1, 2, false),
71         PALMAS_ADC_INFO(IN6, 2064, 3112, 5, 6, false),
72         PALMAS_ADC_INFO(IN7, 2064, 3112, 7, 8, false),
73         PALMAS_ADC_INFO(IN8, 2064, 3112, 9, 10, false),
74         PALMAS_ADC_INFO(IN9, 2064, 3112, 11, 12, false),
75         PALMAS_ADC_INFO(IN10, 2064, 3112, 13, 14, false),
76         PALMAS_ADC_INFO(IN11, 0, 0, INVALID, INVALID, true),
77         PALMAS_ADC_INFO(IN12, 0, 0, INVALID, INVALID, true),
78         PALMAS_ADC_INFO(IN13, 0, 0, INVALID, INVALID, true),
79         PALMAS_ADC_INFO(IN14, 2064, 3112, 15, 16, false),
80         PALMAS_ADC_INFO(IN15, 0, 0, INVALID, INVALID, true),
81 };
82
83 struct palmas_gpadc {
84         struct device                   *dev;
85         struct palmas                   *palmas;
86         u8                              ch0_current;
87         u8                              ch3_current;
88         bool                            ch3_dual_current;
89         bool                            extended_delay;
90         int                             irq;
91         int                             irq_auto_0;
92         int                             irq_auto_1;
93         struct palmas_gpadc_info        *adc_info;
94         struct completion               conv_completion;
95         struct palmas_adc_auto_conv_property auto_conv1_data;
96         struct palmas_adc_auto_conv_property auto_conv2_data;
97         bool                            auto_conv1_enable;
98         bool                            auto_conv2_enable;
99         int                             auto_conversion_period;
100 };
101
102 /*
103  * GPADC lock issue in AUTO mode.
104  * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
105  *         mode feature.
106  * Details:
107  *      When the AUTO mode is the only conversion mode enabled, if the AUTO
108  *      mode feature is disabled with bit GPADC_AUTO_CTRL.  AUTO_CONV1_EN = 0
109  *      or bit GPADC_AUTO_CTRL.  AUTO_CONV0_EN = 0 during a conversion, the
110  *      conversion mechanism can be seen as locked meaning that all following
111  *      conversion will give 0 as a result.  Bit GPADC_STATUS.GPADC_AVAILABLE
112  *      will stay at 0 meaning that GPADC is busy.  An RT conversion can unlock
113  *      the GPADC.
114  *
115  * Workaround(s):
116  *      To avoid the lock mechanism, the workaround to follow before any stop
117  *      conversion request is:
118  *      Force the GPADC state machine to be ON by using the GPADC_CTRL1.
119  *              GPADC_FORCE bit = 1
120  *      Shutdown the GPADC AUTO conversion using
121  *              GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
122  *      After 100us, force the GPADC state machine to be OFF by using the
123  *              GPADC_CTRL1.  GPADC_FORCE bit = 0
124  */
125 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
126 {
127         int ret;
128
129         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
130                         PALMAS_GPADC_CTRL1,
131                         PALMAS_GPADC_CTRL1_GPADC_FORCE,
132                         PALMAS_GPADC_CTRL1_GPADC_FORCE);
133         if (ret < 0) {
134                 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
135                 return ret;
136         }
137
138         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
139                         PALMAS_GPADC_AUTO_CTRL,
140                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
141                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
142                         0);
143         if (ret < 0) {
144                 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
145                 return ret;
146         }
147
148         udelay(100);
149
150         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
151                         PALMAS_GPADC_CTRL1,
152                         PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
153         if (ret < 0) {
154                 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
155                 return ret;
156         }
157         return 0;
158 }
159
160 static irqreturn_t palmas_gpadc_irq(int irq, void *data)
161 {
162         struct palmas_gpadc *adc = data;
163
164         complete(&adc->conv_completion);
165         return IRQ_HANDLED;
166 }
167
168 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
169 {
170         struct palmas_gpadc *adc = data;
171
172         dev_info(adc->dev, "Threshold interrupt %d occurs\n", irq);
173         palmas_disable_auto_conversion(adc);
174         return IRQ_HANDLED;
175 }
176
177 static int palmas_gpadc_auto_conv_configure(struct palmas_gpadc *adc)
178 {
179         int adc_period, conv;
180         int i;
181         int ch0 = 0, ch1 = 0;
182         int thres;
183         int ret;
184
185         adc_period = adc->auto_conversion_period;
186         for (i = 0; i < 16; ++i) {
187                 if (((1000 * (1 << i))/32) > adc_period)
188                         break;
189         }
190         if (i > 0)
191                 i--;
192         adc_period = i;
193         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
194                         PALMAS_GPADC_AUTO_CTRL,
195                         PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
196                         adc_period);
197         if (ret < 0) {
198                 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
199                 return ret;
200         }
201
202         conv = 0;
203         if (adc->auto_conv1_enable) {
204                 int is_high;
205
206                 ch0 = adc->auto_conv1_data.adc_channel_number;
207                 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
208                 conv |= (adc->auto_conv1_data.adc_shutdown ?
209                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 : 0);
210                 if (adc->auto_conv1_data.adc_high_threshold > 0) {
211                         thres = adc->auto_conv1_data.adc_high_threshold;
212                         is_high = 0;
213                 } else {
214                         thres = adc->auto_conv1_data.adc_low_threshold;
215                         is_high = BIT(7);
216                 }
217
218                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
219                                 PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
220                 if (ret < 0) {
221                         dev_err(adc->dev,
222                                 "THRES_CONV0_LSB write failed: %d\n", ret);
223                         return ret;
224                 }
225
226                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
227                                 PALMAS_GPADC_THRES_CONV0_MSB,
228                                 ((thres >> 8) & 0xF) | is_high);
229                 if (ret < 0) {
230                         dev_err(adc->dev,
231                                 "THRES_CONV0_MSB write failed: %d\n", ret);
232                         return ret;
233                 }
234         }
235
236         if (adc->auto_conv2_enable) {
237                 int is_high;
238
239                 ch1 = adc->auto_conv2_data.adc_channel_number;
240                 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
241                 conv |= (adc->auto_conv2_data.adc_shutdown ?
242                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 : 0);
243                 if (adc->auto_conv2_data.adc_high_threshold > 0) {
244                         thres = adc->auto_conv2_data.adc_high_threshold;
245                         is_high = 0;
246                 } else {
247                         thres = adc->auto_conv2_data.adc_low_threshold;
248                         is_high = BIT(7);
249                 }
250
251                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
252                                 PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
253                 if (ret < 0) {
254                         dev_err(adc->dev,
255                                 "THRES_CONV1_LSB write failed: %d\n", ret);
256                         return ret;
257                 }
258
259                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
260                                 PALMAS_GPADC_THRES_CONV1_MSB,
261                                 ((thres >> 8) & 0xF) | is_high);
262                 if (ret < 0) {
263                         dev_err(adc->dev,
264                                 "THRES_CONV1_MSB write failed: %d\n", ret);
265                         return ret;
266                 }
267         }
268
269         ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
270                         PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
271         if (ret < 0) {
272                 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
273                 return ret;
274         }
275
276         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
277                         PALMAS_GPADC_AUTO_CTRL,
278                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
279                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 |
280                         PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
281                         PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
282         if (ret < 0) {
283                 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
284                 return ret;
285         }
286
287         return 0;
288 }
289
290 static int palmas_gpadc_auto_conv_reset(struct palmas_gpadc *adc)
291 {
292         int ret;
293
294         ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
295                         PALMAS_GPADC_AUTO_SELECT, 0);
296         if (ret < 0) {
297                 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
298                 return ret;
299         }
300
301         ret = palmas_disable_auto_conversion(adc);
302         if (ret < 0) {
303                 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
304                 return ret;
305         }
306
307         if (adc->auto_conv1_data.adc_shutdown ||
308                         adc->auto_conv2_data.adc_shutdown) {
309                 ret = palmas_gpadc_auto_conv_configure(adc);
310                 if (ret < 0) {
311                         dev_err(adc->dev,
312                                 "auto conversion configure failed: %d\n", ret);
313                         return ret;
314                 }
315         }
316
317         return 0;
318 }
319
320 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc, int mask)
321 {
322         int ret;
323
324         if (!mask)
325                 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
326                                         PALMAS_INT3_MASK,
327                                         PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
328         else
329                 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
330                                         PALMAS_INT3_MASK,
331                                         PALMAS_INT3_MASK_GPADC_EOC_SW,
332                                         PALMAS_INT3_MASK_GPADC_EOC_SW);
333         if (ret < 0)
334                 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
335
336         return ret;
337 }
338
339 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
340 {
341         s64 k;
342         int d1;
343         int d2;
344         int ret;
345         int x1 =  adc->adc_info[adc_chan].x1;
346         int x2 =  adc->adc_info[adc_chan].x2;
347
348         ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
349                                 adc->adc_info[adc_chan].trim1_reg, &d1);
350         if (ret < 0) {
351                 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
352                 goto scrub;
353         }
354
355         ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
356                                 adc->adc_info[adc_chan].trim2_reg, &d2);
357         if (ret < 0) {
358                 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
359                 goto scrub;
360         }
361
362         /* Gain Calculation */
363         k = PRECISION_MULTIPLIER;
364         k += div64_s64(PRECISION_MULTIPLIER * (d2 - d1), x2 - x1);
365         adc->adc_info[adc_chan].gain = k;
366
367         /* offset Calculation */
368         adc->adc_info[adc_chan].offset = (d1 * PRECISION_MULTIPLIER);
369         adc->adc_info[adc_chan].offset -= ((k - PRECISION_MULTIPLIER) * x1);
370 scrub:
371         return ret;
372 }
373
374 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
375                                         int enable)
376 {
377         unsigned int val, mask;
378         int ret;
379
380         if (enable) {
381                 val = (adc->extended_delay
382                         << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
383                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
384                                         PALMAS_GPADC_RT_CTRL,
385                                         PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
386                 if (ret < 0) {
387                         dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
388                         return ret;
389                 }
390
391                 mask = PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
392                         PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
393                         PALMAS_GPADC_CTRL1_GPADC_FORCE;
394                 val = (adc->ch0_current
395                         << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
396                 val |= (adc->ch3_current
397                         << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
398                 val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
399                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
400                                 PALMAS_GPADC_CTRL1, mask, val);
401                 if (ret < 0) {
402                         dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
403                         return ret;
404                 }
405
406                 mask = PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
407                         PALMAS_GPADC_SW_SELECT_SW_CONV_EN;
408                 val = adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN;
409                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
410                                 PALMAS_GPADC_SW_SELECT, mask, val);
411                 if (ret < 0) {
412                         dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
413                         return ret;
414                 }
415         } else {
416                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
417                                 PALMAS_GPADC_SW_SELECT, 0);
418                 if (ret < 0) {
419                         dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
420                         return ret;
421                 }
422
423                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
424                                 PALMAS_GPADC_CTRL1,
425                                 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
426                 if (ret < 0) {
427                         dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
428                         return ret;
429                 }
430         }
431
432         return 0;
433 }
434
435 static int palmas_gpadc_set_current_src(struct palmas_gpadc *adc,
436                                         int ch0_current, int ch3_current)
437 {
438         unsigned int val, mask;
439         int ret;
440
441         mask = PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
442                 PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK;
443         val = (ch0_current << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT) |
444                 (ch3_current << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
445         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
446                                 PALMAS_GPADC_CTRL1, mask, val);
447         if (ret < 0) {
448                 dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
449                 return ret;
450         }
451
452         return 0;
453 }
454
455 static int palmas_gpadc_start_convertion(struct palmas_gpadc *adc, int adc_chan)
456 {
457         unsigned int val;
458         int ret;
459
460         INIT_COMPLETION(adc->conv_completion);
461         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
462                                 PALMAS_GPADC_SW_SELECT,
463                                 PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
464                                 PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
465         if (ret < 0) {
466                 dev_err(adc->dev, "ADC_SW_START write failed: %d\n", ret);
467                 return ret;
468         }
469
470         ret = wait_for_completion_timeout(&adc->conv_completion,
471                                 ADC_CONVERTION_TIMEOUT);
472         if (ret == 0) {
473                 dev_err(adc->dev, "ADC conversion not completed\n");
474                 ret = -ETIMEDOUT;
475                 return ret;
476         }
477
478         ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
479                         PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
480         if (ret < 0) {
481                 dev_err(adc->dev, "ADCDATA read failed: %d\n", ret);
482                 return ret;
483         }
484
485         ret = (val & 0xFFF);
486         return ret;
487 }
488
489 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
490                                             int adc_chan, int val)
491 {
492         s64 code = val * PRECISION_MULTIPLIER;
493
494         if ((code - adc->adc_info[adc_chan].offset) < 0) {
495                 dev_err(adc->dev, "No Input Connected\n");
496                 return 0;
497         }
498
499         if (!(adc->adc_info[adc_chan].is_correct_code)) {
500                 code -= adc->adc_info[adc_chan].offset;
501                 val = div_s64(code, adc->adc_info[adc_chan].gain);
502         }
503
504         return val;
505 }
506
507 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
508         struct iio_chan_spec const *chan, int *val, int *val2, long mask)
509 {
510         struct  palmas_gpadc *adc = iio_priv(indio_dev);
511         int ret;
512         int adc_chan = chan->channel;
513
514         if (adc_chan > PALMAS_ADC_CH_MAX)
515                 return -EINVAL;
516
517         switch (mask) {
518         case 0:
519         case IIO_CHAN_INFO_CALIBSCALE:
520                 mutex_lock(&indio_dev->mlock);
521                 ret = palmas_gpadc_enable(adc, adc_chan, true);
522                 if (ret < 0)
523                         goto out_unlock;
524
525                 ret = palmas_gpadc_start_mask_interrupt(adc, 0);
526                 if (ret < 0)
527                         goto out_disable;
528
529                 ret = palmas_gpadc_start_convertion(adc, adc_chan);
530                 if (ret < 0) {
531                         dev_err(adc->dev, "ADC start coversion failed\n");
532                         goto out_mask_interrupt;
533                 }
534
535 #if !defined(CONFIG_MACH_TEGRATAB)
536                 if (mask == IIO_CHAN_INFO_CALIBSCALE)
537                         *val = palmas_gpadc_get_calibrated_code(adc, adc_chan,
538                                                                 ret);
539                 else
540                         *val = ret;
541 #else
542                 *val = palmas_gpadc_get_calibrated_code(adc, adc_chan, ret);
543 #endif
544
545                 if ((adc_chan == PALMAS_ADC_CH_IN3) && adc->ch3_dual_current
546                                 && val2) {
547                         ret = palmas_gpadc_set_current_src(adc,
548                                         adc->ch0_current, adc->ch3_current + 1);
549                         if (ret < 0) {
550                                 dev_err(adc->dev, "Current src set failed\n");
551                                 goto out_mask_interrupt;
552                         }
553
554                         ret = palmas_gpadc_start_convertion(adc, adc_chan);
555                         if (ret < 0) {
556                                 dev_err(adc->dev,
557                                         "ADC start coversion failed\n");
558                                 goto out_mask_interrupt;
559                         }
560
561 #if !defined(CONFIG_MACH_TEGRATAB)
562                         if (mask == IIO_CHAN_INFO_CALIBSCALE)
563                                 *val2 = palmas_gpadc_get_calibrated_code(adc,
564                                                                 adc_chan, ret);
565                         else
566                                 *val2 = ret;
567 #else
568                         *val2 = palmas_gpadc_get_calibrated_code(adc,
569                                                                 adc_chan, ret);
570 #endif
571                 }
572
573                 ret = IIO_VAL_INT;
574                 goto out_mask_interrupt;
575         }
576
577         return -EINVAL;
578
579 out_mask_interrupt:
580         palmas_gpadc_start_mask_interrupt(adc, 1);
581 out_disable:
582         palmas_gpadc_enable(adc, adc_chan, false);
583 out_unlock:
584         mutex_unlock(&indio_dev->mlock);
585         return ret;
586 }
587
588 static const struct iio_info palmas_gpadc_iio_info = {
589         .read_raw = &palmas_gpadc_read_raw,
590         .driver_module = THIS_MODULE,
591 };
592
593 #define PALMAS_ADC_CHAN_IIO(chan)                               \
594 {                                                               \
595         .type = IIO_VOLTAGE,                                    \
596         .info_mask = 0 | IIO_CHAN_INFO_CALIBSCALE_SEPARATE_BIT, \
597         .indexed = 1,                                           \
598         .channel = PALMAS_ADC_CH_##chan,                        \
599         .datasheet_name = #chan,                                \
600 }
601
602 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
603         PALMAS_ADC_CHAN_IIO(IN0),
604         PALMAS_ADC_CHAN_IIO(IN1),
605         PALMAS_ADC_CHAN_IIO(IN2),
606         PALMAS_ADC_CHAN_IIO(IN3),
607         PALMAS_ADC_CHAN_IIO(IN4),
608         PALMAS_ADC_CHAN_IIO(IN5),
609         PALMAS_ADC_CHAN_IIO(IN6),
610         PALMAS_ADC_CHAN_IIO(IN7),
611         PALMAS_ADC_CHAN_IIO(IN8),
612         PALMAS_ADC_CHAN_IIO(IN9),
613         PALMAS_ADC_CHAN_IIO(IN10),
614         PALMAS_ADC_CHAN_IIO(IN11),
615         PALMAS_ADC_CHAN_IIO(IN12),
616         PALMAS_ADC_CHAN_IIO(IN13),
617         PALMAS_ADC_CHAN_IIO(IN14),
618         PALMAS_ADC_CHAN_IIO(IN15),
619 };
620
621 static int __devinit palmas_gpadc_probe(struct platform_device *pdev)
622 {
623         struct palmas_gpadc *adc;
624         struct palmas_platform_data *pdata;
625         struct palmas_gpadc_platform_data *adc_pdata;
626         struct iio_dev *iodev;
627         int ret, i;
628
629         pdata = dev_get_platdata(pdev->dev.parent);
630         if (!pdata || !pdata->adc_pdata) {
631                 dev_err(&pdev->dev, "No platform data\n");
632                 return -ENODEV;
633         }
634         adc_pdata = pdata->adc_pdata;
635
636         iodev = iio_allocate_device(sizeof(*adc));
637         if (!iodev) {
638                 dev_err(&pdev->dev, "iio_device_alloc failed\n");
639                 return -ENOMEM;
640         }
641
642         if (adc_pdata->iio_maps) {
643                 ret = iio_map_array_register(iodev, adc_pdata->iio_maps);
644                 if (ret < 0) {
645                         dev_err(&pdev->dev, "iio_map_array_register failed\n");
646                         goto out;
647                 }
648         } else
649                 dev_warn(&pdev->dev, "No iio maps\n");
650
651         adc = iio_priv(iodev);
652         adc->dev = &pdev->dev;
653         adc->palmas = dev_get_drvdata(pdev->dev.parent);
654         adc->adc_info = palmas_gpadc_info;
655         init_completion(&adc->conv_completion);
656         dev_set_drvdata(&pdev->dev, iodev);
657
658         adc->auto_conversion_period = adc_pdata->auto_conversion_period_ms;
659         adc->irq = platform_get_irq(pdev, 0);
660         ret = request_threaded_irq(adc->irq, NULL,
661                 palmas_gpadc_irq,
662                 IRQF_ONESHOT | IRQF_EARLY_RESUME, dev_name(adc->dev),
663                 adc);
664         if (ret < 0) {
665                 dev_err(adc->dev,
666                         "request irq %d failed: %dn", adc->irq, ret);
667                 goto out_unregister_map;
668         }
669
670         if (adc_pdata->adc_auto_conv1_data) {
671                 memcpy(&adc->auto_conv1_data, adc_pdata->adc_auto_conv1_data,
672                         sizeof(adc->auto_conv1_data));
673                 adc->auto_conv1_enable = true;
674                 adc->irq_auto_0 =  platform_get_irq(pdev, 1);
675                 ret = request_threaded_irq(adc->irq_auto_0, NULL,
676                                 palmas_gpadc_irq_auto,
677                                 IRQF_ONESHOT | IRQF_EARLY_RESUME,
678                                 "palmas-adc-auto-0", adc);
679                 if (ret < 0) {
680                         dev_err(adc->dev, "request auto0 irq %d failed: %dn",
681                                 adc->irq_auto_0, ret);
682                         goto out_irq_free;
683                 }
684         }
685
686         if (adc_pdata->adc_auto_conv2_data) {
687                 memcpy(&adc->auto_conv2_data, adc_pdata->adc_auto_conv2_data,
688                                 sizeof(adc->auto_conv2_data));
689                 adc->auto_conv2_enable = true;
690                 adc->irq_auto_1 =  platform_get_irq(pdev, 2);
691                 ret = request_threaded_irq(adc->irq_auto_1, NULL,
692                                 palmas_gpadc_irq_auto,
693                                 IRQF_ONESHOT | IRQF_EARLY_RESUME,
694                                 "palmas-adc-auto-1", adc);
695                 if (ret < 0) {
696                         dev_err(adc->dev, "request auto1 irq %d failed: %dn",
697                                 adc->irq_auto_1, ret);
698                         goto out_irq_auto0_free;
699                 }
700         }
701
702         if (adc_pdata->ch0_current_uA == 0)
703                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
704         else if (adc_pdata->ch0_current_uA <= 5)
705                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
706         else if (adc_pdata->ch0_current_uA <= 15)
707                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
708         else
709                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
710
711         if (adc_pdata->ch3_current_uA == 0)
712                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
713         else if (adc_pdata->ch3_current_uA <= 10)
714                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
715         else if (adc_pdata->ch3_current_uA <= 400)
716                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
717         else
718                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
719
720         /* If ch3_dual_current is true, it will measure ch3 input signal with
721          * ch3_current and the next current of ch3_current. */
722         adc->ch3_dual_current = adc_pdata->ch3_dual_current;
723         if (adc->ch3_dual_current &&
724                         (adc->ch3_current == PALMAS_ADC_CH3_CURRENT_SRC_800)) {
725                 dev_warn(adc->dev,
726                         "Disable ch3_dual_current by wrong current setting\n");
727                 adc->ch3_dual_current = false;
728         }
729
730         adc->extended_delay = adc_pdata->extended_delay;
731
732         iodev->name = MOD_NAME;
733         iodev->dev.parent = &pdev->dev;
734         iodev->info = &palmas_gpadc_iio_info;
735         iodev->modes = INDIO_DIRECT_MODE;
736         iodev->channels = palmas_gpadc_iio_channel;
737         iodev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
738
739         ret = iio_device_register(iodev);
740         if (ret < 0) {
741                 dev_err(adc->dev, "iio_device_register() failed: %d\n", ret);
742                 goto out_irq_auto1_free;
743         }
744
745         device_set_wakeup_capable(&pdev->dev, 1);
746         for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
747                 if (!(adc->adc_info[i].is_correct_code))
748                         palmas_gpadc_calibrate(adc, i);
749         }
750
751         if (adc->auto_conv1_enable || adc->auto_conv2_enable)
752                 device_wakeup_enable(&pdev->dev);
753
754         if (adc->auto_conv1_data.adc_shutdown ||
755                         adc->auto_conv2_data.adc_shutdown) {
756                 ret = palmas_gpadc_auto_conv_configure(adc);
757                 if (ret < 0) {
758                         dev_err(adc->dev,
759                                 "auto conversion configure failed: %d\n", ret);
760                         goto out_irq_auto1_free;
761                 }
762         }
763
764         return 0;
765
766 out_irq_auto1_free:
767         if (adc_pdata->adc_auto_conv2_data)
768                 free_irq(adc->irq_auto_1, adc);
769 out_irq_auto0_free:
770         if (adc_pdata->adc_auto_conv1_data)
771                 free_irq(adc->irq_auto_0, adc);
772 out_irq_free:
773         free_irq(adc->irq, adc);
774 out_unregister_map:
775         if (adc_pdata->iio_maps)
776                 iio_map_array_unregister(iodev, adc_pdata->iio_maps);
777 out:
778         iio_free_device(iodev);
779         return ret;
780 }
781
782 static int __devexit palmas_gpadc_remove(struct platform_device *pdev)
783 {
784         struct iio_dev *iodev = dev_get_drvdata(&pdev->dev);
785         struct palmas_gpadc *adc = iio_priv(iodev);
786         struct palmas_platform_data *pdata = dev_get_platdata(pdev->dev.parent);
787
788         if (pdata->adc_pdata->iio_maps)
789                 iio_map_array_unregister(iodev, pdata->adc_pdata->iio_maps);
790         iio_device_unregister(iodev);
791         free_irq(adc->irq, adc);
792         if (adc->auto_conv1_enable)
793                 free_irq(adc->irq_auto_0, adc);
794         if (adc->auto_conv2_enable)
795                 free_irq(adc->irq_auto_1, adc);
796         iio_free_device(iodev);
797         return 0;
798 }
799
800 #ifdef CONFIG_PM_SLEEP
801 static int palmas_gpadc_suspend(struct device *dev)
802 {
803         struct iio_dev *iodev = dev_get_drvdata(dev);
804         struct palmas_gpadc *adc = iio_priv(iodev);
805         int wakeup = adc->auto_conv1_enable || adc->auto_conv2_enable;
806         int ret;
807
808         if (!device_may_wakeup(dev) || !wakeup)
809                 return 0;
810
811         ret = palmas_gpadc_auto_conv_configure(adc);
812         if (ret < 0)
813                 return ret;
814
815         if (adc->auto_conv1_enable)
816                 enable_irq_wake(adc->irq_auto_0);
817
818         if (adc->auto_conv2_enable)
819                 enable_irq_wake(adc->irq_auto_1);
820
821         return 0;
822 }
823
824 static int palmas_gpadc_resume(struct device *dev)
825 {
826         struct iio_dev *iodev = dev_get_drvdata(dev);
827         struct palmas_gpadc *adc = iio_priv(iodev);
828         int wakeup = adc->auto_conv1_enable || adc->auto_conv2_enable;
829         int ret;
830
831         if (!device_may_wakeup(dev) || !wakeup)
832                 return 0;
833
834         ret = palmas_gpadc_auto_conv_reset(adc);
835         if (ret < 0)
836                 return ret;
837
838         if (adc->auto_conv1_enable)
839                 disable_irq_wake(adc->irq_auto_0);
840
841         if (adc->auto_conv2_enable)
842                 disable_irq_wake(adc->irq_auto_1);
843
844         return 0;
845 };
846 #endif
847
848 static const struct dev_pm_ops palmas_pm_ops = {
849         SET_SYSTEM_SLEEP_PM_OPS(palmas_gpadc_suspend,
850                                 palmas_gpadc_resume)
851 };
852
853 static struct platform_driver palmas_gpadc_driver = {
854         .probe = palmas_gpadc_probe,
855         .remove = __devexit_p(palmas_gpadc_remove),
856         .driver = {
857                 .name = MOD_NAME,
858                 .owner = THIS_MODULE,
859                 .pm = &palmas_pm_ops,
860         },
861 };
862
863 module_platform_driver(palmas_gpadc_driver);
864
865 MODULE_DESCRIPTION("palmas GPADC driver");
866 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>");
867 MODULE_ALIAS("platform:palmas-gpadc");
868 MODULE_LICENSE("GPL v2");