b4b3733aefcf74a976cf7c42aea04648fb1abd8a
[linux-2.6.git] / drivers / ssb / driver_chipcommon.c
1 /*
2  * Sonics Silicon Backplane
3  * Broadcom ChipCommon core driver
4  *
5  * Copyright 2005, Broadcom Corporation
6  * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7  *
8  * Licensed under the GNU/GPL. See COPYING for details.
9  */
10
11 #include <linux/ssb/ssb.h>
12 #include <linux/ssb/ssb_regs.h>
13 #include <linux/pci.h>
14
15 #include "ssb_private.h"
16
17
18 /* Clock sources */
19 enum ssb_clksrc {
20         /* PCI clock */
21         SSB_CHIPCO_CLKSRC_PCI,
22         /* Crystal slow clock oscillator */
23         SSB_CHIPCO_CLKSRC_XTALOS,
24         /* Low power oscillator */
25         SSB_CHIPCO_CLKSRC_LOPWROS,
26 };
27
28
29 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
30                                         u32 mask, u32 value)
31 {
32         value &= mask;
33         value |= chipco_read32(cc, offset) & ~mask;
34         chipco_write32(cc, offset, value);
35
36         return value;
37 }
38
39 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
40                               enum ssb_clkmode mode)
41 {
42         struct ssb_device *ccdev = cc->dev;
43         struct ssb_bus *bus;
44         u32 tmp;
45
46         if (!ccdev)
47                 return;
48         bus = ccdev->bus;
49         /* chipcommon cores prior to rev6 don't support dynamic clock control */
50         if (ccdev->id.revision < 6)
51                 return;
52         /* chipcommon cores rev10 are a whole new ball game */
53         if (ccdev->id.revision >= 10)
54                 return;
55         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
56                 return;
57
58         switch (mode) {
59         case SSB_CLKMODE_SLOW:
60                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
61                 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
62                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
63                 break;
64         case SSB_CLKMODE_FAST:
65                 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
66                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
67                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
68                 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
69                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
70                 break;
71         case SSB_CLKMODE_DYNAMIC:
72                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
73                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
74                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
75                 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
76                 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
77                         tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
78                 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
79
80                 /* for dynamic control, we have to release our xtal_pu "force on" */
81                 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
82                         ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
83                 break;
84         default:
85                 SSB_WARN_ON(1);
86         }
87 }
88
89 /* Get the Slow Clock Source */
90 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
91 {
92         struct ssb_bus *bus = cc->dev->bus;
93         u32 uninitialized_var(tmp);
94
95         if (cc->dev->id.revision < 6) {
96                 if (bus->bustype == SSB_BUSTYPE_SSB ||
97                     bus->bustype == SSB_BUSTYPE_PCMCIA)
98                         return SSB_CHIPCO_CLKSRC_XTALOS;
99                 if (bus->bustype == SSB_BUSTYPE_PCI) {
100                         pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
101                         if (tmp & 0x10)
102                                 return SSB_CHIPCO_CLKSRC_PCI;
103                         return SSB_CHIPCO_CLKSRC_XTALOS;
104                 }
105         }
106         if (cc->dev->id.revision < 10) {
107                 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
108                 tmp &= 0x7;
109                 if (tmp == 0)
110                         return SSB_CHIPCO_CLKSRC_LOPWROS;
111                 if (tmp == 1)
112                         return SSB_CHIPCO_CLKSRC_XTALOS;
113                 if (tmp == 2)
114                         return SSB_CHIPCO_CLKSRC_PCI;
115         }
116
117         return SSB_CHIPCO_CLKSRC_XTALOS;
118 }
119
120 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
121 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
122 {
123         int uninitialized_var(limit);
124         enum ssb_clksrc clocksrc;
125         int divisor = 1;
126         u32 tmp;
127
128         clocksrc = chipco_pctl_get_slowclksrc(cc);
129         if (cc->dev->id.revision < 6) {
130                 switch (clocksrc) {
131                 case SSB_CHIPCO_CLKSRC_PCI:
132                         divisor = 64;
133                         break;
134                 case SSB_CHIPCO_CLKSRC_XTALOS:
135                         divisor = 32;
136                         break;
137                 default:
138                         SSB_WARN_ON(1);
139                 }
140         } else if (cc->dev->id.revision < 10) {
141                 switch (clocksrc) {
142                 case SSB_CHIPCO_CLKSRC_LOPWROS:
143                         break;
144                 case SSB_CHIPCO_CLKSRC_XTALOS:
145                 case SSB_CHIPCO_CLKSRC_PCI:
146                         tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
147                         divisor = (tmp >> 16) + 1;
148                         divisor *= 4;
149                         break;
150                 }
151         } else {
152                 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
153                 divisor = (tmp >> 16) + 1;
154                 divisor *= 4;
155         }
156
157         switch (clocksrc) {
158         case SSB_CHIPCO_CLKSRC_LOPWROS:
159                 if (get_max)
160                         limit = 43000;
161                 else
162                         limit = 25000;
163                 break;
164         case SSB_CHIPCO_CLKSRC_XTALOS:
165                 if (get_max)
166                         limit = 20200000;
167                 else
168                         limit = 19800000;
169                 break;
170         case SSB_CHIPCO_CLKSRC_PCI:
171                 if (get_max)
172                         limit = 34000000;
173                 else
174                         limit = 25000000;
175                 break;
176         }
177         limit /= divisor;
178
179         return limit;
180 }
181
182 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
183 {
184         struct ssb_bus *bus = cc->dev->bus;
185
186         if (bus->chip_id == 0x4321) {
187                 if (bus->chip_rev == 0)
188                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
189                 else if (bus->chip_rev == 1)
190                         chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
191         }
192
193         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
194                 return;
195
196         if (cc->dev->id.revision >= 10) {
197                 /* Set Idle Power clock rate to 1Mhz */
198                 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
199                                (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
200                                 0x0000FFFF) | 0x00040000);
201         } else {
202                 int maxfreq;
203
204                 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
205                 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
206                                (maxfreq * 150 + 999999) / 1000000);
207                 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
208                                (maxfreq * 15 + 999999) / 1000000);
209         }
210 }
211
212 /* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
213 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
214 {
215         struct ssb_bus *bus = cc->dev->bus;
216
217         switch (bus->chip_id) {
218         case 0x4312:
219         case 0x4322:
220         case 0x4328:
221                 return 7000;
222         case 0x4325:
223                 /* TODO: */
224         default:
225                 return 15000;
226         }
227 }
228
229 /* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
230 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
231 {
232         struct ssb_bus *bus = cc->dev->bus;
233         int minfreq;
234         unsigned int tmp;
235         u32 pll_on_delay;
236
237         if (bus->bustype != SSB_BUSTYPE_PCI)
238                 return;
239
240         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
241                 cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
242                 return;
243         }
244
245         if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
246                 return;
247
248         minfreq = chipco_pctl_clockfreqlimit(cc, 0);
249         pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
250         tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
251         SSB_WARN_ON(tmp & ~0xFFFF);
252
253         cc->fast_pwrup_delay = tmp;
254 }
255
256 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
257 {
258         if (!cc->dev)
259                 return; /* We don't have a ChipCommon */
260         if (cc->dev->id.revision >= 11)
261                 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
262         ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
263
264         if (cc->dev->id.revision >= 20) {
265                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
266                 chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
267         }
268
269         ssb_pmu_init(cc);
270         chipco_powercontrol_init(cc);
271         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
272         calc_fast_powerup_delay(cc);
273 }
274
275 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
276 {
277         if (!cc->dev)
278                 return;
279         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
280 }
281
282 void ssb_chipco_resume(struct ssb_chipcommon *cc)
283 {
284         if (!cc->dev)
285                 return;
286         chipco_powercontrol_init(cc);
287         ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
288 }
289
290 /* Get the processor clock */
291 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
292                              u32 *plltype, u32 *n, u32 *m)
293 {
294         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
295         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
296         switch (*plltype) {
297         case SSB_PLLTYPE_2:
298         case SSB_PLLTYPE_4:
299         case SSB_PLLTYPE_6:
300         case SSB_PLLTYPE_7:
301                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
302                 break;
303         case SSB_PLLTYPE_3:
304                 /* 5350 uses m2 to control mips */
305                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
306                 break;
307         default:
308                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
309                 break;
310         }
311 }
312
313 /* Get the bus clock */
314 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
315                                  u32 *plltype, u32 *n, u32 *m)
316 {
317         *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
318         *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
319         switch (*plltype) {
320         case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
321                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
322                 break;
323         case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
324                 if (cc->dev->bus->chip_id != 0x5365) {
325                         *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
326                         break;
327                 }
328                 /* Fallthough */
329         default:
330                 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
331         }
332 }
333
334 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
335                             unsigned long ns)
336 {
337         struct ssb_device *dev = cc->dev;
338         struct ssb_bus *bus = dev->bus;
339         u32 tmp;
340
341         /* set register for external IO to control LED. */
342         chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
343         tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;            /* Waitcount-3 = 10ns */
344         tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;   /* Waitcount-1 = 40ns */
345         tmp |= DIV_ROUND_UP(240, ns);                           /* Waitcount-0 = 240ns */
346         chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp);       /* 0x01020a0c for a 100Mhz clock */
347
348         /* Set timing for the flash */
349         tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT;   /* Waitcount-3 = 10nS */
350         tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT;  /* Waitcount-1 = 10nS */
351         tmp |= DIV_ROUND_UP(120, ns);                           /* Waitcount-0 = 120nS */
352         if ((bus->chip_id == 0x5365) ||
353             (dev->id.revision < 9))
354                 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
355         if ((bus->chip_id == 0x5365) ||
356             (dev->id.revision < 9) ||
357             ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
358                 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
359
360         if (bus->chip_id == 0x5350) {
361                 /* Enable EXTIF */
362                 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;      /* Waitcount-3 = 10ns */
363                 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;  /* Waitcount-2 = 20ns */
364                 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
365                 tmp |= DIV_ROUND_UP(120, ns);                     /* Waitcount-0 = 120ns */
366                 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
367         }
368 }
369
370 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
371 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
372 {
373         /* instant NMI */
374         chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
375 }
376
377 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
378 {
379         chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
380 }
381
382 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
383 {
384         return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
385 }
386
387 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
388 {
389         return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
390 }
391
392 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
393 {
394         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
395 }
396
397 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
398 {
399         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
400 }
401
402 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
403 {
404         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
405 }
406 EXPORT_SYMBOL(ssb_chipco_gpio_control);
407
408 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
409 {
410         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
411 }
412
413 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
414 {
415         return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
416 }
417
418 #ifdef CONFIG_SSB_SERIAL
419 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
420                            struct ssb_serial_port *ports)
421 {
422         struct ssb_bus *bus = cc->dev->bus;
423         int nr_ports = 0;
424         u32 plltype;
425         unsigned int irq;
426         u32 baud_base, div;
427         u32 i, n;
428         unsigned int ccrev = cc->dev->id.revision;
429
430         plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
431         irq = ssb_mips_irq(cc->dev);
432
433         if (plltype == SSB_PLLTYPE_1) {
434                 /* PLL clock */
435                 baud_base = ssb_calc_clock_rate(plltype,
436                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
437                                                 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
438                 div = 1;
439         } else {
440                 if (ccrev == 20) {
441                         /* BCM5354 uses constant 25MHz clock */
442                         baud_base = 25000000;
443                         div = 48;
444                         /* Set the override bit so we don't divide it */
445                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
446                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
447                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
448                 } else if ((ccrev >= 11) && (ccrev != 15)) {
449                         /* Fixed ALP clock */
450                         baud_base = 20000000;
451                         if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
452                                 /* FIXME: baud_base is different for devices with a PMU */
453                                 SSB_WARN_ON(1);
454                         }
455                         div = 1;
456                         if (ccrev >= 21) {
457                                 /* Turn off UART clock before switching clocksource. */
458                                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
459                                                chipco_read32(cc, SSB_CHIPCO_CORECTL)
460                                                & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
461                         }
462                         /* Set the override bit so we don't divide it */
463                         chipco_write32(cc, SSB_CHIPCO_CORECTL,
464                                        chipco_read32(cc, SSB_CHIPCO_CORECTL)
465                                        | SSB_CHIPCO_CORECTL_UARTCLK0);
466                         if (ccrev >= 21) {
467                                 /* Re-enable the UART clock. */
468                                 chipco_write32(cc, SSB_CHIPCO_CORECTL,
469                                                chipco_read32(cc, SSB_CHIPCO_CORECTL)
470                                                | SSB_CHIPCO_CORECTL_UARTCLKEN);
471                         }
472                 } else if (ccrev >= 3) {
473                         /* Internal backplane clock */
474                         baud_base = ssb_clockspeed(bus);
475                         div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
476                               & SSB_CHIPCO_CLKDIV_UART;
477                 } else {
478                         /* Fixed internal backplane clock */
479                         baud_base = 88000000;
480                         div = 48;
481                 }
482
483                 /* Clock source depends on strapping if UartClkOverride is unset */
484                 if ((ccrev > 0) &&
485                     !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
486                         if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
487                             SSB_CHIPCO_CAP_UARTCLK_INT) {
488                                 /* Internal divided backplane clock */
489                                 baud_base /= div;
490                         } else {
491                                 /* Assume external clock of 1.8432 MHz */
492                                 baud_base = 1843200;
493                         }
494                 }
495         }
496
497         /* Determine the registers of the UARTs */
498         n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
499         for (i = 0; i < n; i++) {
500                 void __iomem *cc_mmio;
501                 void __iomem *uart_regs;
502
503                 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
504                 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
505                 /* Offset changed at after rev 0 */
506                 if (ccrev == 0)
507                         uart_regs += (i * 8);
508                 else
509                         uart_regs += (i * 256);
510
511                 nr_ports++;
512                 ports[i].regs = uart_regs;
513                 ports[i].irq = irq;
514                 ports[i].baud_base = baud_base;
515                 ports[i].reg_shift = 0;
516         }
517
518         return nr_ports;
519 }
520 #endif /* CONFIG_SSB_SERIAL */