2 * Driver for Nvidia TEGRA spi controller in slave mode.
4 * Copyright (c) 2011, NVIDIA Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 /*#define VERBOSE_DEBUG 1*/
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/err.h>
27 #include <linux/platform_device.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmapool.h>
31 #include <linux/clk.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/completion.h>
36 #include <linux/spi/spi.h>
37 #include <linux/spi-tegra.h>
43 #define SLINK_COMMAND 0x000
44 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
45 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
46 #define SLINK_BOTH_EN (1 << 10)
47 #define SLINK_CS_SW (1 << 11)
48 #define SLINK_CS_VALUE (1 << 12)
49 #define SLINK_CS_POLARITY (1 << 13)
50 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
51 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
52 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
53 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
54 #define SLINK_IDLE_SDA_MASK (3 << 16)
55 #define SLINK_CS_POLARITY1 (1 << 20)
56 #define SLINK_CK_SDA (1 << 21)
57 #define SLINK_CS_POLARITY2 (1 << 22)
58 #define SLINK_CS_POLARITY3 (1 << 23)
59 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
60 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
61 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
62 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
63 #define SLINK_IDLE_SCLK_MASK (3 << 24)
64 #define SLINK_M_S (1 << 28)
65 #define SLINK_WAIT (1 << 29)
66 #define SLINK_GO (1 << 30)
67 #define SLINK_ENB (1 << 31)
69 #define SLINK_COMMAND2 0x004
70 #define SLINK_LSBFE (1 << 0)
71 #define SLINK_SSOE (1 << 1)
72 #define SLINK_SPIE (1 << 4)
73 #define SLINK_BIDIROE (1 << 6)
74 #define SLINK_MODFEN (1 << 7)
75 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
76 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
77 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
78 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
79 #define SLINK_FIFO_REFILLS_0 (0 << 22)
80 #define SLINK_FIFO_REFILLS_1 (1 << 22)
81 #define SLINK_FIFO_REFILLS_2 (2 << 22)
82 #define SLINK_FIFO_REFILLS_3 (3 << 22)
83 #define SLINK_FIFO_REFILLS_MASK (3 << 22)
84 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
85 #define SLINK_SPC0 (1 << 29)
86 #define SLINK_TXEN (1 << 30)
87 #define SLINK_RXEN (1 << 31)
89 #define SLINK_STATUS 0x008
90 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
91 #define SLINK_WORD(val) (((val) >> 5) & 0x1f)
92 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
93 #define SLINK_MODF (1 << 16)
94 #define SLINK_RX_UNF (1 << 18)
95 #define SLINK_TX_OVF (1 << 19)
96 #define SLINK_TX_FULL (1 << 20)
97 #define SLINK_TX_EMPTY (1 << 21)
98 #define SLINK_RX_FULL (1 << 22)
99 #define SLINK_RX_EMPTY (1 << 23)
100 #define SLINK_TX_UNF (1 << 24)
101 #define SLINK_RX_OVF (1 << 25)
102 #define SLINK_TX_FLUSH (1 << 26)
103 #define SLINK_RX_FLUSH (1 << 27)
104 #define SLINK_SCLK (1 << 28)
105 #define SLINK_ERR (1 << 29)
106 #define SLINK_RDY (1 << 30)
107 #define SLINK_BSY (1 << 31)
109 #define SLINK_MAS_DATA 0x010
110 #define SLINK_SLAVE_DATA 0x014
112 #define SLINK_DMA_CTL 0x018
113 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
114 #define SLINK_TX_TRIG_1 (0 << 16)
115 #define SLINK_TX_TRIG_4 (1 << 16)
116 #define SLINK_TX_TRIG_8 (2 << 16)
117 #define SLINK_TX_TRIG_16 (3 << 16)
118 #define SLINK_TX_TRIG_MASK (3 << 16)
119 #define SLINK_RX_TRIG_1 (0 << 18)
120 #define SLINK_RX_TRIG_4 (1 << 18)
121 #define SLINK_RX_TRIG_8 (2 << 18)
122 #define SLINK_RX_TRIG_16 (3 << 18)
123 #define SLINK_RX_TRIG_MASK (3 << 18)
124 #define SLINK_PACKED (1 << 20)
125 #define SLINK_PACK_SIZE_4 (0 << 21)
126 #define SLINK_PACK_SIZE_8 (1 << 21)
127 #define SLINK_PACK_SIZE_16 (2 << 21)
128 #define SLINK_PACK_SIZE_32 (3 << 21)
129 #define SLINK_PACK_SIZE_MASK (3 << 21)
130 #define SLINK_IE_TXC (1 << 26)
131 #define SLINK_IE_RXC (1 << 27)
132 #define SLINK_DMA_EN (1 << 31)
134 #define SLINK_STATUS2 0x01c
135 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
136 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
137 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
139 #define SLINK_TX_FIFO 0x100
140 #define SLINK_RX_FIFO 0x180
142 #define DATA_DIR_TX (1 << 0)
143 #define DATA_DIR_RX (1 << 1)
145 #define SPI_FIFO_DEPTH 32
146 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
149 static const unsigned long spi_tegra_req_sels[] = {
150 TEGRA_DMA_REQ_SEL_SL2B1,
151 TEGRA_DMA_REQ_SEL_SL2B2,
152 TEGRA_DMA_REQ_SEL_SL2B3,
153 TEGRA_DMA_REQ_SEL_SL2B4,
154 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
155 TEGRA_DMA_REQ_SEL_SL2B5,
156 TEGRA_DMA_REQ_SEL_SL2B6,
161 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
162 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
163 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
165 #define SLINK_STATUS2_RESET \
166 (TX_FIFO_EMPTY_COUNT_MAX | \
167 RX_FIFO_FULL_COUNT_ZERO << 16)
169 #define MAX_CHIP_SELECT 4
170 #define SLINK_FIFO_DEPTH 4
172 struct spi_tegra_data {
173 struct spi_master *master;
174 struct platform_device *pdev;
185 struct list_head queue;
186 struct spi_transfer *cur;
187 struct spi_device *cur_spi;
190 unsigned words_per_32bit;
191 unsigned bytes_per_word;
192 unsigned curr_dma_words;
194 unsigned cur_direction;
198 struct tegra_dma_req rx_dma_req;
199 struct tegra_dma_channel *rx_dma;
201 dma_addr_t rx_buf_phys;
204 struct tegra_dma_req tx_dma_req;
205 struct tegra_dma_channel *tx_dma;
207 dma_addr_t tx_buf_phys;
210 unsigned dma_buf_size;
211 unsigned max_buf_size;
212 bool is_curr_dma_xfer;
214 bool is_clkon_always;
220 struct completion rx_dma_complete;
221 struct completion tx_dma_complete;
229 unsigned long packed_size;
235 u32 def_command2_reg;
237 callback client_slave_ready_cb;
241 static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
244 if (!tspi->clk_state)
246 return readl(tspi->base + reg);
249 static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
250 unsigned long val, unsigned long reg)
252 if (!tspi->clk_state)
254 writel(val, tspi->base + reg);
257 int spi_tegra_register_callback(struct spi_device *spi, callback func,
260 struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
264 tspi->client_slave_ready_cb = func;
265 tspi->client_data = client_data;
268 EXPORT_SYMBOL(spi_tegra_register_callback);
270 static void spi_tegra_clear_status(struct spi_tegra_data *tspi)
273 unsigned long val_write = 0;
275 val = spi_tegra_readl(tspi, SLINK_STATUS);
277 val_write = SLINK_RDY;
278 if (val & SLINK_TX_OVF)
279 val_write |= SLINK_TX_OVF;
280 if (val & SLINK_RX_OVF)
281 val_write |= SLINK_RX_OVF;
282 if (val & SLINK_RX_UNF)
283 val_write |= SLINK_RX_UNF;
284 if (val & SLINK_TX_UNF)
285 val_write |= SLINK_TX_UNF;
287 spi_tegra_writel(tspi, val_write, SLINK_STATUS);
290 static unsigned long spi_tegra_get_packed_size(struct spi_tegra_data *tspi,
291 struct spi_transfer *t)
295 switch (tspi->bytes_per_word) {
297 val = SLINK_PACK_SIZE_4;
300 val = SLINK_PACK_SIZE_8;
303 val = SLINK_PACK_SIZE_16;
306 val = SLINK_PACK_SIZE_32;
314 static unsigned spi_tegra_calculate_curr_xfer_param(
315 struct spi_device *spi, struct spi_tegra_data *tspi,
316 struct spi_transfer *t)
318 unsigned remain_len = t->len - tspi->cur_pos;
320 unsigned bits_per_word ;
322 unsigned total_fifo_words;
324 bits_per_word = t->bits_per_word ? t->bits_per_word :
326 tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1;
328 if (bits_per_word == 8 || bits_per_word == 16) {
330 tspi->words_per_32bit = 32/bits_per_word;
333 tspi->words_per_32bit = 1;
335 tspi->packed_size = spi_tegra_get_packed_size(tspi, t);
337 if (tspi->is_packed) {
338 max_len = min(remain_len, tspi->max_buf_size);
339 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
340 total_fifo_words = remain_len/4;
342 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
343 max_word = min(max_word, tspi->max_buf_size/4);
344 tspi->curr_dma_words = max_word;
345 total_fifo_words = remain_len/tspi->bytes_per_word;
347 /* All transfer should be in one shot */
348 if (tspi->curr_dma_words * tspi->bytes_per_word != t->len) {
349 dev_err(&tspi->pdev->dev, "The requested length can not be"
350 " transferred in one shot\n");
353 return total_fifo_words;
356 static unsigned spi_tegra_fill_tx_fifo_from_client_txbuf(
357 struct spi_tegra_data *tspi, struct spi_transfer *t)
360 unsigned tx_empty_count;
361 unsigned long fifo_status;
362 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
363 unsigned max_n_32bit;
366 unsigned int written_words;
368 fifo_status = spi_tegra_readl(tspi, SLINK_STATUS2);
369 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
371 if (tspi->is_packed) {
372 nbytes = tspi->curr_dma_words * tspi->bytes_per_word;
373 max_n_32bit = (min(nbytes, tx_empty_count*4) - 1)/4 + 1;
374 for (count = 0; count < max_n_32bit; ++count) {
376 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
377 x |= (*tx_buf++) << (i*8);
378 spi_tegra_writel(tspi, x, SLINK_TX_FIFO);
380 written_words = min(max_n_32bit * tspi->words_per_32bit,
381 tspi->curr_dma_words);
383 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
384 nbytes = max_n_32bit * tspi->bytes_per_word;
385 for (count = 0; count < max_n_32bit; ++count) {
387 for (i = 0; nbytes && (i < tspi->bytes_per_word);
389 x |= ((*tx_buf++) << i*8);
390 spi_tegra_writel(tspi, x, SLINK_TX_FIFO);
392 written_words = max_n_32bit;
394 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
395 return written_words;
398 static unsigned int spi_tegra_read_rx_fifo_to_client_rxbuf(
399 struct spi_tegra_data *tspi, struct spi_transfer *t)
401 unsigned rx_full_count;
402 unsigned long fifo_status;
403 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
406 unsigned int read_words;
409 fifo_status = spi_tegra_readl(tspi, SLINK_STATUS2);
410 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
411 dev_dbg(&tspi->pdev->dev, "Rx fifo count %d\n", rx_full_count);
412 if (tspi->is_packed) {
413 len = tspi->curr_dma_words * tspi->bytes_per_word;
414 for (count = 0; count < rx_full_count; ++count) {
415 x = spi_tegra_readl(tspi, SLINK_RX_FIFO);
416 for (i = 0; len && (i < 4); ++i, len--)
417 *rx_buf++ = (x >> i*8) & 0xFF;
419 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
420 read_words += tspi->curr_dma_words;
422 for (count = 0; count < rx_full_count; ++count) {
423 x = spi_tegra_readl(tspi, SLINK_RX_FIFO);
424 for (i = 0; (i < tspi->bytes_per_word); ++i)
425 *rx_buf++ = (x >> (i*8)) & 0xFF;
427 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
428 read_words += rx_full_count;
433 static void spi_tegra_copy_client_txbuf_to_spi_txbuf(
434 struct spi_tegra_data *tspi, struct spi_transfer *t)
437 if (tspi->is_packed) {
438 len = tspi->curr_dma_words * tspi->bytes_per_word;
439 memcpy(tspi->tx_buf, t->tx_buf + tspi->cur_pos, len);
443 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
444 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
447 for (count = 0; count < tspi->curr_dma_words; ++count) {
449 for (i = 0; consume && (i < tspi->bytes_per_word);
451 x |= ((*tx_buf++) << i*8);
452 tspi->tx_buf[count] = x;
455 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
458 static void spi_tegra_copy_spi_rxbuf_to_client_rxbuf(
459 struct spi_tegra_data *tspi, struct spi_transfer *t)
462 if (tspi->is_packed) {
463 len = tspi->curr_dma_words * tspi->bytes_per_word;
464 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_buf, len);
468 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
470 for (count = 0; count < tspi->curr_dma_words; ++count) {
471 x = tspi->rx_buf[count];
472 for (i = 0; (i < tspi->bytes_per_word); ++i)
473 *rx_buf++ = (x >> (i*8)) & 0xFF;
476 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
479 static int spi_tegra_start_dma_based_transfer(
480 struct spi_tegra_data *tspi, struct spi_transfer *t)
483 unsigned long test_val;
487 INIT_COMPLETION(tspi->rx_dma_complete);
488 INIT_COMPLETION(tspi->tx_dma_complete);
490 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
491 val |= tspi->packed_size;
493 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
496 len = tspi->curr_dma_words * 4;
499 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
500 else if (((len) >> 4) & 0x1)
501 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
503 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
505 if (tspi->cur_direction & DATA_DIR_TX)
508 if (tspi->cur_direction & DATA_DIR_RX)
511 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
512 tspi->dma_control_reg = val;
514 if (tspi->cur_direction & DATA_DIR_TX) {
515 spi_tegra_copy_client_txbuf_to_spi_txbuf(tspi, t);
517 tspi->tx_dma_req.size = len;
518 ret = tegra_dma_enqueue_req(tspi->tx_dma, &tspi->tx_dma_req);
520 dev_err(&tspi->pdev->dev, "Error in starting tx dma "
521 " error = %d\n", ret);
525 /* Wait for tx fifo to be fill before starting slink */
526 test_val = spi_tegra_readl(tspi, SLINK_STATUS);
527 while (!(test_val & SLINK_TX_FULL))
528 test_val = spi_tegra_readl(tspi, SLINK_STATUS);
531 if (tspi->cur_direction & DATA_DIR_RX) {
532 tspi->rx_dma_req.size = len;
533 ret = tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
535 dev_err(&tspi->pdev->dev, "Error in starting rx dma "
536 " error = %d\n", ret);
537 if (tspi->cur_direction & DATA_DIR_TX)
538 tegra_dma_dequeue_req(tspi->tx_dma,
543 tspi->is_curr_dma_xfer = true;
544 if (tspi->is_packed) {
546 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
552 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
556 static int spi_tegra_start_cpu_based_transfer(
557 struct spi_tegra_data *tspi, struct spi_transfer *t)
562 val = tspi->packed_size;
563 if (tspi->cur_direction & DATA_DIR_TX)
566 if (tspi->cur_direction & DATA_DIR_RX)
569 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
570 tspi->dma_control_reg = val;
572 if (tspi->cur_direction & DATA_DIR_TX)
573 curr_words = spi_tegra_fill_tx_fifo_from_client_txbuf(tspi, t);
575 curr_words = tspi->curr_dma_words;
576 val |= SLINK_DMA_BLOCK_SIZE(curr_words - 1);
577 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
578 tspi->dma_control_reg = val;
580 tspi->is_curr_dma_xfer = false;
581 if (tspi->is_packed) {
583 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
588 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
592 static void spi_tegra_start_transfer(struct spi_device *spi,
593 struct spi_transfer *t)
595 struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
598 unsigned total_fifo_words;
600 unsigned long command;
601 unsigned long command2;
603 unsigned int cs_pol_bit[] = {
610 bits_per_word = t->bits_per_word ? t->bits_per_word :
613 speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
614 if (speed != tspi->cur_speed) {
615 clk_set_rate(tspi->clk, speed * 4);
616 tspi->cur_speed = speed;
622 tspi->cur_rx_pos = 0;
623 tspi->cur_tx_pos = 0;
624 tspi->rx_complete = 0;
625 tspi->tx_complete = 0;
626 total_fifo_words = spi_tegra_calculate_curr_xfer_param(spi, tspi, t);
628 command2 = tspi->def_command2_reg;
629 if (!tspi->is_clkon_always) {
630 if (!tspi->clk_state) {
631 clk_enable(tspi->clk);
636 spi_tegra_clear_status(tspi);
638 command = tspi->def_command_reg;
639 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
641 command |= SLINK_CS_SW;
642 command ^= cs_pol_bit[spi->chip_select];
644 command &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA;
645 if (spi->mode & SPI_CPHA)
646 command |= SLINK_CK_SDA;
648 if (spi->mode & SPI_CPOL)
649 command |= SLINK_IDLE_SCLK_DRIVE_HIGH;
651 command |= SLINK_IDLE_SCLK_DRIVE_LOW;
653 spi_tegra_writel(tspi, command, SLINK_COMMAND);
654 tspi->command_reg = command;
656 dev_dbg(&tspi->pdev->dev, "The def 0x%x and written 0x%lx\n",
657 tspi->def_command_reg, command);
659 command2 &= ~(SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN);
660 tspi->cur_direction = 0;
662 command2 |= SLINK_RXEN;
663 tspi->cur_direction |= DATA_DIR_RX;
666 command2 |= SLINK_TXEN;
667 tspi->cur_direction |= DATA_DIR_TX;
669 command2 |= SLINK_SS_EN_CS(spi->chip_select);
670 spi_tegra_writel(tspi, command2, SLINK_COMMAND2);
671 tspi->command2_reg = command2;
673 if (total_fifo_words > SPI_FIFO_DEPTH)
674 ret = spi_tegra_start_dma_based_transfer(tspi, t);
676 ret = spi_tegra_start_cpu_based_transfer(tspi, t);
679 if (tspi->client_slave_ready_cb)
680 tspi->client_slave_ready_cb(tspi->client_data);
683 static void spi_tegra_start_message(struct spi_device *spi,
684 struct spi_message *m)
686 struct spi_transfer *t;
687 m->actual_length = 0;
689 t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
690 spi_tegra_start_transfer(spi, t);
693 static int spi_tegra_setup(struct spi_device *spi)
695 struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
696 unsigned long cs_bit;
700 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
702 spi->mode & SPI_CPOL ? "" : "~",
703 spi->mode & SPI_CPHA ? "" : "~",
706 BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
707 switch (spi->chip_select) {
709 cs_bit = SLINK_CS_POLARITY;
713 cs_bit = SLINK_CS_POLARITY1;
717 cs_bit = SLINK_CS_POLARITY2;
721 cs_bit = SLINK_CS_POLARITY3;
728 spin_lock_irqsave(&tspi->lock, flags);
729 val = tspi->def_command_reg;
730 if (spi->mode & SPI_CS_HIGH)
734 tspi->def_command_reg |= val;
736 if (!tspi->is_clkon_always && !tspi->clk_state) {
737 clk_enable(tspi->clk);
740 spi_tegra_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
741 if (!tspi->is_clkon_always && tspi->clk_state) {
742 clk_disable(tspi->clk);
746 spin_unlock_irqrestore(&tspi->lock, flags);
750 static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m)
752 struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
753 struct spi_transfer *t;
760 /* Support only one transfer per message */
761 if (!list_is_singular(&m->transfers))
764 if (list_empty(&m->transfers) || !m->complete)
767 t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
768 if (t->bits_per_word < 0 || t->bits_per_word > 32)
774 bits_per_word = (t->bits_per_word) ? : spi->bits_per_word;
776 /* Check that the all words are available */
777 bytes_per_word = (bits_per_word + 7)/8;
779 if (t->len % bytes_per_word != 0)
782 if (!t->rx_buf && !t->tx_buf)
785 if ((bits_per_word == 8) || (bits_per_word == 16))
786 fifo_word = t->len/4;
788 fifo_word = t->len/bytes_per_word;
789 if (fifo_word >= tspi->max_buf_size/4)
792 spin_lock_irqsave(&tspi->lock, flags);
794 if (WARN_ON(tspi->is_suspended)) {
795 spin_unlock_irqrestore(&tspi->lock, flags);
801 was_empty = list_empty(&tspi->queue);
802 list_add_tail(&m->queue, &tspi->queue);
805 spi_tegra_start_message(spi, m);
807 spin_unlock_irqrestore(&tspi->lock, flags);
812 static void spi_tegra_curr_transfer_complete(struct spi_tegra_data *tspi,
813 unsigned err, unsigned cur_xfer_size)
815 struct spi_message *m;
816 struct spi_device *spi;
818 m = list_first_entry(&tspi->queue, struct spi_message, queue);
823 m->actual_length += cur_xfer_size;
825 m->complete(m->context);
826 if (!list_empty(&tspi->queue)) {
827 m = list_first_entry(&tspi->queue, struct spi_message, queue);
829 spi_tegra_start_message(spi, m);
831 spi_tegra_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
832 spi_tegra_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
833 if (!tspi->is_clkon_always) {
834 if (tspi->clk_state) {
835 /* Provide delay to stablize the signal
838 clk_disable(tspi->clk);
845 static void tegra_spi_tx_dma_complete(struct tegra_dma_req *req)
847 struct spi_tegra_data *tspi = req->dev;
848 complete(&tspi->tx_dma_complete);
851 static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
853 struct spi_tegra_data *tspi = req->dev;
854 complete(&tspi->rx_dma_complete);
857 static void handle_cpu_based_xfer(void *context_data)
859 struct spi_tegra_data *tspi = context_data;
860 struct spi_transfer *t = tspi->cur;
863 spin_lock_irqsave(&tspi->lock, flags);
864 if (tspi->tx_status || tspi->rx_status ||
865 (tspi->status_reg & SLINK_BSY)) {
866 dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n",
867 __func__, tspi->status_reg);
868 tegra_periph_reset_assert(tspi->clk);
870 tegra_periph_reset_deassert(tspi->clk);
872 spi_tegra_curr_transfer_complete(tspi,
873 tspi->tx_status || tspi->rx_status, t->len);
877 dev_vdbg(&tspi->pdev->dev, " Current direction %x\n",
878 tspi->cur_direction);
879 if (tspi->cur_direction & DATA_DIR_RX)
880 spi_tegra_read_rx_fifo_to_client_rxbuf(tspi, t);
882 if (tspi->cur_direction & DATA_DIR_TX)
883 tspi->cur_pos = tspi->cur_tx_pos;
884 else if (tspi->cur_direction & DATA_DIR_RX)
885 tspi->cur_pos = tspi->cur_rx_pos;
889 dev_vdbg(&tspi->pdev->dev, "current position %d and length of the "
890 "transfer %d\n", tspi->cur_pos, t->len);
891 if (tspi->cur_pos == t->len) {
892 spi_tegra_curr_transfer_complete(tspi,
893 tspi->tx_status || tspi->rx_status, t->len);
897 /* There should not be remaining transfer */
900 spin_unlock_irqrestore(&tspi->lock, flags);
904 static irqreturn_t spi_tegra_isr_thread(int irq, void *context_data)
906 struct spi_tegra_data *tspi = context_data;
907 struct spi_transfer *t = tspi->cur;
912 if (!tspi->is_curr_dma_xfer) {
913 handle_cpu_based_xfer(context_data);
917 /* Abort dmas if any error */
918 if (tspi->cur_direction & DATA_DIR_TX) {
919 if (tspi->tx_status) {
920 tegra_dma_dequeue(tspi->tx_dma);
923 wait_status = wait_for_completion_interruptible_timeout(
924 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
925 if (wait_status <= 0) {
926 tegra_dma_dequeue(tspi->tx_dma);
927 dev_err(&tspi->pdev->dev, "Error in Dma Tx "
934 if (tspi->cur_direction & DATA_DIR_RX) {
935 if (tspi->rx_status) {
936 tegra_dma_dequeue(tspi->rx_dma);
939 wait_status = wait_for_completion_interruptible_timeout(
940 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
941 if (wait_status <= 0) {
942 tegra_dma_dequeue(tspi->rx_dma);
943 dev_err(&tspi->pdev->dev, "Error in Dma Rx "
950 spin_lock_irqsave(&tspi->lock, flags);
952 dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n",
953 __func__, tspi->status_reg);
954 tegra_periph_reset_assert(tspi->clk);
956 tegra_periph_reset_deassert(tspi->clk);
958 spi_tegra_curr_transfer_complete(tspi, err, t->len);
959 spin_unlock_irqrestore(&tspi->lock, flags);
963 if (tspi->cur_direction & DATA_DIR_RX)
964 spi_tegra_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
966 if (tspi->cur_direction & DATA_DIR_TX)
967 tspi->cur_pos = tspi->cur_tx_pos;
968 else if (tspi->cur_direction & DATA_DIR_RX)
969 tspi->cur_pos = tspi->cur_rx_pos;
973 if (tspi->cur_pos == t->len) {
974 spi_tegra_curr_transfer_complete(tspi,
975 tspi->tx_status || tspi->rx_status, t->len);
976 spin_unlock_irqrestore(&tspi->lock, flags);
980 spin_unlock_irqrestore(&tspi->lock, flags);
982 /* There should not be remaining transfer */
987 static irqreturn_t spi_tegra_isr(int irq, void *context_data)
989 struct spi_tegra_data *tspi = context_data;
991 tspi->status_reg = spi_tegra_readl(tspi, SLINK_STATUS);
992 if (tspi->cur_direction & DATA_DIR_TX)
993 tspi->tx_status = tspi->status_reg &
994 (SLINK_TX_OVF | SLINK_TX_UNF);
996 if (tspi->cur_direction & DATA_DIR_RX)
997 tspi->rx_status = tspi->status_reg &
998 (SLINK_RX_OVF | SLINK_RX_UNF);
999 spi_tegra_clear_status(tspi);
1002 return IRQ_WAKE_THREAD;
1005 static int __init spi_tegra_probe(struct platform_device *pdev)
1007 struct spi_master *master;
1008 struct spi_tegra_data *tspi;
1010 struct tegra_spi_platform_data *pdata = pdev->dev.platform_data;
1013 master = spi_alloc_master(&pdev->dev, sizeof *tspi);
1014 if (master == NULL) {
1015 dev_err(&pdev->dev, "master allocation failed\n");
1019 /* the spi->mode bits understood by this driver: */
1020 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1023 master->bus_num = pdev->id;
1025 master->setup = spi_tegra_setup;
1026 master->transfer = spi_tegra_transfer;
1027 master->num_chipselect = MAX_CHIP_SELECT;
1029 dev_set_drvdata(&pdev->dev, master);
1030 tspi = spi_master_get_devdata(master);
1031 tspi->master = master;
1033 spin_lock_init(&tspi->lock);
1035 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1041 if (!request_mem_region(r->start, (r->end - r->start) + 1,
1042 dev_name(&pdev->dev))) {
1047 tspi->phys = r->start;
1048 tspi->base = ioremap(r->start, r->end - r->start + 1);
1050 dev_err(&pdev->dev, "can't ioremap iomem\n");
1055 tspi->irq = platform_get_irq(pdev, 0);
1056 if (unlikely(tspi->irq < 0)) {
1057 dev_err(&pdev->dev, "can't find irq resource\n");
1062 sprintf(tspi->port_name, "tegra_spi_%d", pdev->id);
1063 ret = request_threaded_irq(tspi->irq, spi_tegra_isr,
1064 spi_tegra_isr_thread, IRQF_DISABLED,
1065 tspi->port_name, tspi);
1067 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1072 tspi->clk = clk_get(&pdev->dev, NULL);
1073 if (IS_ERR_OR_NULL(tspi->clk)) {
1074 dev_err(&pdev->dev, "can not get clock\n");
1075 ret = PTR_ERR(tspi->clk);
1079 INIT_LIST_HEAD(&tspi->queue);
1082 tspi->is_clkon_always = pdata->is_clkon_always;
1083 tspi->is_dma_allowed = pdata->is_dma_based;
1084 tspi->dma_buf_size = (pdata->max_dma_buffer) ?
1085 pdata->max_dma_buffer : DEFAULT_SPI_DMA_BUF_LEN;
1087 tspi->is_clkon_always = false;
1088 tspi->is_dma_allowed = true;
1089 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1091 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1093 if (!tspi->is_dma_allowed)
1094 goto skip_dma_alloc;
1096 init_completion(&tspi->tx_dma_complete);
1097 init_completion(&tspi->rx_dma_complete);
1100 tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
1101 if (!tspi->rx_dma) {
1102 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
1104 goto fail_rx_dma_alloc;
1107 tspi->rx_buf = dma_alloc_coherent(&pdev->dev, tspi->dma_buf_size,
1108 &tspi->rx_buf_phys, GFP_KERNEL);
1109 if (!tspi->rx_buf) {
1110 dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
1112 goto fail_rx_buf_alloc;
1115 memset(&tspi->rx_dma_req, 0, sizeof(struct tegra_dma_req));
1116 tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
1117 tspi->rx_dma_req.to_memory = 1;
1118 tspi->rx_dma_req.dest_addr = tspi->rx_buf_phys;
1119 tspi->rx_dma_req.virt_addr = tspi->rx_buf;
1120 tspi->rx_dma_req.dest_bus_width = 32;
1121 tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
1122 tspi->rx_dma_req.source_bus_width = 32;
1123 tspi->rx_dma_req.source_wrap = 4;
1124 tspi->rx_dma_req.dest_wrap = 0;
1125 tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
1126 tspi->rx_dma_req.dev = tspi;
1128 tspi->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
1129 if (!tspi->tx_dma) {
1130 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
1132 goto fail_tx_dma_alloc;
1135 tspi->tx_buf = dma_alloc_coherent(&pdev->dev, tspi->dma_buf_size,
1136 &tspi->tx_buf_phys, GFP_KERNEL);
1137 if (!tspi->tx_buf) {
1138 dev_err(&pdev->dev, "can not allocate tx bounce buffer\n");
1140 goto fail_tx_buf_alloc;
1143 memset(&tspi->tx_dma_req, 0, sizeof(struct tegra_dma_req));
1144 tspi->tx_dma_req.complete = tegra_spi_tx_dma_complete;
1145 tspi->tx_dma_req.to_memory = 0;
1146 tspi->tx_dma_req.dest_addr = tspi->phys + SLINK_TX_FIFO;
1147 tspi->tx_dma_req.virt_addr = tspi->tx_buf;
1148 tspi->tx_dma_req.dest_bus_width = 32;
1149 tspi->tx_dma_req.dest_wrap = 4;
1150 tspi->tx_dma_req.source_wrap = 0;
1151 tspi->tx_dma_req.source_addr = tspi->tx_buf_phys;
1152 tspi->tx_dma_req.source_bus_width = 32;
1153 tspi->tx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
1154 tspi->tx_dma_req.dev = tspi;
1155 tspi->max_buf_size = tspi->dma_buf_size;
1156 tspi->def_command_reg = SLINK_CS_SW;
1157 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1160 clk_enable(tspi->clk);
1161 tspi->clk_state = 1;
1162 spi_tegra_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1163 ret = spi_register_master(master);
1164 if (!tspi->is_clkon_always) {
1165 if (tspi->clk_state) {
1166 clk_disable(tspi->clk);
1167 tspi->clk_state = 0;
1172 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1173 goto fail_master_register;
1177 fail_master_register:
1179 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1180 tspi->tx_buf, tspi->tx_buf_phys);
1183 tegra_dma_free_channel(tspi->tx_dma);
1186 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1187 tspi->rx_buf, tspi->rx_buf_phys);
1190 tegra_dma_free_channel(tspi->rx_dma);
1194 free_irq(tspi->irq, tspi);
1196 iounmap(tspi->base);
1198 release_mem_region(r->start, (r->end - r->start) + 1);
1200 spi_master_put(master);
1204 static int __devexit spi_tegra_remove(struct platform_device *pdev)
1206 struct spi_master *master;
1207 struct spi_tegra_data *tspi;
1210 master = dev_get_drvdata(&pdev->dev);
1211 tspi = spi_master_get_devdata(master);
1214 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1215 tspi->tx_buf, tspi->tx_buf_phys);
1217 tegra_dma_free_channel(tspi->tx_dma);
1219 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1220 tspi->rx_buf, tspi->rx_buf_phys);
1222 tegra_dma_free_channel(tspi->rx_dma);
1224 if (tspi->is_clkon_always) {
1225 clk_disable(tspi->clk);
1226 tspi->clk_state = 0;
1230 iounmap(tspi->base);
1232 spi_master_put(master);
1233 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1234 release_mem_region(r->start, (r->end - r->start) + 1);
1240 static int spi_tegra_suspend(struct platform_device *pdev, pm_message_t state)
1242 struct spi_master *master;
1243 struct spi_tegra_data *tspi;
1244 unsigned long flags;
1245 unsigned limit = 50;
1247 master = dev_get_drvdata(&pdev->dev);
1248 tspi = spi_master_get_devdata(master);
1249 spin_lock_irqsave(&tspi->lock, flags);
1250 tspi->is_suspended = true;
1252 WARN_ON(!list_empty(&tspi->queue));
1254 while (!list_empty(&tspi->queue) && limit--) {
1255 spin_unlock_irqrestore(&tspi->lock, flags);
1257 spin_lock_irqsave(&tspi->lock, flags);
1260 spin_unlock_irqrestore(&tspi->lock, flags);
1261 if (tspi->is_clkon_always) {
1262 clk_disable(tspi->clk);
1263 tspi->clk_state = 0;
1268 static int spi_tegra_resume(struct platform_device *pdev)
1270 struct spi_master *master;
1271 struct spi_tegra_data *tspi;
1272 unsigned long flags;
1274 master = dev_get_drvdata(&pdev->dev);
1275 tspi = spi_master_get_devdata(master);
1277 spin_lock_irqsave(&tspi->lock, flags);
1278 clk_enable(tspi->clk);
1279 tspi->clk_state = 1;
1280 spi_tegra_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1281 if (!tspi->is_clkon_always) {
1282 clk_disable(tspi->clk);
1283 tspi->clk_state = 0;
1286 tspi->cur_speed = 0;
1287 tspi->is_suspended = false;
1288 spin_unlock_irqrestore(&tspi->lock, flags);
1293 MODULE_ALIAS("platform:spi_slave_tegra");
1295 static struct platform_driver spi_tegra_driver = {
1297 .name = "spi_slave_tegra",
1298 .owner = THIS_MODULE,
1300 .remove = __devexit_p(spi_tegra_remove),
1302 .suspend = spi_tegra_suspend,
1303 .resume = spi_tegra_resume,
1307 static int __init spi_tegra_init(void)
1309 return platform_driver_probe(&spi_tegra_driver, spi_tegra_probe);
1311 subsys_initcall(spi_tegra_init);
1313 static void __exit spi_tegra_exit(void)
1315 platform_driver_unregister(&spi_tegra_driver);
1317 module_exit(spi_tegra_exit);
1319 MODULE_LICENSE("GPL");