Revert "Merge commit 'main-jb-2012.08.03-B4' into t114-0806"
[linux-2.6.git] / drivers / spi / spi_slave_tegra.c
1 /*
2  * Driver for Nvidia TEGRA spi controller in slave mode.
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 /*#define DEBUG           1*/
22 /*#define VERBOSE_DEBUG   1*/
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/err.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmapool.h>
31 #include <linux/clk.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/completion.h>
35 #include <linux/module.h>
36
37 #include <linux/spi/spi.h>
38 #include <linux/spi-tegra.h>
39
40 #include <mach/dma.h>
41 #include <mach/clk.h>
42 #include <mach/spi.h>
43
44 #define SLINK_COMMAND           0x000
45 #define   SLINK_BIT_LENGTH(x)           (((x) & 0x1f) << 0)
46 #define   SLINK_WORD_SIZE(x)            (((x) & 0x1f) << 5)
47 #define   SLINK_BOTH_EN                 (1 << 10)
48 #define   SLINK_CS_SW                   (1 << 11)
49 #define   SLINK_CS_VALUE                (1 << 12)
50 #define   SLINK_CS_POLARITY             (1 << 13)
51 #define   SLINK_IDLE_SDA_DRIVE_LOW      (0 << 16)
52 #define   SLINK_IDLE_SDA_DRIVE_HIGH     (1 << 16)
53 #define   SLINK_IDLE_SDA_PULL_LOW       (2 << 16)
54 #define   SLINK_IDLE_SDA_PULL_HIGH      (3 << 16)
55 #define   SLINK_IDLE_SDA_MASK           (3 << 16)
56 #define   SLINK_CS_POLARITY1            (1 << 20)
57 #define   SLINK_CK_SDA                  (1 << 21)
58 #define   SLINK_CS_POLARITY2            (1 << 22)
59 #define   SLINK_CS_POLARITY3            (1 << 23)
60 #define   SLINK_IDLE_SCLK_DRIVE_LOW     (0 << 24)
61 #define   SLINK_IDLE_SCLK_DRIVE_HIGH    (1 << 24)
62 #define   SLINK_IDLE_SCLK_PULL_LOW      (2 << 24)
63 #define   SLINK_IDLE_SCLK_PULL_HIGH     (3 << 24)
64 #define   SLINK_IDLE_SCLK_MASK          (3 << 24)
65 #define   SLINK_M_S                     (1 << 28)
66 #define   SLINK_WAIT                    (1 << 29)
67 #define   SLINK_GO                      (1 << 30)
68 #define   SLINK_ENB                     (1 << 31)
69
70 #define SLINK_COMMAND2          0x004
71 #define   SLINK_LSBFE                   (1 << 0)
72 #define   SLINK_SSOE                    (1 << 1)
73 #define   SLINK_SPIE                    (1 << 4)
74 #define   SLINK_BIDIROE                 (1 << 6)
75 #define   SLINK_MODFEN                  (1 << 7)
76 #define   SLINK_INT_SIZE(x)             (((x) & 0x1f) << 8)
77 #define   SLINK_CS_ACTIVE_BETWEEN       (1 << 17)
78 #define   SLINK_SS_EN_CS(x)             (((x) & 0x3) << 18)
79 #define   SLINK_SS_SETUP(x)             (((x) & 0x3) << 20)
80 #define   SLINK_FIFO_REFILLS_0          (0 << 22)
81 #define   SLINK_FIFO_REFILLS_1          (1 << 22)
82 #define   SLINK_FIFO_REFILLS_2          (2 << 22)
83 #define   SLINK_FIFO_REFILLS_3          (3 << 22)
84 #define   SLINK_FIFO_REFILLS_MASK       (3 << 22)
85 #define   SLINK_WAIT_PACK_INT(x)        (((x) & 0x7) << 26)
86 #define   SLINK_SPC0                    (1 << 29)
87 #define   SLINK_TXEN                    (1 << 30)
88 #define   SLINK_RXEN                    (1 << 31)
89
90 #define SLINK_STATUS            0x008
91 #define   SLINK_COUNT(val)              (((val) >> 0) & 0x1f)
92 #define   SLINK_WORD(val)               (((val) >> 5) & 0x1f)
93 #define   SLINK_BLK_CNT(val)            (((val) >> 0) & 0xffff)
94 #define   SLINK_MODF                    (1 << 16)
95 #define   SLINK_RX_UNF                  (1 << 18)
96 #define   SLINK_TX_OVF                  (1 << 19)
97 #define   SLINK_TX_FULL                 (1 << 20)
98 #define   SLINK_TX_EMPTY                (1 << 21)
99 #define   SLINK_RX_FULL                 (1 << 22)
100 #define   SLINK_RX_EMPTY                (1 << 23)
101 #define   SLINK_TX_UNF                  (1 << 24)
102 #define   SLINK_RX_OVF                  (1 << 25)
103 #define   SLINK_TX_FLUSH                (1 << 26)
104 #define   SLINK_RX_FLUSH                (1 << 27)
105 #define   SLINK_SCLK                    (1 << 28)
106 #define   SLINK_ERR                     (1 << 29)
107 #define   SLINK_RDY                     (1 << 30)
108 #define   SLINK_BSY                     (1 << 31)
109
110 #define SLINK_MAS_DATA          0x010
111 #define SLINK_SLAVE_DATA        0x014
112
113 #define SLINK_DMA_CTL           0x018
114 #define   SLINK_DMA_BLOCK_SIZE(x)       (((x) & 0xffff) << 0)
115 #define   SLINK_TX_TRIG_1               (0 << 16)
116 #define   SLINK_TX_TRIG_4               (1 << 16)
117 #define   SLINK_TX_TRIG_8               (2 << 16)
118 #define   SLINK_TX_TRIG_16              (3 << 16)
119 #define   SLINK_TX_TRIG_MASK            (3 << 16)
120 #define   SLINK_RX_TRIG_1               (0 << 18)
121 #define   SLINK_RX_TRIG_4               (1 << 18)
122 #define   SLINK_RX_TRIG_8               (2 << 18)
123 #define   SLINK_RX_TRIG_16              (3 << 18)
124 #define   SLINK_RX_TRIG_MASK            (3 << 18)
125 #define   SLINK_PACKED                  (1 << 20)
126 #define   SLINK_PACK_SIZE_4             (0 << 21)
127 #define   SLINK_PACK_SIZE_8             (1 << 21)
128 #define   SLINK_PACK_SIZE_16            (2 << 21)
129 #define   SLINK_PACK_SIZE_32            (3 << 21)
130 #define   SLINK_PACK_SIZE_MASK          (3 << 21)
131 #define   SLINK_IE_TXC                  (1 << 26)
132 #define   SLINK_IE_RXC                  (1 << 27)
133 #define   SLINK_DMA_EN                  (1 << 31)
134
135 #define SLINK_STATUS2           0x01c
136 #define   SLINK_TX_FIFO_EMPTY_COUNT(val)        (((val) & 0x3f) >> 0)
137 #define   SLINK_RX_FIFO_FULL_COUNT(val)         (((val) & 0x3f0000) >> 16)
138 #define   SLINK_SS_HOLD_TIME(val)               (((val) & 0xF) << 6)
139
140 #define SLINK_TX_FIFO           0x100
141 #define SLINK_RX_FIFO           0x180
142
143 #define DATA_DIR_TX             (1 << 0)
144 #define DATA_DIR_RX             (1 << 1)
145
146 #define SPI_FIFO_DEPTH          32
147 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
148
149
150 static const unsigned long spi_tegra_req_sels[] = {
151         TEGRA_DMA_REQ_SEL_SL2B1,
152         TEGRA_DMA_REQ_SEL_SL2B2,
153         TEGRA_DMA_REQ_SEL_SL2B3,
154         TEGRA_DMA_REQ_SEL_SL2B4,
155 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
156         TEGRA_DMA_REQ_SEL_SL2B5,
157         TEGRA_DMA_REQ_SEL_SL2B6,
158 #endif
159
160 };
161
162 #define DEFAULT_SPI_DMA_BUF_LEN         (16*1024)
163 #define TX_FIFO_EMPTY_COUNT_MAX         SLINK_TX_FIFO_EMPTY_COUNT(0x20)
164 #define RX_FIFO_FULL_COUNT_ZERO         SLINK_RX_FIFO_FULL_COUNT(0)
165
166 #define SLINK_STATUS2_RESET \
167         (TX_FIFO_EMPTY_COUNT_MAX | \
168         RX_FIFO_FULL_COUNT_ZERO << 16)
169
170 #define MAX_CHIP_SELECT         4
171 #define SLINK_FIFO_DEPTH        4
172
173 struct spi_tegra_data {
174         struct spi_master       *master;
175         struct platform_device  *pdev;
176         spinlock_t              lock;
177         char                    port_name[32];
178
179         struct clk              *clk;
180         void __iomem            *base;
181         unsigned long           phys;
182         unsigned                irq;
183
184         u32                     cur_speed;
185
186         struct list_head        queue;
187         struct spi_transfer     *cur;
188         struct spi_device       *cur_spi;
189         unsigned                cur_pos;
190         unsigned                cur_len;
191         unsigned                words_per_32bit;
192         unsigned                bytes_per_word;
193         unsigned                curr_dma_words;
194
195         unsigned                cur_direction;
196
197         bool                    is_dma_allowed;
198
199         struct tegra_dma_req    rx_dma_req;
200         struct tegra_dma_channel *rx_dma;
201         u32                     *rx_buf;
202         dma_addr_t              rx_buf_phys;
203         unsigned                cur_rx_pos;
204
205         struct tegra_dma_req    tx_dma_req;
206         struct tegra_dma_channel *tx_dma;
207         u32                     *tx_buf;
208         dma_addr_t              tx_buf_phys;
209         unsigned                cur_tx_pos;
210
211         unsigned                dma_buf_size;
212         unsigned                max_buf_size;
213         bool                    is_curr_dma_xfer;
214
215         bool                    is_clkon_always;
216         bool                    clk_state;
217         bool                    is_suspended;
218
219         bool                    is_hw_based_cs;
220
221         struct completion       rx_dma_complete;
222         struct completion       tx_dma_complete;
223
224         u32                     rx_complete;
225         u32                     tx_complete;
226         u32                     tx_status;
227         u32                     rx_status;
228         u32                     status_reg;
229         bool                    is_packed;
230         unsigned long           packed_size;
231
232         u32                     command_reg;
233         u32                     command2_reg;
234         u32                     dma_control_reg;
235         u32                     def_command_reg;
236         u32                     def_command2_reg;
237
238         callback                client_slave_ready_cb;
239         void                    *client_data;
240
241         struct spi_clk_parent   *parent_clk_list;
242         int                     parent_clk_count;
243         unsigned long           max_rate;
244         unsigned long           max_parent_rate;
245         int                     min_div;
246 };
247
248 static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
249                     unsigned long reg)
250 {
251         if (!tspi->clk_state)
252                 BUG();
253         return readl(tspi->base + reg);
254 }
255
256 static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
257                     unsigned long val, unsigned long reg)
258 {
259         if (!tspi->clk_state)
260                 BUG();
261         writel(val, tspi->base + reg);
262 }
263
264 static void cancel_dma(struct tegra_dma_channel *dma_chan,
265                 struct tegra_dma_req *req)
266 {
267         tegra_dma_cancel(dma_chan);
268         if (req->status == -TEGRA_DMA_REQ_ERROR_ABORTED)
269                 req->complete(req);
270 }
271
272 int spi_tegra_register_callback(struct spi_device *spi, callback func,
273                         void *client_data)
274 {
275         struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
276
277         if (!tspi || !func)
278                 return -EINVAL;
279         tspi->client_slave_ready_cb = func;
280         tspi->client_data = client_data;
281         return 0;
282 }
283 EXPORT_SYMBOL_GPL(spi_tegra_register_callback);
284
285 static void spi_tegra_clear_status(struct spi_tegra_data *tspi)
286 {
287         unsigned long val;
288         unsigned long val_write = 0;
289
290         val = spi_tegra_readl(tspi, SLINK_STATUS);
291
292         val_write = SLINK_RDY;
293         if (val & SLINK_TX_OVF)
294                 val_write |= SLINK_TX_OVF;
295         if (val & SLINK_RX_OVF)
296                 val_write |= SLINK_RX_OVF;
297         if (val & SLINK_RX_UNF)
298                 val_write |= SLINK_RX_UNF;
299         if (val & SLINK_TX_UNF)
300                 val_write |= SLINK_TX_UNF;
301
302         spi_tegra_writel(tspi, val_write, SLINK_STATUS);
303 }
304
305 static unsigned long spi_tegra_get_packed_size(struct spi_tegra_data *tspi,
306                                   struct spi_transfer *t)
307 {
308         unsigned long val;
309
310         switch (tspi->bytes_per_word) {
311         case 0:
312                 val = SLINK_PACK_SIZE_4;
313                 break;
314         case 1:
315                 val = SLINK_PACK_SIZE_8;
316                 break;
317         case 2:
318                 val = SLINK_PACK_SIZE_16;
319                 break;
320         case 4:
321                 val = SLINK_PACK_SIZE_32;
322                 break;
323         default:
324                 val = 0;
325         }
326         return val;
327 }
328
329 static unsigned spi_tegra_calculate_curr_xfer_param(
330         struct spi_device *spi, struct spi_tegra_data *tspi,
331         struct spi_transfer *t)
332 {
333         unsigned remain_len = t->len - tspi->cur_pos;
334         unsigned max_word;
335         unsigned bits_per_word ;
336         unsigned max_len;
337         unsigned total_fifo_words;
338
339         bits_per_word = t->bits_per_word ? t->bits_per_word :
340                                                 spi->bits_per_word;
341         tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1;
342
343         if (bits_per_word == 8 || bits_per_word == 16) {
344                 tspi->is_packed = 1;
345                 tspi->words_per_32bit = 32/bits_per_word;
346         } else {
347                 tspi->is_packed = 0;
348                 tspi->words_per_32bit = 1;
349         }
350         tspi->packed_size = spi_tegra_get_packed_size(tspi, t);
351
352         if (tspi->is_packed) {
353                 max_len = min(remain_len, tspi->max_buf_size);
354                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
355                 total_fifo_words = remain_len/4;
356         } else {
357                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
358                 max_word = min(max_word, tspi->max_buf_size/4);
359                 tspi->curr_dma_words = max_word;
360                 total_fifo_words = remain_len/tspi->bytes_per_word;
361         }
362         /* All transfer should be in one shot */
363         if (tspi->curr_dma_words * tspi->bytes_per_word != t->len) {
364                 dev_err(&tspi->pdev->dev, "The requested length can not be"
365                                         " transferred in one shot\n");
366                 BUG();
367         }
368         return total_fifo_words;
369 }
370
371 static unsigned spi_tegra_fill_tx_fifo_from_client_txbuf(
372         struct spi_tegra_data *tspi, struct spi_transfer *t)
373 {
374         unsigned nbytes;
375         unsigned tx_empty_count;
376         unsigned long fifo_status;
377         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
378         unsigned max_n_32bit;
379         unsigned i, count;
380         unsigned long x;
381         unsigned int written_words;
382
383         fifo_status = spi_tegra_readl(tspi, SLINK_STATUS2);
384         tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
385
386         if (tspi->is_packed) {
387                 nbytes = tspi->curr_dma_words * tspi->bytes_per_word;
388                 max_n_32bit = (min(nbytes,  tx_empty_count*4) - 1)/4 + 1;
389                 for (count = 0; count < max_n_32bit; ++count) {
390                         x = 0;
391                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
392                                 x |= (*tx_buf++) << (i*8);
393                         spi_tegra_writel(tspi, x, SLINK_TX_FIFO);
394                 }
395                 written_words =  min(max_n_32bit * tspi->words_per_32bit,
396                                         tspi->curr_dma_words);
397         } else {
398                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
399                 nbytes = max_n_32bit * tspi->bytes_per_word;
400                 for (count = 0; count < max_n_32bit; ++count) {
401                         x = 0;
402                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
403                                                         ++i, nbytes--)
404                                 x |= ((*tx_buf++) << i*8);
405                         spi_tegra_writel(tspi, x, SLINK_TX_FIFO);
406                 }
407                 written_words = max_n_32bit;
408         }
409         tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
410         return written_words;
411 }
412
413 static unsigned int spi_tegra_read_rx_fifo_to_client_rxbuf(
414                 struct spi_tegra_data *tspi, struct spi_transfer *t)
415 {
416         unsigned rx_full_count;
417         unsigned long fifo_status;
418         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
419         unsigned i, count;
420         unsigned long x;
421         unsigned int read_words;
422         unsigned len;
423
424         fifo_status = spi_tegra_readl(tspi, SLINK_STATUS2);
425         rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
426         dev_dbg(&tspi->pdev->dev, "Rx fifo count %d\n", rx_full_count);
427         if (tspi->is_packed) {
428                 len = tspi->curr_dma_words * tspi->bytes_per_word;
429                 for (count = 0; count < rx_full_count; ++count) {
430                         x = spi_tegra_readl(tspi, SLINK_RX_FIFO);
431                         for (i = 0; len && (i < 4); ++i, len--)
432                                 *rx_buf++ = (x >> i*8) & 0xFF;
433                 }
434                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
435                 read_words += tspi->curr_dma_words;
436         } else {
437                 for (count = 0; count < rx_full_count; ++count) {
438                         x = spi_tegra_readl(tspi, SLINK_RX_FIFO);
439                         for (i = 0; (i < tspi->bytes_per_word); ++i)
440                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
441                 }
442                 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
443                 read_words += rx_full_count;
444         }
445         return read_words;
446 }
447
448 static void spi_tegra_copy_client_txbuf_to_spi_txbuf(
449                 struct spi_tegra_data *tspi, struct spi_transfer *t)
450 {
451         unsigned len;
452         if (tspi->is_packed) {
453                 len = tspi->curr_dma_words * tspi->bytes_per_word;
454                 memcpy(tspi->tx_buf, t->tx_buf + tspi->cur_pos, len);
455         } else {
456                 unsigned int i;
457                 unsigned int count;
458                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
459                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
460                 unsigned int x;
461
462                 for (count = 0; count < tspi->curr_dma_words; ++count) {
463                         x = 0;
464                         for (i = 0; consume && (i < tspi->bytes_per_word);
465                                                         ++i, consume--)
466                                 x |= ((*tx_buf++) << i*8);
467                         tspi->tx_buf[count] = x;
468                 }
469         }
470         tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
471 }
472
473 static void spi_tegra_copy_spi_rxbuf_to_client_rxbuf(
474                 struct spi_tegra_data *tspi, struct spi_transfer *t)
475 {
476         unsigned len;
477         if (tspi->is_packed) {
478                 len = tspi->curr_dma_words * tspi->bytes_per_word;
479                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_buf, len);
480         } else {
481                 unsigned int i;
482                 unsigned int count;
483                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
484                 unsigned int x;
485                 for (count = 0; count < tspi->curr_dma_words; ++count) {
486                         x = tspi->rx_buf[count];
487                         for (i = 0; (i < tspi->bytes_per_word); ++i)
488                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
489                 }
490         }
491         tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
492 }
493
494 static int spi_tegra_start_dma_based_transfer(
495                 struct spi_tegra_data *tspi, struct spi_transfer *t)
496 {
497         unsigned long val;
498         unsigned long test_val;
499         unsigned int len;
500         int ret = 0;
501
502         INIT_COMPLETION(tspi->rx_dma_complete);
503         INIT_COMPLETION(tspi->tx_dma_complete);
504
505         val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
506         val |= tspi->packed_size;
507         if (tspi->is_packed)
508                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
509                                         4) * 4;
510         else
511                 len = tspi->curr_dma_words * 4;
512
513         if (len & 0xF)
514                 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
515         else if (((len) >> 4) & 0x1)
516                 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
517         else
518                 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
519
520         if (tspi->cur_direction & DATA_DIR_TX)
521                 val |= SLINK_IE_TXC;
522
523         if (tspi->cur_direction & DATA_DIR_RX)
524                 val |= SLINK_IE_RXC;
525
526         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
527         tspi->dma_control_reg = val;
528
529         if (tspi->cur_direction & DATA_DIR_TX) {
530                 spi_tegra_copy_client_txbuf_to_spi_txbuf(tspi, t);
531                 wmb();
532                 tspi->tx_dma_req.size = len;
533                 ret = tegra_dma_enqueue_req(tspi->tx_dma, &tspi->tx_dma_req);
534                 if (ret < 0) {
535                         dev_err(&tspi->pdev->dev, "Error in starting tx dma "
536                                                 " error = %d\n", ret);
537                         return ret;
538                 }
539
540                 /* Wait for tx fifo to be fill before starting slink */
541                 test_val = spi_tegra_readl(tspi, SLINK_STATUS);
542                 while (!(test_val & SLINK_TX_FULL))
543                         test_val = spi_tegra_readl(tspi, SLINK_STATUS);
544         }
545
546         if (tspi->cur_direction & DATA_DIR_RX) {
547                 tspi->rx_dma_req.size = len;
548                 ret = tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
549                 if (ret < 0) {
550                         dev_err(&tspi->pdev->dev, "Error in starting rx dma "
551                                                 " error = %d\n", ret);
552                         if (tspi->cur_direction & DATA_DIR_TX)
553                                 cancel_dma(tspi->tx_dma, &tspi->tx_dma_req);
554                         return ret;
555                 }
556         }
557         tspi->is_curr_dma_xfer = true;
558         if (tspi->is_packed) {
559                 val |= SLINK_PACKED;
560                 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
561                 udelay(1);
562                 wmb();
563         }
564
565         val |= SLINK_DMA_EN;
566         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
567         return ret;
568 }
569
570 static int spi_tegra_start_cpu_based_transfer(
571                 struct spi_tegra_data *tspi, struct spi_transfer *t)
572 {
573         unsigned long val;
574         unsigned curr_words;
575
576         val = tspi->packed_size;
577         if (tspi->cur_direction & DATA_DIR_TX)
578                 val |= SLINK_IE_TXC;
579
580         if (tspi->cur_direction & DATA_DIR_RX)
581                 val |= SLINK_IE_RXC;
582
583         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
584         tspi->dma_control_reg = val;
585
586         if (tspi->cur_direction & DATA_DIR_TX)
587                 curr_words = spi_tegra_fill_tx_fifo_from_client_txbuf(tspi, t);
588         else
589                 curr_words = tspi->curr_dma_words;
590         val |= SLINK_DMA_BLOCK_SIZE(curr_words - 1);
591         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
592         tspi->dma_control_reg = val;
593
594         tspi->is_curr_dma_xfer = false;
595         if (tspi->is_packed) {
596                 val |= SLINK_PACKED;
597                 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
598                 udelay(1);
599                 wmb();
600         }
601         val |= SLINK_DMA_EN;
602         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
603         return 0;
604 }
605
606 static void set_best_clk_source(struct spi_tegra_data *tspi,
607                 unsigned long speed)
608 {
609         long new_rate;
610         unsigned long err_rate;
611         int rate = speed * 4;
612         unsigned int fin_err = speed * 4;
613         int final_index = -1;
614         int count;
615         int ret;
616         struct clk *pclk;
617         unsigned long prate, crate, nrate;
618         unsigned long cdiv;
619
620         if (!tspi->parent_clk_count || !tspi->parent_clk_list)
621                 return;
622
623         /* make sure divisor is more than min_div */
624         pclk = clk_get_parent(tspi->clk);
625         prate = clk_get_rate(pclk);
626         crate = clk_get_rate(tspi->clk);
627         cdiv = DIV_ROUND_UP(prate, crate);
628         if (cdiv < tspi->min_div) {
629                 nrate = DIV_ROUND_UP(prate, tspi->min_div);
630                 clk_set_rate(tspi->clk, nrate);
631         }
632
633         for (count = 0; count < tspi->parent_clk_count; ++count) {
634                 if (!tspi->parent_clk_list[count].parent_clk)
635                         continue;
636                 ret = clk_set_parent(tspi->clk,
637                         tspi->parent_clk_list[count].parent_clk);
638                 if (ret < 0) {
639                         dev_warn(&tspi->pdev->dev, "Error in setting parent "
640                                 " clk src %s\n",
641                                 tspi->parent_clk_list[count].name);
642                         continue;
643                 }
644
645                 new_rate = clk_round_rate(tspi->clk, rate);
646                 if (new_rate < 0)
647                         continue;
648
649                 err_rate = abs(new_rate - rate);
650                 if (err_rate < fin_err) {
651                         final_index = count;
652                         fin_err = err_rate;
653                 }
654         }
655
656         if (final_index >= 0) {
657                 dev_info(&tspi->pdev->dev, "Setting clk_src %s\n",
658                                 tspi->parent_clk_list[final_index].name);
659                 clk_set_parent(tspi->clk,
660                         tspi->parent_clk_list[final_index].parent_clk);
661         }
662 }
663
664 static void spi_tegra_start_transfer(struct spi_device *spi,
665                     struct spi_transfer *t)
666 {
667         struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
668         u32 speed;
669         u8 bits_per_word;
670         unsigned total_fifo_words;
671         int ret;
672         unsigned long command;
673         unsigned long command2;
674
675         bits_per_word = t->bits_per_word ? t->bits_per_word :
676                                         spi->bits_per_word;
677
678         speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
679         if (speed != tspi->cur_speed) {
680                 set_best_clk_source(tspi, speed);
681                 clk_set_rate(tspi->clk, speed * 4);
682                 tspi->cur_speed = speed;
683         }
684
685         tspi->cur = t;
686         tspi->cur_spi = spi;
687         tspi->cur_pos = 0;
688         tspi->cur_rx_pos = 0;
689         tspi->cur_tx_pos = 0;
690         tspi->rx_complete = 0;
691         tspi->tx_complete = 0;
692         total_fifo_words = spi_tegra_calculate_curr_xfer_param(spi, tspi, t);
693
694         command2 = tspi->def_command2_reg;
695         if (!tspi->is_clkon_always) {
696                 if (!tspi->clk_state) {
697                         clk_enable(tspi->clk);
698                         tspi->clk_state = 1;
699                 }
700         }
701
702         spi_tegra_clear_status(tspi);
703
704         command = tspi->def_command_reg;
705         command |= SLINK_BIT_LENGTH(bits_per_word - 1);
706
707         command |= SLINK_CS_SW;
708
709         command &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA;
710         if (spi->mode & SPI_CPHA)
711                 command |= SLINK_CK_SDA;
712
713         if (spi->mode & SPI_CPOL)
714                 command |= SLINK_IDLE_SCLK_DRIVE_HIGH;
715         else
716                 command |= SLINK_IDLE_SCLK_DRIVE_LOW;
717
718         spi_tegra_writel(tspi, command, SLINK_COMMAND);
719         tspi->command_reg = command;
720
721         dev_dbg(&tspi->pdev->dev, "The def 0x%x and written 0x%lx\n",
722                                 tspi->def_command_reg, command);
723
724         command2 &= ~(SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN);
725         tspi->cur_direction = 0;
726         if (t->rx_buf) {
727                 command2 |= SLINK_RXEN;
728                 tspi->cur_direction |= DATA_DIR_RX;
729         }
730         if (t->tx_buf) {
731                 command2 |= SLINK_TXEN;
732                 tspi->cur_direction |= DATA_DIR_TX;
733         }
734         command2 |= SLINK_SS_EN_CS(spi->chip_select);
735         spi_tegra_writel(tspi, command2, SLINK_COMMAND2);
736         tspi->command2_reg = command2;
737
738         if (total_fifo_words > SPI_FIFO_DEPTH)
739                 ret = spi_tegra_start_dma_based_transfer(tspi, t);
740         else
741                 ret = spi_tegra_start_cpu_based_transfer(tspi, t);
742         WARN_ON(ret < 0);
743
744         if (tspi->client_slave_ready_cb)
745                 tspi->client_slave_ready_cb(tspi->client_data);
746 }
747
748 static void spi_tegra_start_message(struct spi_device *spi,
749                                     struct spi_message *m)
750 {
751         struct spi_transfer *t;
752         m->actual_length = 0;
753         m->status = 0;
754         t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
755         spi_tegra_start_transfer(spi, t);
756 }
757
758 static int spi_tegra_setup(struct spi_device *spi)
759 {
760         struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
761         unsigned long cs_bit;
762         unsigned long val;
763         unsigned long flags;
764
765         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
766                 spi->bits_per_word,
767                 spi->mode & SPI_CPOL ? "" : "~",
768                 spi->mode & SPI_CPHA ? "" : "~",
769                 spi->max_speed_hz);
770
771         BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
772         switch (spi->chip_select) {
773         case 0:
774                 cs_bit = SLINK_CS_POLARITY;
775                 break;
776
777         case 1:
778                 cs_bit = SLINK_CS_POLARITY1;
779                 break;
780
781         case 2:
782                 cs_bit = SLINK_CS_POLARITY2;
783                 break;
784
785         case 3:
786                 cs_bit = SLINK_CS_POLARITY3;
787                 break;
788
789         default:
790                 return -EINVAL;
791         }
792
793         spin_lock_irqsave(&tspi->lock, flags);
794         val = tspi->def_command_reg;
795         if (spi->mode & SPI_CS_HIGH)
796                 val |= cs_bit;
797         else
798                 val &= ~cs_bit;
799         tspi->def_command_reg = val;
800
801         if (!tspi->is_clkon_always && !tspi->clk_state) {
802                 clk_enable(tspi->clk);
803                 tspi->clk_state = 1;
804         }
805         spi_tegra_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
806         if (!tspi->is_clkon_always && tspi->clk_state) {
807                 clk_disable(tspi->clk);
808                 tspi->clk_state = 0;
809         }
810
811         spin_unlock_irqrestore(&tspi->lock, flags);
812         return 0;
813 }
814
815 static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m)
816 {
817         struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
818         struct spi_transfer *t;
819         unsigned long flags;
820         int was_empty;
821         int bytes_per_word;
822         u8 bits_per_word;
823         int fifo_word;
824
825         /* Support only one transfer per message */
826         if (!list_is_singular(&m->transfers))
827                 return -EINVAL;
828
829         if (list_empty(&m->transfers) || !m->complete)
830                 return -EINVAL;
831
832         t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
833         if (t->bits_per_word < 0 || t->bits_per_word > 32)
834                 return -EINVAL;
835
836         if (t->len == 0)
837                 return -EINVAL;
838
839         bits_per_word = (t->bits_per_word) ? : spi->bits_per_word;
840
841         /* Check that the all words are available */
842         bytes_per_word = (bits_per_word + 7)/8;
843
844         if (t->len % bytes_per_word != 0)
845                 return -EINVAL;
846
847         if (!t->rx_buf && !t->tx_buf)
848                 return -EINVAL;
849
850         if ((bits_per_word == 8) || (bits_per_word == 16))
851                 fifo_word = t->len/4;
852         else
853                 fifo_word = t->len/bytes_per_word;
854         if (fifo_word >= tspi->max_buf_size/4)
855                 return -EINVAL;
856
857         spin_lock_irqsave(&tspi->lock, flags);
858
859         if (WARN_ON(tspi->is_suspended)) {
860                 spin_unlock_irqrestore(&tspi->lock, flags);
861                 return -EBUSY;
862         }
863
864         m->state = spi;
865
866         was_empty = list_empty(&tspi->queue);
867         list_add_tail(&m->queue, &tspi->queue);
868
869         if (was_empty)
870                 spi_tegra_start_message(spi, m);
871
872         spin_unlock_irqrestore(&tspi->lock, flags);
873
874         return 0;
875 }
876
877 static void spi_tegra_curr_transfer_complete(struct spi_tegra_data *tspi,
878         unsigned err, unsigned cur_xfer_size)
879 {
880         struct spi_message *m;
881         struct spi_device *spi;
882
883         m = list_first_entry(&tspi->queue, struct spi_message, queue);
884         if (err)
885                 m->status = -EIO;
886         spi = m->state;
887
888         m->actual_length += cur_xfer_size;
889         list_del(&m->queue);
890         m->complete(m->context);
891         if (!list_empty(&tspi->queue)) {
892                 m = list_first_entry(&tspi->queue, struct spi_message, queue);
893                 spi = m->state;
894                 spi_tegra_start_message(spi, m);
895         } else {
896                 spi_tegra_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
897                 spi_tegra_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
898                 if (!tspi->is_clkon_always) {
899                         if (tspi->clk_state) {
900                                 /* Provide delay to stablize the signal
901                                    state */
902                                 udelay(10);
903                                 clk_disable(tspi->clk);
904                                 tspi->clk_state = 0;
905                         }
906                 }
907         }
908 }
909
910 static void tegra_spi_tx_dma_complete(struct tegra_dma_req *req)
911 {
912         struct spi_tegra_data *tspi = req->dev;
913         complete(&tspi->tx_dma_complete);
914 }
915
916 static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
917 {
918         struct spi_tegra_data *tspi = req->dev;
919         complete(&tspi->rx_dma_complete);
920 }
921
922 static void handle_cpu_based_xfer(void *context_data)
923 {
924         struct spi_tegra_data *tspi = context_data;
925         struct spi_transfer *t = tspi->cur;
926         unsigned long flags;
927
928         spin_lock_irqsave(&tspi->lock, flags);
929         if (tspi->tx_status ||  tspi->rx_status ||
930                                 (tspi->status_reg & SLINK_BSY)) {
931                 dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n",
932                                          __func__, tspi->status_reg);
933                 tegra_periph_reset_assert(tspi->clk);
934                 udelay(2);
935                 tegra_periph_reset_deassert(tspi->clk);
936                 WARN_ON(1);
937                 spi_tegra_curr_transfer_complete(tspi,
938                                 tspi->tx_status ||  tspi->rx_status, t->len);
939                 goto exit;
940         }
941
942         dev_vdbg(&tspi->pdev->dev, " Current direction %x\n",
943                                                 tspi->cur_direction);
944         if (tspi->cur_direction & DATA_DIR_RX)
945                 spi_tegra_read_rx_fifo_to_client_rxbuf(tspi, t);
946
947         if (tspi->cur_direction & DATA_DIR_TX)
948                 tspi->cur_pos = tspi->cur_tx_pos;
949         else if (tspi->cur_direction & DATA_DIR_RX)
950                 tspi->cur_pos = tspi->cur_rx_pos;
951         else
952                 WARN_ON(1);
953
954         dev_vdbg(&tspi->pdev->dev, "current position %d and length of the "
955                                 "transfer %d\n", tspi->cur_pos, t->len);
956         if (tspi->cur_pos == t->len) {
957                 spi_tegra_curr_transfer_complete(tspi,
958                         tspi->tx_status || tspi->rx_status, t->len);
959                 goto exit;
960         }
961
962         /* There should not be remaining transfer */
963         BUG();
964 exit:
965         spin_unlock_irqrestore(&tspi->lock, flags);
966         return;
967 }
968
969 static irqreturn_t spi_tegra_isr_thread(int irq, void *context_data)
970 {
971         struct spi_tegra_data *tspi = context_data;
972         struct spi_transfer *t = tspi->cur;
973         long wait_status;
974         int err = 0;
975         unsigned long flags;
976
977         if (!tspi->is_curr_dma_xfer) {
978                 handle_cpu_based_xfer(context_data);
979                 return IRQ_HANDLED;
980         }
981
982         /* Abort dmas if any error */
983         if (tspi->cur_direction & DATA_DIR_TX) {
984                 if (tspi->tx_status) {
985                         cancel_dma(tspi->tx_dma, &tspi->tx_dma_req);
986                         err += 1;
987                 } else {
988                         wait_status = wait_for_completion_interruptible_timeout(
989                                 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
990                         if (wait_status <= 0) {
991                                 cancel_dma(tspi->tx_dma, &tspi->tx_dma_req);
992                                 dev_err(&tspi->pdev->dev, "Error in Dma Tx "
993                                                         "transfer\n");
994                                 err += 1;
995                         }
996                 }
997         }
998
999         if (tspi->cur_direction & DATA_DIR_RX) {
1000                 if (tspi->rx_status) {
1001                         cancel_dma(tspi->rx_dma, &tspi->rx_dma_req);
1002                         err += 2;
1003                 } else {
1004                         wait_status = wait_for_completion_interruptible_timeout(
1005                                 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
1006                         if (wait_status <= 0) {
1007                                 cancel_dma(tspi->rx_dma, &tspi->rx_dma_req);
1008                                 dev_err(&tspi->pdev->dev, "Error in Dma Rx "
1009                                                         "transfer\n");
1010                                 err += 2;
1011                         }
1012                 }
1013         }
1014
1015         spin_lock_irqsave(&tspi->lock, flags);
1016         if (err) {
1017                 dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n",
1018                                          __func__, tspi->status_reg);
1019                 tegra_periph_reset_assert(tspi->clk);
1020                 udelay(2);
1021                 tegra_periph_reset_deassert(tspi->clk);
1022                 WARN_ON(1);
1023                 spi_tegra_curr_transfer_complete(tspi, err, t->len);
1024                 spin_unlock_irqrestore(&tspi->lock, flags);
1025                 return IRQ_HANDLED;
1026         }
1027
1028         if (tspi->cur_direction & DATA_DIR_RX)
1029                 spi_tegra_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1030
1031         if (tspi->cur_direction & DATA_DIR_TX)
1032                 tspi->cur_pos = tspi->cur_tx_pos;
1033         else if (tspi->cur_direction & DATA_DIR_RX)
1034                 tspi->cur_pos = tspi->cur_rx_pos;
1035         else
1036                 WARN_ON(1);
1037
1038         if (tspi->cur_pos == t->len) {
1039                 spi_tegra_curr_transfer_complete(tspi,
1040                         tspi->tx_status || tspi->rx_status, t->len);
1041                 spin_unlock_irqrestore(&tspi->lock, flags);
1042                 return IRQ_HANDLED;
1043         }
1044
1045         spin_unlock_irqrestore(&tspi->lock, flags);
1046
1047         /* There should not be remaining transfer */
1048         BUG();
1049         return IRQ_HANDLED;
1050 }
1051
1052 static irqreturn_t spi_tegra_isr(int irq, void *context_data)
1053 {
1054         struct spi_tegra_data *tspi = context_data;
1055
1056         tspi->status_reg = spi_tegra_readl(tspi, SLINK_STATUS);
1057         if (tspi->cur_direction & DATA_DIR_TX)
1058                 tspi->tx_status = tspi->status_reg &
1059                                         (SLINK_TX_OVF | SLINK_TX_UNF);
1060
1061         if (tspi->cur_direction & DATA_DIR_RX)
1062                 tspi->rx_status = tspi->status_reg &
1063                                         (SLINK_RX_OVF | SLINK_RX_UNF);
1064         spi_tegra_clear_status(tspi);
1065
1066
1067         return IRQ_WAKE_THREAD;
1068 }
1069
1070 static int __init spi_tegra_probe(struct platform_device *pdev)
1071 {
1072         struct spi_master       *master;
1073         struct spi_tegra_data   *tspi;
1074         struct resource         *r;
1075         struct tegra_spi_platform_data *pdata = pdev->dev.platform_data;
1076         int ret;
1077         int i;
1078
1079         master = spi_alloc_master(&pdev->dev, sizeof *tspi);
1080         if (master == NULL) {
1081                 dev_err(&pdev->dev, "master allocation failed\n");
1082                 return -ENOMEM;
1083         }
1084
1085         /* the spi->mode bits understood by this driver: */
1086         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1087
1088         if (pdev->id != -1)
1089                 master->bus_num = pdev->id;
1090
1091         master->setup = spi_tegra_setup;
1092         master->transfer = spi_tegra_transfer;
1093         master->num_chipselect = MAX_CHIP_SELECT;
1094
1095         dev_set_drvdata(&pdev->dev, master);
1096         tspi = spi_master_get_devdata(master);
1097         tspi->master = master;
1098         tspi->pdev = pdev;
1099         spin_lock_init(&tspi->lock);
1100
1101         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102         if (r == NULL) {
1103                 ret = -ENODEV;
1104                 goto fail_no_mem;
1105         }
1106
1107         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1108                                 dev_name(&pdev->dev))) {
1109                 ret = -EBUSY;
1110                 goto fail_no_mem;
1111         }
1112
1113         tspi->phys = r->start;
1114         tspi->base = ioremap(r->start, r->end - r->start + 1);
1115         if (!tspi->base) {
1116                 dev_err(&pdev->dev, "can't ioremap iomem\n");
1117                 ret = -ENOMEM;
1118                 goto fail_io_map;
1119         }
1120
1121         tspi->irq = platform_get_irq(pdev, 0);
1122         if (unlikely(tspi->irq < 0)) {
1123                 dev_err(&pdev->dev, "can't find irq resource\n");
1124                 ret = -ENXIO;
1125                 goto fail_irq_req;
1126         }
1127
1128         sprintf(tspi->port_name, "tegra_spi_%d", pdev->id);
1129         ret = request_threaded_irq(tspi->irq, spi_tegra_isr,
1130                         spi_tegra_isr_thread, IRQF_DISABLED,
1131                         tspi->port_name, tspi);
1132         if (ret < 0) {
1133                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1134                                         tspi->irq);
1135                 goto fail_irq_req;
1136         }
1137
1138         tspi->clk = clk_get(&pdev->dev, NULL);
1139         if (IS_ERR_OR_NULL(tspi->clk)) {
1140                 dev_err(&pdev->dev, "can not get clock\n");
1141                 ret = PTR_ERR(tspi->clk);
1142                 goto fail_clk_get;
1143         }
1144
1145         INIT_LIST_HEAD(&tspi->queue);
1146
1147         if (pdata) {
1148                 tspi->is_clkon_always = pdata->is_clkon_always;
1149                 tspi->is_dma_allowed = pdata->is_dma_based;
1150                 tspi->dma_buf_size = (pdata->max_dma_buffer) ?
1151                                 pdata->max_dma_buffer : DEFAULT_SPI_DMA_BUF_LEN;
1152                 tspi->parent_clk_count = pdata->parent_clk_count;
1153                 tspi->parent_clk_list = pdata->parent_clk_list;
1154                 tspi->max_rate = pdata->max_rate;
1155         } else {
1156                 tspi->is_clkon_always = false;
1157                 tspi->is_dma_allowed = true;
1158                 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1159                 tspi->parent_clk_count = 0;
1160                 tspi->parent_clk_list = NULL;
1161                 tspi->max_rate = 0;
1162         }
1163
1164         tspi->max_parent_rate = 0;
1165         tspi->min_div = 0;
1166
1167         if (tspi->parent_clk_count) {
1168                 tspi->max_parent_rate = tspi->parent_clk_list[0].fixed_clk_rate;
1169                 for (i = 1; i < tspi->parent_clk_count; ++i) {
1170                         tspi->max_parent_rate = max(tspi->max_parent_rate,
1171                                 tspi->parent_clk_list[i].fixed_clk_rate);
1172                 }
1173                 if (tspi->max_rate)
1174                         tspi->min_div = DIV_ROUND_UP(tspi->max_parent_rate,
1175                                                 tspi->max_rate);
1176         }
1177         tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1178
1179         if (!tspi->is_dma_allowed)
1180                 goto skip_dma_alloc;
1181
1182         init_completion(&tspi->tx_dma_complete);
1183         init_completion(&tspi->rx_dma_complete);
1184
1185
1186         tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT,
1187                                 "spi_rx_%d", pdev->id);
1188         if (!tspi->rx_dma) {
1189                 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
1190                 ret = -ENODEV;
1191                 goto fail_rx_dma_alloc;
1192         }
1193
1194         tspi->rx_buf = dma_alloc_coherent(&pdev->dev, tspi->dma_buf_size,
1195                                          &tspi->rx_buf_phys, GFP_KERNEL);
1196         if (!tspi->rx_buf) {
1197                 dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
1198                 ret = -ENOMEM;
1199                 goto fail_rx_buf_alloc;
1200         }
1201
1202         memset(&tspi->rx_dma_req, 0, sizeof(struct tegra_dma_req));
1203         tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
1204         tspi->rx_dma_req.to_memory = 1;
1205         tspi->rx_dma_req.dest_addr = tspi->rx_buf_phys;
1206         tspi->rx_dma_req.virt_addr = tspi->rx_buf;
1207         tspi->rx_dma_req.dest_bus_width = 32;
1208         tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
1209         tspi->rx_dma_req.source_bus_width = 32;
1210         tspi->rx_dma_req.source_wrap = 4;
1211         tspi->rx_dma_req.dest_wrap = 0;
1212         tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
1213         tspi->rx_dma_req.dev = tspi;
1214
1215         tspi->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT,
1216                                 "spi_tx_%d", pdev->id);
1217         if (!tspi->tx_dma) {
1218                 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
1219                 ret = -ENODEV;
1220                 goto fail_tx_dma_alloc;
1221         }
1222
1223         tspi->tx_buf = dma_alloc_coherent(&pdev->dev, tspi->dma_buf_size,
1224                                          &tspi->tx_buf_phys, GFP_KERNEL);
1225         if (!tspi->tx_buf) {
1226                 dev_err(&pdev->dev, "can not allocate tx bounce buffer\n");
1227                 ret = -ENOMEM;
1228                 goto fail_tx_buf_alloc;
1229         }
1230
1231         memset(&tspi->tx_dma_req, 0, sizeof(struct tegra_dma_req));
1232         tspi->tx_dma_req.complete = tegra_spi_tx_dma_complete;
1233         tspi->tx_dma_req.to_memory = 0;
1234         tspi->tx_dma_req.dest_addr = tspi->phys + SLINK_TX_FIFO;
1235         tspi->tx_dma_req.virt_addr = tspi->tx_buf;
1236         tspi->tx_dma_req.dest_bus_width = 32;
1237         tspi->tx_dma_req.dest_wrap = 4;
1238         tspi->tx_dma_req.source_wrap = 0;
1239         tspi->tx_dma_req.source_addr = tspi->tx_buf_phys;
1240         tspi->tx_dma_req.source_bus_width = 32;
1241         tspi->tx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
1242         tspi->tx_dma_req.dev = tspi;
1243         tspi->max_buf_size = tspi->dma_buf_size;
1244         tspi->def_command_reg  = SLINK_CS_SW;
1245         tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1246
1247 skip_dma_alloc:
1248         clk_enable(tspi->clk);
1249         tspi->clk_state = 1;
1250         spi_tegra_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1251         ret = spi_register_master(master);
1252         if (!tspi->is_clkon_always) {
1253                 if (tspi->clk_state) {
1254                         clk_disable(tspi->clk);
1255                         tspi->clk_state = 0;
1256                 }
1257         }
1258
1259         if (ret < 0) {
1260                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1261                 goto fail_master_register;
1262         }
1263         return ret;
1264
1265 fail_master_register:
1266         if (tspi->tx_buf)
1267                 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1268                                 tspi->tx_buf, tspi->tx_buf_phys);
1269 fail_tx_buf_alloc:
1270         if (tspi->tx_dma)
1271                 tegra_dma_free_channel(tspi->tx_dma);
1272 fail_tx_dma_alloc:
1273         if (tspi->rx_buf)
1274                 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1275                           tspi->rx_buf, tspi->rx_buf_phys);
1276 fail_rx_buf_alloc:
1277         if (tspi->rx_dma)
1278                 tegra_dma_free_channel(tspi->rx_dma);
1279 fail_rx_dma_alloc:
1280         clk_put(tspi->clk);
1281 fail_clk_get:
1282         free_irq(tspi->irq, tspi);
1283 fail_irq_req:
1284         iounmap(tspi->base);
1285 fail_io_map:
1286         release_mem_region(r->start, (r->end - r->start) + 1);
1287 fail_no_mem:
1288         spi_master_put(master);
1289         return ret;
1290 }
1291
1292 static int __devexit spi_tegra_remove(struct platform_device *pdev)
1293 {
1294         struct spi_master       *master;
1295         struct spi_tegra_data   *tspi;
1296         struct resource         *r;
1297
1298         master = dev_get_drvdata(&pdev->dev);
1299         tspi = spi_master_get_devdata(master);
1300
1301         if (tspi->tx_buf)
1302                 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1303                                 tspi->tx_buf, tspi->tx_buf_phys);
1304         if (tspi->tx_dma)
1305                 tegra_dma_free_channel(tspi->tx_dma);
1306         if (tspi->rx_buf)
1307                 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1308                           tspi->rx_buf, tspi->rx_buf_phys);
1309         if (tspi->rx_dma)
1310                 tegra_dma_free_channel(tspi->rx_dma);
1311
1312         if (tspi->is_clkon_always) {
1313                 clk_disable(tspi->clk);
1314                 tspi->clk_state = 0;
1315         }
1316
1317         clk_put(tspi->clk);
1318         iounmap(tspi->base);
1319
1320         spi_master_put(master);
1321         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1322         release_mem_region(r->start, (r->end - r->start) + 1);
1323
1324         return 0;
1325 }
1326
1327 #ifdef CONFIG_PM
1328 static int spi_tegra_suspend(struct platform_device *pdev, pm_message_t state)
1329 {
1330         struct spi_master       *master;
1331         struct spi_tegra_data   *tspi;
1332         unsigned long           flags;
1333         unsigned                limit = 50;
1334
1335         master = dev_get_drvdata(&pdev->dev);
1336         tspi = spi_master_get_devdata(master);
1337         spin_lock_irqsave(&tspi->lock, flags);
1338         tspi->is_suspended = true;
1339
1340         WARN_ON(!list_empty(&tspi->queue));
1341
1342         while (!list_empty(&tspi->queue) && limit--) {
1343                 spin_unlock_irqrestore(&tspi->lock, flags);
1344                 msleep(20);
1345                 spin_lock_irqsave(&tspi->lock, flags);
1346         }
1347
1348         spin_unlock_irqrestore(&tspi->lock, flags);
1349         if (tspi->is_clkon_always) {
1350                 clk_disable(tspi->clk);
1351                 tspi->clk_state = 0;
1352         }
1353         return 0;
1354 }
1355
1356 static int spi_tegra_resume(struct platform_device *pdev)
1357 {
1358         struct spi_master       *master;
1359         struct spi_tegra_data   *tspi;
1360         unsigned long           flags;
1361
1362         master = dev_get_drvdata(&pdev->dev);
1363         tspi = spi_master_get_devdata(master);
1364
1365         spin_lock_irqsave(&tspi->lock, flags);
1366         clk_enable(tspi->clk);
1367         tspi->clk_state = 1;
1368         spi_tegra_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1369         if (!tspi->is_clkon_always) {
1370                 clk_disable(tspi->clk);
1371                 tspi->clk_state = 0;
1372         }
1373
1374         tspi->cur_speed = 0;
1375         tspi->is_suspended = false;
1376         spin_unlock_irqrestore(&tspi->lock, flags);
1377         return 0;
1378 }
1379 #endif
1380
1381 MODULE_ALIAS("platform:spi_slave_tegra");
1382
1383 static struct platform_driver spi_tegra_driver = {
1384         .driver = {
1385                 .name =         "spi_slave_tegra",
1386                 .owner =        THIS_MODULE,
1387         },
1388         .remove =       __devexit_p(spi_tegra_remove),
1389 #ifdef CONFIG_PM
1390         .suspend =      spi_tegra_suspend,
1391         .resume  =      spi_tegra_resume,
1392 #endif
1393 };
1394
1395 static int __init spi_tegra_init(void)
1396 {
1397         return platform_driver_probe(&spi_tegra_driver, spi_tegra_probe);
1398 }
1399 subsys_initcall(spi_tegra_init);
1400
1401 static void __exit spi_tegra_exit(void)
1402 {
1403         platform_driver_unregister(&spi_tegra_driver);
1404 }
1405 module_exit(spi_tegra_exit);
1406
1407 MODULE_LICENSE("GPL");