spi: tegra: Fixed spi slave CS polarity
[linux-2.6.git] / drivers / spi / spi_slave_tegra.c
1 /*
2  * Driver for Nvidia TEGRA spi controller in slave mode.
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 /*#define DEBUG           1*/
22 /*#define VERBOSE_DEBUG   1*/
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/err.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmapool.h>
31 #include <linux/clk.h>
32 #include <linux/interrupt.h>
33 #include <linux/delay.h>
34 #include <linux/completion.h>
35
36 #include <linux/spi/spi.h>
37 #include <linux/spi-tegra.h>
38
39 #include <mach/dma.h>
40 #include <mach/clk.h>
41 #include <mach/spi.h>
42
43 #define SLINK_COMMAND           0x000
44 #define   SLINK_BIT_LENGTH(x)           (((x) & 0x1f) << 0)
45 #define   SLINK_WORD_SIZE(x)            (((x) & 0x1f) << 5)
46 #define   SLINK_BOTH_EN                 (1 << 10)
47 #define   SLINK_CS_SW                   (1 << 11)
48 #define   SLINK_CS_VALUE                (1 << 12)
49 #define   SLINK_CS_POLARITY             (1 << 13)
50 #define   SLINK_IDLE_SDA_DRIVE_LOW      (0 << 16)
51 #define   SLINK_IDLE_SDA_DRIVE_HIGH     (1 << 16)
52 #define   SLINK_IDLE_SDA_PULL_LOW       (2 << 16)
53 #define   SLINK_IDLE_SDA_PULL_HIGH      (3 << 16)
54 #define   SLINK_IDLE_SDA_MASK           (3 << 16)
55 #define   SLINK_CS_POLARITY1            (1 << 20)
56 #define   SLINK_CK_SDA                  (1 << 21)
57 #define   SLINK_CS_POLARITY2            (1 << 22)
58 #define   SLINK_CS_POLARITY3            (1 << 23)
59 #define   SLINK_IDLE_SCLK_DRIVE_LOW     (0 << 24)
60 #define   SLINK_IDLE_SCLK_DRIVE_HIGH    (1 << 24)
61 #define   SLINK_IDLE_SCLK_PULL_LOW      (2 << 24)
62 #define   SLINK_IDLE_SCLK_PULL_HIGH     (3 << 24)
63 #define   SLINK_IDLE_SCLK_MASK          (3 << 24)
64 #define   SLINK_M_S                     (1 << 28)
65 #define   SLINK_WAIT                    (1 << 29)
66 #define   SLINK_GO                      (1 << 30)
67 #define   SLINK_ENB                     (1 << 31)
68
69 #define SLINK_COMMAND2          0x004
70 #define   SLINK_LSBFE                   (1 << 0)
71 #define   SLINK_SSOE                    (1 << 1)
72 #define   SLINK_SPIE                    (1 << 4)
73 #define   SLINK_BIDIROE                 (1 << 6)
74 #define   SLINK_MODFEN                  (1 << 7)
75 #define   SLINK_INT_SIZE(x)             (((x) & 0x1f) << 8)
76 #define   SLINK_CS_ACTIVE_BETWEEN       (1 << 17)
77 #define   SLINK_SS_EN_CS(x)             (((x) & 0x3) << 18)
78 #define   SLINK_SS_SETUP(x)             (((x) & 0x3) << 20)
79 #define   SLINK_FIFO_REFILLS_0          (0 << 22)
80 #define   SLINK_FIFO_REFILLS_1          (1 << 22)
81 #define   SLINK_FIFO_REFILLS_2          (2 << 22)
82 #define   SLINK_FIFO_REFILLS_3          (3 << 22)
83 #define   SLINK_FIFO_REFILLS_MASK       (3 << 22)
84 #define   SLINK_WAIT_PACK_INT(x)        (((x) & 0x7) << 26)
85 #define   SLINK_SPC0                    (1 << 29)
86 #define   SLINK_TXEN                    (1 << 30)
87 #define   SLINK_RXEN                    (1 << 31)
88
89 #define SLINK_STATUS            0x008
90 #define   SLINK_COUNT(val)              (((val) >> 0) & 0x1f)
91 #define   SLINK_WORD(val)               (((val) >> 5) & 0x1f)
92 #define   SLINK_BLK_CNT(val)            (((val) >> 0) & 0xffff)
93 #define   SLINK_MODF                    (1 << 16)
94 #define   SLINK_RX_UNF                  (1 << 18)
95 #define   SLINK_TX_OVF                  (1 << 19)
96 #define   SLINK_TX_FULL                 (1 << 20)
97 #define   SLINK_TX_EMPTY                (1 << 21)
98 #define   SLINK_RX_FULL                 (1 << 22)
99 #define   SLINK_RX_EMPTY                (1 << 23)
100 #define   SLINK_TX_UNF                  (1 << 24)
101 #define   SLINK_RX_OVF                  (1 << 25)
102 #define   SLINK_TX_FLUSH                (1 << 26)
103 #define   SLINK_RX_FLUSH                (1 << 27)
104 #define   SLINK_SCLK                    (1 << 28)
105 #define   SLINK_ERR                     (1 << 29)
106 #define   SLINK_RDY                     (1 << 30)
107 #define   SLINK_BSY                     (1 << 31)
108
109 #define SLINK_MAS_DATA          0x010
110 #define SLINK_SLAVE_DATA        0x014
111
112 #define SLINK_DMA_CTL           0x018
113 #define   SLINK_DMA_BLOCK_SIZE(x)       (((x) & 0xffff) << 0)
114 #define   SLINK_TX_TRIG_1               (0 << 16)
115 #define   SLINK_TX_TRIG_4               (1 << 16)
116 #define   SLINK_TX_TRIG_8               (2 << 16)
117 #define   SLINK_TX_TRIG_16              (3 << 16)
118 #define   SLINK_TX_TRIG_MASK            (3 << 16)
119 #define   SLINK_RX_TRIG_1               (0 << 18)
120 #define   SLINK_RX_TRIG_4               (1 << 18)
121 #define   SLINK_RX_TRIG_8               (2 << 18)
122 #define   SLINK_RX_TRIG_16              (3 << 18)
123 #define   SLINK_RX_TRIG_MASK            (3 << 18)
124 #define   SLINK_PACKED                  (1 << 20)
125 #define   SLINK_PACK_SIZE_4             (0 << 21)
126 #define   SLINK_PACK_SIZE_8             (1 << 21)
127 #define   SLINK_PACK_SIZE_16            (2 << 21)
128 #define   SLINK_PACK_SIZE_32            (3 << 21)
129 #define   SLINK_PACK_SIZE_MASK          (3 << 21)
130 #define   SLINK_IE_TXC                  (1 << 26)
131 #define   SLINK_IE_RXC                  (1 << 27)
132 #define   SLINK_DMA_EN                  (1 << 31)
133
134 #define SLINK_STATUS2           0x01c
135 #define   SLINK_TX_FIFO_EMPTY_COUNT(val)        (((val) & 0x3f) >> 0)
136 #define   SLINK_RX_FIFO_FULL_COUNT(val)         (((val) & 0x3f0000) >> 16)
137 #define   SLINK_SS_HOLD_TIME(val)               (((val) & 0xF) << 6)
138
139 #define SLINK_TX_FIFO           0x100
140 #define SLINK_RX_FIFO           0x180
141
142 #define DATA_DIR_TX             (1 << 0)
143 #define DATA_DIR_RX             (1 << 1)
144
145 #define SPI_FIFO_DEPTH          32
146 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
147
148
149 static const unsigned long spi_tegra_req_sels[] = {
150         TEGRA_DMA_REQ_SEL_SL2B1,
151         TEGRA_DMA_REQ_SEL_SL2B2,
152         TEGRA_DMA_REQ_SEL_SL2B3,
153         TEGRA_DMA_REQ_SEL_SL2B4,
154 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
155         TEGRA_DMA_REQ_SEL_SL2B5,
156         TEGRA_DMA_REQ_SEL_SL2B6,
157 #endif
158
159 };
160
161 #define DEFAULT_SPI_DMA_BUF_LEN         (16*1024)
162 #define TX_FIFO_EMPTY_COUNT_MAX         SLINK_TX_FIFO_EMPTY_COUNT(0x20)
163 #define RX_FIFO_FULL_COUNT_ZERO         SLINK_RX_FIFO_FULL_COUNT(0)
164
165 #define SLINK_STATUS2_RESET \
166         (TX_FIFO_EMPTY_COUNT_MAX | \
167         RX_FIFO_FULL_COUNT_ZERO << 16)
168
169 #define MAX_CHIP_SELECT         4
170 #define SLINK_FIFO_DEPTH        4
171
172 struct spi_tegra_data {
173         struct spi_master       *master;
174         struct platform_device  *pdev;
175         spinlock_t              lock;
176         char                    port_name[32];
177
178         struct clk              *clk;
179         void __iomem            *base;
180         unsigned long           phys;
181         unsigned                irq;
182
183         u32                     cur_speed;
184
185         struct list_head        queue;
186         struct spi_transfer     *cur;
187         struct spi_device       *cur_spi;
188         unsigned                cur_pos;
189         unsigned                cur_len;
190         unsigned                words_per_32bit;
191         unsigned                bytes_per_word;
192         unsigned                curr_dma_words;
193
194         unsigned                cur_direction;
195
196         bool                    is_dma_allowed;
197
198         struct tegra_dma_req    rx_dma_req;
199         struct tegra_dma_channel *rx_dma;
200         u32                     *rx_buf;
201         dma_addr_t              rx_buf_phys;
202         unsigned                cur_rx_pos;
203
204         struct tegra_dma_req    tx_dma_req;
205         struct tegra_dma_channel *tx_dma;
206         u32                     *tx_buf;
207         dma_addr_t              tx_buf_phys;
208         unsigned                cur_tx_pos;
209
210         unsigned                dma_buf_size;
211         unsigned                max_buf_size;
212         bool                    is_curr_dma_xfer;
213
214         bool                    is_clkon_always;
215         bool                    clk_state;
216         bool                    is_suspended;
217
218         bool                    is_hw_based_cs;
219
220         struct completion       rx_dma_complete;
221         struct completion       tx_dma_complete;
222
223         u32                     rx_complete;
224         u32                     tx_complete;
225         u32                     tx_status;
226         u32                     rx_status;
227         u32                     status_reg;
228         bool                    is_packed;
229         unsigned long           packed_size;
230
231         u32                     command_reg;
232         u32                     command2_reg;
233         u32                     dma_control_reg;
234         u32                     def_command_reg;
235         u32                     def_command2_reg;
236
237         callback                client_slave_ready_cb;
238         void                    *client_data;
239
240         struct spi_clk_parent   *parent_clk_list;
241         int                     parent_clk_count;
242         unsigned long           max_rate;
243         unsigned long           max_parent_rate;
244         int                     min_div;
245 };
246
247 static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
248                     unsigned long reg)
249 {
250         if (!tspi->clk_state)
251                 BUG();
252         return readl(tspi->base + reg);
253 }
254
255 static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
256                     unsigned long val, unsigned long reg)
257 {
258         if (!tspi->clk_state)
259                 BUG();
260         writel(val, tspi->base + reg);
261 }
262
263 int spi_tegra_register_callback(struct spi_device *spi, callback func,
264                         void *client_data)
265 {
266         struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
267
268         if (!tspi || !func)
269                 return -EINVAL;
270         tspi->client_slave_ready_cb = func;
271         tspi->client_data = client_data;
272         return 0;
273 }
274 EXPORT_SYMBOL_GPL(spi_tegra_register_callback);
275
276 static void spi_tegra_clear_status(struct spi_tegra_data *tspi)
277 {
278         unsigned long val;
279         unsigned long val_write = 0;
280
281         val = spi_tegra_readl(tspi, SLINK_STATUS);
282
283         val_write = SLINK_RDY;
284         if (val & SLINK_TX_OVF)
285                 val_write |= SLINK_TX_OVF;
286         if (val & SLINK_RX_OVF)
287                 val_write |= SLINK_RX_OVF;
288         if (val & SLINK_RX_UNF)
289                 val_write |= SLINK_RX_UNF;
290         if (val & SLINK_TX_UNF)
291                 val_write |= SLINK_TX_UNF;
292
293         spi_tegra_writel(tspi, val_write, SLINK_STATUS);
294 }
295
296 static unsigned long spi_tegra_get_packed_size(struct spi_tegra_data *tspi,
297                                   struct spi_transfer *t)
298 {
299         unsigned long val;
300
301         switch (tspi->bytes_per_word) {
302         case 0:
303                 val = SLINK_PACK_SIZE_4;
304                 break;
305         case 1:
306                 val = SLINK_PACK_SIZE_8;
307                 break;
308         case 2:
309                 val = SLINK_PACK_SIZE_16;
310                 break;
311         case 4:
312                 val = SLINK_PACK_SIZE_32;
313                 break;
314         default:
315                 val = 0;
316         }
317         return val;
318 }
319
320 static unsigned spi_tegra_calculate_curr_xfer_param(
321         struct spi_device *spi, struct spi_tegra_data *tspi,
322         struct spi_transfer *t)
323 {
324         unsigned remain_len = t->len - tspi->cur_pos;
325         unsigned max_word;
326         unsigned bits_per_word ;
327         unsigned max_len;
328         unsigned total_fifo_words;
329
330         bits_per_word = t->bits_per_word ? t->bits_per_word :
331                                                 spi->bits_per_word;
332         tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1;
333
334         if (bits_per_word == 8 || bits_per_word == 16) {
335                 tspi->is_packed = 1;
336                 tspi->words_per_32bit = 32/bits_per_word;
337         } else {
338                 tspi->is_packed = 0;
339                 tspi->words_per_32bit = 1;
340         }
341         tspi->packed_size = spi_tegra_get_packed_size(tspi, t);
342
343         if (tspi->is_packed) {
344                 max_len = min(remain_len, tspi->max_buf_size);
345                 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
346                 total_fifo_words = remain_len/4;
347         } else {
348                 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
349                 max_word = min(max_word, tspi->max_buf_size/4);
350                 tspi->curr_dma_words = max_word;
351                 total_fifo_words = remain_len/tspi->bytes_per_word;
352         }
353         /* All transfer should be in one shot */
354         if (tspi->curr_dma_words * tspi->bytes_per_word != t->len) {
355                 dev_err(&tspi->pdev->dev, "The requested length can not be"
356                                         " transferred in one shot\n");
357                 BUG();
358         }
359         return total_fifo_words;
360 }
361
362 static unsigned spi_tegra_fill_tx_fifo_from_client_txbuf(
363         struct spi_tegra_data *tspi, struct spi_transfer *t)
364 {
365         unsigned nbytes;
366         unsigned tx_empty_count;
367         unsigned long fifo_status;
368         u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
369         unsigned max_n_32bit;
370         unsigned i, count;
371         unsigned long x;
372         unsigned int written_words;
373
374         fifo_status = spi_tegra_readl(tspi, SLINK_STATUS2);
375         tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
376
377         if (tspi->is_packed) {
378                 nbytes = tspi->curr_dma_words * tspi->bytes_per_word;
379                 max_n_32bit = (min(nbytes,  tx_empty_count*4) - 1)/4 + 1;
380                 for (count = 0; count < max_n_32bit; ++count) {
381                         x = 0;
382                         for (i = 0; (i < 4) && nbytes; i++, nbytes--)
383                                 x |= (*tx_buf++) << (i*8);
384                         spi_tegra_writel(tspi, x, SLINK_TX_FIFO);
385                 }
386                 written_words =  min(max_n_32bit * tspi->words_per_32bit,
387                                         tspi->curr_dma_words);
388         } else {
389                 max_n_32bit = min(tspi->curr_dma_words,  tx_empty_count);
390                 nbytes = max_n_32bit * tspi->bytes_per_word;
391                 for (count = 0; count < max_n_32bit; ++count) {
392                         x = 0;
393                         for (i = 0; nbytes && (i < tspi->bytes_per_word);
394                                                         ++i, nbytes--)
395                                 x |= ((*tx_buf++) << i*8);
396                         spi_tegra_writel(tspi, x, SLINK_TX_FIFO);
397                 }
398                 written_words = max_n_32bit;
399         }
400         tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
401         return written_words;
402 }
403
404 static unsigned int spi_tegra_read_rx_fifo_to_client_rxbuf(
405                 struct spi_tegra_data *tspi, struct spi_transfer *t)
406 {
407         unsigned rx_full_count;
408         unsigned long fifo_status;
409         u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
410         unsigned i, count;
411         unsigned long x;
412         unsigned int read_words;
413         unsigned len;
414
415         fifo_status = spi_tegra_readl(tspi, SLINK_STATUS2);
416         rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
417         dev_dbg(&tspi->pdev->dev, "Rx fifo count %d\n", rx_full_count);
418         if (tspi->is_packed) {
419                 len = tspi->curr_dma_words * tspi->bytes_per_word;
420                 for (count = 0; count < rx_full_count; ++count) {
421                         x = spi_tegra_readl(tspi, SLINK_RX_FIFO);
422                         for (i = 0; len && (i < 4); ++i, len--)
423                                 *rx_buf++ = (x >> i*8) & 0xFF;
424                 }
425                 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
426                 read_words += tspi->curr_dma_words;
427         } else {
428                 for (count = 0; count < rx_full_count; ++count) {
429                         x = spi_tegra_readl(tspi, SLINK_RX_FIFO);
430                         for (i = 0; (i < tspi->bytes_per_word); ++i)
431                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
432                 }
433                 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
434                 read_words += rx_full_count;
435         }
436         return read_words;
437 }
438
439 static void spi_tegra_copy_client_txbuf_to_spi_txbuf(
440                 struct spi_tegra_data *tspi, struct spi_transfer *t)
441 {
442         unsigned len;
443         if (tspi->is_packed) {
444                 len = tspi->curr_dma_words * tspi->bytes_per_word;
445                 memcpy(tspi->tx_buf, t->tx_buf + tspi->cur_pos, len);
446         } else {
447                 unsigned int i;
448                 unsigned int count;
449                 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
450                 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
451                 unsigned int x;
452
453                 for (count = 0; count < tspi->curr_dma_words; ++count) {
454                         x = 0;
455                         for (i = 0; consume && (i < tspi->bytes_per_word);
456                                                         ++i, consume--)
457                                 x |= ((*tx_buf++) << i*8);
458                         tspi->tx_buf[count] = x;
459                 }
460         }
461         tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
462 }
463
464 static void spi_tegra_copy_spi_rxbuf_to_client_rxbuf(
465                 struct spi_tegra_data *tspi, struct spi_transfer *t)
466 {
467         unsigned len;
468         if (tspi->is_packed) {
469                 len = tspi->curr_dma_words * tspi->bytes_per_word;
470                 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_buf, len);
471         } else {
472                 unsigned int i;
473                 unsigned int count;
474                 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
475                 unsigned int x;
476                 for (count = 0; count < tspi->curr_dma_words; ++count) {
477                         x = tspi->rx_buf[count];
478                         for (i = 0; (i < tspi->bytes_per_word); ++i)
479                                 *rx_buf++ = (x >> (i*8)) & 0xFF;
480                 }
481         }
482         tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
483 }
484
485 static int spi_tegra_start_dma_based_transfer(
486                 struct spi_tegra_data *tspi, struct spi_transfer *t)
487 {
488         unsigned long val;
489         unsigned long test_val;
490         unsigned int len;
491         int ret = 0;
492
493         INIT_COMPLETION(tspi->rx_dma_complete);
494         INIT_COMPLETION(tspi->tx_dma_complete);
495
496         val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
497         val |= tspi->packed_size;
498         if (tspi->is_packed)
499                 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
500                                         4) * 4;
501         else
502                 len = tspi->curr_dma_words * 4;
503
504         if (len & 0xF)
505                 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
506         else if (((len) >> 4) & 0x1)
507                 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
508         else
509                 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
510
511         if (tspi->cur_direction & DATA_DIR_TX)
512                 val |= SLINK_IE_TXC;
513
514         if (tspi->cur_direction & DATA_DIR_RX)
515                 val |= SLINK_IE_RXC;
516
517         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
518         tspi->dma_control_reg = val;
519
520         if (tspi->cur_direction & DATA_DIR_TX) {
521                 spi_tegra_copy_client_txbuf_to_spi_txbuf(tspi, t);
522                 wmb();
523                 tspi->tx_dma_req.size = len;
524                 ret = tegra_dma_enqueue_req(tspi->tx_dma, &tspi->tx_dma_req);
525                 if (ret < 0) {
526                         dev_err(&tspi->pdev->dev, "Error in starting tx dma "
527                                                 " error = %d\n", ret);
528                         return ret;
529                 }
530
531                 /* Wait for tx fifo to be fill before starting slink */
532                 test_val = spi_tegra_readl(tspi, SLINK_STATUS);
533                 while (!(test_val & SLINK_TX_FULL))
534                         test_val = spi_tegra_readl(tspi, SLINK_STATUS);
535         }
536
537         if (tspi->cur_direction & DATA_DIR_RX) {
538                 tspi->rx_dma_req.size = len;
539                 ret = tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
540                 if (ret < 0) {
541                         dev_err(&tspi->pdev->dev, "Error in starting rx dma "
542                                                 " error = %d\n", ret);
543                         if (tspi->cur_direction & DATA_DIR_TX)
544                                 tegra_dma_dequeue_req(tspi->tx_dma,
545                                                         &tspi->tx_dma_req);
546                         return ret;
547                 }
548         }
549         tspi->is_curr_dma_xfer = true;
550         if (tspi->is_packed) {
551                 val |= SLINK_PACKED;
552                 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
553                 udelay(1);
554                 wmb();
555         }
556
557         val |= SLINK_DMA_EN;
558         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
559         return ret;
560 }
561
562 static int spi_tegra_start_cpu_based_transfer(
563                 struct spi_tegra_data *tspi, struct spi_transfer *t)
564 {
565         unsigned long val;
566         unsigned curr_words;
567
568         val = tspi->packed_size;
569         if (tspi->cur_direction & DATA_DIR_TX)
570                 val |= SLINK_IE_TXC;
571
572         if (tspi->cur_direction & DATA_DIR_RX)
573                 val |= SLINK_IE_RXC;
574
575         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
576         tspi->dma_control_reg = val;
577
578         if (tspi->cur_direction & DATA_DIR_TX)
579                 curr_words = spi_tegra_fill_tx_fifo_from_client_txbuf(tspi, t);
580         else
581                 curr_words = tspi->curr_dma_words;
582         val |= SLINK_DMA_BLOCK_SIZE(curr_words - 1);
583         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
584         tspi->dma_control_reg = val;
585
586         tspi->is_curr_dma_xfer = false;
587         if (tspi->is_packed) {
588                 val |= SLINK_PACKED;
589                 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
590                 udelay(1);
591                 wmb();
592         }
593         val |= SLINK_DMA_EN;
594         spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
595         return 0;
596 }
597
598 static void set_best_clk_source(struct spi_tegra_data *tspi,
599                 unsigned long speed)
600 {
601         long new_rate;
602         unsigned long err_rate;
603         int rate = speed * 4;
604         unsigned int fin_err = speed * 4;
605         int final_index = -1;
606         int count;
607         int ret;
608         struct clk *pclk;
609         unsigned long prate, crate, nrate;
610         unsigned long cdiv;
611
612         if (!tspi->parent_clk_count || !tspi->parent_clk_list)
613                 return;
614
615         /* make sure divisor is more than min_div */
616         pclk = clk_get_parent(tspi->clk);
617         prate = clk_get_rate(pclk);
618         crate = clk_get_rate(tspi->clk);
619         cdiv = DIV_ROUND_UP(prate, crate);
620         if (cdiv < tspi->min_div) {
621                 nrate = DIV_ROUND_UP(prate, tspi->min_div);
622                 clk_set_rate(tspi->clk, nrate);
623         }
624
625         for (count = 0; count < tspi->parent_clk_count; ++count) {
626                 if (!tspi->parent_clk_list[count].parent_clk)
627                         continue;
628                 ret = clk_set_parent(tspi->clk,
629                         tspi->parent_clk_list[count].parent_clk);
630                 if (ret < 0) {
631                         dev_warn(&tspi->pdev->dev, "Error in setting parent "
632                                 " clk src %s\n",
633                                 tspi->parent_clk_list[count].name);
634                         continue;
635                 }
636
637                 new_rate = clk_round_rate(tspi->clk, rate);
638                 if (new_rate < 0)
639                         continue;
640
641                 err_rate = abs(new_rate - rate);
642                 if (err_rate < fin_err) {
643                         final_index = count;
644                         fin_err = err_rate;
645                 }
646         }
647
648         if (final_index >= 0) {
649                 dev_info(&tspi->pdev->dev, "Setting clk_src %s\n",
650                                 tspi->parent_clk_list[final_index].name);
651                 clk_set_parent(tspi->clk,
652                         tspi->parent_clk_list[final_index].parent_clk);
653         }
654 }
655
656 static void spi_tegra_start_transfer(struct spi_device *spi,
657                     struct spi_transfer *t)
658 {
659         struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
660         u32 speed;
661         u8 bits_per_word;
662         unsigned total_fifo_words;
663         int ret;
664         unsigned long command;
665         unsigned long command2;
666
667         unsigned int cs_pol_bit[] = {
668                         SLINK_CS_POLARITY,
669                         SLINK_CS_POLARITY1,
670                         SLINK_CS_POLARITY2,
671                         SLINK_CS_POLARITY3,
672         };
673
674         bits_per_word = t->bits_per_word ? t->bits_per_word :
675                                         spi->bits_per_word;
676
677         speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
678         if (speed != tspi->cur_speed) {
679                 set_best_clk_source(tspi, speed);
680                 clk_set_rate(tspi->clk, speed * 4);
681                 tspi->cur_speed = speed;
682         }
683
684         tspi->cur = t;
685         tspi->cur_spi = spi;
686         tspi->cur_pos = 0;
687         tspi->cur_rx_pos = 0;
688         tspi->cur_tx_pos = 0;
689         tspi->rx_complete = 0;
690         tspi->tx_complete = 0;
691         total_fifo_words = spi_tegra_calculate_curr_xfer_param(spi, tspi, t);
692
693         command2 = tspi->def_command2_reg;
694         if (!tspi->is_clkon_always) {
695                 if (!tspi->clk_state) {
696                         clk_enable(tspi->clk);
697                         tspi->clk_state = 1;
698                 }
699         }
700
701         spi_tegra_clear_status(tspi);
702
703         command = tspi->def_command_reg;
704         command |= SLINK_BIT_LENGTH(bits_per_word - 1);
705
706         command |= SLINK_CS_SW;
707
708         command &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA;
709         if (spi->mode & SPI_CPHA)
710                 command |= SLINK_CK_SDA;
711
712         if (spi->mode & SPI_CPOL)
713                 command |= SLINK_IDLE_SCLK_DRIVE_HIGH;
714         else
715                 command |= SLINK_IDLE_SCLK_DRIVE_LOW;
716
717         spi_tegra_writel(tspi, command, SLINK_COMMAND);
718         tspi->command_reg = command;
719
720         dev_dbg(&tspi->pdev->dev, "The def 0x%x and written 0x%lx\n",
721                                 tspi->def_command_reg, command);
722
723         command2 &= ~(SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN);
724         tspi->cur_direction = 0;
725         if (t->rx_buf) {
726                 command2 |= SLINK_RXEN;
727                 tspi->cur_direction |= DATA_DIR_RX;
728         }
729         if (t->tx_buf) {
730                 command2 |= SLINK_TXEN;
731                 tspi->cur_direction |= DATA_DIR_TX;
732         }
733         command2 |= SLINK_SS_EN_CS(spi->chip_select);
734         spi_tegra_writel(tspi, command2, SLINK_COMMAND2);
735         tspi->command2_reg = command2;
736
737         if (total_fifo_words > SPI_FIFO_DEPTH)
738                 ret = spi_tegra_start_dma_based_transfer(tspi, t);
739         else
740                 ret = spi_tegra_start_cpu_based_transfer(tspi, t);
741         WARN_ON(ret < 0);
742
743         if (tspi->client_slave_ready_cb)
744                 tspi->client_slave_ready_cb(tspi->client_data);
745 }
746
747 static void spi_tegra_start_message(struct spi_device *spi,
748                                     struct spi_message *m)
749 {
750         struct spi_transfer *t;
751         m->actual_length = 0;
752         m->status = 0;
753         t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
754         spi_tegra_start_transfer(spi, t);
755 }
756
757 static int spi_tegra_setup(struct spi_device *spi)
758 {
759         struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
760         unsigned long cs_bit;
761         unsigned long val;
762         unsigned long flags;
763
764         dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
765                 spi->bits_per_word,
766                 spi->mode & SPI_CPOL ? "" : "~",
767                 spi->mode & SPI_CPHA ? "" : "~",
768                 spi->max_speed_hz);
769
770         BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
771         switch (spi->chip_select) {
772         case 0:
773                 cs_bit = SLINK_CS_POLARITY;
774                 break;
775
776         case 1:
777                 cs_bit = SLINK_CS_POLARITY1;
778                 break;
779
780         case 2:
781                 cs_bit = SLINK_CS_POLARITY2;
782                 break;
783
784         case 3:
785                 cs_bit = SLINK_CS_POLARITY3;
786                 break;
787
788         default:
789                 return -EINVAL;
790         }
791
792         spin_lock_irqsave(&tspi->lock, flags);
793         val = tspi->def_command_reg;
794         if (spi->mode & SPI_CS_HIGH)
795                 val |= cs_bit;
796         else
797                 val &= ~cs_bit;
798         tspi->def_command_reg |= val;
799
800         if (!tspi->is_clkon_always && !tspi->clk_state) {
801                 clk_enable(tspi->clk);
802                 tspi->clk_state = 1;
803         }
804         spi_tegra_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
805         if (!tspi->is_clkon_always && tspi->clk_state) {
806                 clk_disable(tspi->clk);
807                 tspi->clk_state = 0;
808         }
809
810         spin_unlock_irqrestore(&tspi->lock, flags);
811         return 0;
812 }
813
814 static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m)
815 {
816         struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
817         struct spi_transfer *t;
818         unsigned long flags;
819         int was_empty;
820         int bytes_per_word;
821         u8 bits_per_word;
822         int fifo_word;
823
824         /* Support only one transfer per message */
825         if (!list_is_singular(&m->transfers))
826                 return -EINVAL;
827
828         if (list_empty(&m->transfers) || !m->complete)
829                 return -EINVAL;
830
831         t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
832         if (t->bits_per_word < 0 || t->bits_per_word > 32)
833                 return -EINVAL;
834
835         if (t->len == 0)
836                 return -EINVAL;
837
838         bits_per_word = (t->bits_per_word) ? : spi->bits_per_word;
839
840         /* Check that the all words are available */
841         bytes_per_word = (bits_per_word + 7)/8;
842
843         if (t->len % bytes_per_word != 0)
844                 return -EINVAL;
845
846         if (!t->rx_buf && !t->tx_buf)
847                 return -EINVAL;
848
849         if ((bits_per_word == 8) || (bits_per_word == 16))
850                 fifo_word = t->len/4;
851         else
852                 fifo_word = t->len/bytes_per_word;
853         if (fifo_word >= tspi->max_buf_size/4)
854                 return -EINVAL;
855
856         spin_lock_irqsave(&tspi->lock, flags);
857
858         if (WARN_ON(tspi->is_suspended)) {
859                 spin_unlock_irqrestore(&tspi->lock, flags);
860                 return -EBUSY;
861         }
862
863         m->state = spi;
864
865         was_empty = list_empty(&tspi->queue);
866         list_add_tail(&m->queue, &tspi->queue);
867
868         if (was_empty)
869                 spi_tegra_start_message(spi, m);
870
871         spin_unlock_irqrestore(&tspi->lock, flags);
872
873         return 0;
874 }
875
876 static void spi_tegra_curr_transfer_complete(struct spi_tegra_data *tspi,
877         unsigned err, unsigned cur_xfer_size)
878 {
879         struct spi_message *m;
880         struct spi_device *spi;
881
882         m = list_first_entry(&tspi->queue, struct spi_message, queue);
883         if (err)
884                 m->status = -EIO;
885         spi = m->state;
886
887         m->actual_length += cur_xfer_size;
888         list_del(&m->queue);
889         m->complete(m->context);
890         if (!list_empty(&tspi->queue)) {
891                 m = list_first_entry(&tspi->queue, struct spi_message, queue);
892                 spi = m->state;
893                 spi_tegra_start_message(spi, m);
894         } else {
895                 spi_tegra_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
896                 spi_tegra_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
897                 if (!tspi->is_clkon_always) {
898                         if (tspi->clk_state) {
899                                 /* Provide delay to stablize the signal
900                                    state */
901                                 udelay(10);
902                                 clk_disable(tspi->clk);
903                                 tspi->clk_state = 0;
904                         }
905                 }
906         }
907 }
908
909 static void tegra_spi_tx_dma_complete(struct tegra_dma_req *req)
910 {
911         struct spi_tegra_data *tspi = req->dev;
912         complete(&tspi->tx_dma_complete);
913 }
914
915 static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
916 {
917         struct spi_tegra_data *tspi = req->dev;
918         complete(&tspi->rx_dma_complete);
919 }
920
921 static void handle_cpu_based_xfer(void *context_data)
922 {
923         struct spi_tegra_data *tspi = context_data;
924         struct spi_transfer *t = tspi->cur;
925         unsigned long flags;
926
927         spin_lock_irqsave(&tspi->lock, flags);
928         if (tspi->tx_status ||  tspi->rx_status ||
929                                 (tspi->status_reg & SLINK_BSY)) {
930                 dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n",
931                                          __func__, tspi->status_reg);
932                 tegra_periph_reset_assert(tspi->clk);
933                 udelay(2);
934                 tegra_periph_reset_deassert(tspi->clk);
935                 WARN_ON(1);
936                 spi_tegra_curr_transfer_complete(tspi,
937                                 tspi->tx_status ||  tspi->rx_status, t->len);
938                 goto exit;
939         }
940
941         dev_vdbg(&tspi->pdev->dev, " Current direction %x\n",
942                                                 tspi->cur_direction);
943         if (tspi->cur_direction & DATA_DIR_RX)
944                 spi_tegra_read_rx_fifo_to_client_rxbuf(tspi, t);
945
946         if (tspi->cur_direction & DATA_DIR_TX)
947                 tspi->cur_pos = tspi->cur_tx_pos;
948         else if (tspi->cur_direction & DATA_DIR_RX)
949                 tspi->cur_pos = tspi->cur_rx_pos;
950         else
951                 WARN_ON(1);
952
953         dev_vdbg(&tspi->pdev->dev, "current position %d and length of the "
954                                 "transfer %d\n", tspi->cur_pos, t->len);
955         if (tspi->cur_pos == t->len) {
956                 spi_tegra_curr_transfer_complete(tspi,
957                         tspi->tx_status || tspi->rx_status, t->len);
958                 goto exit;
959         }
960
961         /* There should not be remaining transfer */
962         BUG();
963 exit:
964         spin_unlock_irqrestore(&tspi->lock, flags);
965         return;
966 }
967
968 static irqreturn_t spi_tegra_isr_thread(int irq, void *context_data)
969 {
970         struct spi_tegra_data *tspi = context_data;
971         struct spi_transfer *t = tspi->cur;
972         long wait_status;
973         int err = 0;
974         unsigned long flags;
975
976         if (!tspi->is_curr_dma_xfer) {
977                 handle_cpu_based_xfer(context_data);
978                 return IRQ_HANDLED;
979         }
980
981         /* Abort dmas if any error */
982         if (tspi->cur_direction & DATA_DIR_TX) {
983                 if (tspi->tx_status) {
984                         tegra_dma_dequeue(tspi->tx_dma);
985                         err += 1;
986                 } else {
987                         wait_status = wait_for_completion_interruptible_timeout(
988                                 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
989                         if (wait_status <= 0) {
990                                 tegra_dma_dequeue(tspi->tx_dma);
991                                 dev_err(&tspi->pdev->dev, "Error in Dma Tx "
992                                                         "transfer\n");
993                                 err += 1;
994                         }
995                 }
996         }
997
998         if (tspi->cur_direction & DATA_DIR_RX) {
999                 if (tspi->rx_status) {
1000                         tegra_dma_dequeue(tspi->rx_dma);
1001                         err += 2;
1002                 } else {
1003                         wait_status = wait_for_completion_interruptible_timeout(
1004                                 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
1005                         if (wait_status <= 0) {
1006                                 tegra_dma_dequeue(tspi->rx_dma);
1007                                 dev_err(&tspi->pdev->dev, "Error in Dma Rx "
1008                                                         "transfer\n");
1009                                 err += 2;
1010                         }
1011                 }
1012         }
1013
1014         spin_lock_irqsave(&tspi->lock, flags);
1015         if (err) {
1016                 dev_err(&tspi->pdev->dev, "%s ERROR bit set 0x%x\n",
1017                                          __func__, tspi->status_reg);
1018                 tegra_periph_reset_assert(tspi->clk);
1019                 udelay(2);
1020                 tegra_periph_reset_deassert(tspi->clk);
1021                 WARN_ON(1);
1022                 spi_tegra_curr_transfer_complete(tspi, err, t->len);
1023                 spin_unlock_irqrestore(&tspi->lock, flags);
1024                 return IRQ_HANDLED;
1025         }
1026
1027         if (tspi->cur_direction & DATA_DIR_RX)
1028                 spi_tegra_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1029
1030         if (tspi->cur_direction & DATA_DIR_TX)
1031                 tspi->cur_pos = tspi->cur_tx_pos;
1032         else if (tspi->cur_direction & DATA_DIR_RX)
1033                 tspi->cur_pos = tspi->cur_rx_pos;
1034         else
1035                 WARN_ON(1);
1036
1037         if (tspi->cur_pos == t->len) {
1038                 spi_tegra_curr_transfer_complete(tspi,
1039                         tspi->tx_status || tspi->rx_status, t->len);
1040                 spin_unlock_irqrestore(&tspi->lock, flags);
1041                 return IRQ_HANDLED;
1042         }
1043
1044         spin_unlock_irqrestore(&tspi->lock, flags);
1045
1046         /* There should not be remaining transfer */
1047         BUG();
1048         return IRQ_HANDLED;
1049 }
1050
1051 static irqreturn_t spi_tegra_isr(int irq, void *context_data)
1052 {
1053         struct spi_tegra_data *tspi = context_data;
1054
1055         tspi->status_reg = spi_tegra_readl(tspi, SLINK_STATUS);
1056         if (tspi->cur_direction & DATA_DIR_TX)
1057                 tspi->tx_status = tspi->status_reg &
1058                                         (SLINK_TX_OVF | SLINK_TX_UNF);
1059
1060         if (tspi->cur_direction & DATA_DIR_RX)
1061                 tspi->rx_status = tspi->status_reg &
1062                                         (SLINK_RX_OVF | SLINK_RX_UNF);
1063         spi_tegra_clear_status(tspi);
1064
1065
1066         return IRQ_WAKE_THREAD;
1067 }
1068
1069 static int __init spi_tegra_probe(struct platform_device *pdev)
1070 {
1071         struct spi_master       *master;
1072         struct spi_tegra_data   *tspi;
1073         struct resource         *r;
1074         struct tegra_spi_platform_data *pdata = pdev->dev.platform_data;
1075         int ret;
1076         int i;
1077
1078         master = spi_alloc_master(&pdev->dev, sizeof *tspi);
1079         if (master == NULL) {
1080                 dev_err(&pdev->dev, "master allocation failed\n");
1081                 return -ENOMEM;
1082         }
1083
1084         /* the spi->mode bits understood by this driver: */
1085         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1086
1087         if (pdev->id != -1)
1088                 master->bus_num = pdev->id;
1089
1090         master->setup = spi_tegra_setup;
1091         master->transfer = spi_tegra_transfer;
1092         master->num_chipselect = MAX_CHIP_SELECT;
1093
1094         dev_set_drvdata(&pdev->dev, master);
1095         tspi = spi_master_get_devdata(master);
1096         tspi->master = master;
1097         tspi->pdev = pdev;
1098         spin_lock_init(&tspi->lock);
1099
1100         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1101         if (r == NULL) {
1102                 ret = -ENODEV;
1103                 goto fail_no_mem;
1104         }
1105
1106         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1107                                 dev_name(&pdev->dev))) {
1108                 ret = -EBUSY;
1109                 goto fail_no_mem;
1110         }
1111
1112         tspi->phys = r->start;
1113         tspi->base = ioremap(r->start, r->end - r->start + 1);
1114         if (!tspi->base) {
1115                 dev_err(&pdev->dev, "can't ioremap iomem\n");
1116                 ret = -ENOMEM;
1117                 goto fail_io_map;
1118         }
1119
1120         tspi->irq = platform_get_irq(pdev, 0);
1121         if (unlikely(tspi->irq < 0)) {
1122                 dev_err(&pdev->dev, "can't find irq resource\n");
1123                 ret = -ENXIO;
1124                 goto fail_irq_req;
1125         }
1126
1127         sprintf(tspi->port_name, "tegra_spi_%d", pdev->id);
1128         ret = request_threaded_irq(tspi->irq, spi_tegra_isr,
1129                         spi_tegra_isr_thread, IRQF_DISABLED,
1130                         tspi->port_name, tspi);
1131         if (ret < 0) {
1132                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1133                                         tspi->irq);
1134                 goto fail_irq_req;
1135         }
1136
1137         tspi->clk = clk_get(&pdev->dev, NULL);
1138         if (IS_ERR_OR_NULL(tspi->clk)) {
1139                 dev_err(&pdev->dev, "can not get clock\n");
1140                 ret = PTR_ERR(tspi->clk);
1141                 goto fail_clk_get;
1142         }
1143
1144         INIT_LIST_HEAD(&tspi->queue);
1145
1146         if (pdata) {
1147                 tspi->is_clkon_always = pdata->is_clkon_always;
1148                 tspi->is_dma_allowed = pdata->is_dma_based;
1149                 tspi->dma_buf_size = (pdata->max_dma_buffer) ?
1150                                 pdata->max_dma_buffer : DEFAULT_SPI_DMA_BUF_LEN;
1151                 tspi->parent_clk_count = pdata->parent_clk_count;
1152                 tspi->parent_clk_list = pdata->parent_clk_list;
1153                 tspi->max_rate = pdata->max_rate;
1154         } else {
1155                 tspi->is_clkon_always = false;
1156                 tspi->is_dma_allowed = true;
1157                 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1158                 tspi->parent_clk_count = 0;
1159                 tspi->parent_clk_list = NULL;
1160                 tspi->max_rate = 0;
1161         }
1162
1163         tspi->max_parent_rate = 0;
1164         tspi->min_div = 0;
1165
1166         if (tspi->parent_clk_count) {
1167                 tspi->max_parent_rate = tspi->parent_clk_list[0].fixed_clk_rate;
1168                 for (i = 1; i < tspi->parent_clk_count; ++i) {
1169                         tspi->max_parent_rate = max(tspi->max_parent_rate,
1170                                 tspi->parent_clk_list[i].fixed_clk_rate);
1171                 }
1172                 if (tspi->max_rate)
1173                         tspi->min_div = DIV_ROUND_UP(tspi->max_parent_rate,
1174                                                 tspi->max_rate);
1175         }
1176         tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1177
1178         if (!tspi->is_dma_allowed)
1179                 goto skip_dma_alloc;
1180
1181         init_completion(&tspi->tx_dma_complete);
1182         init_completion(&tspi->rx_dma_complete);
1183
1184
1185         tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT,
1186                                 "spi_rx_%d", pdev->id);
1187         if (!tspi->rx_dma) {
1188                 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
1189                 ret = -ENODEV;
1190                 goto fail_rx_dma_alloc;
1191         }
1192
1193         tspi->rx_buf = dma_alloc_coherent(&pdev->dev, tspi->dma_buf_size,
1194                                          &tspi->rx_buf_phys, GFP_KERNEL);
1195         if (!tspi->rx_buf) {
1196                 dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
1197                 ret = -ENOMEM;
1198                 goto fail_rx_buf_alloc;
1199         }
1200
1201         memset(&tspi->rx_dma_req, 0, sizeof(struct tegra_dma_req));
1202         tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
1203         tspi->rx_dma_req.to_memory = 1;
1204         tspi->rx_dma_req.dest_addr = tspi->rx_buf_phys;
1205         tspi->rx_dma_req.virt_addr = tspi->rx_buf;
1206         tspi->rx_dma_req.dest_bus_width = 32;
1207         tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
1208         tspi->rx_dma_req.source_bus_width = 32;
1209         tspi->rx_dma_req.source_wrap = 4;
1210         tspi->rx_dma_req.dest_wrap = 0;
1211         tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
1212         tspi->rx_dma_req.dev = tspi;
1213
1214         tspi->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT,
1215                                 "spi_tx_%d", pdev->id);
1216         if (!tspi->tx_dma) {
1217                 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
1218                 ret = -ENODEV;
1219                 goto fail_tx_dma_alloc;
1220         }
1221
1222         tspi->tx_buf = dma_alloc_coherent(&pdev->dev, tspi->dma_buf_size,
1223                                          &tspi->tx_buf_phys, GFP_KERNEL);
1224         if (!tspi->tx_buf) {
1225                 dev_err(&pdev->dev, "can not allocate tx bounce buffer\n");
1226                 ret = -ENOMEM;
1227                 goto fail_tx_buf_alloc;
1228         }
1229
1230         memset(&tspi->tx_dma_req, 0, sizeof(struct tegra_dma_req));
1231         tspi->tx_dma_req.complete = tegra_spi_tx_dma_complete;
1232         tspi->tx_dma_req.to_memory = 0;
1233         tspi->tx_dma_req.dest_addr = tspi->phys + SLINK_TX_FIFO;
1234         tspi->tx_dma_req.virt_addr = tspi->tx_buf;
1235         tspi->tx_dma_req.dest_bus_width = 32;
1236         tspi->tx_dma_req.dest_wrap = 4;
1237         tspi->tx_dma_req.source_wrap = 0;
1238         tspi->tx_dma_req.source_addr = tspi->tx_buf_phys;
1239         tspi->tx_dma_req.source_bus_width = 32;
1240         tspi->tx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
1241         tspi->tx_dma_req.dev = tspi;
1242         tspi->max_buf_size = tspi->dma_buf_size;
1243         tspi->def_command_reg  = SLINK_CS_SW;
1244         tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1245
1246 skip_dma_alloc:
1247         clk_enable(tspi->clk);
1248         tspi->clk_state = 1;
1249         spi_tegra_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1250         ret = spi_register_master(master);
1251         if (!tspi->is_clkon_always) {
1252                 if (tspi->clk_state) {
1253                         clk_disable(tspi->clk);
1254                         tspi->clk_state = 0;
1255                 }
1256         }
1257
1258         if (ret < 0) {
1259                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1260                 goto fail_master_register;
1261         }
1262         return ret;
1263
1264 fail_master_register:
1265         if (tspi->tx_buf)
1266                 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1267                                 tspi->tx_buf, tspi->tx_buf_phys);
1268 fail_tx_buf_alloc:
1269         if (tspi->tx_dma)
1270                 tegra_dma_free_channel(tspi->tx_dma);
1271 fail_tx_dma_alloc:
1272         if (tspi->rx_buf)
1273                 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1274                           tspi->rx_buf, tspi->rx_buf_phys);
1275 fail_rx_buf_alloc:
1276         if (tspi->rx_dma)
1277                 tegra_dma_free_channel(tspi->rx_dma);
1278 fail_rx_dma_alloc:
1279         clk_put(tspi->clk);
1280 fail_clk_get:
1281         free_irq(tspi->irq, tspi);
1282 fail_irq_req:
1283         iounmap(tspi->base);
1284 fail_io_map:
1285         release_mem_region(r->start, (r->end - r->start) + 1);
1286 fail_no_mem:
1287         spi_master_put(master);
1288         return ret;
1289 }
1290
1291 static int __devexit spi_tegra_remove(struct platform_device *pdev)
1292 {
1293         struct spi_master       *master;
1294         struct spi_tegra_data   *tspi;
1295         struct resource         *r;
1296
1297         master = dev_get_drvdata(&pdev->dev);
1298         tspi = spi_master_get_devdata(master);
1299
1300         if (tspi->tx_buf)
1301                 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1302                                 tspi->tx_buf, tspi->tx_buf_phys);
1303         if (tspi->tx_dma)
1304                 tegra_dma_free_channel(tspi->tx_dma);
1305         if (tspi->rx_buf)
1306                 dma_free_coherent(&pdev->dev, tspi->dma_buf_size,
1307                           tspi->rx_buf, tspi->rx_buf_phys);
1308         if (tspi->rx_dma)
1309                 tegra_dma_free_channel(tspi->rx_dma);
1310
1311         if (tspi->is_clkon_always) {
1312                 clk_disable(tspi->clk);
1313                 tspi->clk_state = 0;
1314         }
1315
1316         clk_put(tspi->clk);
1317         iounmap(tspi->base);
1318
1319         spi_master_put(master);
1320         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1321         release_mem_region(r->start, (r->end - r->start) + 1);
1322
1323         return 0;
1324 }
1325
1326 #ifdef CONFIG_PM
1327 static int spi_tegra_suspend(struct platform_device *pdev, pm_message_t state)
1328 {
1329         struct spi_master       *master;
1330         struct spi_tegra_data   *tspi;
1331         unsigned long           flags;
1332         unsigned                limit = 50;
1333
1334         master = dev_get_drvdata(&pdev->dev);
1335         tspi = spi_master_get_devdata(master);
1336         spin_lock_irqsave(&tspi->lock, flags);
1337         tspi->is_suspended = true;
1338
1339         WARN_ON(!list_empty(&tspi->queue));
1340
1341         while (!list_empty(&tspi->queue) && limit--) {
1342                 spin_unlock_irqrestore(&tspi->lock, flags);
1343                 msleep(20);
1344                 spin_lock_irqsave(&tspi->lock, flags);
1345         }
1346
1347         spin_unlock_irqrestore(&tspi->lock, flags);
1348         if (tspi->is_clkon_always) {
1349                 clk_disable(tspi->clk);
1350                 tspi->clk_state = 0;
1351         }
1352         return 0;
1353 }
1354
1355 static int spi_tegra_resume(struct platform_device *pdev)
1356 {
1357         struct spi_master       *master;
1358         struct spi_tegra_data   *tspi;
1359         unsigned long           flags;
1360
1361         master = dev_get_drvdata(&pdev->dev);
1362         tspi = spi_master_get_devdata(master);
1363
1364         spin_lock_irqsave(&tspi->lock, flags);
1365         clk_enable(tspi->clk);
1366         tspi->clk_state = 1;
1367         spi_tegra_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1368         if (!tspi->is_clkon_always) {
1369                 clk_disable(tspi->clk);
1370                 tspi->clk_state = 0;
1371         }
1372
1373         tspi->cur_speed = 0;
1374         tspi->is_suspended = false;
1375         spin_unlock_irqrestore(&tspi->lock, flags);
1376         return 0;
1377 }
1378 #endif
1379
1380 MODULE_ALIAS("platform:spi_slave_tegra");
1381
1382 static struct platform_driver spi_tegra_driver = {
1383         .driver = {
1384                 .name =         "spi_slave_tegra",
1385                 .owner =        THIS_MODULE,
1386         },
1387         .remove =       __devexit_p(spi_tegra_remove),
1388 #ifdef CONFIG_PM
1389         .suspend =      spi_tegra_suspend,
1390         .resume  =      spi_tegra_resume,
1391 #endif
1392 };
1393
1394 static int __init spi_tegra_init(void)
1395 {
1396         return platform_driver_probe(&spi_tegra_driver, spi_tegra_probe);
1397 }
1398 subsys_initcall(spi_tegra_init);
1399
1400 static void __exit spi_tegra_exit(void)
1401 {
1402         platform_driver_unregister(&spi_tegra_driver);
1403 }
1404 module_exit(spi_tegra_exit);
1405
1406 MODULE_LICENSE("GPL");