igbvf: do not modify tx_queue_len on link speed change
[linux-2.6.git] / drivers / spi / spi_mpc8xxx.c
1 /*
2  * MPC8xxx SPI controller driver.
3  *
4  * Maintainer: Kumar Gala
5  *
6  * Copyright (C) 2006 Polycom, Inc.
7  *
8  * CPM SPI and QE buffer descriptors mode support:
9  * Copyright (c) 2009  MontaVista Software, Inc.
10  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
11  *
12  * This program is free software; you can redistribute  it and/or modify it
13  * under  the terms of  the GNU General  Public License as published by the
14  * Free Software Foundation;  either version 2 of the  License, or (at your
15  * option) any later version.
16  */
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/bug.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/completion.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28 #include <linux/irq.h>
29 #include <linux/device.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/platform_device.h>
33 #include <linux/fsl_devices.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/mm.h>
36 #include <linux/mutex.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
41 #include <linux/of_spi.h>
42
43 #include <sysdev/fsl_soc.h>
44 #include <asm/cpm.h>
45 #include <asm/qe.h>
46 #include <asm/irq.h>
47
48 /* CPM1 and CPM2 are mutually exclusive. */
49 #ifdef CONFIG_CPM1
50 #include <asm/cpm1.h>
51 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
52 #else
53 #include <asm/cpm2.h>
54 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
55 #endif
56
57 /* SPI Controller registers */
58 struct mpc8xxx_spi_reg {
59         u8 res1[0x20];
60         __be32 mode;
61         __be32 event;
62         __be32 mask;
63         __be32 command;
64         __be32 transmit;
65         __be32 receive;
66 };
67
68 /* SPI Parameter RAM */
69 struct spi_pram {
70         __be16  rbase;  /* Rx Buffer descriptor base address */
71         __be16  tbase;  /* Tx Buffer descriptor base address */
72         u8      rfcr;   /* Rx function code */
73         u8      tfcr;   /* Tx function code */
74         __be16  mrblr;  /* Max receive buffer length */
75         __be32  rstate; /* Internal */
76         __be32  rdp;    /* Internal */
77         __be16  rbptr;  /* Internal */
78         __be16  rbc;    /* Internal */
79         __be32  rxtmp;  /* Internal */
80         __be32  tstate; /* Internal */
81         __be32  tdp;    /* Internal */
82         __be16  tbptr;  /* Internal */
83         __be16  tbc;    /* Internal */
84         __be32  txtmp;  /* Internal */
85         __be32  res;    /* Tx temp. */
86         __be16  rpbase; /* Relocation pointer (CPM1 only) */
87         __be16  res1;   /* Reserved */
88 };
89
90 /* SPI Controller mode register definitions */
91 #define SPMODE_LOOP             (1 << 30)
92 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
93 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
94 #define SPMODE_DIV16            (1 << 27)
95 #define SPMODE_REV              (1 << 26)
96 #define SPMODE_MS               (1 << 25)
97 #define SPMODE_ENABLE           (1 << 24)
98 #define SPMODE_LEN(x)           ((x) << 20)
99 #define SPMODE_PM(x)            ((x) << 16)
100 #define SPMODE_OP               (1 << 14)
101 #define SPMODE_CG(x)            ((x) << 7)
102
103 /*
104  * Default for SPI Mode:
105  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
106  */
107 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
108                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
109
110 /* SPIE register values */
111 #define SPIE_NE         0x00000200      /* Not empty */
112 #define SPIE_NF         0x00000100      /* Not full */
113
114 /* SPIM register values */
115 #define SPIM_NE         0x00000200      /* Not empty */
116 #define SPIM_NF         0x00000100      /* Not full */
117
118 #define SPIE_TXB        0x00000200      /* Last char is written to tx fifo */
119 #define SPIE_RXB        0x00000100      /* Last char is written to rx buf */
120
121 /* SPCOM register values */
122 #define SPCOM_STR       (1 << 23)       /* Start transmit */
123
124 #define SPI_PRAM_SIZE   0x100
125 #define SPI_MRBLR       ((unsigned int)PAGE_SIZE)
126
127 /* SPI Controller driver's private data. */
128 struct mpc8xxx_spi {
129         struct device *dev;
130         struct mpc8xxx_spi_reg __iomem *base;
131
132         /* rx & tx bufs from the spi_transfer */
133         const void *tx;
134         void *rx;
135
136         int subblock;
137         struct spi_pram __iomem *pram;
138         struct cpm_buf_desc __iomem *tx_bd;
139         struct cpm_buf_desc __iomem *rx_bd;
140
141         struct spi_transfer *xfer_in_progress;
142
143         /* dma addresses for CPM transfers */
144         dma_addr_t tx_dma;
145         dma_addr_t rx_dma;
146         bool map_tx_dma;
147         bool map_rx_dma;
148
149         dma_addr_t dma_dummy_tx;
150         dma_addr_t dma_dummy_rx;
151
152         /* functions to deal with different sized buffers */
153         void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
154         u32(*get_tx) (struct mpc8xxx_spi *);
155
156         unsigned int count;
157         unsigned int irq;
158
159         unsigned nsecs;         /* (clock cycle time)/2 */
160
161         u32 spibrg;             /* SPIBRG input clock */
162         u32 rx_shift;           /* RX data reg shift when in qe mode */
163         u32 tx_shift;           /* TX data reg shift when in qe mode */
164
165         unsigned int flags;
166
167         struct workqueue_struct *workqueue;
168         struct work_struct work;
169
170         struct list_head queue;
171         spinlock_t lock;
172
173         struct completion done;
174 };
175
176 static void *mpc8xxx_dummy_rx;
177 static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
178 static int mpc8xxx_dummy_rx_refcnt;
179
180 struct spi_mpc8xxx_cs {
181         /* functions to deal with different sized buffers */
182         void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
183         u32 (*get_tx) (struct mpc8xxx_spi *);
184         u32 rx_shift;           /* RX data reg shift when in qe mode */
185         u32 tx_shift;           /* TX data reg shift when in qe mode */
186         u32 hw_mode;            /* Holds HW mode register settings */
187 };
188
189 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
190 {
191         out_be32(reg, val);
192 }
193
194 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
195 {
196         return in_be32(reg);
197 }
198
199 #define MPC83XX_SPI_RX_BUF(type)                                          \
200 static                                                                    \
201 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
202 {                                                                         \
203         type *rx = mpc8xxx_spi->rx;                                       \
204         *rx++ = (type)(data >> mpc8xxx_spi->rx_shift);                    \
205         mpc8xxx_spi->rx = rx;                                             \
206 }
207
208 #define MPC83XX_SPI_TX_BUF(type)                                \
209 static                                                          \
210 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi)  \
211 {                                                               \
212         u32 data;                                               \
213         const type *tx = mpc8xxx_spi->tx;                       \
214         if (!tx)                                                \
215                 return 0;                                       \
216         data = *tx++ << mpc8xxx_spi->tx_shift;                  \
217         mpc8xxx_spi->tx = tx;                                   \
218         return data;                                            \
219 }
220
221 MPC83XX_SPI_RX_BUF(u8)
222 MPC83XX_SPI_RX_BUF(u16)
223 MPC83XX_SPI_RX_BUF(u32)
224 MPC83XX_SPI_TX_BUF(u8)
225 MPC83XX_SPI_TX_BUF(u16)
226 MPC83XX_SPI_TX_BUF(u32)
227
228 static void mpc8xxx_spi_change_mode(struct spi_device *spi)
229 {
230         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
231         struct spi_mpc8xxx_cs *cs = spi->controller_state;
232         __be32 __iomem *mode = &mspi->base->mode;
233         unsigned long flags;
234
235         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
236                 return;
237
238         /* Turn off IRQs locally to minimize time that SPI is disabled. */
239         local_irq_save(flags);
240
241         /* Turn off SPI unit prior changing mode */
242         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
243         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
244
245         /* When in CPM mode, we need to reinit tx and rx. */
246         if (mspi->flags & SPI_CPM_MODE) {
247                 if (mspi->flags & SPI_QE) {
248                         qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
249                                      QE_CR_PROTOCOL_UNSPECIFIED, 0);
250                 } else {
251                         cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
252                         if (mspi->flags & SPI_CPM1) {
253                                 out_be16(&mspi->pram->rbptr,
254                                          in_be16(&mspi->pram->rbase));
255                                 out_be16(&mspi->pram->tbptr,
256                                          in_be16(&mspi->pram->tbase));
257                         }
258                 }
259         }
260
261         local_irq_restore(flags);
262 }
263
264 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
265 {
266         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
267         struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
268         bool pol = spi->mode & SPI_CS_HIGH;
269         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
270
271         if (value == BITBANG_CS_INACTIVE) {
272                 if (pdata->cs_control)
273                         pdata->cs_control(spi, !pol);
274         }
275
276         if (value == BITBANG_CS_ACTIVE) {
277                 mpc8xxx_spi->rx_shift = cs->rx_shift;
278                 mpc8xxx_spi->tx_shift = cs->tx_shift;
279                 mpc8xxx_spi->get_rx = cs->get_rx;
280                 mpc8xxx_spi->get_tx = cs->get_tx;
281
282                 mpc8xxx_spi_change_mode(spi);
283
284                 if (pdata->cs_control)
285                         pdata->cs_control(spi, pol);
286         }
287 }
288
289 static
290 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
291 {
292         struct mpc8xxx_spi *mpc8xxx_spi;
293         u8 bits_per_word, pm;
294         u32 hz;
295         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
296
297         mpc8xxx_spi = spi_master_get_devdata(spi->master);
298
299         if (t) {
300                 bits_per_word = t->bits_per_word;
301                 hz = t->speed_hz;
302         } else {
303                 bits_per_word = 0;
304                 hz = 0;
305         }
306
307         /* spi_transfer level calls that work per-word */
308         if (!bits_per_word)
309                 bits_per_word = spi->bits_per_word;
310
311         /* Make sure its a bit width we support [4..16, 32] */
312         if ((bits_per_word < 4)
313             || ((bits_per_word > 16) && (bits_per_word != 32)))
314                 return -EINVAL;
315
316         if (!hz)
317                 hz = spi->max_speed_hz;
318
319         cs->rx_shift = 0;
320         cs->tx_shift = 0;
321         if (bits_per_word <= 8) {
322                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
323                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
324                 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
325                         cs->rx_shift = 16;
326                         cs->tx_shift = 24;
327                 }
328         } else if (bits_per_word <= 16) {
329                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
330                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
331                 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
332                         cs->rx_shift = 16;
333                         cs->tx_shift = 16;
334                 }
335         } else if (bits_per_word <= 32) {
336                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
337                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
338         } else
339                 return -EINVAL;
340
341         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
342                         spi->mode & SPI_LSB_FIRST) {
343                 cs->tx_shift = 0;
344                 if (bits_per_word <= 8)
345                         cs->rx_shift = 8;
346                 else
347                         cs->rx_shift = 0;
348         }
349
350         mpc8xxx_spi->rx_shift = cs->rx_shift;
351         mpc8xxx_spi->tx_shift = cs->tx_shift;
352         mpc8xxx_spi->get_rx = cs->get_rx;
353         mpc8xxx_spi->get_tx = cs->get_tx;
354
355         if (bits_per_word == 32)
356                 bits_per_word = 0;
357         else
358                 bits_per_word = bits_per_word - 1;
359
360         /* mask out bits we are going to set */
361         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
362                                   | SPMODE_PM(0xF));
363
364         cs->hw_mode |= SPMODE_LEN(bits_per_word);
365
366         if ((mpc8xxx_spi->spibrg / hz) > 64) {
367                 cs->hw_mode |= SPMODE_DIV16;
368                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
369
370                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
371                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
372                           hz, mpc8xxx_spi->spibrg / 1024);
373                 if (pm > 16)
374                         pm = 16;
375         } else
376                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
377         if (pm)
378                 pm--;
379
380         cs->hw_mode |= SPMODE_PM(pm);
381
382         mpc8xxx_spi_change_mode(spi);
383         return 0;
384 }
385
386 static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
387 {
388         struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
389         struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
390         unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
391         unsigned int xfer_ofs;
392
393         xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
394
395         out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
396         out_be16(&rx_bd->cbd_datlen, 0);
397         out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
398
399         out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
400         out_be16(&tx_bd->cbd_datlen, xfer_len);
401         out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
402                                  BD_SC_LAST);
403
404         /* start transfer */
405         mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
406 }
407
408 static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
409                                 struct spi_transfer *t, bool is_dma_mapped)
410 {
411         struct device *dev = mspi->dev;
412
413         if (is_dma_mapped) {
414                 mspi->map_tx_dma = 0;
415                 mspi->map_rx_dma = 0;
416         } else {
417                 mspi->map_tx_dma = 1;
418                 mspi->map_rx_dma = 1;
419         }
420
421         if (!t->tx_buf) {
422                 mspi->tx_dma = mspi->dma_dummy_tx;
423                 mspi->map_tx_dma = 0;
424         }
425
426         if (!t->rx_buf) {
427                 mspi->rx_dma = mspi->dma_dummy_rx;
428                 mspi->map_rx_dma = 0;
429         }
430
431         if (mspi->map_tx_dma) {
432                 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
433
434                 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
435                                               DMA_TO_DEVICE);
436                 if (dma_mapping_error(dev, mspi->tx_dma)) {
437                         dev_err(dev, "unable to map tx dma\n");
438                         return -ENOMEM;
439                 }
440         } else {
441                 mspi->tx_dma = t->tx_dma;
442         }
443
444         if (mspi->map_rx_dma) {
445                 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
446                                               DMA_FROM_DEVICE);
447                 if (dma_mapping_error(dev, mspi->rx_dma)) {
448                         dev_err(dev, "unable to map rx dma\n");
449                         goto err_rx_dma;
450                 }
451         } else {
452                 mspi->rx_dma = t->rx_dma;
453         }
454
455         /* enable rx ints */
456         mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
457
458         mspi->xfer_in_progress = t;
459         mspi->count = t->len;
460
461         /* start CPM transfers */
462         mpc8xxx_spi_cpm_bufs_start(mspi);
463
464         return 0;
465
466 err_rx_dma:
467         if (mspi->map_tx_dma)
468                 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
469         return -ENOMEM;
470 }
471
472 static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
473 {
474         struct device *dev = mspi->dev;
475         struct spi_transfer *t = mspi->xfer_in_progress;
476
477         if (mspi->map_tx_dma)
478                 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
479         if (mspi->map_tx_dma)
480                 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
481         mspi->xfer_in_progress = NULL;
482 }
483
484 static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
485                                 struct spi_transfer *t, unsigned int len)
486 {
487         u32 word;
488
489         mspi->count = len;
490
491         /* enable rx ints */
492         mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
493
494         /* transmit word */
495         word = mspi->get_tx(mspi);
496         mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
497
498         return 0;
499 }
500
501 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
502                             bool is_dma_mapped)
503 {
504         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
505         unsigned int len = t->len;
506         u8 bits_per_word;
507         int ret;
508
509         bits_per_word = spi->bits_per_word;
510         if (t->bits_per_word)
511                 bits_per_word = t->bits_per_word;
512
513         if (bits_per_word > 8) {
514                 /* invalid length? */
515                 if (len & 1)
516                         return -EINVAL;
517                 len /= 2;
518         }
519         if (bits_per_word > 16) {
520                 /* invalid length? */
521                 if (len & 1)
522                         return -EINVAL;
523                 len /= 2;
524         }
525
526         mpc8xxx_spi->tx = t->tx_buf;
527         mpc8xxx_spi->rx = t->rx_buf;
528
529         INIT_COMPLETION(mpc8xxx_spi->done);
530
531         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
532                 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
533         else
534                 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
535         if (ret)
536                 return ret;
537
538         wait_for_completion(&mpc8xxx_spi->done);
539
540         /* disable rx ints */
541         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
542
543         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
544                 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
545
546         return mpc8xxx_spi->count;
547 }
548
549 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
550 {
551         struct spi_device *spi = m->spi;
552         struct spi_transfer *t;
553         unsigned int cs_change;
554         const int nsecs = 50;
555         int status;
556
557         cs_change = 1;
558         status = 0;
559         list_for_each_entry(t, &m->transfers, transfer_list) {
560                 if (t->bits_per_word || t->speed_hz) {
561                         /* Don't allow changes if CS is active */
562                         status = -EINVAL;
563
564                         if (cs_change)
565                                 status = mpc8xxx_spi_setup_transfer(spi, t);
566                         if (status < 0)
567                                 break;
568                 }
569
570                 if (cs_change) {
571                         mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
572                         ndelay(nsecs);
573                 }
574                 cs_change = t->cs_change;
575                 if (t->len)
576                         status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
577                 if (status) {
578                         status = -EMSGSIZE;
579                         break;
580                 }
581                 m->actual_length += t->len;
582
583                 if (t->delay_usecs)
584                         udelay(t->delay_usecs);
585
586                 if (cs_change) {
587                         ndelay(nsecs);
588                         mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
589                         ndelay(nsecs);
590                 }
591         }
592
593         m->status = status;
594         m->complete(m->context);
595
596         if (status || !cs_change) {
597                 ndelay(nsecs);
598                 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
599         }
600
601         mpc8xxx_spi_setup_transfer(spi, NULL);
602 }
603
604 static void mpc8xxx_spi_work(struct work_struct *work)
605 {
606         struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
607                                                        work);
608
609         spin_lock_irq(&mpc8xxx_spi->lock);
610         while (!list_empty(&mpc8xxx_spi->queue)) {
611                 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
612                                                    struct spi_message, queue);
613
614                 list_del_init(&m->queue);
615                 spin_unlock_irq(&mpc8xxx_spi->lock);
616
617                 mpc8xxx_spi_do_one_msg(m);
618
619                 spin_lock_irq(&mpc8xxx_spi->lock);
620         }
621         spin_unlock_irq(&mpc8xxx_spi->lock);
622 }
623
624 static int mpc8xxx_spi_setup(struct spi_device *spi)
625 {
626         struct mpc8xxx_spi *mpc8xxx_spi;
627         int retval;
628         u32 hw_mode;
629         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
630
631         if (!spi->max_speed_hz)
632                 return -EINVAL;
633
634         if (!cs) {
635                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
636                 if (!cs)
637                         return -ENOMEM;
638                 spi->controller_state = cs;
639         }
640         mpc8xxx_spi = spi_master_get_devdata(spi->master);
641
642         hw_mode = cs->hw_mode; /* Save orginal settings */
643         cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
644         /* mask out bits we are going to set */
645         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
646                          | SPMODE_REV | SPMODE_LOOP);
647
648         if (spi->mode & SPI_CPHA)
649                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
650         if (spi->mode & SPI_CPOL)
651                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
652         if (!(spi->mode & SPI_LSB_FIRST))
653                 cs->hw_mode |= SPMODE_REV;
654         if (spi->mode & SPI_LOOP)
655                 cs->hw_mode |= SPMODE_LOOP;
656
657         retval = mpc8xxx_spi_setup_transfer(spi, NULL);
658         if (retval < 0) {
659                 cs->hw_mode = hw_mode; /* Restore settings */
660                 return retval;
661         }
662         return 0;
663 }
664
665 static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
666 {
667         u16 len;
668
669         dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
670                 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
671
672         len = in_be16(&mspi->rx_bd->cbd_datlen);
673         if (len > mspi->count) {
674                 WARN_ON(1);
675                 len = mspi->count;
676         }
677
678         /* Clear the events */
679         mpc8xxx_spi_write_reg(&mspi->base->event, events);
680
681         mspi->count -= len;
682         if (mspi->count)
683                 mpc8xxx_spi_cpm_bufs_start(mspi);
684         else
685                 complete(&mspi->done);
686 }
687
688 static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
689 {
690         /* We need handle RX first */
691         if (events & SPIE_NE) {
692                 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
693
694                 if (mspi->rx)
695                         mspi->get_rx(rx_data, mspi);
696         }
697
698         if ((events & SPIE_NF) == 0)
699                 /* spin until TX is done */
700                 while (((events =
701                         mpc8xxx_spi_read_reg(&mspi->base->event)) &
702                                                 SPIE_NF) == 0)
703                         cpu_relax();
704
705         /* Clear the events */
706         mpc8xxx_spi_write_reg(&mspi->base->event, events);
707
708         mspi->count -= 1;
709         if (mspi->count) {
710                 u32 word = mspi->get_tx(mspi);
711
712                 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
713         } else {
714                 complete(&mspi->done);
715         }
716 }
717
718 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
719 {
720         struct mpc8xxx_spi *mspi = context_data;
721         irqreturn_t ret = IRQ_NONE;
722         u32 events;
723
724         /* Get interrupt events(tx/rx) */
725         events = mpc8xxx_spi_read_reg(&mspi->base->event);
726         if (events)
727                 ret = IRQ_HANDLED;
728
729         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
730
731         if (mspi->flags & SPI_CPM_MODE)
732                 mpc8xxx_spi_cpm_irq(mspi, events);
733         else
734                 mpc8xxx_spi_cpu_irq(mspi, events);
735
736         return ret;
737 }
738
739 static int mpc8xxx_spi_transfer(struct spi_device *spi,
740                                 struct spi_message *m)
741 {
742         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
743         unsigned long flags;
744
745         m->actual_length = 0;
746         m->status = -EINPROGRESS;
747
748         spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
749         list_add_tail(&m->queue, &mpc8xxx_spi->queue);
750         queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
751         spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
752
753         return 0;
754 }
755
756
757 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
758 {
759         kfree(spi->controller_state);
760 }
761
762 static void *mpc8xxx_spi_alloc_dummy_rx(void)
763 {
764         mutex_lock(&mpc8xxx_dummy_rx_lock);
765
766         if (!mpc8xxx_dummy_rx)
767                 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
768         if (mpc8xxx_dummy_rx)
769                 mpc8xxx_dummy_rx_refcnt++;
770
771         mutex_unlock(&mpc8xxx_dummy_rx_lock);
772
773         return mpc8xxx_dummy_rx;
774 }
775
776 static void mpc8xxx_spi_free_dummy_rx(void)
777 {
778         mutex_lock(&mpc8xxx_dummy_rx_lock);
779
780         switch (mpc8xxx_dummy_rx_refcnt) {
781         case 0:
782                 WARN_ON(1);
783                 break;
784         case 1:
785                 kfree(mpc8xxx_dummy_rx);
786                 mpc8xxx_dummy_rx = NULL;
787                 /* fall through */
788         default:
789                 mpc8xxx_dummy_rx_refcnt--;
790                 break;
791         }
792
793         mutex_unlock(&mpc8xxx_dummy_rx_lock);
794 }
795
796 static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
797 {
798         struct device *dev = mspi->dev;
799         struct device_node *np = dev_archdata_get_node(&dev->archdata);
800         const u32 *iprop;
801         int size;
802         unsigned long spi_base_ofs;
803         unsigned long pram_ofs = -ENOMEM;
804
805         /* Can't use of_address_to_resource(), QE muram isn't at 0. */
806         iprop = of_get_property(np, "reg", &size);
807
808         /* QE with a fixed pram location? */
809         if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
810                 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
811
812         /* QE but with a dynamic pram location? */
813         if (mspi->flags & SPI_QE) {
814                 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
815                 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
816                                 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
817                 return pram_ofs;
818         }
819
820         /* CPM1 and CPM2 pram must be at a fixed addr. */
821         if (!iprop || size != sizeof(*iprop) * 4)
822                 return -ENOMEM;
823
824         spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
825         if (IS_ERR_VALUE(spi_base_ofs))
826                 return -ENOMEM;
827
828         if (mspi->flags & SPI_CPM2) {
829                 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
830                 if (!IS_ERR_VALUE(pram_ofs)) {
831                         u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
832
833                         out_be16(spi_base, pram_ofs);
834                 }
835         } else {
836                 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
837                 u16 rpbase = in_be16(&pram->rpbase);
838
839                 /* Microcode relocation patch applied? */
840                 if (rpbase)
841                         pram_ofs = rpbase;
842                 else
843                         return spi_base_ofs;
844         }
845
846         cpm_muram_free(spi_base_ofs);
847         return pram_ofs;
848 }
849
850 static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
851 {
852         struct device *dev = mspi->dev;
853         struct device_node *np = dev_archdata_get_node(&dev->archdata);
854         const u32 *iprop;
855         int size;
856         unsigned long pram_ofs;
857         unsigned long bds_ofs;
858
859         if (!(mspi->flags & SPI_CPM_MODE))
860                 return 0;
861
862         if (!mpc8xxx_spi_alloc_dummy_rx())
863                 return -ENOMEM;
864
865         if (mspi->flags & SPI_QE) {
866                 iprop = of_get_property(np, "cell-index", &size);
867                 if (iprop && size == sizeof(*iprop))
868                         mspi->subblock = *iprop;
869
870                 switch (mspi->subblock) {
871                 default:
872                         dev_warn(dev, "cell-index unspecified, assuming SPI1");
873                         /* fall through */
874                 case 0:
875                         mspi->subblock = QE_CR_SUBBLOCK_SPI1;
876                         break;
877                 case 1:
878                         mspi->subblock = QE_CR_SUBBLOCK_SPI2;
879                         break;
880                 }
881         }
882
883         pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
884         if (IS_ERR_VALUE(pram_ofs)) {
885                 dev_err(dev, "can't allocate spi parameter ram\n");
886                 goto err_pram;
887         }
888
889         bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
890                                   sizeof(*mspi->rx_bd), 8);
891         if (IS_ERR_VALUE(bds_ofs)) {
892                 dev_err(dev, "can't allocate bds\n");
893                 goto err_bds;
894         }
895
896         mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
897                                             DMA_TO_DEVICE);
898         if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
899                 dev_err(dev, "unable to map dummy tx buffer\n");
900                 goto err_dummy_tx;
901         }
902
903         mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
904                                             DMA_FROM_DEVICE);
905         if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
906                 dev_err(dev, "unable to map dummy rx buffer\n");
907                 goto err_dummy_rx;
908         }
909
910         mspi->pram = cpm_muram_addr(pram_ofs);
911
912         mspi->tx_bd = cpm_muram_addr(bds_ofs);
913         mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
914
915         /* Initialize parameter ram. */
916         out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
917         out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
918         out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
919         out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
920         out_be16(&mspi->pram->mrblr, SPI_MRBLR);
921         out_be32(&mspi->pram->rstate, 0);
922         out_be32(&mspi->pram->rdp, 0);
923         out_be16(&mspi->pram->rbptr, 0);
924         out_be16(&mspi->pram->rbc, 0);
925         out_be32(&mspi->pram->rxtmp, 0);
926         out_be32(&mspi->pram->tstate, 0);
927         out_be32(&mspi->pram->tdp, 0);
928         out_be16(&mspi->pram->tbptr, 0);
929         out_be16(&mspi->pram->tbc, 0);
930         out_be32(&mspi->pram->txtmp, 0);
931
932         return 0;
933
934 err_dummy_rx:
935         dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
936 err_dummy_tx:
937         cpm_muram_free(bds_ofs);
938 err_bds:
939         cpm_muram_free(pram_ofs);
940 err_pram:
941         mpc8xxx_spi_free_dummy_rx();
942         return -ENOMEM;
943 }
944
945 static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
946 {
947         struct device *dev = mspi->dev;
948
949         dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
950         dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
951         cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
952         cpm_muram_free(cpm_muram_offset(mspi->pram));
953         mpc8xxx_spi_free_dummy_rx();
954 }
955
956 static const char *mpc8xxx_spi_strmode(unsigned int flags)
957 {
958         if (flags & SPI_QE_CPU_MODE) {
959                 return "QE CPU";
960         } else if (flags & SPI_CPM_MODE) {
961                 if (flags & SPI_QE)
962                         return "QE";
963                 else if (flags & SPI_CPM2)
964                         return "CPM2";
965                 else
966                         return "CPM1";
967         }
968         return "CPU";
969 }
970
971 static struct spi_master * __devinit
972 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
973 {
974         struct fsl_spi_platform_data *pdata = dev->platform_data;
975         struct spi_master *master;
976         struct mpc8xxx_spi *mpc8xxx_spi;
977         u32 regval;
978         int ret = 0;
979
980         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
981         if (master == NULL) {
982                 ret = -ENOMEM;
983                 goto err;
984         }
985
986         dev_set_drvdata(dev, master);
987
988         /* the spi->mode bits understood by this driver: */
989         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
990                         | SPI_LSB_FIRST | SPI_LOOP;
991
992         master->setup = mpc8xxx_spi_setup;
993         master->transfer = mpc8xxx_spi_transfer;
994         master->cleanup = mpc8xxx_spi_cleanup;
995
996         mpc8xxx_spi = spi_master_get_devdata(master);
997         mpc8xxx_spi->dev = dev;
998         mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
999         mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
1000         mpc8xxx_spi->flags = pdata->flags;
1001         mpc8xxx_spi->spibrg = pdata->sysclk;
1002
1003         ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
1004         if (ret)
1005                 goto err_cpm_init;
1006
1007         mpc8xxx_spi->rx_shift = 0;
1008         mpc8xxx_spi->tx_shift = 0;
1009         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
1010                 mpc8xxx_spi->rx_shift = 16;
1011                 mpc8xxx_spi->tx_shift = 24;
1012         }
1013
1014         init_completion(&mpc8xxx_spi->done);
1015
1016         mpc8xxx_spi->base = ioremap(mem->start, resource_size(mem));
1017         if (mpc8xxx_spi->base == NULL) {
1018                 ret = -ENOMEM;
1019                 goto err_ioremap;
1020         }
1021
1022         mpc8xxx_spi->irq = irq;
1023
1024         /* Register for SPI Interrupt */
1025         ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1026                           0, "mpc8xxx_spi", mpc8xxx_spi);
1027
1028         if (ret != 0)
1029                 goto unmap_io;
1030
1031         master->bus_num = pdata->bus_num;
1032         master->num_chipselect = pdata->max_chipselect;
1033
1034         /* SPI controller initializations */
1035         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1036         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1037         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1038         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
1039
1040         /* Enable SPI interface */
1041         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1042         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1043                 regval |= SPMODE_OP;
1044
1045         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1046         spin_lock_init(&mpc8xxx_spi->lock);
1047         init_completion(&mpc8xxx_spi->done);
1048         INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1049         INIT_LIST_HEAD(&mpc8xxx_spi->queue);
1050
1051         mpc8xxx_spi->workqueue = create_singlethread_workqueue(
1052                 dev_name(master->dev.parent));
1053         if (mpc8xxx_spi->workqueue == NULL) {
1054                 ret = -EBUSY;
1055                 goto free_irq;
1056         }
1057
1058         ret = spi_register_master(master);
1059         if (ret < 0)
1060                 goto unreg_master;
1061
1062         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1063                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1064
1065         return master;
1066
1067 unreg_master:
1068         destroy_workqueue(mpc8xxx_spi->workqueue);
1069 free_irq:
1070         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1071 unmap_io:
1072         iounmap(mpc8xxx_spi->base);
1073 err_ioremap:
1074         mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1075 err_cpm_init:
1076         spi_master_put(master);
1077 err:
1078         return ERR_PTR(ret);
1079 }
1080
1081 static int __devexit mpc8xxx_spi_remove(struct device *dev)
1082 {
1083         struct mpc8xxx_spi *mpc8xxx_spi;
1084         struct spi_master *master;
1085
1086         master = dev_get_drvdata(dev);
1087         mpc8xxx_spi = spi_master_get_devdata(master);
1088
1089         flush_workqueue(mpc8xxx_spi->workqueue);
1090         destroy_workqueue(mpc8xxx_spi->workqueue);
1091         spi_unregister_master(master);
1092
1093         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1094         iounmap(mpc8xxx_spi->base);
1095         mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1096
1097         return 0;
1098 }
1099
1100 struct mpc8xxx_spi_probe_info {
1101         struct fsl_spi_platform_data pdata;
1102         int *gpios;
1103         bool *alow_flags;
1104 };
1105
1106 static struct mpc8xxx_spi_probe_info *
1107 to_of_pinfo(struct fsl_spi_platform_data *pdata)
1108 {
1109         return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
1110 }
1111
1112 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1113 {
1114         struct device *dev = spi->dev.parent;
1115         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
1116         u16 cs = spi->chip_select;
1117         int gpio = pinfo->gpios[cs];
1118         bool alow = pinfo->alow_flags[cs];
1119
1120         gpio_set_value(gpio, on ^ alow);
1121 }
1122
1123 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
1124 {
1125         struct device_node *np = dev_archdata_get_node(&dev->archdata);
1126         struct fsl_spi_platform_data *pdata = dev->platform_data;
1127         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1128         unsigned int ngpios;
1129         int i = 0;
1130         int ret;
1131
1132         ngpios = of_gpio_count(np);
1133         if (!ngpios) {
1134                 /*
1135                  * SPI w/o chip-select line. One SPI device is still permitted
1136                  * though.
1137                  */
1138                 pdata->max_chipselect = 1;
1139                 return 0;
1140         }
1141
1142         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
1143         if (!pinfo->gpios)
1144                 return -ENOMEM;
1145         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
1146
1147         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
1148                                     GFP_KERNEL);
1149         if (!pinfo->alow_flags) {
1150                 ret = -ENOMEM;
1151                 goto err_alloc_flags;
1152         }
1153
1154         for (; i < ngpios; i++) {
1155                 int gpio;
1156                 enum of_gpio_flags flags;
1157
1158                 gpio = of_get_gpio_flags(np, i, &flags);
1159                 if (!gpio_is_valid(gpio)) {
1160                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
1161                         ret = gpio;
1162                         goto err_loop;
1163                 }
1164
1165                 ret = gpio_request(gpio, dev_name(dev));
1166                 if (ret) {
1167                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1168                         goto err_loop;
1169                 }
1170
1171                 pinfo->gpios[i] = gpio;
1172                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1173
1174                 ret = gpio_direction_output(pinfo->gpios[i],
1175                                             pinfo->alow_flags[i]);
1176                 if (ret) {
1177                         dev_err(dev, "can't set output direction for gpio "
1178                                 "#%d: %d\n", i, ret);
1179                         goto err_loop;
1180                 }
1181         }
1182
1183         pdata->max_chipselect = ngpios;
1184         pdata->cs_control = mpc8xxx_spi_cs_control;
1185
1186         return 0;
1187
1188 err_loop:
1189         while (i >= 0) {
1190                 if (gpio_is_valid(pinfo->gpios[i]))
1191                         gpio_free(pinfo->gpios[i]);
1192                 i--;
1193         }
1194
1195         kfree(pinfo->alow_flags);
1196         pinfo->alow_flags = NULL;
1197 err_alloc_flags:
1198         kfree(pinfo->gpios);
1199         pinfo->gpios = NULL;
1200         return ret;
1201 }
1202
1203 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1204 {
1205         struct fsl_spi_platform_data *pdata = dev->platform_data;
1206         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1207         int i;
1208
1209         if (!pinfo->gpios)
1210                 return 0;
1211
1212         for (i = 0; i < pdata->max_chipselect; i++) {
1213                 if (gpio_is_valid(pinfo->gpios[i]))
1214                         gpio_free(pinfo->gpios[i]);
1215         }
1216
1217         kfree(pinfo->gpios);
1218         kfree(pinfo->alow_flags);
1219         return 0;
1220 }
1221
1222 static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
1223                                           const struct of_device_id *ofid)
1224 {
1225         struct device *dev = &ofdev->dev;
1226         struct device_node *np = ofdev->node;
1227         struct mpc8xxx_spi_probe_info *pinfo;
1228         struct fsl_spi_platform_data *pdata;
1229         struct spi_master *master;
1230         struct resource mem;
1231         struct resource irq;
1232         const void *prop;
1233         int ret = -ENOMEM;
1234
1235         pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1236         if (!pinfo)
1237                 return -ENOMEM;
1238
1239         pdata = &pinfo->pdata;
1240         dev->platform_data = pdata;
1241
1242         /* Allocate bus num dynamically. */
1243         pdata->bus_num = -1;
1244
1245         /* SPI controller is either clocked from QE or SoC clock. */
1246         pdata->sysclk = get_brgfreq();
1247         if (pdata->sysclk == -1) {
1248                 pdata->sysclk = fsl_get_sys_freq();
1249                 if (pdata->sysclk == -1) {
1250                         ret = -ENODEV;
1251                         goto err_clk;
1252                 }
1253         }
1254
1255         prop = of_get_property(np, "mode", NULL);
1256         if (prop && !strcmp(prop, "cpu-qe"))
1257                 pdata->flags = SPI_QE_CPU_MODE;
1258         else if (prop && !strcmp(prop, "qe"))
1259                 pdata->flags = SPI_CPM_MODE | SPI_QE;
1260         else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1261                 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1262         else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1263                 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1264
1265         ret = of_mpc8xxx_spi_get_chipselects(dev);
1266         if (ret)
1267                 goto err;
1268
1269         ret = of_address_to_resource(np, 0, &mem);
1270         if (ret)
1271                 goto err;
1272
1273         ret = of_irq_to_resource(np, 0, &irq);
1274         if (!ret) {
1275                 ret = -EINVAL;
1276                 goto err;
1277         }
1278
1279         master = mpc8xxx_spi_probe(dev, &mem, irq.start);
1280         if (IS_ERR(master)) {
1281                 ret = PTR_ERR(master);
1282                 goto err;
1283         }
1284
1285         of_register_spi_devices(master, np);
1286
1287         return 0;
1288
1289 err:
1290         of_mpc8xxx_spi_free_chipselects(dev);
1291 err_clk:
1292         kfree(pinfo);
1293         return ret;
1294 }
1295
1296 static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
1297 {
1298         int ret;
1299
1300         ret = mpc8xxx_spi_remove(&ofdev->dev);
1301         if (ret)
1302                 return ret;
1303         of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
1304         return 0;
1305 }
1306
1307 static const struct of_device_id of_mpc8xxx_spi_match[] = {
1308         { .compatible = "fsl,spi" },
1309         {},
1310 };
1311 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
1312
1313 static struct of_platform_driver of_mpc8xxx_spi_driver = {
1314         .name           = "mpc8xxx_spi",
1315         .match_table    = of_mpc8xxx_spi_match,
1316         .probe          = of_mpc8xxx_spi_probe,
1317         .remove         = __devexit_p(of_mpc8xxx_spi_remove),
1318 };
1319
1320 #ifdef CONFIG_MPC832x_RDB
1321 /*
1322  *                              XXX XXX XXX
1323  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1324  * only. The driver should go away soon, since newer MPC8323E-RDB's device
1325  * tree can work with OpenFirmware driver. But for now we support old trees
1326  * as well.
1327  */
1328 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1329 {
1330         struct resource *mem;
1331         int irq;
1332         struct spi_master *master;
1333
1334         if (!pdev->dev.platform_data)
1335                 return -EINVAL;
1336
1337         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1338         if (!mem)
1339                 return -EINVAL;
1340
1341         irq = platform_get_irq(pdev, 0);
1342         if (irq <= 0)
1343                 return -EINVAL;
1344
1345         master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
1346         if (IS_ERR(master))
1347                 return PTR_ERR(master);
1348         return 0;
1349 }
1350
1351 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1352 {
1353         return mpc8xxx_spi_remove(&pdev->dev);
1354 }
1355
1356 MODULE_ALIAS("platform:mpc8xxx_spi");
1357 static struct platform_driver mpc8xxx_spi_driver = {
1358         .probe = plat_mpc8xxx_spi_probe,
1359         .remove = __devexit_p(plat_mpc8xxx_spi_remove),
1360         .driver = {
1361                 .name = "mpc8xxx_spi",
1362                 .owner = THIS_MODULE,
1363         },
1364 };
1365
1366 static bool legacy_driver_failed;
1367
1368 static void __init legacy_driver_register(void)
1369 {
1370         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1371 }
1372
1373 static void __exit legacy_driver_unregister(void)
1374 {
1375         if (legacy_driver_failed)
1376                 return;
1377         platform_driver_unregister(&mpc8xxx_spi_driver);
1378 }
1379 #else
1380 static void __init legacy_driver_register(void) {}
1381 static void __exit legacy_driver_unregister(void) {}
1382 #endif /* CONFIG_MPC832x_RDB */
1383
1384 static int __init mpc8xxx_spi_init(void)
1385 {
1386         legacy_driver_register();
1387         return of_register_platform_driver(&of_mpc8xxx_spi_driver);
1388 }
1389
1390 static void __exit mpc8xxx_spi_exit(void)
1391 {
1392         of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
1393         legacy_driver_unregister();
1394 }
1395
1396 module_init(mpc8xxx_spi_init);
1397 module_exit(mpc8xxx_spi_exit);
1398
1399 MODULE_AUTHOR("Kumar Gala");
1400 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
1401 MODULE_LICENSE("GPL");