igbvf: do not modify tx_queue_len on link speed change
[linux-2.6.git] / drivers / spi / spi_imx.c
1 /*
2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3  * Copyright (C) 2008 Juergen Beisert
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the
16  * Free Software Foundation
17  * 51 Franklin Street, Fifth Floor
18  * Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
35 #include <linux/types.h>
36
37 #include <mach/spi.h>
38
39 #define DRIVER_NAME "spi_imx"
40
41 #define MXC_CSPIRXDATA          0x00
42 #define MXC_CSPITXDATA          0x04
43 #define MXC_CSPICTRL            0x08
44 #define MXC_CSPIINT             0x0c
45 #define MXC_RESET               0x1c
46
47 #define MX3_CSPISTAT            0x14
48 #define MX3_CSPISTAT_RR         (1 << 3)
49
50 /* generic defines to abstract from the different register layouts */
51 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
52 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
53
54 struct spi_imx_config {
55         unsigned int speed_hz;
56         unsigned int bpw;
57         unsigned int mode;
58         int cs;
59 };
60
61 struct spi_imx_data {
62         struct spi_bitbang bitbang;
63
64         struct completion xfer_done;
65         void *base;
66         int irq;
67         struct clk *clk;
68         unsigned long spi_clk;
69         int *chipselect;
70
71         unsigned int count;
72         void (*tx)(struct spi_imx_data *);
73         void (*rx)(struct spi_imx_data *);
74         void *rx_buf;
75         const void *tx_buf;
76         unsigned int txfifo; /* number of words pushed in tx FIFO */
77
78         /* SoC specific functions */
79         void (*intctrl)(struct spi_imx_data *, int);
80         int (*config)(struct spi_imx_data *, struct spi_imx_config *);
81         void (*trigger)(struct spi_imx_data *);
82         int (*rx_available)(struct spi_imx_data *);
83 };
84
85 #define MXC_SPI_BUF_RX(type)                                            \
86 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
87 {                                                                       \
88         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
89                                                                         \
90         if (spi_imx->rx_buf) {                                          \
91                 *(type *)spi_imx->rx_buf = val;                         \
92                 spi_imx->rx_buf += sizeof(type);                        \
93         }                                                               \
94 }
95
96 #define MXC_SPI_BUF_TX(type)                                            \
97 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
98 {                                                                       \
99         type val = 0;                                                   \
100                                                                         \
101         if (spi_imx->tx_buf) {                                          \
102                 val = *(type *)spi_imx->tx_buf;                         \
103                 spi_imx->tx_buf += sizeof(type);                        \
104         }                                                               \
105                                                                         \
106         spi_imx->count -= sizeof(type);                                 \
107                                                                         \
108         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
109 }
110
111 MXC_SPI_BUF_RX(u8)
112 MXC_SPI_BUF_TX(u8)
113 MXC_SPI_BUF_RX(u16)
114 MXC_SPI_BUF_TX(u16)
115 MXC_SPI_BUF_RX(u32)
116 MXC_SPI_BUF_TX(u32)
117
118 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
119  * (which is currently not the case in this driver)
120  */
121 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
122         256, 384, 512, 768, 1024};
123
124 /* MX21, MX27 */
125 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
126                 unsigned int fspi)
127 {
128         int i, max;
129
130         if (cpu_is_mx21())
131                 max = 18;
132         else
133                 max = 16;
134
135         for (i = 2; i < max; i++)
136                 if (fspi * mxc_clkdivs[i] >= fin)
137                         return i;
138
139         return max;
140 }
141
142 /* MX1, MX31, MX35 */
143 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
144                 unsigned int fspi)
145 {
146         int i, div = 4;
147
148         for (i = 0; i < 7; i++) {
149                 if (fspi * div >= fin)
150                         return i;
151                 div <<= 1;
152         }
153
154         return 7;
155 }
156
157 #define MX31_INTREG_TEEN        (1 << 0)
158 #define MX31_INTREG_RREN        (1 << 3)
159
160 #define MX31_CSPICTRL_ENABLE    (1 << 0)
161 #define MX31_CSPICTRL_MASTER    (1 << 1)
162 #define MX31_CSPICTRL_XCH       (1 << 2)
163 #define MX31_CSPICTRL_POL       (1 << 4)
164 #define MX31_CSPICTRL_PHA       (1 << 5)
165 #define MX31_CSPICTRL_SSCTL     (1 << 6)
166 #define MX31_CSPICTRL_SSPOL     (1 << 7)
167 #define MX31_CSPICTRL_BC_SHIFT  8
168 #define MX35_CSPICTRL_BL_SHIFT  20
169 #define MX31_CSPICTRL_CS_SHIFT  24
170 #define MX35_CSPICTRL_CS_SHIFT  12
171 #define MX31_CSPICTRL_DR_SHIFT  16
172
173 #define MX31_CSPISTATUS         0x14
174 #define MX31_STATUS_RR          (1 << 3)
175
176 /* These functions also work for the i.MX35, but be aware that
177  * the i.MX35 has a slightly different register layout for bits
178  * we do not use here.
179  */
180 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
181 {
182         unsigned int val = 0;
183
184         if (enable & MXC_INT_TE)
185                 val |= MX31_INTREG_TEEN;
186         if (enable & MXC_INT_RR)
187                 val |= MX31_INTREG_RREN;
188
189         writel(val, spi_imx->base + MXC_CSPIINT);
190 }
191
192 static void mx31_trigger(struct spi_imx_data *spi_imx)
193 {
194         unsigned int reg;
195
196         reg = readl(spi_imx->base + MXC_CSPICTRL);
197         reg |= MX31_CSPICTRL_XCH;
198         writel(reg, spi_imx->base + MXC_CSPICTRL);
199 }
200
201 static int mx31_config(struct spi_imx_data *spi_imx,
202                 struct spi_imx_config *config)
203 {
204         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
205
206         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
207                 MX31_CSPICTRL_DR_SHIFT;
208
209         if (cpu_is_mx31())
210                 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
211         else if (cpu_is_mx25() || cpu_is_mx35()) {
212                 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
213                 reg |= MX31_CSPICTRL_SSCTL;
214         }
215
216         if (config->mode & SPI_CPHA)
217                 reg |= MX31_CSPICTRL_PHA;
218         if (config->mode & SPI_CPOL)
219                 reg |= MX31_CSPICTRL_POL;
220         if (config->mode & SPI_CS_HIGH)
221                 reg |= MX31_CSPICTRL_SSPOL;
222         if (config->cs < 0) {
223                 if (cpu_is_mx31())
224                         reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
225                 else if (cpu_is_mx25() || cpu_is_mx35())
226                         reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
227         }
228
229         writel(reg, spi_imx->base + MXC_CSPICTRL);
230
231         return 0;
232 }
233
234 static int mx31_rx_available(struct spi_imx_data *spi_imx)
235 {
236         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
237 }
238
239 #define MX27_INTREG_RR          (1 << 4)
240 #define MX27_INTREG_TEEN        (1 << 9)
241 #define MX27_INTREG_RREN        (1 << 13)
242
243 #define MX27_CSPICTRL_POL       (1 << 5)
244 #define MX27_CSPICTRL_PHA       (1 << 6)
245 #define MX27_CSPICTRL_SSPOL     (1 << 8)
246 #define MX27_CSPICTRL_XCH       (1 << 9)
247 #define MX27_CSPICTRL_ENABLE    (1 << 10)
248 #define MX27_CSPICTRL_MASTER    (1 << 11)
249 #define MX27_CSPICTRL_DR_SHIFT  14
250 #define MX27_CSPICTRL_CS_SHIFT  19
251
252 static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
253 {
254         unsigned int val = 0;
255
256         if (enable & MXC_INT_TE)
257                 val |= MX27_INTREG_TEEN;
258         if (enable & MXC_INT_RR)
259                 val |= MX27_INTREG_RREN;
260
261         writel(val, spi_imx->base + MXC_CSPIINT);
262 }
263
264 static void mx27_trigger(struct spi_imx_data *spi_imx)
265 {
266         unsigned int reg;
267
268         reg = readl(spi_imx->base + MXC_CSPICTRL);
269         reg |= MX27_CSPICTRL_XCH;
270         writel(reg, spi_imx->base + MXC_CSPICTRL);
271 }
272
273 static int mx27_config(struct spi_imx_data *spi_imx,
274                 struct spi_imx_config *config)
275 {
276         unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
277
278         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
279                 MX27_CSPICTRL_DR_SHIFT;
280         reg |= config->bpw - 1;
281
282         if (config->mode & SPI_CPHA)
283                 reg |= MX27_CSPICTRL_PHA;
284         if (config->mode & SPI_CPOL)
285                 reg |= MX27_CSPICTRL_POL;
286         if (config->mode & SPI_CS_HIGH)
287                 reg |= MX27_CSPICTRL_SSPOL;
288         if (config->cs < 0)
289                 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT;
290
291         writel(reg, spi_imx->base + MXC_CSPICTRL);
292
293         return 0;
294 }
295
296 static int mx27_rx_available(struct spi_imx_data *spi_imx)
297 {
298         return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
299 }
300
301 #define MX1_INTREG_RR           (1 << 3)
302 #define MX1_INTREG_TEEN         (1 << 8)
303 #define MX1_INTREG_RREN         (1 << 11)
304
305 #define MX1_CSPICTRL_POL        (1 << 4)
306 #define MX1_CSPICTRL_PHA        (1 << 5)
307 #define MX1_CSPICTRL_XCH        (1 << 8)
308 #define MX1_CSPICTRL_ENABLE     (1 << 9)
309 #define MX1_CSPICTRL_MASTER     (1 << 10)
310 #define MX1_CSPICTRL_DR_SHIFT   13
311
312 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
313 {
314         unsigned int val = 0;
315
316         if (enable & MXC_INT_TE)
317                 val |= MX1_INTREG_TEEN;
318         if (enable & MXC_INT_RR)
319                 val |= MX1_INTREG_RREN;
320
321         writel(val, spi_imx->base + MXC_CSPIINT);
322 }
323
324 static void mx1_trigger(struct spi_imx_data *spi_imx)
325 {
326         unsigned int reg;
327
328         reg = readl(spi_imx->base + MXC_CSPICTRL);
329         reg |= MX1_CSPICTRL_XCH;
330         writel(reg, spi_imx->base + MXC_CSPICTRL);
331 }
332
333 static int mx1_config(struct spi_imx_data *spi_imx,
334                 struct spi_imx_config *config)
335 {
336         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
337
338         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
339                 MX1_CSPICTRL_DR_SHIFT;
340         reg |= config->bpw - 1;
341
342         if (config->mode & SPI_CPHA)
343                 reg |= MX1_CSPICTRL_PHA;
344         if (config->mode & SPI_CPOL)
345                 reg |= MX1_CSPICTRL_POL;
346
347         writel(reg, spi_imx->base + MXC_CSPICTRL);
348
349         return 0;
350 }
351
352 static int mx1_rx_available(struct spi_imx_data *spi_imx)
353 {
354         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
355 }
356
357 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
358 {
359         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
360         int gpio = spi_imx->chipselect[spi->chip_select];
361         int active = is_active != BITBANG_CS_INACTIVE;
362         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
363
364         if (gpio < 0)
365                 return;
366
367         gpio_set_value(gpio, dev_is_lowactive ^ active);
368 }
369
370 static void spi_imx_push(struct spi_imx_data *spi_imx)
371 {
372         while (spi_imx->txfifo < 8) {
373                 if (!spi_imx->count)
374                         break;
375                 spi_imx->tx(spi_imx);
376                 spi_imx->txfifo++;
377         }
378
379         spi_imx->trigger(spi_imx);
380 }
381
382 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
383 {
384         struct spi_imx_data *spi_imx = dev_id;
385
386         while (spi_imx->rx_available(spi_imx)) {
387                 spi_imx->rx(spi_imx);
388                 spi_imx->txfifo--;
389         }
390
391         if (spi_imx->count) {
392                 spi_imx_push(spi_imx);
393                 return IRQ_HANDLED;
394         }
395
396         if (spi_imx->txfifo) {
397                 /* No data left to push, but still waiting for rx data,
398                  * enable receive data available interrupt.
399                  */
400                 spi_imx->intctrl(spi_imx, MXC_INT_RR);
401                 return IRQ_HANDLED;
402         }
403
404         spi_imx->intctrl(spi_imx, 0);
405         complete(&spi_imx->xfer_done);
406
407         return IRQ_HANDLED;
408 }
409
410 static int spi_imx_setupxfer(struct spi_device *spi,
411                                  struct spi_transfer *t)
412 {
413         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
414         struct spi_imx_config config;
415
416         config.bpw = t ? t->bits_per_word : spi->bits_per_word;
417         config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
418         config.mode = spi->mode;
419         config.cs = spi_imx->chipselect[spi->chip_select];
420
421         if (!config.speed_hz)
422                 config.speed_hz = spi->max_speed_hz;
423         if (!config.bpw)
424                 config.bpw = spi->bits_per_word;
425         if (!config.speed_hz)
426                 config.speed_hz = spi->max_speed_hz;
427
428         /* Initialize the functions for transfer */
429         if (config.bpw <= 8) {
430                 spi_imx->rx = spi_imx_buf_rx_u8;
431                 spi_imx->tx = spi_imx_buf_tx_u8;
432         } else if (config.bpw <= 16) {
433                 spi_imx->rx = spi_imx_buf_rx_u16;
434                 spi_imx->tx = spi_imx_buf_tx_u16;
435         } else if (config.bpw <= 32) {
436                 spi_imx->rx = spi_imx_buf_rx_u32;
437                 spi_imx->tx = spi_imx_buf_tx_u32;
438         } else
439                 BUG();
440
441         spi_imx->config(spi_imx, &config);
442
443         return 0;
444 }
445
446 static int spi_imx_transfer(struct spi_device *spi,
447                                 struct spi_transfer *transfer)
448 {
449         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
450
451         spi_imx->tx_buf = transfer->tx_buf;
452         spi_imx->rx_buf = transfer->rx_buf;
453         spi_imx->count = transfer->len;
454         spi_imx->txfifo = 0;
455
456         init_completion(&spi_imx->xfer_done);
457
458         spi_imx_push(spi_imx);
459
460         spi_imx->intctrl(spi_imx, MXC_INT_TE);
461
462         wait_for_completion(&spi_imx->xfer_done);
463
464         return transfer->len;
465 }
466
467 static int spi_imx_setup(struct spi_device *spi)
468 {
469         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
470         int gpio = spi_imx->chipselect[spi->chip_select];
471
472         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
473                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
474
475         if (gpio >= 0)
476                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
477
478         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
479
480         return 0;
481 }
482
483 static void spi_imx_cleanup(struct spi_device *spi)
484 {
485 }
486
487 static int __devinit spi_imx_probe(struct platform_device *pdev)
488 {
489         struct spi_imx_master *mxc_platform_info;
490         struct spi_master *master;
491         struct spi_imx_data *spi_imx;
492         struct resource *res;
493         int i, ret;
494
495         mxc_platform_info = dev_get_platdata(&pdev->dev);
496         if (!mxc_platform_info) {
497                 dev_err(&pdev->dev, "can't get the platform data\n");
498                 return -EINVAL;
499         }
500
501         master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
502         if (!master)
503                 return -ENOMEM;
504
505         platform_set_drvdata(pdev, master);
506
507         master->bus_num = pdev->id;
508         master->num_chipselect = mxc_platform_info->num_chipselect;
509
510         spi_imx = spi_master_get_devdata(master);
511         spi_imx->bitbang.master = spi_master_get(master);
512         spi_imx->chipselect = mxc_platform_info->chipselect;
513
514         for (i = 0; i < master->num_chipselect; i++) {
515                 if (spi_imx->chipselect[i] < 0)
516                         continue;
517                 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
518                 if (ret) {
519                         while (i > 0) {
520                                 i--;
521                                 if (spi_imx->chipselect[i] >= 0)
522                                         gpio_free(spi_imx->chipselect[i]);
523                         }
524                         dev_err(&pdev->dev, "can't get cs gpios\n");
525                         goto out_master_put;
526                 }
527         }
528
529         spi_imx->bitbang.chipselect = spi_imx_chipselect;
530         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
531         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
532         spi_imx->bitbang.master->setup = spi_imx_setup;
533         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
534         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
535
536         init_completion(&spi_imx->xfer_done);
537
538         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
539         if (!res) {
540                 dev_err(&pdev->dev, "can't get platform resource\n");
541                 ret = -ENOMEM;
542                 goto out_gpio_free;
543         }
544
545         if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
546                 dev_err(&pdev->dev, "request_mem_region failed\n");
547                 ret = -EBUSY;
548                 goto out_gpio_free;
549         }
550
551         spi_imx->base = ioremap(res->start, resource_size(res));
552         if (!spi_imx->base) {
553                 ret = -EINVAL;
554                 goto out_release_mem;
555         }
556
557         spi_imx->irq = platform_get_irq(pdev, 0);
558         if (spi_imx->irq <= 0) {
559                 ret = -EINVAL;
560                 goto out_iounmap;
561         }
562
563         ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
564         if (ret) {
565                 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
566                 goto out_iounmap;
567         }
568
569         if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
570                 spi_imx->intctrl = mx31_intctrl;
571                 spi_imx->config = mx31_config;
572                 spi_imx->trigger = mx31_trigger;
573                 spi_imx->rx_available = mx31_rx_available;
574         } else  if (cpu_is_mx27() || cpu_is_mx21()) {
575                 spi_imx->intctrl = mx27_intctrl;
576                 spi_imx->config = mx27_config;
577                 spi_imx->trigger = mx27_trigger;
578                 spi_imx->rx_available = mx27_rx_available;
579         } else if (cpu_is_mx1()) {
580                 spi_imx->intctrl = mx1_intctrl;
581                 spi_imx->config = mx1_config;
582                 spi_imx->trigger = mx1_trigger;
583                 spi_imx->rx_available = mx1_rx_available;
584         } else
585                 BUG();
586
587         spi_imx->clk = clk_get(&pdev->dev, NULL);
588         if (IS_ERR(spi_imx->clk)) {
589                 dev_err(&pdev->dev, "unable to get clock\n");
590                 ret = PTR_ERR(spi_imx->clk);
591                 goto out_free_irq;
592         }
593
594         clk_enable(spi_imx->clk);
595         spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
596
597         if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
598                 writel(1, spi_imx->base + MXC_RESET);
599
600         /* drain receive buffer */
601         if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
602                 while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
603                         readl(spi_imx->base + MXC_CSPIRXDATA);
604
605         spi_imx->intctrl(spi_imx, 0);
606
607         ret = spi_bitbang_start(&spi_imx->bitbang);
608         if (ret) {
609                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
610                 goto out_clk_put;
611         }
612
613         dev_info(&pdev->dev, "probed\n");
614
615         return ret;
616
617 out_clk_put:
618         clk_disable(spi_imx->clk);
619         clk_put(spi_imx->clk);
620 out_free_irq:
621         free_irq(spi_imx->irq, spi_imx);
622 out_iounmap:
623         iounmap(spi_imx->base);
624 out_release_mem:
625         release_mem_region(res->start, resource_size(res));
626 out_gpio_free:
627         for (i = 0; i < master->num_chipselect; i++)
628                 if (spi_imx->chipselect[i] >= 0)
629                         gpio_free(spi_imx->chipselect[i]);
630 out_master_put:
631         spi_master_put(master);
632         kfree(master);
633         platform_set_drvdata(pdev, NULL);
634         return ret;
635 }
636
637 static int __devexit spi_imx_remove(struct platform_device *pdev)
638 {
639         struct spi_master *master = platform_get_drvdata(pdev);
640         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
642         int i;
643
644         spi_bitbang_stop(&spi_imx->bitbang);
645
646         writel(0, spi_imx->base + MXC_CSPICTRL);
647         clk_disable(spi_imx->clk);
648         clk_put(spi_imx->clk);
649         free_irq(spi_imx->irq, spi_imx);
650         iounmap(spi_imx->base);
651
652         for (i = 0; i < master->num_chipselect; i++)
653                 if (spi_imx->chipselect[i] >= 0)
654                         gpio_free(spi_imx->chipselect[i]);
655
656         spi_master_put(master);
657
658         release_mem_region(res->start, resource_size(res));
659
660         platform_set_drvdata(pdev, NULL);
661
662         return 0;
663 }
664
665 static struct platform_driver spi_imx_driver = {
666         .driver = {
667                    .name = DRIVER_NAME,
668                    .owner = THIS_MODULE,
669                    },
670         .probe = spi_imx_probe,
671         .remove = __devexit_p(spi_imx_remove),
672 };
673
674 static int __init spi_imx_init(void)
675 {
676         return platform_driver_register(&spi_imx_driver);
677 }
678
679 static void __exit spi_imx_exit(void)
680 {
681         platform_driver_unregister(&spi_imx_driver);
682 }
683
684 module_init(spi_imx_init);
685 module_exit(spi_imx_exit);
686
687 MODULE_DESCRIPTION("SPI Master Controller driver");
688 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
689 MODULE_LICENSE("GPL");