arm: tegra: fb: Apply new mode even if its current
[linux-2.6.git] / drivers / spi / spi-topcliff-pch.c
1 /*
2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
3  *
4  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
18  */
19
20 #include <linux/delay.h>
21 #include <linux/pci.h>
22 #include <linux/wait.h>
23 #include <linux/spi/spi.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/spi/spidev.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30
31 #include <linux/dmaengine.h>
32 #include <linux/pch_dma.h>
33
34 /* Register offsets */
35 #define PCH_SPCR                0x00    /* SPI control register */
36 #define PCH_SPBRR               0x04    /* SPI baud rate register */
37 #define PCH_SPSR                0x08    /* SPI status register */
38 #define PCH_SPDWR               0x0C    /* SPI write data register */
39 #define PCH_SPDRR               0x10    /* SPI read data register */
40 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
41 #define PCH_SRST                0x1C    /* SPI reset register */
42 #define PCH_ADDRESS_SIZE        0x20
43
44 #define PCH_SPSR_TFD            0x000007C0
45 #define PCH_SPSR_RFD            0x0000F800
46
47 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
48 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
49
50 #define PCH_RX_THOLD            7
51 #define PCH_RX_THOLD_MAX        15
52
53 #define PCH_TX_THOLD            2
54
55 #define PCH_MAX_BAUDRATE        5000000
56 #define PCH_MAX_FIFO_DEPTH      16
57
58 #define STATUS_RUNNING          1
59 #define STATUS_EXITING          2
60 #define PCH_SLEEP_TIME          10
61
62 #define SSN_LOW                 0x02U
63 #define SSN_HIGH                0x03U
64 #define SSN_NO_CONTROL          0x00U
65 #define PCH_MAX_CS              0xFF
66 #define PCI_DEVICE_ID_GE_SPI    0x8816
67
68 #define SPCR_SPE_BIT            (1 << 0)
69 #define SPCR_MSTR_BIT           (1 << 1)
70 #define SPCR_LSBF_BIT           (1 << 4)
71 #define SPCR_CPHA_BIT           (1 << 5)
72 #define SPCR_CPOL_BIT           (1 << 6)
73 #define SPCR_TFIE_BIT           (1 << 8)
74 #define SPCR_RFIE_BIT           (1 << 9)
75 #define SPCR_FIE_BIT            (1 << 10)
76 #define SPCR_ORIE_BIT           (1 << 11)
77 #define SPCR_MDFIE_BIT          (1 << 12)
78 #define SPCR_FICLR_BIT          (1 << 24)
79 #define SPSR_TFI_BIT            (1 << 0)
80 #define SPSR_RFI_BIT            (1 << 1)
81 #define SPSR_FI_BIT             (1 << 2)
82 #define SPSR_ORF_BIT            (1 << 3)
83 #define SPBRR_SIZE_BIT          (1 << 10)
84
85 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
86                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
87
88 #define SPCR_RFIC_FIELD         20
89 #define SPCR_TFIC_FIELD         16
90
91 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
92 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
93 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
94
95 #define PCH_CLOCK_HZ            50000000
96 #define PCH_MAX_SPBR            1023
97
98 /* Definition for ML7213 by OKI SEMICONDUCTOR */
99 #define PCI_VENDOR_ID_ROHM              0x10DB
100 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
101 #define PCI_DEVICE_ID_ML7223_SPI        0x800F
102
103 /*
104  * Set the number of SPI instance max
105  * Intel EG20T PCH :            1ch
106  * OKI SEMICONDUCTOR ML7213 IOH :       2ch
107  * OKI SEMICONDUCTOR ML7223 IOH :       1ch
108 */
109 #define PCH_SPI_MAX_DEV                 2
110
111 #define PCH_BUF_SIZE            4096
112 #define PCH_DMA_TRANS_SIZE      12
113
114 static int use_dma = 1;
115
116 struct pch_spi_dma_ctrl {
117         struct dma_async_tx_descriptor  *desc_tx;
118         struct dma_async_tx_descriptor  *desc_rx;
119         struct pch_dma_slave            param_tx;
120         struct pch_dma_slave            param_rx;
121         struct dma_chan         *chan_tx;
122         struct dma_chan         *chan_rx;
123         struct scatterlist              *sg_tx_p;
124         struct scatterlist              *sg_rx_p;
125         struct scatterlist              sg_tx;
126         struct scatterlist              sg_rx;
127         int                             nent;
128         void                            *tx_buf_virt;
129         void                            *rx_buf_virt;
130         dma_addr_t                      tx_buf_dma;
131         dma_addr_t                      rx_buf_dma;
132 };
133 /**
134  * struct pch_spi_data - Holds the SPI channel specific details
135  * @io_remap_addr:              The remapped PCI base address
136  * @master:                     Pointer to the SPI master structure
137  * @work:                       Reference to work queue handler
138  * @wk:                         Workqueue for carrying out execution of the
139  *                              requests
140  * @wait:                       Wait queue for waking up upon receiving an
141  *                              interrupt.
142  * @transfer_complete:          Status of SPI Transfer
143  * @bcurrent_msg_processing:    Status flag for message processing
144  * @lock:                       Lock for protecting this structure
145  * @queue:                      SPI Message queue
146  * @status:                     Status of the SPI driver
147  * @bpw_len:                    Length of data to be transferred in bits per
148  *                              word
149  * @transfer_active:            Flag showing active transfer
150  * @tx_index:                   Transmit data count; for bookkeeping during
151  *                              transfer
152  * @rx_index:                   Receive data count; for bookkeeping during
153  *                              transfer
154  * @tx_buff:                    Buffer for data to be transmitted
155  * @rx_index:                   Buffer for Received data
156  * @n_curnt_chip:               The chip number that this SPI driver currently
157  *                              operates on
158  * @current_chip:               Reference to the current chip that this SPI
159  *                              driver currently operates on
160  * @current_msg:                The current message that this SPI driver is
161  *                              handling
162  * @cur_trans:                  The current transfer that this SPI driver is
163  *                              handling
164  * @board_dat:                  Reference to the SPI device data structure
165  * @plat_dev:                   platform_device structure
166  * @ch:                         SPI channel number
167  * @irq_reg_sts:                Status of IRQ registration
168  */
169 struct pch_spi_data {
170         void __iomem *io_remap_addr;
171         unsigned long io_base_addr;
172         struct spi_master *master;
173         struct work_struct work;
174         struct workqueue_struct *wk;
175         wait_queue_head_t wait;
176         u8 transfer_complete;
177         u8 bcurrent_msg_processing;
178         spinlock_t lock;
179         struct list_head queue;
180         u8 status;
181         u32 bpw_len;
182         u8 transfer_active;
183         u32 tx_index;
184         u32 rx_index;
185         u16 *pkt_tx_buff;
186         u16 *pkt_rx_buff;
187         u8 n_curnt_chip;
188         struct spi_device *current_chip;
189         struct spi_message *current_msg;
190         struct spi_transfer *cur_trans;
191         struct pch_spi_board_data *board_dat;
192         struct platform_device  *plat_dev;
193         int ch;
194         struct pch_spi_dma_ctrl dma;
195         int use_dma;
196         u8 irq_reg_sts;
197 };
198
199 /**
200  * struct pch_spi_board_data - Holds the SPI device specific details
201  * @pdev:               Pointer to the PCI device
202  * @suspend_sts:        Status of suspend
203  * @num:                The number of SPI device instance
204  */
205 struct pch_spi_board_data {
206         struct pci_dev *pdev;
207         u8 suspend_sts;
208         int num;
209 };
210
211 struct pch_pd_dev_save {
212         int num;
213         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
214         struct pch_spi_board_data *board_dat;
215 };
216
217 static struct pci_device_id pch_spi_pcidev_id[] = {
218         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
219         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
220         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
221         { }
222 };
223
224 /**
225  * pch_spi_writereg() - Performs  register writes
226  * @master:     Pointer to struct spi_master.
227  * @idx:        Register offset.
228  * @val:        Value to be written to register.
229  */
230 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
231 {
232         struct pch_spi_data *data = spi_master_get_devdata(master);
233         iowrite32(val, (data->io_remap_addr + idx));
234 }
235
236 /**
237  * pch_spi_readreg() - Performs register reads
238  * @master:     Pointer to struct spi_master.
239  * @idx:        Register offset.
240  */
241 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
242 {
243         struct pch_spi_data *data = spi_master_get_devdata(master);
244         return ioread32(data->io_remap_addr + idx);
245 }
246
247 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
248                                       u32 set, u32 clr)
249 {
250         u32 tmp = pch_spi_readreg(master, idx);
251         tmp = (tmp & ~clr) | set;
252         pch_spi_writereg(master, idx, tmp);
253 }
254
255 static void pch_spi_set_master_mode(struct spi_master *master)
256 {
257         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
258 }
259
260 /**
261  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
262  * @master:     Pointer to struct spi_master.
263  */
264 static void pch_spi_clear_fifo(struct spi_master *master)
265 {
266         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
267         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
268 }
269
270 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
271                                 void __iomem *io_remap_addr)
272 {
273         u32 n_read, tx_index, rx_index, bpw_len;
274         u16 *pkt_rx_buffer, *pkt_tx_buff;
275         int read_cnt;
276         u32 reg_spcr_val;
277         void __iomem *spsr;
278         void __iomem *spdrr;
279         void __iomem *spdwr;
280
281         spsr = io_remap_addr + PCH_SPSR;
282         iowrite32(reg_spsr_val, spsr);
283
284         if (data->transfer_active) {
285                 rx_index = data->rx_index;
286                 tx_index = data->tx_index;
287                 bpw_len = data->bpw_len;
288                 pkt_rx_buffer = data->pkt_rx_buff;
289                 pkt_tx_buff = data->pkt_tx_buff;
290
291                 spdrr = io_remap_addr + PCH_SPDRR;
292                 spdwr = io_remap_addr + PCH_SPDWR;
293
294                 n_read = PCH_READABLE(reg_spsr_val);
295
296                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
297                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
298                         if (tx_index < bpw_len)
299                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
300                 }
301
302                 /* disable RFI if not needed */
303                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
304                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
305                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
306
307                         /* reset rx threshold */
308                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
309                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
310
311                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
312                 }
313
314                 /* update counts */
315                 data->tx_index = tx_index;
316                 data->rx_index = rx_index;
317
318         }
319
320         /* if transfer complete interrupt */
321         if (reg_spsr_val & SPSR_FI_BIT) {
322                 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
323                         /* disable interrupts */
324                         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
325
326                         /* transfer is completed;
327                            inform pch_spi_process_messages */
328                         data->transfer_complete = true;
329                         data->transfer_active = false;
330                         wake_up(&data->wait);
331                 } else {
332                         dev_err(&data->master->dev,
333                                 "%s : Transfer is not completed", __func__);
334                 }
335         }
336 }
337
338 /**
339  * pch_spi_handler() - Interrupt handler
340  * @irq:        The interrupt number.
341  * @dev_id:     Pointer to struct pch_spi_board_data.
342  */
343 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
344 {
345         u32 reg_spsr_val;
346         void __iomem *spsr;
347         void __iomem *io_remap_addr;
348         irqreturn_t ret = IRQ_NONE;
349         struct pch_spi_data *data = dev_id;
350         struct pch_spi_board_data *board_dat = data->board_dat;
351
352         if (board_dat->suspend_sts) {
353                 dev_dbg(&board_dat->pdev->dev,
354                         "%s returning due to suspend\n", __func__);
355                 return IRQ_NONE;
356         }
357
358         io_remap_addr = data->io_remap_addr;
359         spsr = io_remap_addr + PCH_SPSR;
360
361         reg_spsr_val = ioread32(spsr);
362
363         if (reg_spsr_val & SPSR_ORF_BIT) {
364                 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
365                 if (data->current_msg->complete != 0) {
366                         data->transfer_complete = true;
367                         data->current_msg->status = -EIO;
368                         data->current_msg->complete(data->current_msg->context);
369                         data->bcurrent_msg_processing = false;
370                         data->current_msg = NULL;
371                         data->cur_trans = NULL;
372                 }
373         }
374
375         if (data->use_dma)
376                 return IRQ_NONE;
377
378         /* Check if the interrupt is for SPI device */
379         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
380                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
381                 ret = IRQ_HANDLED;
382         }
383
384         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
385                 __func__, ret);
386
387         return ret;
388 }
389
390 /**
391  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
392  * @master:     Pointer to struct spi_master.
393  * @speed_hz:   Baud rate.
394  */
395 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
396 {
397         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
398
399         /* if baud rate is less than we can support limit it */
400         if (n_spbr > PCH_MAX_SPBR)
401                 n_spbr = PCH_MAX_SPBR;
402
403         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
404 }
405
406 /**
407  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
408  * @master:             Pointer to struct spi_master.
409  * @bits_per_word:      Bits per word for SPI transfer.
410  */
411 static void pch_spi_set_bits_per_word(struct spi_master *master,
412                                       u8 bits_per_word)
413 {
414         if (bits_per_word == 8)
415                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
416         else
417                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
418 }
419
420 /**
421  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
422  * @spi:        Pointer to struct spi_device.
423  */
424 static void pch_spi_setup_transfer(struct spi_device *spi)
425 {
426         u32 flags = 0;
427
428         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
429                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
430                 spi->max_speed_hz);
431         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
432
433         /* set bits per word */
434         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
435
436         if (!(spi->mode & SPI_LSB_FIRST))
437                 flags |= SPCR_LSBF_BIT;
438         if (spi->mode & SPI_CPOL)
439                 flags |= SPCR_CPOL_BIT;
440         if (spi->mode & SPI_CPHA)
441                 flags |= SPCR_CPHA_BIT;
442         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
443                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
444
445         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
446         pch_spi_clear_fifo(spi->master);
447 }
448
449 /**
450  * pch_spi_reset() - Clears SPI registers
451  * @master:     Pointer to struct spi_master.
452  */
453 static void pch_spi_reset(struct spi_master *master)
454 {
455         /* write 1 to reset SPI */
456         pch_spi_writereg(master, PCH_SRST, 0x1);
457
458         /* clear reset */
459         pch_spi_writereg(master, PCH_SRST, 0x0);
460 }
461
462 static int pch_spi_setup(struct spi_device *pspi)
463 {
464         /* check bits per word */
465         if (pspi->bits_per_word == 0) {
466                 pspi->bits_per_word = 8;
467                 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
468         }
469
470         if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
471                 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
472                 return -EINVAL;
473         }
474
475         /* Check baud rate setting */
476         /* if baud rate of chip is greater than
477            max we can support,return error */
478         if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
479                 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
480
481         dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
482                 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
483
484         return 0;
485 }
486
487 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
488 {
489
490         struct spi_transfer *transfer;
491         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
492         int retval;
493         unsigned long flags;
494
495         /* validate spi message and baud rate */
496         if (unlikely(list_empty(&pmsg->transfers) == 1)) {
497                 dev_err(&pspi->dev, "%s list empty\n", __func__);
498                 retval = -EINVAL;
499                 goto err_out;
500         }
501
502         if (unlikely(pspi->max_speed_hz == 0)) {
503                 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
504                         __func__, pspi->max_speed_hz);
505                 retval = -EINVAL;
506                 goto err_out;
507         }
508
509         dev_dbg(&pspi->dev, "%s Transfer List not empty. "
510                 "Transfer Speed is set.\n", __func__);
511
512         spin_lock_irqsave(&data->lock, flags);
513         /* validate Tx/Rx buffers and Transfer length */
514         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
515                 if (!transfer->tx_buf && !transfer->rx_buf) {
516                         dev_err(&pspi->dev,
517                                 "%s Tx and Rx buffer NULL\n", __func__);
518                         retval = -EINVAL;
519                         goto err_return_spinlock;
520                 }
521
522                 if (!transfer->len) {
523                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
524                                 __func__);
525                         retval = -EINVAL;
526                         goto err_return_spinlock;
527                 }
528
529                 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
530                         " valid\n", __func__);
531
532                 /* if baud rate has been specified validate the same */
533                 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
534                         transfer->speed_hz = PCH_MAX_BAUDRATE;
535
536                 /* if bits per word has been specified validate the same */
537                 if (transfer->bits_per_word) {
538                         if ((transfer->bits_per_word != 8)
539                             && (transfer->bits_per_word != 16)) {
540                                 retval = -EINVAL;
541                                 dev_err(&pspi->dev,
542                                         "%s Invalid bits per word\n", __func__);
543                                 goto err_return_spinlock;
544                         }
545                 }
546         }
547         spin_unlock_irqrestore(&data->lock, flags);
548
549         /* We won't process any messages if we have been asked to terminate */
550         if (data->status == STATUS_EXITING) {
551                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
552                 retval = -ESHUTDOWN;
553                 goto err_out;
554         }
555
556         /* If suspended ,return -EINVAL */
557         if (data->board_dat->suspend_sts) {
558                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
559                 retval = -EINVAL;
560                 goto err_out;
561         }
562
563         /* set status of message */
564         pmsg->actual_length = 0;
565         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
566
567         pmsg->status = -EINPROGRESS;
568         spin_lock_irqsave(&data->lock, flags);
569         /* add message to queue */
570         list_add_tail(&pmsg->queue, &data->queue);
571         spin_unlock_irqrestore(&data->lock, flags);
572
573         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
574
575         /* schedule work queue to run */
576         queue_work(data->wk, &data->work);
577         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
578
579         retval = 0;
580
581 err_out:
582         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
583         return retval;
584 err_return_spinlock:
585         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
586         spin_unlock_irqrestore(&data->lock, flags);
587         return retval;
588 }
589
590 static inline void pch_spi_select_chip(struct pch_spi_data *data,
591                                        struct spi_device *pspi)
592 {
593         if (data->current_chip != NULL) {
594                 if (pspi->chip_select != data->n_curnt_chip) {
595                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
596                         data->current_chip = NULL;
597                 }
598         }
599
600         data->current_chip = pspi;
601
602         data->n_curnt_chip = data->current_chip->chip_select;
603
604         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
605         pch_spi_setup_transfer(pspi);
606 }
607
608 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
609 {
610         int size;
611         u32 n_writes;
612         int j;
613         struct spi_message *pmsg;
614         const u8 *tx_buf;
615         const u16 *tx_sbuf;
616
617         /* set baud rate if needed */
618         if (data->cur_trans->speed_hz) {
619                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
620                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
621         }
622
623         /* set bits per word if needed */
624         if (data->cur_trans->bits_per_word &&
625             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
626                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
627                 pch_spi_set_bits_per_word(data->master,
628                                           data->cur_trans->bits_per_word);
629                 *bpw = data->cur_trans->bits_per_word;
630         } else {
631                 *bpw = data->current_msg->spi->bits_per_word;
632         }
633
634         /* reset Tx/Rx index */
635         data->tx_index = 0;
636         data->rx_index = 0;
637
638         data->bpw_len = data->cur_trans->len / (*bpw / 8);
639
640         /* find alloc size */
641         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
642
643         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
644         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
645         if (data->pkt_tx_buff != NULL) {
646                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
647                 if (!data->pkt_rx_buff)
648                         kfree(data->pkt_tx_buff);
649         }
650
651         if (!data->pkt_rx_buff) {
652                 /* flush queue and set status of all transfers to -ENOMEM */
653                 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
654                 list_for_each_entry(pmsg, data->queue.next, queue) {
655                         pmsg->status = -ENOMEM;
656
657                         if (pmsg->complete != 0)
658                                 pmsg->complete(pmsg->context);
659
660                         /* delete from queue */
661                         list_del_init(&pmsg->queue);
662                 }
663                 return;
664         }
665
666         /* copy Tx Data */
667         if (data->cur_trans->tx_buf != NULL) {
668                 if (*bpw == 8) {
669                         tx_buf = data->cur_trans->tx_buf;
670                         for (j = 0; j < data->bpw_len; j++)
671                                 data->pkt_tx_buff[j] = *tx_buf++;
672                 } else {
673                         tx_sbuf = data->cur_trans->tx_buf;
674                         for (j = 0; j < data->bpw_len; j++)
675                                 data->pkt_tx_buff[j] = *tx_sbuf++;
676                 }
677         }
678
679         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
680         n_writes = data->bpw_len;
681         if (n_writes > PCH_MAX_FIFO_DEPTH)
682                 n_writes = PCH_MAX_FIFO_DEPTH;
683
684         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
685                 "0x2 to SSNXCR\n", __func__);
686         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
687
688         for (j = 0; j < n_writes; j++)
689                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
690
691         /* update tx_index */
692         data->tx_index = j;
693
694         /* reset transfer complete flag */
695         data->transfer_complete = false;
696         data->transfer_active = true;
697 }
698
699 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
700 {
701         struct spi_message *pmsg;
702         dev_dbg(&data->master->dev, "%s called\n", __func__);
703         /* Invoke complete callback
704          * [To the spi core..indicating end of transfer] */
705         data->current_msg->status = 0;
706
707         if (data->current_msg->complete != 0) {
708                 dev_dbg(&data->master->dev,
709                         "%s:Invoking callback of SPI core\n", __func__);
710                 data->current_msg->complete(data->current_msg->context);
711         }
712
713         /* update status in global variable */
714         data->bcurrent_msg_processing = false;
715
716         dev_dbg(&data->master->dev,
717                 "%s:data->bcurrent_msg_processing = false\n", __func__);
718
719         data->current_msg = NULL;
720         data->cur_trans = NULL;
721
722         /* check if we have items in list and not suspending
723          * return 1 if list empty */
724         if ((list_empty(&data->queue) == 0) &&
725             (!data->board_dat->suspend_sts) &&
726             (data->status != STATUS_EXITING)) {
727                 /* We have some more work to do (either there is more tranint
728                  * bpw;sfer requests in the current message or there are
729                  *more messages)
730                  */
731                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
732                 queue_work(data->wk, &data->work);
733         } else if (data->board_dat->suspend_sts ||
734                    data->status == STATUS_EXITING) {
735                 dev_dbg(&data->master->dev,
736                         "%s suspend/remove initiated, flushing queue\n",
737                         __func__);
738                 list_for_each_entry(pmsg, data->queue.next, queue) {
739                         pmsg->status = -EIO;
740
741                         if (pmsg->complete)
742                                 pmsg->complete(pmsg->context);
743
744                         /* delete from queue */
745                         list_del_init(&pmsg->queue);
746                 }
747         }
748 }
749
750 static void pch_spi_set_ir(struct pch_spi_data *data)
751 {
752         /* enable interrupts, set threshold, enable SPI */
753         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
754                 /* set receive threshold to PCH_RX_THOLD */
755                 pch_spi_setclr_reg(data->master, PCH_SPCR,
756                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
757                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
758                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
759                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
760         else
761                 /* set receive threshold to maximum */
762                 pch_spi_setclr_reg(data->master, PCH_SPCR,
763                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
764                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
765                                    SPCR_SPE_BIT,
766                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
767
768         /* Wait until the transfer completes; go to sleep after
769                                  initiating the transfer. */
770         dev_dbg(&data->master->dev,
771                 "%s:waiting for transfer to get over\n", __func__);
772
773         wait_event_interruptible(data->wait, data->transfer_complete);
774
775         /* clear all interrupts */
776         pch_spi_writereg(data->master, PCH_SPSR,
777                          pch_spi_readreg(data->master, PCH_SPSR));
778         /* Disable interrupts and SPI transfer */
779         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
780         /* clear FIFO */
781         pch_spi_clear_fifo(data->master);
782 }
783
784 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
785 {
786         int j;
787         u8 *rx_buf;
788         u16 *rx_sbuf;
789
790         /* copy Rx Data */
791         if (!data->cur_trans->rx_buf)
792                 return;
793
794         if (bpw == 8) {
795                 rx_buf = data->cur_trans->rx_buf;
796                 for (j = 0; j < data->bpw_len; j++)
797                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
798         } else {
799                 rx_sbuf = data->cur_trans->rx_buf;
800                 for (j = 0; j < data->bpw_len; j++)
801                         *rx_sbuf++ = data->pkt_rx_buff[j];
802         }
803 }
804
805 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
806 {
807         int j;
808         u8 *rx_buf;
809         u16 *rx_sbuf;
810         const u8 *rx_dma_buf;
811         const u16 *rx_dma_sbuf;
812
813         /* copy Rx Data */
814         if (!data->cur_trans->rx_buf)
815                 return;
816
817         if (bpw == 8) {
818                 rx_buf = data->cur_trans->rx_buf;
819                 rx_dma_buf = data->dma.rx_buf_virt;
820                 for (j = 0; j < data->bpw_len; j++)
821                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
822         } else {
823                 rx_sbuf = data->cur_trans->rx_buf;
824                 rx_dma_sbuf = data->dma.rx_buf_virt;
825                 for (j = 0; j < data->bpw_len; j++)
826                         *rx_sbuf++ = *rx_dma_sbuf++;
827         }
828 }
829
830 static int pch_spi_start_transfer(struct pch_spi_data *data)
831 {
832         struct pch_spi_dma_ctrl *dma;
833         unsigned long flags;
834         int rtn;
835
836         dma = &data->dma;
837
838         spin_lock_irqsave(&data->lock, flags);
839
840         /* disable interrupts, SPI set enable */
841         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
842
843         spin_unlock_irqrestore(&data->lock, flags);
844
845         /* Wait until the transfer completes; go to sleep after
846                                  initiating the transfer. */
847         dev_dbg(&data->master->dev,
848                 "%s:waiting for transfer to get over\n", __func__);
849         rtn = wait_event_interruptible_timeout(data->wait,
850                                                data->transfer_complete,
851                                                msecs_to_jiffies(2 * HZ));
852
853         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
854                             DMA_FROM_DEVICE);
855
856         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
857                             DMA_FROM_DEVICE);
858         memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
859
860         async_tx_ack(dma->desc_rx);
861         async_tx_ack(dma->desc_tx);
862         kfree(dma->sg_tx_p);
863         kfree(dma->sg_rx_p);
864
865         spin_lock_irqsave(&data->lock, flags);
866
867         /* clear fifo threshold, disable interrupts, disable SPI transfer */
868         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
869                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
870                            SPCR_SPE_BIT);
871         /* clear all interrupts */
872         pch_spi_writereg(data->master, PCH_SPSR,
873                          pch_spi_readreg(data->master, PCH_SPSR));
874         /* clear FIFO */
875         pch_spi_clear_fifo(data->master);
876
877         spin_unlock_irqrestore(&data->lock, flags);
878
879         return rtn;
880 }
881
882 static void pch_dma_rx_complete(void *arg)
883 {
884         struct pch_spi_data *data = arg;
885
886         /* transfer is completed;inform pch_spi_process_messages_dma */
887         data->transfer_complete = true;
888         wake_up_interruptible(&data->wait);
889 }
890
891 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
892 {
893         struct pch_dma_slave *param = slave;
894
895         if ((chan->chan_id == param->chan_id) &&
896             (param->dma_dev == chan->device->dev)) {
897                 chan->private = param;
898                 return true;
899         } else {
900                 return false;
901         }
902 }
903
904 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
905 {
906         dma_cap_mask_t mask;
907         struct dma_chan *chan;
908         struct pci_dev *dma_dev;
909         struct pch_dma_slave *param;
910         struct pch_spi_dma_ctrl *dma;
911         unsigned int width;
912
913         if (bpw == 8)
914                 width = PCH_DMA_WIDTH_1_BYTE;
915         else
916                 width = PCH_DMA_WIDTH_2_BYTES;
917
918         dma = &data->dma;
919         dma_cap_zero(mask);
920         dma_cap_set(DMA_SLAVE, mask);
921
922         /* Get DMA's dev information */
923         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
924
925         /* Set Tx DMA */
926         param = &dma->param_tx;
927         param->dma_dev = &dma_dev->dev;
928         param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
929         param->tx_reg = data->io_base_addr + PCH_SPDWR;
930         param->width = width;
931         chan = dma_request_channel(mask, pch_spi_filter, param);
932         if (!chan) {
933                 dev_err(&data->master->dev,
934                         "ERROR: dma_request_channel FAILS(Tx)\n");
935                 data->use_dma = 0;
936                 return;
937         }
938         dma->chan_tx = chan;
939
940         /* Set Rx DMA */
941         param = &dma->param_rx;
942         param->dma_dev = &dma_dev->dev;
943         param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
944         param->rx_reg = data->io_base_addr + PCH_SPDRR;
945         param->width = width;
946         chan = dma_request_channel(mask, pch_spi_filter, param);
947         if (!chan) {
948                 dev_err(&data->master->dev,
949                         "ERROR: dma_request_channel FAILS(Rx)\n");
950                 dma_release_channel(dma->chan_tx);
951                 dma->chan_tx = NULL;
952                 data->use_dma = 0;
953                 return;
954         }
955         dma->chan_rx = chan;
956 }
957
958 static void pch_spi_release_dma(struct pch_spi_data *data)
959 {
960         struct pch_spi_dma_ctrl *dma;
961
962         dma = &data->dma;
963         if (dma->chan_tx) {
964                 dma_release_channel(dma->chan_tx);
965                 dma->chan_tx = NULL;
966         }
967         if (dma->chan_rx) {
968                 dma_release_channel(dma->chan_rx);
969                 dma->chan_rx = NULL;
970         }
971         return;
972 }
973
974 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
975 {
976         const u8 *tx_buf;
977         const u16 *tx_sbuf;
978         u8 *tx_dma_buf;
979         u16 *tx_dma_sbuf;
980         struct scatterlist *sg;
981         struct dma_async_tx_descriptor *desc_tx;
982         struct dma_async_tx_descriptor *desc_rx;
983         int num;
984         int i;
985         int size;
986         int rem;
987         unsigned long flags;
988         struct pch_spi_dma_ctrl *dma;
989
990         dma = &data->dma;
991
992         /* set baud rate if needed */
993         if (data->cur_trans->speed_hz) {
994                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
995                 spin_lock_irqsave(&data->lock, flags);
996                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
997                 spin_unlock_irqrestore(&data->lock, flags);
998         }
999
1000         /* set bits per word if needed */
1001         if (data->cur_trans->bits_per_word &&
1002             (data->current_msg->spi->bits_per_word !=
1003              data->cur_trans->bits_per_word)) {
1004                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
1005                 spin_lock_irqsave(&data->lock, flags);
1006                 pch_spi_set_bits_per_word(data->master,
1007                                           data->cur_trans->bits_per_word);
1008                 spin_unlock_irqrestore(&data->lock, flags);
1009                 *bpw = data->cur_trans->bits_per_word;
1010         } else {
1011                 *bpw = data->current_msg->spi->bits_per_word;
1012         }
1013         data->bpw_len = data->cur_trans->len / (*bpw / 8);
1014
1015         /* copy Tx Data */
1016         if (data->cur_trans->tx_buf != NULL) {
1017                 if (*bpw == 8) {
1018                         tx_buf = data->cur_trans->tx_buf;
1019                         tx_dma_buf = dma->tx_buf_virt;
1020                         for (i = 0; i < data->bpw_len; i++)
1021                                 *tx_dma_buf++ = *tx_buf++;
1022                 } else {
1023                         tx_sbuf = data->cur_trans->tx_buf;
1024                         tx_dma_sbuf = dma->tx_buf_virt;
1025                         for (i = 0; i < data->bpw_len; i++)
1026                                 *tx_dma_sbuf++ = *tx_sbuf++;
1027                 }
1028         }
1029         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1030                 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1031                 size = PCH_DMA_TRANS_SIZE;
1032                 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1033         } else {
1034                 num = 1;
1035                 size = data->bpw_len;
1036                 rem = data->bpw_len;
1037         }
1038         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1039                 __func__, num, size, rem);
1040         spin_lock_irqsave(&data->lock, flags);
1041
1042         /* set receive fifo threshold and transmit fifo threshold */
1043         pch_spi_setclr_reg(data->master, PCH_SPCR,
1044                            ((size - 1) << SPCR_RFIC_FIELD) |
1045                            (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1046                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1047
1048         spin_unlock_irqrestore(&data->lock, flags);
1049
1050         /* RX */
1051         dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1052         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1053         /* offset, length setting */
1054         sg = dma->sg_rx_p;
1055         for (i = 0; i < num; i++, sg++) {
1056                 if (i == (num - 2)) {
1057                         sg->offset = size * i;
1058                         sg->offset = sg->offset * (*bpw / 8);
1059                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1060                                     sg->offset);
1061                         sg_dma_len(sg) = rem;
1062                 } else if (i == (num - 1)) {
1063                         sg->offset = size * (i - 1) + rem;
1064                         sg->offset = sg->offset * (*bpw / 8);
1065                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1066                                     sg->offset);
1067                         sg_dma_len(sg) = size;
1068                 } else {
1069                         sg->offset = size * i;
1070                         sg->offset = sg->offset * (*bpw / 8);
1071                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1072                                     sg->offset);
1073                         sg_dma_len(sg) = size;
1074                 }
1075                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1076         }
1077         sg = dma->sg_rx_p;
1078         desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1079                                         num, DMA_DEV_TO_MEM,
1080                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1081         if (!desc_rx) {
1082                 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1083                         __func__);
1084                 return;
1085         }
1086         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1087         desc_rx->callback = pch_dma_rx_complete;
1088         desc_rx->callback_param = data;
1089         dma->nent = num;
1090         dma->desc_rx = desc_rx;
1091
1092         /* TX */
1093         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1094                 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1095                 size = PCH_DMA_TRANS_SIZE;
1096                 rem = 16;
1097         } else {
1098                 num = 1;
1099                 size = data->bpw_len;
1100                 rem = data->bpw_len;
1101         }
1102
1103         dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1104         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1105         /* offset, length setting */
1106         sg = dma->sg_tx_p;
1107         for (i = 0; i < num; i++, sg++) {
1108                 if (i == 0) {
1109                         sg->offset = 0;
1110                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1111                                     sg->offset);
1112                         sg_dma_len(sg) = rem;
1113                 } else {
1114                         sg->offset = rem + size * (i - 1);
1115                         sg->offset = sg->offset * (*bpw / 8);
1116                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1117                                     sg->offset);
1118                         sg_dma_len(sg) = size;
1119                 }
1120                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1121         }
1122         sg = dma->sg_tx_p;
1123         desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1124                                         sg, num, DMA_MEM_TO_DEV,
1125                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1126         if (!desc_tx) {
1127                 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1128                         __func__);
1129                 return;
1130         }
1131         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1132         desc_tx->callback = NULL;
1133         desc_tx->callback_param = data;
1134         dma->nent = num;
1135         dma->desc_tx = desc_tx;
1136
1137         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1138                 "0x2 to SSNXCR\n", __func__);
1139
1140         spin_lock_irqsave(&data->lock, flags);
1141         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1142         desc_rx->tx_submit(desc_rx);
1143         desc_tx->tx_submit(desc_tx);
1144         spin_unlock_irqrestore(&data->lock, flags);
1145
1146         /* reset transfer complete flag */
1147         data->transfer_complete = false;
1148 }
1149
1150 static void pch_spi_process_messages(struct work_struct *pwork)
1151 {
1152         struct spi_message *pmsg;
1153         struct pch_spi_data *data;
1154         int bpw;
1155
1156         data = container_of(pwork, struct pch_spi_data, work);
1157         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1158
1159         spin_lock(&data->lock);
1160         /* check if suspend has been initiated;if yes flush queue */
1161         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1162                 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1163                         "flushing queue\n", __func__);
1164                 list_for_each_entry(pmsg, data->queue.next, queue) {
1165                         pmsg->status = -EIO;
1166
1167                         if (pmsg->complete != 0) {
1168                                 spin_unlock(&data->lock);
1169                                 pmsg->complete(pmsg->context);
1170                                 spin_lock(&data->lock);
1171                         }
1172
1173                         /* delete from queue */
1174                         list_del_init(&pmsg->queue);
1175                 }
1176
1177                 spin_unlock(&data->lock);
1178                 return;
1179         }
1180
1181         data->bcurrent_msg_processing = true;
1182         dev_dbg(&data->master->dev,
1183                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1184
1185         /* Get the message from the queue and delete it from there. */
1186         data->current_msg = list_entry(data->queue.next, struct spi_message,
1187                                         queue);
1188
1189         list_del_init(&data->current_msg->queue);
1190
1191         data->current_msg->status = 0;
1192
1193         pch_spi_select_chip(data, data->current_msg->spi);
1194
1195         spin_unlock(&data->lock);
1196
1197         if (data->use_dma)
1198                 pch_spi_request_dma(data,
1199                                     data->current_msg->spi->bits_per_word);
1200         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1201         do {
1202                 /* If we are already processing a message get the next
1203                 transfer structure from the message otherwise retrieve
1204                 the 1st transfer request from the message. */
1205                 spin_lock(&data->lock);
1206                 if (data->cur_trans == NULL) {
1207                         data->cur_trans =
1208                                 list_entry(data->current_msg->transfers.next,
1209                                            struct spi_transfer, transfer_list);
1210                         dev_dbg(&data->master->dev, "%s "
1211                                 ":Getting 1st transfer message\n", __func__);
1212                 } else {
1213                         data->cur_trans =
1214                                 list_entry(data->cur_trans->transfer_list.next,
1215                                            struct spi_transfer, transfer_list);
1216                         dev_dbg(&data->master->dev, "%s "
1217                                 ":Getting next transfer message\n", __func__);
1218                 }
1219                 spin_unlock(&data->lock);
1220
1221                 if (data->use_dma) {
1222                         pch_spi_handle_dma(data, &bpw);
1223                         if (!pch_spi_start_transfer(data))
1224                                 goto out;
1225                         pch_spi_copy_rx_data_for_dma(data, bpw);
1226                 } else {
1227                         pch_spi_set_tx(data, &bpw);
1228                         pch_spi_set_ir(data);
1229                         pch_spi_copy_rx_data(data, bpw);
1230                         kfree(data->pkt_rx_buff);
1231                         data->pkt_rx_buff = NULL;
1232                         kfree(data->pkt_tx_buff);
1233                         data->pkt_tx_buff = NULL;
1234                 }
1235                 /* increment message count */
1236                 data->current_msg->actual_length += data->cur_trans->len;
1237
1238                 dev_dbg(&data->master->dev,
1239                         "%s:data->current_msg->actual_length=%d\n",
1240                         __func__, data->current_msg->actual_length);
1241
1242                 /* check for delay */
1243                 if (data->cur_trans->delay_usecs) {
1244                         dev_dbg(&data->master->dev, "%s:"
1245                                 "delay in usec=%d\n", __func__,
1246                                 data->cur_trans->delay_usecs);
1247                         udelay(data->cur_trans->delay_usecs);
1248                 }
1249
1250                 spin_lock(&data->lock);
1251
1252                 /* No more transfer in this message. */
1253                 if ((data->cur_trans->transfer_list.next) ==
1254                     &(data->current_msg->transfers)) {
1255                         pch_spi_nomore_transfer(data);
1256                 }
1257
1258                 spin_unlock(&data->lock);
1259
1260         } while (data->cur_trans != NULL);
1261
1262 out:
1263         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1264         if (data->use_dma)
1265                 pch_spi_release_dma(data);
1266 }
1267
1268 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1269                                    struct pch_spi_data *data)
1270 {
1271         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1272
1273         /* free workqueue */
1274         if (data->wk != NULL) {
1275                 destroy_workqueue(data->wk);
1276                 data->wk = NULL;
1277                 dev_dbg(&board_dat->pdev->dev,
1278                         "%s destroy_workqueue invoked successfully\n",
1279                         __func__);
1280         }
1281 }
1282
1283 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1284                                  struct pch_spi_data *data)
1285 {
1286         int retval = 0;
1287
1288         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1289
1290         /* create workqueue */
1291         data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1292         if (!data->wk) {
1293                 dev_err(&board_dat->pdev->dev,
1294                         "%s create_singlet hread_workqueue failed\n", __func__);
1295                 retval = -EBUSY;
1296                 goto err_return;
1297         }
1298
1299         /* reset PCH SPI h/w */
1300         pch_spi_reset(data->master);
1301         dev_dbg(&board_dat->pdev->dev,
1302                 "%s pch_spi_reset invoked successfully\n", __func__);
1303
1304         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1305
1306 err_return:
1307         if (retval != 0) {
1308                 dev_err(&board_dat->pdev->dev,
1309                         "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1310                 pch_spi_free_resources(board_dat, data);
1311         }
1312
1313         dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1314
1315         return retval;
1316 }
1317
1318 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1319                              struct pch_spi_data *data)
1320 {
1321         struct pch_spi_dma_ctrl *dma;
1322
1323         dma = &data->dma;
1324         if (dma->tx_buf_dma)
1325                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1326                                   dma->tx_buf_virt, dma->tx_buf_dma);
1327         if (dma->rx_buf_dma)
1328                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1329                                   dma->rx_buf_virt, dma->rx_buf_dma);
1330         return;
1331 }
1332
1333 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1334                               struct pch_spi_data *data)
1335 {
1336         struct pch_spi_dma_ctrl *dma;
1337
1338         dma = &data->dma;
1339         /* Get Consistent memory for Tx DMA */
1340         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1341                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1342         /* Get Consistent memory for Rx DMA */
1343         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1344                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1345 }
1346
1347 static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1348 {
1349         int ret;
1350         struct spi_master *master;
1351         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1352         struct pch_spi_data *data;
1353
1354         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1355
1356         master = spi_alloc_master(&board_dat->pdev->dev,
1357                                   sizeof(struct pch_spi_data));
1358         if (!master) {
1359                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1360                         plat_dev->id);
1361                 return -ENOMEM;
1362         }
1363
1364         data = spi_master_get_devdata(master);
1365         data->master = master;
1366
1367         platform_set_drvdata(plat_dev, data);
1368
1369         /* baseaddress + address offset) */
1370         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1371                                          PCH_ADDRESS_SIZE * plat_dev->id;
1372         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1373                                          PCH_ADDRESS_SIZE * plat_dev->id;
1374         if (!data->io_remap_addr) {
1375                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1376                 ret = -ENOMEM;
1377                 goto err_pci_iomap;
1378         }
1379
1380         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1381                 plat_dev->id, data->io_remap_addr);
1382
1383         /* initialize members of SPI master */
1384         master->bus_num = -1;
1385         master->num_chipselect = PCH_MAX_CS;
1386         master->setup = pch_spi_setup;
1387         master->transfer = pch_spi_transfer;
1388
1389         data->board_dat = board_dat;
1390         data->plat_dev = plat_dev;
1391         data->n_curnt_chip = 255;
1392         data->status = STATUS_RUNNING;
1393         data->ch = plat_dev->id;
1394         data->use_dma = use_dma;
1395
1396         INIT_LIST_HEAD(&data->queue);
1397         spin_lock_init(&data->lock);
1398         INIT_WORK(&data->work, pch_spi_process_messages);
1399         init_waitqueue_head(&data->wait);
1400
1401         ret = pch_spi_get_resources(board_dat, data);
1402         if (ret) {
1403                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1404                 goto err_spi_get_resources;
1405         }
1406
1407         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1408                           IRQF_SHARED, KBUILD_MODNAME, data);
1409         if (ret) {
1410                 dev_err(&plat_dev->dev,
1411                         "%s request_irq failed\n", __func__);
1412                 goto err_request_irq;
1413         }
1414         data->irq_reg_sts = true;
1415
1416         pch_spi_set_master_mode(master);
1417
1418         ret = spi_register_master(master);
1419         if (ret != 0) {
1420                 dev_err(&plat_dev->dev,
1421                         "%s spi_register_master FAILED\n", __func__);
1422                 goto err_spi_register_master;
1423         }
1424
1425         if (use_dma) {
1426                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1427                 pch_alloc_dma_buf(board_dat, data);
1428         }
1429
1430         return 0;
1431
1432 err_spi_register_master:
1433         free_irq(board_dat->pdev->irq, board_dat);
1434 err_request_irq:
1435         pch_spi_free_resources(board_dat, data);
1436 err_spi_get_resources:
1437         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1438 err_pci_iomap:
1439         spi_master_put(master);
1440
1441         return ret;
1442 }
1443
1444 static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1445 {
1446         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1447         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1448         int count;
1449         unsigned long flags;
1450
1451         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1452                 __func__, plat_dev->id, board_dat->pdev->irq);
1453
1454         if (use_dma)
1455                 pch_free_dma_buf(board_dat, data);
1456
1457         /* check for any pending messages; no action is taken if the queue
1458          * is still full; but at least we tried.  Unload anyway */
1459         count = 500;
1460         spin_lock_irqsave(&data->lock, flags);
1461         data->status = STATUS_EXITING;
1462         while ((list_empty(&data->queue) == 0) && --count) {
1463                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1464                         __func__);
1465                 spin_unlock_irqrestore(&data->lock, flags);
1466                 msleep(PCH_SLEEP_TIME);
1467                 spin_lock_irqsave(&data->lock, flags);
1468         }
1469         spin_unlock_irqrestore(&data->lock, flags);
1470
1471         pch_spi_free_resources(board_dat, data);
1472         /* disable interrupts & free IRQ */
1473         if (data->irq_reg_sts) {
1474                 /* disable interrupts */
1475                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1476                 data->irq_reg_sts = false;
1477                 free_irq(board_dat->pdev->irq, data);
1478         }
1479
1480         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1481         spi_unregister_master(data->master);
1482         spi_master_put(data->master);
1483         platform_set_drvdata(plat_dev, NULL);
1484
1485         return 0;
1486 }
1487 #ifdef CONFIG_PM
1488 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1489                               pm_message_t state)
1490 {
1491         u8 count;
1492         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1493         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1494
1495         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1496
1497         if (!board_dat) {
1498                 dev_err(&pd_dev->dev,
1499                         "%s pci_get_drvdata returned NULL\n", __func__);
1500                 return -EFAULT;
1501         }
1502
1503         /* check if the current message is processed:
1504            Only after thats done the transfer will be suspended */
1505         count = 255;
1506         while ((--count) > 0) {
1507                 if (!(data->bcurrent_msg_processing))
1508                         break;
1509                 msleep(PCH_SLEEP_TIME);
1510         }
1511
1512         /* Free IRQ */
1513         if (data->irq_reg_sts) {
1514                 /* disable all interrupts */
1515                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1516                 pch_spi_reset(data->master);
1517                 free_irq(board_dat->pdev->irq, data);
1518
1519                 data->irq_reg_sts = false;
1520                 dev_dbg(&pd_dev->dev,
1521                         "%s free_irq invoked successfully.\n", __func__);
1522         }
1523
1524         return 0;
1525 }
1526
1527 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1528 {
1529         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1530         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1531         int retval;
1532
1533         if (!board_dat) {
1534                 dev_err(&pd_dev->dev,
1535                         "%s pci_get_drvdata returned NULL\n", __func__);
1536                 return -EFAULT;
1537         }
1538
1539         if (!data->irq_reg_sts) {
1540                 /* register IRQ */
1541                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1542                                      IRQF_SHARED, KBUILD_MODNAME, data);
1543                 if (retval < 0) {
1544                         dev_err(&pd_dev->dev,
1545                                 "%s request_irq failed\n", __func__);
1546                         return retval;
1547                 }
1548
1549                 /* reset PCH SPI h/w */
1550                 pch_spi_reset(data->master);
1551                 pch_spi_set_master_mode(data->master);
1552                 data->irq_reg_sts = true;
1553         }
1554         return 0;
1555 }
1556 #else
1557 #define pch_spi_pd_suspend NULL
1558 #define pch_spi_pd_resume NULL
1559 #endif
1560
1561 static struct platform_driver pch_spi_pd_driver = {
1562         .driver = {
1563                 .name = "pch-spi",
1564                 .owner = THIS_MODULE,
1565         },
1566         .probe = pch_spi_pd_probe,
1567         .remove = __devexit_p(pch_spi_pd_remove),
1568         .suspend = pch_spi_pd_suspend,
1569         .resume = pch_spi_pd_resume
1570 };
1571
1572 static int __devinit pch_spi_probe(struct pci_dev *pdev,
1573                                    const struct pci_device_id *id)
1574 {
1575         struct pch_spi_board_data *board_dat;
1576         struct platform_device *pd_dev = NULL;
1577         int retval;
1578         int i;
1579         struct pch_pd_dev_save *pd_dev_save;
1580
1581         pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1582         if (!pd_dev_save) {
1583                 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1584                 return -ENOMEM;
1585         }
1586
1587         board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1588         if (!board_dat) {
1589                 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1590                 retval = -ENOMEM;
1591                 goto err_no_mem;
1592         }
1593
1594         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1595         if (retval) {
1596                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1597                 goto pci_request_regions;
1598         }
1599
1600         board_dat->pdev = pdev;
1601         board_dat->num = id->driver_data;
1602         pd_dev_save->num = id->driver_data;
1603         pd_dev_save->board_dat = board_dat;
1604
1605         retval = pci_enable_device(pdev);
1606         if (retval) {
1607                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1608                 goto pci_enable_device;
1609         }
1610
1611         for (i = 0; i < board_dat->num; i++) {
1612                 pd_dev = platform_device_alloc("pch-spi", i);
1613                 if (!pd_dev) {
1614                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1615                         goto err_platform_device;
1616                 }
1617                 pd_dev_save->pd_save[i] = pd_dev;
1618                 pd_dev->dev.parent = &pdev->dev;
1619
1620                 retval = platform_device_add_data(pd_dev, board_dat,
1621                                                   sizeof(*board_dat));
1622                 if (retval) {
1623                         dev_err(&pdev->dev,
1624                                 "platform_device_add_data failed\n");
1625                         platform_device_put(pd_dev);
1626                         goto err_platform_device;
1627                 }
1628
1629                 retval = platform_device_add(pd_dev);
1630                 if (retval) {
1631                         dev_err(&pdev->dev, "platform_device_add failed\n");
1632                         platform_device_put(pd_dev);
1633                         goto err_platform_device;
1634                 }
1635         }
1636
1637         pci_set_drvdata(pdev, pd_dev_save);
1638
1639         return 0;
1640
1641 err_platform_device:
1642         pci_disable_device(pdev);
1643 pci_enable_device:
1644         pci_release_regions(pdev);
1645 pci_request_regions:
1646         kfree(board_dat);
1647 err_no_mem:
1648         kfree(pd_dev_save);
1649
1650         return retval;
1651 }
1652
1653 static void __devexit pch_spi_remove(struct pci_dev *pdev)
1654 {
1655         int i;
1656         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1657
1658         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1659
1660         for (i = 0; i < pd_dev_save->num; i++)
1661                 platform_device_unregister(pd_dev_save->pd_save[i]);
1662
1663         pci_disable_device(pdev);
1664         pci_release_regions(pdev);
1665         kfree(pd_dev_save->board_dat);
1666         kfree(pd_dev_save);
1667 }
1668
1669 #ifdef CONFIG_PM
1670 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1671 {
1672         int retval;
1673         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1674
1675         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1676
1677         pd_dev_save->board_dat->suspend_sts = true;
1678
1679         /* save config space */
1680         retval = pci_save_state(pdev);
1681         if (retval == 0) {
1682                 pci_enable_wake(pdev, PCI_D3hot, 0);
1683                 pci_disable_device(pdev);
1684                 pci_set_power_state(pdev, PCI_D3hot);
1685         } else {
1686                 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1687         }
1688
1689         return retval;
1690 }
1691
1692 static int pch_spi_resume(struct pci_dev *pdev)
1693 {
1694         int retval;
1695         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1696         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1697
1698         pci_set_power_state(pdev, PCI_D0);
1699         pci_restore_state(pdev);
1700
1701         retval = pci_enable_device(pdev);
1702         if (retval < 0) {
1703                 dev_err(&pdev->dev,
1704                         "%s pci_enable_device failed\n", __func__);
1705         } else {
1706                 pci_enable_wake(pdev, PCI_D3hot, 0);
1707
1708                 /* set suspend status to false */
1709                 pd_dev_save->board_dat->suspend_sts = false;
1710         }
1711
1712         return retval;
1713 }
1714 #else
1715 #define pch_spi_suspend NULL
1716 #define pch_spi_resume NULL
1717
1718 #endif
1719
1720 static struct pci_driver pch_spi_pcidev = {
1721         .name = "pch_spi",
1722         .id_table = pch_spi_pcidev_id,
1723         .probe = pch_spi_probe,
1724         .remove = pch_spi_remove,
1725         .suspend = pch_spi_suspend,
1726         .resume = pch_spi_resume,
1727 };
1728
1729 static int __init pch_spi_init(void)
1730 {
1731         int ret;
1732         ret = platform_driver_register(&pch_spi_pd_driver);
1733         if (ret)
1734                 return ret;
1735
1736         ret = pci_register_driver(&pch_spi_pcidev);
1737         if (ret)
1738                 return ret;
1739
1740         return 0;
1741 }
1742 module_init(pch_spi_init);
1743
1744 static void __exit pch_spi_exit(void)
1745 {
1746         pci_unregister_driver(&pch_spi_pcidev);
1747         platform_driver_unregister(&pch_spi_pd_driver);
1748 }
1749 module_exit(pch_spi_exit);
1750
1751 module_param(use_dma, int, 0644);
1752 MODULE_PARM_DESC(use_dma,
1753                  "to use DMA for data transfers pass 1 else 0; default 1");
1754
1755 MODULE_LICENSE("GPL");
1756 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver");