Merge branch 'spi/merge' into spi/next
[linux-2.6.git] / drivers / spi / spi-bfin5xx.c
1 /*
2  * Blackfin On-Chip SPI Driver
3  *
4  * Copyright 2004-2010 Analog Devices Inc.
5  *
6  * Enter bugs at http://blackfin.uclinux.org/
7  *
8  * Licensed under the GPL-2 or later.
9  */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
25
26 #include <asm/dma.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
30
31 #define DRV_NAME        "bfin-spi"
32 #define DRV_AUTHOR      "Bryan Wu, Luke Yang"
33 #define DRV_DESC        "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION     "1.0"
35
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
39
40 #define START_STATE     ((void *)0)
41 #define RUNNING_STATE   ((void *)1)
42 #define DONE_STATE      ((void *)2)
43 #define ERROR_STATE     ((void *)-1)
44
45 struct bfin_spi_master_data;
46
47 struct bfin_spi_transfer_ops {
48         void (*write) (struct bfin_spi_master_data *);
49         void (*read) (struct bfin_spi_master_data *);
50         void (*duplex) (struct bfin_spi_master_data *);
51 };
52
53 struct bfin_spi_master_data {
54         /* Driver model hookup */
55         struct platform_device *pdev;
56
57         /* SPI framework hookup */
58         struct spi_master *master;
59
60         /* Regs base of SPI controller */
61         void __iomem *regs_base;
62
63         /* Pin request list */
64         u16 *pin_req;
65
66         /* BFIN hookup */
67         struct bfin5xx_spi_master *master_info;
68
69         /* Driver message queue */
70         struct workqueue_struct *workqueue;
71         struct work_struct pump_messages;
72         spinlock_t lock;
73         struct list_head queue;
74         int busy;
75         bool running;
76
77         /* Message Transfer pump */
78         struct tasklet_struct pump_transfers;
79
80         /* Current message transfer state info */
81         struct spi_message *cur_msg;
82         struct spi_transfer *cur_transfer;
83         struct bfin_spi_slave_data *cur_chip;
84         size_t len_in_bytes;
85         size_t len;
86         void *tx;
87         void *tx_end;
88         void *rx;
89         void *rx_end;
90
91         /* DMA stuffs */
92         int dma_channel;
93         int dma_mapped;
94         int dma_requested;
95         dma_addr_t rx_dma;
96         dma_addr_t tx_dma;
97
98         int irq_requested;
99         int spi_irq;
100
101         size_t rx_map_len;
102         size_t tx_map_len;
103         u8 n_bytes;
104         u16 ctrl_reg;
105         u16 flag_reg;
106
107         int cs_change;
108         const struct bfin_spi_transfer_ops *ops;
109 };
110
111 struct bfin_spi_slave_data {
112         u16 ctl_reg;
113         u16 baud;
114         u16 flag;
115
116         u8 chip_select_num;
117         u8 enable_dma;
118         u16 cs_chg_udelay;      /* Some devices require > 255usec delay */
119         u32 cs_gpio;
120         u16 idle_tx_val;
121         u8 pio_interrupt;       /* use spi data irq */
122         const struct bfin_spi_transfer_ops *ops;
123 };
124
125 #define DEFINE_SPI_REG(reg, off) \
126 static inline u16 read_##reg(struct bfin_spi_master_data *drv_data) \
127         { return bfin_read16(drv_data->regs_base + off); } \
128 static inline void write_##reg(struct bfin_spi_master_data *drv_data, u16 v) \
129         { bfin_write16(drv_data->regs_base + off, v); }
130
131 DEFINE_SPI_REG(CTRL, 0x00)
132 DEFINE_SPI_REG(FLAG, 0x04)
133 DEFINE_SPI_REG(STAT, 0x08)
134 DEFINE_SPI_REG(TDBR, 0x0C)
135 DEFINE_SPI_REG(RDBR, 0x10)
136 DEFINE_SPI_REG(BAUD, 0x14)
137 DEFINE_SPI_REG(SHAW, 0x18)
138
139 static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
140 {
141         u16 cr;
142
143         cr = read_CTRL(drv_data);
144         write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
145 }
146
147 static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
148 {
149         u16 cr;
150
151         cr = read_CTRL(drv_data);
152         write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
153 }
154
155 /* Caculate the SPI_BAUD register value based on input HZ */
156 static u16 hz_to_spi_baud(u32 speed_hz)
157 {
158         u_long sclk = get_sclk();
159         u16 spi_baud = (sclk / (2 * speed_hz));
160
161         if ((sclk % (2 * speed_hz)) > 0)
162                 spi_baud++;
163
164         if (spi_baud < MIN_SPI_BAUD_VAL)
165                 spi_baud = MIN_SPI_BAUD_VAL;
166
167         return spi_baud;
168 }
169
170 static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
171 {
172         unsigned long limit = loops_per_jiffy << 1;
173
174         /* wait for stop and clear stat */
175         while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
176                 cpu_relax();
177
178         write_STAT(drv_data, BIT_STAT_CLR);
179
180         return limit;
181 }
182
183 /* Chip select operation functions for cs_change flag */
184 static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
185 {
186         if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
187                 u16 flag = read_FLAG(drv_data);
188
189                 flag &= ~chip->flag;
190
191                 write_FLAG(drv_data, flag);
192         } else {
193                 gpio_set_value(chip->cs_gpio, 0);
194         }
195 }
196
197 static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
198                                  struct bfin_spi_slave_data *chip)
199 {
200         if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
201                 u16 flag = read_FLAG(drv_data);
202
203                 flag |= chip->flag;
204
205                 write_FLAG(drv_data, flag);
206         } else {
207                 gpio_set_value(chip->cs_gpio, 1);
208         }
209
210         /* Move delay here for consistency */
211         if (chip->cs_chg_udelay)
212                 udelay(chip->cs_chg_udelay);
213 }
214
215 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
216 static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
217                                       struct bfin_spi_slave_data *chip)
218 {
219         if (chip->chip_select_num < MAX_CTRL_CS) {
220                 u16 flag = read_FLAG(drv_data);
221
222                 flag |= (chip->flag >> 8);
223
224                 write_FLAG(drv_data, flag);
225         }
226 }
227
228 static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
229                                        struct bfin_spi_slave_data *chip)
230 {
231         if (chip->chip_select_num < MAX_CTRL_CS) {
232                 u16 flag = read_FLAG(drv_data);
233
234                 flag &= ~(chip->flag >> 8);
235
236                 write_FLAG(drv_data, flag);
237         }
238 }
239
240 /* stop controller and re-config current chip*/
241 static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
242 {
243         struct bfin_spi_slave_data *chip = drv_data->cur_chip;
244
245         /* Clear status and disable clock */
246         write_STAT(drv_data, BIT_STAT_CLR);
247         bfin_spi_disable(drv_data);
248         dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
249
250         SSYNC();
251
252         /* Load the registers */
253         write_CTRL(drv_data, chip->ctl_reg);
254         write_BAUD(drv_data, chip->baud);
255
256         bfin_spi_enable(drv_data);
257         bfin_spi_cs_active(drv_data, chip);
258 }
259
260 /* used to kick off transfer in rx mode and read unwanted RX data */
261 static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
262 {
263         (void) read_RDBR(drv_data);
264 }
265
266 static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
267 {
268         /* clear RXS (we check for RXS inside the loop) */
269         bfin_spi_dummy_read(drv_data);
270
271         while (drv_data->tx < drv_data->tx_end) {
272                 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
273                 /* wait until transfer finished.
274                    checking SPIF or TXS may not guarantee transfer completion */
275                 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
276                         cpu_relax();
277                 /* discard RX data and clear RXS */
278                 bfin_spi_dummy_read(drv_data);
279         }
280 }
281
282 static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
283 {
284         u16 tx_val = drv_data->cur_chip->idle_tx_val;
285
286         /* discard old RX data and clear RXS */
287         bfin_spi_dummy_read(drv_data);
288
289         while (drv_data->rx < drv_data->rx_end) {
290                 write_TDBR(drv_data, tx_val);
291                 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
292                         cpu_relax();
293                 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
294         }
295 }
296
297 static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
298 {
299         /* discard old RX data and clear RXS */
300         bfin_spi_dummy_read(drv_data);
301
302         while (drv_data->rx < drv_data->rx_end) {
303                 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
304                 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
305                         cpu_relax();
306                 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
307         }
308 }
309
310 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
311         .write  = bfin_spi_u8_writer,
312         .read   = bfin_spi_u8_reader,
313         .duplex = bfin_spi_u8_duplex,
314 };
315
316 static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
317 {
318         /* clear RXS (we check for RXS inside the loop) */
319         bfin_spi_dummy_read(drv_data);
320
321         while (drv_data->tx < drv_data->tx_end) {
322                 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
323                 drv_data->tx += 2;
324                 /* wait until transfer finished.
325                    checking SPIF or TXS may not guarantee transfer completion */
326                 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
327                         cpu_relax();
328                 /* discard RX data and clear RXS */
329                 bfin_spi_dummy_read(drv_data);
330         }
331 }
332
333 static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
334 {
335         u16 tx_val = drv_data->cur_chip->idle_tx_val;
336
337         /* discard old RX data and clear RXS */
338         bfin_spi_dummy_read(drv_data);
339
340         while (drv_data->rx < drv_data->rx_end) {
341                 write_TDBR(drv_data, tx_val);
342                 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
343                         cpu_relax();
344                 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
345                 drv_data->rx += 2;
346         }
347 }
348
349 static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
350 {
351         /* discard old RX data and clear RXS */
352         bfin_spi_dummy_read(drv_data);
353
354         while (drv_data->rx < drv_data->rx_end) {
355                 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
356                 drv_data->tx += 2;
357                 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
358                         cpu_relax();
359                 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
360                 drv_data->rx += 2;
361         }
362 }
363
364 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
365         .write  = bfin_spi_u16_writer,
366         .read   = bfin_spi_u16_reader,
367         .duplex = bfin_spi_u16_duplex,
368 };
369
370 /* test if there is more transfer to be done */
371 static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
372 {
373         struct spi_message *msg = drv_data->cur_msg;
374         struct spi_transfer *trans = drv_data->cur_transfer;
375
376         /* Move to next transfer */
377         if (trans->transfer_list.next != &msg->transfers) {
378                 drv_data->cur_transfer =
379                     list_entry(trans->transfer_list.next,
380                                struct spi_transfer, transfer_list);
381                 return RUNNING_STATE;
382         } else
383                 return DONE_STATE;
384 }
385
386 /*
387  * caller already set message->status;
388  * dma and pio irqs are blocked give finished message back
389  */
390 static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
391 {
392         struct bfin_spi_slave_data *chip = drv_data->cur_chip;
393         struct spi_transfer *last_transfer;
394         unsigned long flags;
395         struct spi_message *msg;
396
397         spin_lock_irqsave(&drv_data->lock, flags);
398         msg = drv_data->cur_msg;
399         drv_data->cur_msg = NULL;
400         drv_data->cur_transfer = NULL;
401         drv_data->cur_chip = NULL;
402         queue_work(drv_data->workqueue, &drv_data->pump_messages);
403         spin_unlock_irqrestore(&drv_data->lock, flags);
404
405         last_transfer = list_entry(msg->transfers.prev,
406                                    struct spi_transfer, transfer_list);
407
408         msg->state = NULL;
409
410         if (!drv_data->cs_change)
411                 bfin_spi_cs_deactive(drv_data, chip);
412
413         /* Not stop spi in autobuffer mode */
414         if (drv_data->tx_dma != 0xFFFF)
415                 bfin_spi_disable(drv_data);
416
417         if (msg->complete)
418                 msg->complete(msg->context);
419 }
420
421 /* spi data irq handler */
422 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
423 {
424         struct bfin_spi_master_data *drv_data = dev_id;
425         struct bfin_spi_slave_data *chip = drv_data->cur_chip;
426         struct spi_message *msg = drv_data->cur_msg;
427         int n_bytes = drv_data->n_bytes;
428         int loop = 0;
429
430         /* wait until transfer finished. */
431         while (!(read_STAT(drv_data) & BIT_STAT_RXS))
432                 cpu_relax();
433
434         if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
435                 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
436                 /* last read */
437                 if (drv_data->rx) {
438                         dev_dbg(&drv_data->pdev->dev, "last read\n");
439                         if (n_bytes % 2) {
440                                 u16 *buf = (u16 *)drv_data->rx;
441                                 for (loop = 0; loop < n_bytes / 2; loop++)
442                                         *buf++ = read_RDBR(drv_data);
443                         } else {
444                                 u8 *buf = (u8 *)drv_data->rx;
445                                 for (loop = 0; loop < n_bytes; loop++)
446                                         *buf++ = read_RDBR(drv_data);
447                         }
448                         drv_data->rx += n_bytes;
449                 }
450
451                 msg->actual_length += drv_data->len_in_bytes;
452                 if (drv_data->cs_change)
453                         bfin_spi_cs_deactive(drv_data, chip);
454                 /* Move to next transfer */
455                 msg->state = bfin_spi_next_transfer(drv_data);
456
457                 disable_irq_nosync(drv_data->spi_irq);
458
459                 /* Schedule transfer tasklet */
460                 tasklet_schedule(&drv_data->pump_transfers);
461                 return IRQ_HANDLED;
462         }
463
464         if (drv_data->rx && drv_data->tx) {
465                 /* duplex */
466                 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
467                 if (n_bytes % 2) {
468                         u16 *buf = (u16 *)drv_data->rx;
469                         u16 *buf2 = (u16 *)drv_data->tx;
470                         for (loop = 0; loop < n_bytes / 2; loop++) {
471                                 *buf++ = read_RDBR(drv_data);
472                                 write_TDBR(drv_data, *buf2++);
473                         }
474                 } else {
475                         u8 *buf = (u8 *)drv_data->rx;
476                         u8 *buf2 = (u8 *)drv_data->tx;
477                         for (loop = 0; loop < n_bytes; loop++) {
478                                 *buf++ = read_RDBR(drv_data);
479                                 write_TDBR(drv_data, *buf2++);
480                         }
481                 }
482         } else if (drv_data->rx) {
483                 /* read */
484                 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
485                 if (n_bytes % 2) {
486                         u16 *buf = (u16 *)drv_data->rx;
487                         for (loop = 0; loop < n_bytes / 2; loop++) {
488                                 *buf++ = read_RDBR(drv_data);
489                                 write_TDBR(drv_data, chip->idle_tx_val);
490                         }
491                 } else {
492                         u8 *buf = (u8 *)drv_data->rx;
493                         for (loop = 0; loop < n_bytes; loop++) {
494                                 *buf++ = read_RDBR(drv_data);
495                                 write_TDBR(drv_data, chip->idle_tx_val);
496                         }
497                 }
498         } else if (drv_data->tx) {
499                 /* write */
500                 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
501                 if (n_bytes % 2) {
502                         u16 *buf = (u16 *)drv_data->tx;
503                         for (loop = 0; loop < n_bytes / 2; loop++) {
504                                 read_RDBR(drv_data);
505                                 write_TDBR(drv_data, *buf++);
506                         }
507                 } else {
508                         u8 *buf = (u8 *)drv_data->tx;
509                         for (loop = 0; loop < n_bytes; loop++) {
510                                 read_RDBR(drv_data);
511                                 write_TDBR(drv_data, *buf++);
512                         }
513                 }
514         }
515
516         if (drv_data->tx)
517                 drv_data->tx += n_bytes;
518         if (drv_data->rx)
519                 drv_data->rx += n_bytes;
520
521         return IRQ_HANDLED;
522 }
523
524 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
525 {
526         struct bfin_spi_master_data *drv_data = dev_id;
527         struct bfin_spi_slave_data *chip = drv_data->cur_chip;
528         struct spi_message *msg = drv_data->cur_msg;
529         unsigned long timeout;
530         unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
531         u16 spistat = read_STAT(drv_data);
532
533         dev_dbg(&drv_data->pdev->dev,
534                 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
535                 dmastat, spistat);
536
537         if (drv_data->rx != NULL) {
538                 u16 cr = read_CTRL(drv_data);
539                 /* discard old RX data and clear RXS */
540                 bfin_spi_dummy_read(drv_data);
541                 write_CTRL(drv_data, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
542                 write_CTRL(drv_data, cr & ~BIT_CTL_TIMOD); /* Restore State */
543                 write_STAT(drv_data, BIT_STAT_CLR); /* Clear Status */
544         }
545
546         clear_dma_irqstat(drv_data->dma_channel);
547
548         /*
549          * wait for the last transaction shifted out.  HRM states:
550          * at this point there may still be data in the SPI DMA FIFO waiting
551          * to be transmitted ... software needs to poll TXS in the SPI_STAT
552          * register until it goes low for 2 successive reads
553          */
554         if (drv_data->tx != NULL) {
555                 while ((read_STAT(drv_data) & BIT_STAT_TXS) ||
556                        (read_STAT(drv_data) & BIT_STAT_TXS))
557                         cpu_relax();
558         }
559
560         dev_dbg(&drv_data->pdev->dev,
561                 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
562                 dmastat, read_STAT(drv_data));
563
564         timeout = jiffies + HZ;
565         while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
566                 if (!time_before(jiffies, timeout)) {
567                         dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
568                         break;
569                 } else
570                         cpu_relax();
571
572         if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
573                 msg->state = ERROR_STATE;
574                 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
575         } else {
576                 msg->actual_length += drv_data->len_in_bytes;
577
578                 if (drv_data->cs_change)
579                         bfin_spi_cs_deactive(drv_data, chip);
580
581                 /* Move to next transfer */
582                 msg->state = bfin_spi_next_transfer(drv_data);
583         }
584
585         /* Schedule transfer tasklet */
586         tasklet_schedule(&drv_data->pump_transfers);
587
588         /* free the irq handler before next transfer */
589         dev_dbg(&drv_data->pdev->dev,
590                 "disable dma channel irq%d\n",
591                 drv_data->dma_channel);
592         dma_disable_irq_nosync(drv_data->dma_channel);
593
594         return IRQ_HANDLED;
595 }
596
597 static void bfin_spi_pump_transfers(unsigned long data)
598 {
599         struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
600         struct spi_message *message = NULL;
601         struct spi_transfer *transfer = NULL;
602         struct spi_transfer *previous = NULL;
603         struct bfin_spi_slave_data *chip = NULL;
604         unsigned int bits_per_word;
605         u16 cr, cr_width, dma_width, dma_config;
606         u32 tranf_success = 1;
607         u8 full_duplex = 0;
608
609         /* Get current state information */
610         message = drv_data->cur_msg;
611         transfer = drv_data->cur_transfer;
612         chip = drv_data->cur_chip;
613
614         /*
615          * if msg is error or done, report it back using complete() callback
616          */
617
618          /* Handle for abort */
619         if (message->state == ERROR_STATE) {
620                 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
621                 message->status = -EIO;
622                 bfin_spi_giveback(drv_data);
623                 return;
624         }
625
626         /* Handle end of message */
627         if (message->state == DONE_STATE) {
628                 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
629                 message->status = 0;
630                 bfin_spi_giveback(drv_data);
631                 return;
632         }
633
634         /* Delay if requested at end of transfer */
635         if (message->state == RUNNING_STATE) {
636                 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
637                 previous = list_entry(transfer->transfer_list.prev,
638                                       struct spi_transfer, transfer_list);
639                 if (previous->delay_usecs)
640                         udelay(previous->delay_usecs);
641         }
642
643         /* Flush any existing transfers that may be sitting in the hardware */
644         if (bfin_spi_flush(drv_data) == 0) {
645                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
646                 message->status = -EIO;
647                 bfin_spi_giveback(drv_data);
648                 return;
649         }
650
651         if (transfer->len == 0) {
652                 /* Move to next transfer of this msg */
653                 message->state = bfin_spi_next_transfer(drv_data);
654                 /* Schedule next transfer tasklet */
655                 tasklet_schedule(&drv_data->pump_transfers);
656                 return;
657         }
658
659         if (transfer->tx_buf != NULL) {
660                 drv_data->tx = (void *)transfer->tx_buf;
661                 drv_data->tx_end = drv_data->tx + transfer->len;
662                 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
663                         transfer->tx_buf, drv_data->tx_end);
664         } else {
665                 drv_data->tx = NULL;
666         }
667
668         if (transfer->rx_buf != NULL) {
669                 full_duplex = transfer->tx_buf != NULL;
670                 drv_data->rx = transfer->rx_buf;
671                 drv_data->rx_end = drv_data->rx + transfer->len;
672                 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
673                         transfer->rx_buf, drv_data->rx_end);
674         } else {
675                 drv_data->rx = NULL;
676         }
677
678         drv_data->rx_dma = transfer->rx_dma;
679         drv_data->tx_dma = transfer->tx_dma;
680         drv_data->len_in_bytes = transfer->len;
681         drv_data->cs_change = transfer->cs_change;
682
683         /* Bits per word setup */
684         bits_per_word = transfer->bits_per_word ? :
685                 message->spi->bits_per_word ? : 8;
686         if (bits_per_word % 16 == 0) {
687                 drv_data->n_bytes = bits_per_word/8;
688                 drv_data->len = (transfer->len) >> 1;
689                 cr_width = BIT_CTL_WORDSIZE;
690                 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
691         } else if (bits_per_word % 8 == 0) {
692                 drv_data->n_bytes = bits_per_word/8;
693                 drv_data->len = transfer->len;
694                 cr_width = 0;
695                 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
696         } else {
697                 dev_err(&drv_data->pdev->dev, "transfer: unsupported bits_per_word\n");
698                 message->status = -EINVAL;
699                 bfin_spi_giveback(drv_data);
700                 return;
701         }
702         cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
703         cr |= cr_width;
704         write_CTRL(drv_data, cr);
705
706         dev_dbg(&drv_data->pdev->dev,
707                 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
708                 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
709
710         message->state = RUNNING_STATE;
711         dma_config = 0;
712
713         /* Speed setup (surely valid because already checked) */
714         if (transfer->speed_hz)
715                 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
716         else
717                 write_BAUD(drv_data, chip->baud);
718
719         write_STAT(drv_data, BIT_STAT_CLR);
720         bfin_spi_cs_active(drv_data, chip);
721
722         dev_dbg(&drv_data->pdev->dev,
723                 "now pumping a transfer: width is %d, len is %d\n",
724                 cr_width, transfer->len);
725
726         /*
727          * Try to map dma buffer and do a dma transfer.  If successful use,
728          * different way to r/w according to the enable_dma settings and if
729          * we are not doing a full duplex transfer (since the hardware does
730          * not support full duplex DMA transfers).
731          */
732         if (!full_duplex && drv_data->cur_chip->enable_dma
733                                 && drv_data->len > 6) {
734
735                 unsigned long dma_start_addr, flags;
736
737                 disable_dma(drv_data->dma_channel);
738                 clear_dma_irqstat(drv_data->dma_channel);
739
740                 /* config dma channel */
741                 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
742                 set_dma_x_count(drv_data->dma_channel, drv_data->len);
743                 if (cr_width == BIT_CTL_WORDSIZE) {
744                         set_dma_x_modify(drv_data->dma_channel, 2);
745                         dma_width = WDSIZE_16;
746                 } else {
747                         set_dma_x_modify(drv_data->dma_channel, 1);
748                         dma_width = WDSIZE_8;
749                 }
750
751                 /* poll for SPI completion before start */
752                 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
753                         cpu_relax();
754
755                 /* dirty hack for autobuffer DMA mode */
756                 if (drv_data->tx_dma == 0xFFFF) {
757                         dev_dbg(&drv_data->pdev->dev,
758                                 "doing autobuffer DMA out.\n");
759
760                         /* no irq in autobuffer mode */
761                         dma_config =
762                             (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
763                         set_dma_config(drv_data->dma_channel, dma_config);
764                         set_dma_start_addr(drv_data->dma_channel,
765                                         (unsigned long)drv_data->tx);
766                         enable_dma(drv_data->dma_channel);
767
768                         /* start SPI transfer */
769                         write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
770
771                         /* just return here, there can only be one transfer
772                          * in this mode
773                          */
774                         message->status = 0;
775                         bfin_spi_giveback(drv_data);
776                         return;
777                 }
778
779                 /* In dma mode, rx or tx must be NULL in one transfer */
780                 dma_config = (RESTART | dma_width | DI_EN);
781                 if (drv_data->rx != NULL) {
782                         /* set transfer mode, and enable SPI */
783                         dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
784                                 drv_data->rx, drv_data->len_in_bytes);
785
786                         /* invalidate caches, if needed */
787                         if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
788                                 invalidate_dcache_range((unsigned long) drv_data->rx,
789                                                         (unsigned long) (drv_data->rx +
790                                                         drv_data->len_in_bytes));
791
792                         dma_config |= WNR;
793                         dma_start_addr = (unsigned long)drv_data->rx;
794                         cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
795
796                 } else if (drv_data->tx != NULL) {
797                         dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
798
799                         /* flush caches, if needed */
800                         if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
801                                 flush_dcache_range((unsigned long) drv_data->tx,
802                                                 (unsigned long) (drv_data->tx +
803                                                 drv_data->len_in_bytes));
804
805                         dma_start_addr = (unsigned long)drv_data->tx;
806                         cr |= BIT_CTL_TIMOD_DMA_TX;
807
808                 } else
809                         BUG();
810
811                 /* oh man, here there be monsters ... and i dont mean the
812                  * fluffy cute ones from pixar, i mean the kind that'll eat
813                  * your data, kick your dog, and love it all.  do *not* try
814                  * and change these lines unless you (1) heavily test DMA
815                  * with SPI flashes on a loaded system (e.g. ping floods),
816                  * (2) know just how broken the DMA engine interaction with
817                  * the SPI peripheral is, and (3) have someone else to blame
818                  * when you screw it all up anyways.
819                  */
820                 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
821                 set_dma_config(drv_data->dma_channel, dma_config);
822                 local_irq_save(flags);
823                 SSYNC();
824                 write_CTRL(drv_data, cr);
825                 enable_dma(drv_data->dma_channel);
826                 dma_enable_irq(drv_data->dma_channel);
827                 local_irq_restore(flags);
828
829                 return;
830         }
831
832         /*
833          * We always use SPI_WRITE mode (transfer starts with TDBR write).
834          * SPI_READ mode (transfer starts with RDBR read) seems to have
835          * problems with setting up the output value in TDBR prior to the
836          * start of the transfer.
837          */
838         write_CTRL(drv_data, cr | BIT_CTL_TXMOD);
839
840         if (chip->pio_interrupt) {
841                 /* SPI irq should have been disabled by now */
842
843                 /* discard old RX data and clear RXS */
844                 bfin_spi_dummy_read(drv_data);
845
846                 /* start transfer */
847                 if (drv_data->tx == NULL)
848                         write_TDBR(drv_data, chip->idle_tx_val);
849                 else {
850                         int loop;
851                         if (bits_per_word % 16 == 0) {
852                                 u16 *buf = (u16 *)drv_data->tx;
853                                 for (loop = 0; loop < bits_per_word / 16;
854                                                 loop++) {
855                                         write_TDBR(drv_data, *buf++);
856                                 }
857                         } else if (bits_per_word % 8 == 0) {
858                                 u8 *buf = (u8 *)drv_data->tx;
859                                 for (loop = 0; loop < bits_per_word / 8; loop++)
860                                         write_TDBR(drv_data, *buf++);
861                         }
862
863                         drv_data->tx += drv_data->n_bytes;
864                 }
865
866                 /* once TDBR is empty, interrupt is triggered */
867                 enable_irq(drv_data->spi_irq);
868                 return;
869         }
870
871         /* IO mode */
872         dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
873
874         if (full_duplex) {
875                 /* full duplex mode */
876                 BUG_ON((drv_data->tx_end - drv_data->tx) !=
877                        (drv_data->rx_end - drv_data->rx));
878                 dev_dbg(&drv_data->pdev->dev,
879                         "IO duplex: cr is 0x%x\n", cr);
880
881                 drv_data->ops->duplex(drv_data);
882
883                 if (drv_data->tx != drv_data->tx_end)
884                         tranf_success = 0;
885         } else if (drv_data->tx != NULL) {
886                 /* write only half duplex */
887                 dev_dbg(&drv_data->pdev->dev,
888                         "IO write: cr is 0x%x\n", cr);
889
890                 drv_data->ops->write(drv_data);
891
892                 if (drv_data->tx != drv_data->tx_end)
893                         tranf_success = 0;
894         } else if (drv_data->rx != NULL) {
895                 /* read only half duplex */
896                 dev_dbg(&drv_data->pdev->dev,
897                         "IO read: cr is 0x%x\n", cr);
898
899                 drv_data->ops->read(drv_data);
900                 if (drv_data->rx != drv_data->rx_end)
901                         tranf_success = 0;
902         }
903
904         if (!tranf_success) {
905                 dev_dbg(&drv_data->pdev->dev,
906                         "IO write error!\n");
907                 message->state = ERROR_STATE;
908         } else {
909                 /* Update total byte transferred */
910                 message->actual_length += drv_data->len_in_bytes;
911                 /* Move to next transfer of this msg */
912                 message->state = bfin_spi_next_transfer(drv_data);
913                 if (drv_data->cs_change)
914                         bfin_spi_cs_deactive(drv_data, chip);
915         }
916
917         /* Schedule next transfer tasklet */
918         tasklet_schedule(&drv_data->pump_transfers);
919 }
920
921 /* pop a msg from queue and kick off real transfer */
922 static void bfin_spi_pump_messages(struct work_struct *work)
923 {
924         struct bfin_spi_master_data *drv_data;
925         unsigned long flags;
926
927         drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
928
929         /* Lock queue and check for queue work */
930         spin_lock_irqsave(&drv_data->lock, flags);
931         if (list_empty(&drv_data->queue) || !drv_data->running) {
932                 /* pumper kicked off but no work to do */
933                 drv_data->busy = 0;
934                 spin_unlock_irqrestore(&drv_data->lock, flags);
935                 return;
936         }
937
938         /* Make sure we are not already running a message */
939         if (drv_data->cur_msg) {
940                 spin_unlock_irqrestore(&drv_data->lock, flags);
941                 return;
942         }
943
944         /* Extract head of queue */
945         drv_data->cur_msg = list_entry(drv_data->queue.next,
946                                        struct spi_message, queue);
947
948         /* Setup the SSP using the per chip configuration */
949         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
950         bfin_spi_restore_state(drv_data);
951
952         list_del_init(&drv_data->cur_msg->queue);
953
954         /* Initial message state */
955         drv_data->cur_msg->state = START_STATE;
956         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
957                                             struct spi_transfer, transfer_list);
958
959         dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
960                 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
961                 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
962                 drv_data->cur_chip->ctl_reg);
963
964         dev_dbg(&drv_data->pdev->dev,
965                 "the first transfer len is %d\n",
966                 drv_data->cur_transfer->len);
967
968         /* Mark as busy and launch transfers */
969         tasklet_schedule(&drv_data->pump_transfers);
970
971         drv_data->busy = 1;
972         spin_unlock_irqrestore(&drv_data->lock, flags);
973 }
974
975 /*
976  * got a msg to transfer, queue it in drv_data->queue.
977  * And kick off message pumper
978  */
979 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
980 {
981         struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
982         unsigned long flags;
983
984         spin_lock_irqsave(&drv_data->lock, flags);
985
986         if (!drv_data->running) {
987                 spin_unlock_irqrestore(&drv_data->lock, flags);
988                 return -ESHUTDOWN;
989         }
990
991         msg->actual_length = 0;
992         msg->status = -EINPROGRESS;
993         msg->state = START_STATE;
994
995         dev_dbg(&spi->dev, "adding an msg in transfer() \n");
996         list_add_tail(&msg->queue, &drv_data->queue);
997
998         if (drv_data->running && !drv_data->busy)
999                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1000
1001         spin_unlock_irqrestore(&drv_data->lock, flags);
1002
1003         return 0;
1004 }
1005
1006 #define MAX_SPI_SSEL    7
1007
1008 static u16 ssel[][MAX_SPI_SSEL] = {
1009         {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1010         P_SPI0_SSEL4, P_SPI0_SSEL5,
1011         P_SPI0_SSEL6, P_SPI0_SSEL7},
1012
1013         {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1014         P_SPI1_SSEL4, P_SPI1_SSEL5,
1015         P_SPI1_SSEL6, P_SPI1_SSEL7},
1016
1017         {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1018         P_SPI2_SSEL4, P_SPI2_SSEL5,
1019         P_SPI2_SSEL6, P_SPI2_SSEL7},
1020 };
1021
1022 /* setup for devices (may be called multiple times -- not just first setup) */
1023 static int bfin_spi_setup(struct spi_device *spi)
1024 {
1025         struct bfin5xx_spi_chip *chip_info;
1026         struct bfin_spi_slave_data *chip = NULL;
1027         struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1028         u16 bfin_ctl_reg;
1029         int ret = -EINVAL;
1030
1031         /* Only alloc (or use chip_info) on first setup */
1032         chip_info = NULL;
1033         chip = spi_get_ctldata(spi);
1034         if (chip == NULL) {
1035                 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1036                 if (!chip) {
1037                         dev_err(&spi->dev, "cannot allocate chip data\n");
1038                         ret = -ENOMEM;
1039                         goto error;
1040                 }
1041
1042                 chip->enable_dma = 0;
1043                 chip_info = spi->controller_data;
1044         }
1045
1046         /* Let people set non-standard bits directly */
1047         bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
1048                 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
1049
1050         /* chip_info isn't always needed */
1051         if (chip_info) {
1052                 /* Make sure people stop trying to set fields via ctl_reg
1053                  * when they should actually be using common SPI framework.
1054                  * Currently we let through: WOM EMISO PSSE GM SZ.
1055                  * Not sure if a user actually needs/uses any of these,
1056                  * but let's assume (for now) they do.
1057                  */
1058                 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1059                         dev_err(&spi->dev, "do not set bits in ctl_reg "
1060                                 "that the SPI framework manages\n");
1061                         goto error;
1062                 }
1063                 chip->enable_dma = chip_info->enable_dma != 0
1064                     && drv_data->master_info->enable_dma;
1065                 chip->ctl_reg = chip_info->ctl_reg;
1066                 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1067                 chip->idle_tx_val = chip_info->idle_tx_val;
1068                 chip->pio_interrupt = chip_info->pio_interrupt;
1069                 spi->bits_per_word = chip_info->bits_per_word;
1070         } else {
1071                 /* force a default base state */
1072                 chip->ctl_reg &= bfin_ctl_reg;
1073         }
1074
1075         if (spi->bits_per_word % 8) {
1076                 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1077                                 spi->bits_per_word);
1078                 goto error;
1079         }
1080
1081         /* translate common spi framework into our register */
1082         if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1083                 dev_err(&spi->dev, "unsupported spi modes detected\n");
1084                 goto error;
1085         }
1086         if (spi->mode & SPI_CPOL)
1087                 chip->ctl_reg |= BIT_CTL_CPOL;
1088         if (spi->mode & SPI_CPHA)
1089                 chip->ctl_reg |= BIT_CTL_CPHA;
1090         if (spi->mode & SPI_LSB_FIRST)
1091                 chip->ctl_reg |= BIT_CTL_LSBF;
1092         /* we dont support running in slave mode (yet?) */
1093         chip->ctl_reg |= BIT_CTL_MASTER;
1094
1095         /*
1096          * Notice: for blackfin, the speed_hz is the value of register
1097          * SPI_BAUD, not the real baudrate
1098          */
1099         chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1100         chip->chip_select_num = spi->chip_select;
1101         if (chip->chip_select_num < MAX_CTRL_CS) {
1102                 if (!(spi->mode & SPI_CPHA))
1103                         dev_warn(&spi->dev, "Warning: SPI CPHA not set:"
1104                                 " Slave Select not under software control!\n"
1105                                 " See Documentation/blackfin/bfin-spi-notes.txt");
1106
1107                 chip->flag = (1 << spi->chip_select) << 8;
1108         } else
1109                 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1110
1111         if (chip->enable_dma && chip->pio_interrupt) {
1112                 dev_err(&spi->dev, "enable_dma is set, "
1113                                 "do not set pio_interrupt\n");
1114                 goto error;
1115         }
1116         /*
1117          * if any one SPI chip is registered and wants DMA, request the
1118          * DMA channel for it
1119          */
1120         if (chip->enable_dma && !drv_data->dma_requested) {
1121                 /* register dma irq handler */
1122                 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1123                 if (ret) {
1124                         dev_err(&spi->dev,
1125                                 "Unable to request BlackFin SPI DMA channel\n");
1126                         goto error;
1127                 }
1128                 drv_data->dma_requested = 1;
1129
1130                 ret = set_dma_callback(drv_data->dma_channel,
1131                         bfin_spi_dma_irq_handler, drv_data);
1132                 if (ret) {
1133                         dev_err(&spi->dev, "Unable to set dma callback\n");
1134                         goto error;
1135                 }
1136                 dma_disable_irq(drv_data->dma_channel);
1137         }
1138
1139         if (chip->pio_interrupt && !drv_data->irq_requested) {
1140                 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1141                         IRQF_DISABLED, "BFIN_SPI", drv_data);
1142                 if (ret) {
1143                         dev_err(&spi->dev, "Unable to register spi IRQ\n");
1144                         goto error;
1145                 }
1146                 drv_data->irq_requested = 1;
1147                 /* we use write mode, spi irq has to be disabled here */
1148                 disable_irq(drv_data->spi_irq);
1149         }
1150
1151         if (chip->chip_select_num >= MAX_CTRL_CS) {
1152                 /* Only request on first setup */
1153                 if (spi_get_ctldata(spi) == NULL) {
1154                         ret = gpio_request(chip->cs_gpio, spi->modalias);
1155                         if (ret) {
1156                                 dev_err(&spi->dev, "gpio_request() error\n");
1157                                 goto pin_error;
1158                         }
1159                         gpio_direction_output(chip->cs_gpio, 1);
1160                 }
1161         }
1162
1163         dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1164                         spi->modalias, spi->bits_per_word, chip->enable_dma);
1165         dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1166                         chip->ctl_reg, chip->flag);
1167
1168         spi_set_ctldata(spi, chip);
1169
1170         dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1171         if (chip->chip_select_num < MAX_CTRL_CS) {
1172                 ret = peripheral_request(ssel[spi->master->bus_num]
1173                                          [chip->chip_select_num-1], spi->modalias);
1174                 if (ret) {
1175                         dev_err(&spi->dev, "peripheral_request() error\n");
1176                         goto pin_error;
1177                 }
1178         }
1179
1180         bfin_spi_cs_enable(drv_data, chip);
1181         bfin_spi_cs_deactive(drv_data, chip);
1182
1183         return 0;
1184
1185  pin_error:
1186         if (chip->chip_select_num >= MAX_CTRL_CS)
1187                 gpio_free(chip->cs_gpio);
1188         else
1189                 peripheral_free(ssel[spi->master->bus_num]
1190                         [chip->chip_select_num - 1]);
1191  error:
1192         if (chip) {
1193                 if (drv_data->dma_requested)
1194                         free_dma(drv_data->dma_channel);
1195                 drv_data->dma_requested = 0;
1196
1197                 kfree(chip);
1198                 /* prevent free 'chip' twice */
1199                 spi_set_ctldata(spi, NULL);
1200         }
1201
1202         return ret;
1203 }
1204
1205 /*
1206  * callback for spi framework.
1207  * clean driver specific data
1208  */
1209 static void bfin_spi_cleanup(struct spi_device *spi)
1210 {
1211         struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1212         struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1213
1214         if (!chip)
1215                 return;
1216
1217         if (chip->chip_select_num < MAX_CTRL_CS) {
1218                 peripheral_free(ssel[spi->master->bus_num]
1219                                         [chip->chip_select_num-1]);
1220                 bfin_spi_cs_disable(drv_data, chip);
1221         } else
1222                 gpio_free(chip->cs_gpio);
1223
1224         kfree(chip);
1225         /* prevent free 'chip' twice */
1226         spi_set_ctldata(spi, NULL);
1227 }
1228
1229 static inline int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1230 {
1231         INIT_LIST_HEAD(&drv_data->queue);
1232         spin_lock_init(&drv_data->lock);
1233
1234         drv_data->running = false;
1235         drv_data->busy = 0;
1236
1237         /* init transfer tasklet */
1238         tasklet_init(&drv_data->pump_transfers,
1239                      bfin_spi_pump_transfers, (unsigned long)drv_data);
1240
1241         /* init messages workqueue */
1242         INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1243         drv_data->workqueue = create_singlethread_workqueue(
1244                                 dev_name(drv_data->master->dev.parent));
1245         if (drv_data->workqueue == NULL)
1246                 return -EBUSY;
1247
1248         return 0;
1249 }
1250
1251 static inline int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1252 {
1253         unsigned long flags;
1254
1255         spin_lock_irqsave(&drv_data->lock, flags);
1256
1257         if (drv_data->running || drv_data->busy) {
1258                 spin_unlock_irqrestore(&drv_data->lock, flags);
1259                 return -EBUSY;
1260         }
1261
1262         drv_data->running = true;
1263         drv_data->cur_msg = NULL;
1264         drv_data->cur_transfer = NULL;
1265         drv_data->cur_chip = NULL;
1266         spin_unlock_irqrestore(&drv_data->lock, flags);
1267
1268         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1269
1270         return 0;
1271 }
1272
1273 static inline int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1274 {
1275         unsigned long flags;
1276         unsigned limit = 500;
1277         int status = 0;
1278
1279         spin_lock_irqsave(&drv_data->lock, flags);
1280
1281         /*
1282          * This is a bit lame, but is optimized for the common execution path.
1283          * A wait_queue on the drv_data->busy could be used, but then the common
1284          * execution path (pump_messages) would be required to call wake_up or
1285          * friends on every SPI message. Do this instead
1286          */
1287         drv_data->running = false;
1288         while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1289                 spin_unlock_irqrestore(&drv_data->lock, flags);
1290                 msleep(10);
1291                 spin_lock_irqsave(&drv_data->lock, flags);
1292         }
1293
1294         if (!list_empty(&drv_data->queue) || drv_data->busy)
1295                 status = -EBUSY;
1296
1297         spin_unlock_irqrestore(&drv_data->lock, flags);
1298
1299         return status;
1300 }
1301
1302 static inline int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1303 {
1304         int status;
1305
1306         status = bfin_spi_stop_queue(drv_data);
1307         if (status != 0)
1308                 return status;
1309
1310         destroy_workqueue(drv_data->workqueue);
1311
1312         return 0;
1313 }
1314
1315 static int __init bfin_spi_probe(struct platform_device *pdev)
1316 {
1317         struct device *dev = &pdev->dev;
1318         struct bfin5xx_spi_master *platform_info;
1319         struct spi_master *master;
1320         struct bfin_spi_master_data *drv_data;
1321         struct resource *res;
1322         int status = 0;
1323
1324         platform_info = dev->platform_data;
1325
1326         /* Allocate master with space for drv_data */
1327         master = spi_alloc_master(dev, sizeof(*drv_data));
1328         if (!master) {
1329                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1330                 return -ENOMEM;
1331         }
1332
1333         drv_data = spi_master_get_devdata(master);
1334         drv_data->master = master;
1335         drv_data->master_info = platform_info;
1336         drv_data->pdev = pdev;
1337         drv_data->pin_req = platform_info->pin_req;
1338
1339         /* the spi->mode bits supported by this driver: */
1340         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1341
1342         master->bus_num = pdev->id;
1343         master->num_chipselect = platform_info->num_chipselect;
1344         master->cleanup = bfin_spi_cleanup;
1345         master->setup = bfin_spi_setup;
1346         master->transfer = bfin_spi_transfer;
1347
1348         /* Find and map our resources */
1349         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1350         if (res == NULL) {
1351                 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1352                 status = -ENOENT;
1353                 goto out_error_get_res;
1354         }
1355
1356         drv_data->regs_base = ioremap(res->start, resource_size(res));
1357         if (drv_data->regs_base == NULL) {
1358                 dev_err(dev, "Cannot map IO\n");
1359                 status = -ENXIO;
1360                 goto out_error_ioremap;
1361         }
1362
1363         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1364         if (res == NULL) {
1365                 dev_err(dev, "No DMA channel specified\n");
1366                 status = -ENOENT;
1367                 goto out_error_free_io;
1368         }
1369         drv_data->dma_channel = res->start;
1370
1371         drv_data->spi_irq = platform_get_irq(pdev, 0);
1372         if (drv_data->spi_irq < 0) {
1373                 dev_err(dev, "No spi pio irq specified\n");
1374                 status = -ENOENT;
1375                 goto out_error_free_io;
1376         }
1377
1378         /* Initial and start queue */
1379         status = bfin_spi_init_queue(drv_data);
1380         if (status != 0) {
1381                 dev_err(dev, "problem initializing queue\n");
1382                 goto out_error_queue_alloc;
1383         }
1384
1385         status = bfin_spi_start_queue(drv_data);
1386         if (status != 0) {
1387                 dev_err(dev, "problem starting queue\n");
1388                 goto out_error_queue_alloc;
1389         }
1390
1391         status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1392         if (status != 0) {
1393                 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1394                 goto out_error_queue_alloc;
1395         }
1396
1397         /* Reset SPI registers. If these registers were used by the boot loader,
1398          * the sky may fall on your head if you enable the dma controller.
1399          */
1400         write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1401         write_FLAG(drv_data, 0xFF00);
1402
1403         /* Register with the SPI framework */
1404         platform_set_drvdata(pdev, drv_data);
1405         status = spi_register_master(master);
1406         if (status != 0) {
1407                 dev_err(dev, "problem registering spi master\n");
1408                 goto out_error_queue_alloc;
1409         }
1410
1411         dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1412                 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1413                 drv_data->dma_channel);
1414         return status;
1415
1416 out_error_queue_alloc:
1417         bfin_spi_destroy_queue(drv_data);
1418 out_error_free_io:
1419         iounmap((void *) drv_data->regs_base);
1420 out_error_ioremap:
1421 out_error_get_res:
1422         spi_master_put(master);
1423
1424         return status;
1425 }
1426
1427 /* stop hardware and remove the driver */
1428 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1429 {
1430         struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1431         int status = 0;
1432
1433         if (!drv_data)
1434                 return 0;
1435
1436         /* Remove the queue */
1437         status = bfin_spi_destroy_queue(drv_data);
1438         if (status != 0)
1439                 return status;
1440
1441         /* Disable the SSP at the peripheral and SOC level */
1442         bfin_spi_disable(drv_data);
1443
1444         /* Release DMA */
1445         if (drv_data->master_info->enable_dma) {
1446                 if (dma_channel_active(drv_data->dma_channel))
1447                         free_dma(drv_data->dma_channel);
1448         }
1449
1450         if (drv_data->irq_requested) {
1451                 free_irq(drv_data->spi_irq, drv_data);
1452                 drv_data->irq_requested = 0;
1453         }
1454
1455         /* Disconnect from the SPI framework */
1456         spi_unregister_master(drv_data->master);
1457
1458         peripheral_free_list(drv_data->pin_req);
1459
1460         /* Prevent double remove */
1461         platform_set_drvdata(pdev, NULL);
1462
1463         return 0;
1464 }
1465
1466 #ifdef CONFIG_PM
1467 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1468 {
1469         struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1470         int status = 0;
1471
1472         status = bfin_spi_stop_queue(drv_data);
1473         if (status != 0)
1474                 return status;
1475
1476         drv_data->ctrl_reg = read_CTRL(drv_data);
1477         drv_data->flag_reg = read_FLAG(drv_data);
1478
1479         /*
1480          * reset SPI_CTL and SPI_FLG registers
1481          */
1482         write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1483         write_FLAG(drv_data, 0xFF00);
1484
1485         return 0;
1486 }
1487
1488 static int bfin_spi_resume(struct platform_device *pdev)
1489 {
1490         struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1491         int status = 0;
1492
1493         write_CTRL(drv_data, drv_data->ctrl_reg);
1494         write_FLAG(drv_data, drv_data->flag_reg);
1495
1496         /* Start the queue running */
1497         status = bfin_spi_start_queue(drv_data);
1498         if (status != 0) {
1499                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1500                 return status;
1501         }
1502
1503         return 0;
1504 }
1505 #else
1506 #define bfin_spi_suspend NULL
1507 #define bfin_spi_resume NULL
1508 #endif                          /* CONFIG_PM */
1509
1510 MODULE_ALIAS("platform:bfin-spi");
1511 static struct platform_driver bfin_spi_driver = {
1512         .driver = {
1513                 .name   = DRV_NAME,
1514                 .owner  = THIS_MODULE,
1515         },
1516         .suspend        = bfin_spi_suspend,
1517         .resume         = bfin_spi_resume,
1518         .remove         = __devexit_p(bfin_spi_remove),
1519 };
1520
1521 static int __init bfin_spi_init(void)
1522 {
1523         return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1524 }
1525 subsys_initcall(bfin_spi_init);
1526
1527 static void __exit bfin_spi_exit(void)
1528 {
1529         platform_driver_unregister(&bfin_spi_driver);
1530 }
1531 module_exit(bfin_spi_exit);