Merge branch 'origin' into devel
[linux-2.6.git] / drivers / spi / omap2_mcspi.c
1 /*
2  * OMAP2 McSPI controller driver
3  *
4  * Copyright (C) 2005, 2006 Nokia Corporation
5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
6  *              Juha Yrjölä <juha.yrjola@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  *
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/io.h>
35
36 #include <linux/spi/spi.h>
37
38 #include <mach/dma.h>
39 #include <mach/clock.h>
40
41
42 #define OMAP2_MCSPI_MAX_FREQ            48000000
43
44 #define OMAP2_MCSPI_REVISION            0x00
45 #define OMAP2_MCSPI_SYSCONFIG           0x10
46 #define OMAP2_MCSPI_SYSSTATUS           0x14
47 #define OMAP2_MCSPI_IRQSTATUS           0x18
48 #define OMAP2_MCSPI_IRQENABLE           0x1c
49 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
50 #define OMAP2_MCSPI_SYST                0x24
51 #define OMAP2_MCSPI_MODULCTRL           0x28
52
53 /* per-channel banks, 0x14 bytes each, first is: */
54 #define OMAP2_MCSPI_CHCONF0             0x2c
55 #define OMAP2_MCSPI_CHSTAT0             0x30
56 #define OMAP2_MCSPI_CHCTRL0             0x34
57 #define OMAP2_MCSPI_TX0                 0x38
58 #define OMAP2_MCSPI_RX0                 0x3c
59
60 /* per-register bitmasks: */
61
62 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE  (1 << 0)
63 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
64
65 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
66
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    (1 << 0)
68 #define OMAP2_MCSPI_MODULCTRL_MS        (1 << 2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST     (1 << 3)
70
71 #define OMAP2_MCSPI_CHCONF_PHA          (1 << 0)
72 #define OMAP2_MCSPI_CHCONF_POL          (1 << 1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL         (1 << 6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  (0x01 << 12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  (0x02 << 12)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW         (1 << 14)
80 #define OMAP2_MCSPI_CHCONF_DMAR         (1 << 15)
81 #define OMAP2_MCSPI_CHCONF_DPE0         (1 << 16)
82 #define OMAP2_MCSPI_CHCONF_DPE1         (1 << 17)
83 #define OMAP2_MCSPI_CHCONF_IS           (1 << 18)
84 #define OMAP2_MCSPI_CHCONF_TURBO        (1 << 19)
85 #define OMAP2_MCSPI_CHCONF_FORCE        (1 << 20)
86
87 #define OMAP2_MCSPI_CHSTAT_RXS          (1 << 0)
88 #define OMAP2_MCSPI_CHSTAT_TXS          (1 << 1)
89 #define OMAP2_MCSPI_CHSTAT_EOT          (1 << 2)
90
91 #define OMAP2_MCSPI_CHCTRL_EN           (1 << 0)
92
93
94 /* We have 2 DMA channels per CS, one for RX and one for TX */
95 struct omap2_mcspi_dma {
96         int dma_tx_channel;
97         int dma_rx_channel;
98
99         int dma_tx_sync_dev;
100         int dma_rx_sync_dev;
101
102         struct completion dma_tx_completion;
103         struct completion dma_rx_completion;
104 };
105
106 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
107  * cache operations; better heuristics consider wordsize and bitrate.
108  */
109 #define DMA_MIN_BYTES                   8
110
111
112 struct omap2_mcspi {
113         struct work_struct      work;
114         /* lock protects queue and registers */
115         spinlock_t              lock;
116         struct list_head        msg_queue;
117         struct spi_master       *master;
118         struct clk              *ick;
119         struct clk              *fck;
120         /* Virtual base address of the controller */
121         void __iomem            *base;
122         unsigned long           phys;
123         /* SPI1 has 4 channels, while SPI2 has 2 */
124         struct omap2_mcspi_dma  *dma_channels;
125 };
126
127 struct omap2_mcspi_cs {
128         void __iomem            *base;
129         unsigned long           phys;
130         int                     word_len;
131 };
132
133 static struct workqueue_struct *omap2_mcspi_wq;
134
135 #define MOD_REG_BIT(val, mask, set) do { \
136         if (set) \
137                 val |= mask; \
138         else \
139                 val &= ~mask; \
140 } while (0)
141
142 static inline void mcspi_write_reg(struct spi_master *master,
143                 int idx, u32 val)
144 {
145         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
146
147         __raw_writel(val, mcspi->base + idx);
148 }
149
150 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
151 {
152         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
153
154         return __raw_readl(mcspi->base + idx);
155 }
156
157 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
158                 int idx, u32 val)
159 {
160         struct omap2_mcspi_cs   *cs = spi->controller_state;
161
162         __raw_writel(val, cs->base +  idx);
163 }
164
165 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
166 {
167         struct omap2_mcspi_cs   *cs = spi->controller_state;
168
169         return __raw_readl(cs->base + idx);
170 }
171
172 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
173                 int is_read, int enable)
174 {
175         u32 l, rw;
176
177         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
178
179         if (is_read) /* 1 is read, 0 write */
180                 rw = OMAP2_MCSPI_CHCONF_DMAR;
181         else
182                 rw = OMAP2_MCSPI_CHCONF_DMAW;
183
184         MOD_REG_BIT(l, rw, enable);
185         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
186 }
187
188 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
189 {
190         u32 l;
191
192         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
193         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
194 }
195
196 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
197 {
198         u32 l;
199
200         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
201         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
202         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
203 }
204
205 static void omap2_mcspi_set_master_mode(struct spi_master *master)
206 {
207         u32 l;
208
209         /* setup when switching from (reset default) slave mode
210          * to single-channel master mode
211          */
212         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
213         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
214         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
215         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
216         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
217 }
218
219 static unsigned
220 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
221 {
222         struct omap2_mcspi      *mcspi;
223         struct omap2_mcspi_cs   *cs = spi->controller_state;
224         struct omap2_mcspi_dma  *mcspi_dma;
225         unsigned int            count, c;
226         unsigned long           base, tx_reg, rx_reg;
227         int                     word_len, data_type, element_count;
228         u8                      * rx;
229         const u8                * tx;
230
231         mcspi = spi_master_get_devdata(spi->master);
232         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
233
234         count = xfer->len;
235         c = count;
236         word_len = cs->word_len;
237
238         base = cs->phys;
239         tx_reg = base + OMAP2_MCSPI_TX0;
240         rx_reg = base + OMAP2_MCSPI_RX0;
241         rx = xfer->rx_buf;
242         tx = xfer->tx_buf;
243
244         if (word_len <= 8) {
245                 data_type = OMAP_DMA_DATA_TYPE_S8;
246                 element_count = count;
247         } else if (word_len <= 16) {
248                 data_type = OMAP_DMA_DATA_TYPE_S16;
249                 element_count = count >> 1;
250         } else /* word_len <= 32 */ {
251                 data_type = OMAP_DMA_DATA_TYPE_S32;
252                 element_count = count >> 2;
253         }
254
255         if (tx != NULL) {
256                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
257                                 data_type, element_count, 1,
258                                 OMAP_DMA_SYNC_ELEMENT,
259                                 mcspi_dma->dma_tx_sync_dev, 0);
260
261                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
262                                 OMAP_DMA_AMODE_CONSTANT,
263                                 tx_reg, 0, 0);
264
265                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
266                                 OMAP_DMA_AMODE_POST_INC,
267                                 xfer->tx_dma, 0, 0);
268         }
269
270         if (rx != NULL) {
271                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
272                                 data_type, element_count, 1,
273                                 OMAP_DMA_SYNC_ELEMENT,
274                                 mcspi_dma->dma_rx_sync_dev, 1);
275
276                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
277                                 OMAP_DMA_AMODE_CONSTANT,
278                                 rx_reg, 0, 0);
279
280                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
281                                 OMAP_DMA_AMODE_POST_INC,
282                                 xfer->rx_dma, 0, 0);
283         }
284
285         if (tx != NULL) {
286                 omap_start_dma(mcspi_dma->dma_tx_channel);
287                 omap2_mcspi_set_dma_req(spi, 0, 1);
288         }
289
290         if (rx != NULL) {
291                 omap_start_dma(mcspi_dma->dma_rx_channel);
292                 omap2_mcspi_set_dma_req(spi, 1, 1);
293         }
294
295         if (tx != NULL) {
296                 wait_for_completion(&mcspi_dma->dma_tx_completion);
297                 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
298         }
299
300         if (rx != NULL) {
301                 wait_for_completion(&mcspi_dma->dma_rx_completion);
302                 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
303         }
304         return count;
305 }
306
307 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
308 {
309         unsigned long timeout;
310
311         timeout = jiffies + msecs_to_jiffies(1000);
312         while (!(__raw_readl(reg) & bit)) {
313                 if (time_after(jiffies, timeout))
314                         return -1;
315                 cpu_relax();
316         }
317         return 0;
318 }
319
320 static unsigned
321 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
322 {
323         struct omap2_mcspi      *mcspi;
324         struct omap2_mcspi_cs   *cs = spi->controller_state;
325         unsigned int            count, c;
326         u32                     l;
327         void __iomem            *base = cs->base;
328         void __iomem            *tx_reg;
329         void __iomem            *rx_reg;
330         void __iomem            *chstat_reg;
331         int                     word_len;
332
333         mcspi = spi_master_get_devdata(spi->master);
334         count = xfer->len;
335         c = count;
336         word_len = cs->word_len;
337
338         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
339         l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
340
341         /* We store the pre-calculated register addresses on stack to speed
342          * up the transfer loop. */
343         tx_reg          = base + OMAP2_MCSPI_TX0;
344         rx_reg          = base + OMAP2_MCSPI_RX0;
345         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
346
347         if (word_len <= 8) {
348                 u8              *rx;
349                 const u8        *tx;
350
351                 rx = xfer->rx_buf;
352                 tx = xfer->tx_buf;
353
354                 do {
355                         c -= 1;
356                         if (tx != NULL) {
357                                 if (mcspi_wait_for_reg_bit(chstat_reg,
358                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
359                                         dev_err(&spi->dev, "TXS timed out\n");
360                                         goto out;
361                                 }
362 #ifdef VERBOSE
363                                 dev_dbg(&spi->dev, "write-%d %02x\n",
364                                                 word_len, *tx);
365 #endif
366                                 __raw_writel(*tx++, tx_reg);
367                         }
368                         if (rx != NULL) {
369                                 if (mcspi_wait_for_reg_bit(chstat_reg,
370                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
371                                         dev_err(&spi->dev, "RXS timed out\n");
372                                         goto out;
373                                 }
374                                 /* prevent last RX_ONLY read from triggering
375                                  * more word i/o: switch to rx+tx
376                                  */
377                                 if (c == 0 && tx == NULL)
378                                         mcspi_write_cs_reg(spi,
379                                                         OMAP2_MCSPI_CHCONF0, l);
380                                 *rx++ = __raw_readl(rx_reg);
381 #ifdef VERBOSE
382                                 dev_dbg(&spi->dev, "read-%d %02x\n",
383                                                 word_len, *(rx - 1));
384 #endif
385                         }
386                 } while (c);
387         } else if (word_len <= 16) {
388                 u16             *rx;
389                 const u16       *tx;
390
391                 rx = xfer->rx_buf;
392                 tx = xfer->tx_buf;
393                 do {
394                         c -= 2;
395                         if (tx != NULL) {
396                                 if (mcspi_wait_for_reg_bit(chstat_reg,
397                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
398                                         dev_err(&spi->dev, "TXS timed out\n");
399                                         goto out;
400                                 }
401 #ifdef VERBOSE
402                                 dev_dbg(&spi->dev, "write-%d %04x\n",
403                                                 word_len, *tx);
404 #endif
405                                 __raw_writel(*tx++, tx_reg);
406                         }
407                         if (rx != NULL) {
408                                 if (mcspi_wait_for_reg_bit(chstat_reg,
409                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
410                                         dev_err(&spi->dev, "RXS timed out\n");
411                                         goto out;
412                                 }
413                                 /* prevent last RX_ONLY read from triggering
414                                  * more word i/o: switch to rx+tx
415                                  */
416                                 if (c == 0 && tx == NULL)
417                                         mcspi_write_cs_reg(spi,
418                                                         OMAP2_MCSPI_CHCONF0, l);
419                                 *rx++ = __raw_readl(rx_reg);
420 #ifdef VERBOSE
421                                 dev_dbg(&spi->dev, "read-%d %04x\n",
422                                                 word_len, *(rx - 1));
423 #endif
424                         }
425                 } while (c);
426         } else if (word_len <= 32) {
427                 u32             *rx;
428                 const u32       *tx;
429
430                 rx = xfer->rx_buf;
431                 tx = xfer->tx_buf;
432                 do {
433                         c -= 4;
434                         if (tx != NULL) {
435                                 if (mcspi_wait_for_reg_bit(chstat_reg,
436                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
437                                         dev_err(&spi->dev, "TXS timed out\n");
438                                         goto out;
439                                 }
440 #ifdef VERBOSE
441                                 dev_dbg(&spi->dev, "write-%d %04x\n",
442                                                 word_len, *tx);
443 #endif
444                                 __raw_writel(*tx++, tx_reg);
445                         }
446                         if (rx != NULL) {
447                                 if (mcspi_wait_for_reg_bit(chstat_reg,
448                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
449                                         dev_err(&spi->dev, "RXS timed out\n");
450                                         goto out;
451                                 }
452                                 /* prevent last RX_ONLY read from triggering
453                                  * more word i/o: switch to rx+tx
454                                  */
455                                 if (c == 0 && tx == NULL)
456                                         mcspi_write_cs_reg(spi,
457                                                         OMAP2_MCSPI_CHCONF0, l);
458                                 *rx++ = __raw_readl(rx_reg);
459 #ifdef VERBOSE
460                                 dev_dbg(&spi->dev, "read-%d %04x\n",
461                                                 word_len, *(rx - 1));
462 #endif
463                         }
464                 } while (c);
465         }
466
467         /* for TX_ONLY mode, be sure all words have shifted out */
468         if (xfer->rx_buf == NULL) {
469                 if (mcspi_wait_for_reg_bit(chstat_reg,
470                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
471                         dev_err(&spi->dev, "TXS timed out\n");
472                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
473                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
474                         dev_err(&spi->dev, "EOT timed out\n");
475         }
476 out:
477         return count - c;
478 }
479
480 /* called only when no transfer is active to this device */
481 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
482                 struct spi_transfer *t)
483 {
484         struct omap2_mcspi_cs *cs = spi->controller_state;
485         struct omap2_mcspi *mcspi;
486         u32 l = 0, div = 0;
487         u8 word_len = spi->bits_per_word;
488
489         mcspi = spi_master_get_devdata(spi->master);
490
491         if (t != NULL && t->bits_per_word)
492                 word_len = t->bits_per_word;
493
494         cs->word_len = word_len;
495
496         if (spi->max_speed_hz) {
497                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
498                                         > spi->max_speed_hz)
499                         div++;
500         } else
501                 div = 15;
502
503         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
504
505         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
506          * REVISIT: this controller could support SPI_3WIRE mode.
507          */
508         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
509         l |= OMAP2_MCSPI_CHCONF_DPE0;
510
511         /* wordlength */
512         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
513         l |= (word_len - 1) << 7;
514
515         /* set chipselect polarity; manage with FORCE */
516         if (!(spi->mode & SPI_CS_HIGH))
517                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
518         else
519                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
520
521         /* set clock divisor */
522         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
523         l |= div << 2;
524
525         /* set SPI mode 0..3 */
526         if (spi->mode & SPI_CPOL)
527                 l |= OMAP2_MCSPI_CHCONF_POL;
528         else
529                 l &= ~OMAP2_MCSPI_CHCONF_POL;
530         if (spi->mode & SPI_CPHA)
531                 l |= OMAP2_MCSPI_CHCONF_PHA;
532         else
533                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
534
535         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
536
537         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
538                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
539                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
540                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
541
542         return 0;
543 }
544
545 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
546 {
547         struct spi_device       *spi = data;
548         struct omap2_mcspi      *mcspi;
549         struct omap2_mcspi_dma  *mcspi_dma;
550
551         mcspi = spi_master_get_devdata(spi->master);
552         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
553
554         complete(&mcspi_dma->dma_rx_completion);
555
556         /* We must disable the DMA RX request */
557         omap2_mcspi_set_dma_req(spi, 1, 0);
558 }
559
560 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
561 {
562         struct spi_device       *spi = data;
563         struct omap2_mcspi      *mcspi;
564         struct omap2_mcspi_dma  *mcspi_dma;
565
566         mcspi = spi_master_get_devdata(spi->master);
567         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
568
569         complete(&mcspi_dma->dma_tx_completion);
570
571         /* We must disable the DMA TX request */
572         omap2_mcspi_set_dma_req(spi, 0, 0);
573 }
574
575 static int omap2_mcspi_request_dma(struct spi_device *spi)
576 {
577         struct spi_master       *master = spi->master;
578         struct omap2_mcspi      *mcspi;
579         struct omap2_mcspi_dma  *mcspi_dma;
580
581         mcspi = spi_master_get_devdata(master);
582         mcspi_dma = mcspi->dma_channels + spi->chip_select;
583
584         if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
585                         omap2_mcspi_dma_rx_callback, spi,
586                         &mcspi_dma->dma_rx_channel)) {
587                 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
588                 return -EAGAIN;
589         }
590
591         if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
592                         omap2_mcspi_dma_tx_callback, spi,
593                         &mcspi_dma->dma_tx_channel)) {
594                 omap_free_dma(mcspi_dma->dma_rx_channel);
595                 mcspi_dma->dma_rx_channel = -1;
596                 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
597                 return -EAGAIN;
598         }
599
600         init_completion(&mcspi_dma->dma_rx_completion);
601         init_completion(&mcspi_dma->dma_tx_completion);
602
603         return 0;
604 }
605
606 /* the spi->mode bits understood by this driver: */
607 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
608
609 static int omap2_mcspi_setup(struct spi_device *spi)
610 {
611         int                     ret;
612         struct omap2_mcspi      *mcspi;
613         struct omap2_mcspi_dma  *mcspi_dma;
614         struct omap2_mcspi_cs   *cs = spi->controller_state;
615
616         if (spi->mode & ~MODEBITS) {
617                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
618                         spi->mode & ~MODEBITS);
619                 return -EINVAL;
620         }
621
622         if (spi->bits_per_word == 0)
623                 spi->bits_per_word = 8;
624         else if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
625                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
626                         spi->bits_per_word);
627                 return -EINVAL;
628         }
629
630         mcspi = spi_master_get_devdata(spi->master);
631         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
632
633         if (!cs) {
634                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
635                 if (!cs)
636                         return -ENOMEM;
637                 cs->base = mcspi->base + spi->chip_select * 0x14;
638                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
639                 spi->controller_state = cs;
640         }
641
642         if (mcspi_dma->dma_rx_channel == -1
643                         || mcspi_dma->dma_tx_channel == -1) {
644                 ret = omap2_mcspi_request_dma(spi);
645                 if (ret < 0)
646                         return ret;
647         }
648
649         clk_enable(mcspi->ick);
650         clk_enable(mcspi->fck);
651         ret = omap2_mcspi_setup_transfer(spi, NULL);
652         clk_disable(mcspi->fck);
653         clk_disable(mcspi->ick);
654
655         return ret;
656 }
657
658 static void omap2_mcspi_cleanup(struct spi_device *spi)
659 {
660         struct omap2_mcspi      *mcspi;
661         struct omap2_mcspi_dma  *mcspi_dma;
662
663         mcspi = spi_master_get_devdata(spi->master);
664         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
665
666         kfree(spi->controller_state);
667
668         if (mcspi_dma->dma_rx_channel != -1) {
669                 omap_free_dma(mcspi_dma->dma_rx_channel);
670                 mcspi_dma->dma_rx_channel = -1;
671         }
672         if (mcspi_dma->dma_tx_channel != -1) {
673                 omap_free_dma(mcspi_dma->dma_tx_channel);
674                 mcspi_dma->dma_tx_channel = -1;
675         }
676 }
677
678 static void omap2_mcspi_work(struct work_struct *work)
679 {
680         struct omap2_mcspi      *mcspi;
681
682         mcspi = container_of(work, struct omap2_mcspi, work);
683         spin_lock_irq(&mcspi->lock);
684
685         clk_enable(mcspi->ick);
686         clk_enable(mcspi->fck);
687
688         /* We only enable one channel at a time -- the one whose message is
689          * at the head of the queue -- although this controller would gladly
690          * arbitrate among multiple channels.  This corresponds to "single
691          * channel" master mode.  As a side effect, we need to manage the
692          * chipselect with the FORCE bit ... CS != channel enable.
693          */
694         while (!list_empty(&mcspi->msg_queue)) {
695                 struct spi_message              *m;
696                 struct spi_device               *spi;
697                 struct spi_transfer             *t = NULL;
698                 int                             cs_active = 0;
699                 struct omap2_mcspi_cs           *cs;
700                 int                             par_override = 0;
701                 int                             status = 0;
702                 u32                             chconf;
703
704                 m = container_of(mcspi->msg_queue.next, struct spi_message,
705                                  queue);
706
707                 list_del_init(&m->queue);
708                 spin_unlock_irq(&mcspi->lock);
709
710                 spi = m->spi;
711                 cs = spi->controller_state;
712
713                 omap2_mcspi_set_enable(spi, 1);
714                 list_for_each_entry(t, &m->transfers, transfer_list) {
715                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
716                                 status = -EINVAL;
717                                 break;
718                         }
719                         if (par_override || t->speed_hz || t->bits_per_word) {
720                                 par_override = 1;
721                                 status = omap2_mcspi_setup_transfer(spi, t);
722                                 if (status < 0)
723                                         break;
724                                 if (!t->speed_hz && !t->bits_per_word)
725                                         par_override = 0;
726                         }
727
728                         if (!cs_active) {
729                                 omap2_mcspi_force_cs(spi, 1);
730                                 cs_active = 1;
731                         }
732
733                         chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
734                         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
735                         if (t->tx_buf == NULL)
736                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
737                         else if (t->rx_buf == NULL)
738                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
739                         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
740
741                         if (t->len) {
742                                 unsigned        count;
743
744                                 /* RX_ONLY mode needs dummy data in TX reg */
745                                 if (t->tx_buf == NULL)
746                                         __raw_writel(0, cs->base
747                                                         + OMAP2_MCSPI_TX0);
748
749                                 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
750                                         count = omap2_mcspi_txrx_dma(spi, t);
751                                 else
752                                         count = omap2_mcspi_txrx_pio(spi, t);
753                                 m->actual_length += count;
754
755                                 if (count != t->len) {
756                                         status = -EIO;
757                                         break;
758                                 }
759                         }
760
761                         if (t->delay_usecs)
762                                 udelay(t->delay_usecs);
763
764                         /* ignore the "leave it on after last xfer" hint */
765                         if (t->cs_change) {
766                                 omap2_mcspi_force_cs(spi, 0);
767                                 cs_active = 0;
768                         }
769                 }
770
771                 /* Restore defaults if they were overriden */
772                 if (par_override) {
773                         par_override = 0;
774                         status = omap2_mcspi_setup_transfer(spi, NULL);
775                 }
776
777                 if (cs_active)
778                         omap2_mcspi_force_cs(spi, 0);
779
780                 omap2_mcspi_set_enable(spi, 0);
781
782                 m->status = status;
783                 m->complete(m->context);
784
785                 spin_lock_irq(&mcspi->lock);
786         }
787
788         clk_disable(mcspi->fck);
789         clk_disable(mcspi->ick);
790
791         spin_unlock_irq(&mcspi->lock);
792 }
793
794 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
795 {
796         struct omap2_mcspi      *mcspi;
797         unsigned long           flags;
798         struct spi_transfer     *t;
799
800         m->actual_length = 0;
801         m->status = 0;
802
803         /* reject invalid messages and transfers */
804         if (list_empty(&m->transfers) || !m->complete)
805                 return -EINVAL;
806         list_for_each_entry(t, &m->transfers, transfer_list) {
807                 const void      *tx_buf = t->tx_buf;
808                 void            *rx_buf = t->rx_buf;
809                 unsigned        len = t->len;
810
811                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
812                                 || (len && !(rx_buf || tx_buf))
813                                 || (t->bits_per_word &&
814                                         (  t->bits_per_word < 4
815                                         || t->bits_per_word > 32))) {
816                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
817                                         t->speed_hz,
818                                         len,
819                                         tx_buf ? "tx" : "",
820                                         rx_buf ? "rx" : "",
821                                         t->bits_per_word);
822                         return -EINVAL;
823                 }
824                 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
825                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
826                                         t->speed_hz,
827                                         OMAP2_MCSPI_MAX_FREQ/(1<<16));
828                         return -EINVAL;
829                 }
830
831                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
832                         continue;
833
834                 /* Do DMA mapping "early" for better error reporting and
835                  * dcache use.  Note that if dma_unmap_single() ever starts
836                  * to do real work on ARM, we'd need to clean up mappings
837                  * for previous transfers on *ALL* exits of this loop...
838                  */
839                 if (tx_buf != NULL) {
840                         t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
841                                         len, DMA_TO_DEVICE);
842                         if (dma_mapping_error(&spi->dev, t->tx_dma)) {
843                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
844                                                 'T', len);
845                                 return -EINVAL;
846                         }
847                 }
848                 if (rx_buf != NULL) {
849                         t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
850                                         DMA_FROM_DEVICE);
851                         if (dma_mapping_error(&spi->dev, t->rx_dma)) {
852                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
853                                                 'R', len);
854                                 if (tx_buf != NULL)
855                                         dma_unmap_single(NULL, t->tx_dma,
856                                                         len, DMA_TO_DEVICE);
857                                 return -EINVAL;
858                         }
859                 }
860         }
861
862         mcspi = spi_master_get_devdata(spi->master);
863
864         spin_lock_irqsave(&mcspi->lock, flags);
865         list_add_tail(&m->queue, &mcspi->msg_queue);
866         queue_work(omap2_mcspi_wq, &mcspi->work);
867         spin_unlock_irqrestore(&mcspi->lock, flags);
868
869         return 0;
870 }
871
872 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
873 {
874         struct spi_master       *master = mcspi->master;
875         u32                     tmp;
876
877         clk_enable(mcspi->ick);
878         clk_enable(mcspi->fck);
879
880         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
881                         OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
882         do {
883                 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
884         } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
885
886         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
887                         /* (3 << 8) | (2 << 3) | */
888                         OMAP2_MCSPI_SYSCONFIG_AUTOIDLE);
889
890         omap2_mcspi_set_master_mode(master);
891
892         clk_disable(mcspi->fck);
893         clk_disable(mcspi->ick);
894         return 0;
895 }
896
897 static u8 __initdata spi1_rxdma_id [] = {
898         OMAP24XX_DMA_SPI1_RX0,
899         OMAP24XX_DMA_SPI1_RX1,
900         OMAP24XX_DMA_SPI1_RX2,
901         OMAP24XX_DMA_SPI1_RX3,
902 };
903
904 static u8 __initdata spi1_txdma_id [] = {
905         OMAP24XX_DMA_SPI1_TX0,
906         OMAP24XX_DMA_SPI1_TX1,
907         OMAP24XX_DMA_SPI1_TX2,
908         OMAP24XX_DMA_SPI1_TX3,
909 };
910
911 static u8 __initdata spi2_rxdma_id[] = {
912         OMAP24XX_DMA_SPI2_RX0,
913         OMAP24XX_DMA_SPI2_RX1,
914 };
915
916 static u8 __initdata spi2_txdma_id[] = {
917         OMAP24XX_DMA_SPI2_TX0,
918         OMAP24XX_DMA_SPI2_TX1,
919 };
920
921 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
922 static u8 __initdata spi3_rxdma_id[] = {
923         OMAP24XX_DMA_SPI3_RX0,
924         OMAP24XX_DMA_SPI3_RX1,
925 };
926
927 static u8 __initdata spi3_txdma_id[] = {
928         OMAP24XX_DMA_SPI3_TX0,
929         OMAP24XX_DMA_SPI3_TX1,
930 };
931 #endif
932
933 #ifdef CONFIG_ARCH_OMAP3
934 static u8 __initdata spi4_rxdma_id[] = {
935         OMAP34XX_DMA_SPI4_RX0,
936 };
937
938 static u8 __initdata spi4_txdma_id[] = {
939         OMAP34XX_DMA_SPI4_TX0,
940 };
941 #endif
942
943 static int __init omap2_mcspi_probe(struct platform_device *pdev)
944 {
945         struct spi_master       *master;
946         struct omap2_mcspi      *mcspi;
947         struct resource         *r;
948         int                     status = 0, i;
949         const u8                *rxdma_id, *txdma_id;
950         unsigned                num_chipselect;
951
952         switch (pdev->id) {
953         case 1:
954                 rxdma_id = spi1_rxdma_id;
955                 txdma_id = spi1_txdma_id;
956                 num_chipselect = 4;
957                 break;
958         case 2:
959                 rxdma_id = spi2_rxdma_id;
960                 txdma_id = spi2_txdma_id;
961                 num_chipselect = 2;
962                 break;
963 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
964         case 3:
965                 rxdma_id = spi3_rxdma_id;
966                 txdma_id = spi3_txdma_id;
967                 num_chipselect = 2;
968                 break;
969 #endif
970 #ifdef CONFIG_ARCH_OMAP3
971         case 4:
972                 rxdma_id = spi4_rxdma_id;
973                 txdma_id = spi4_txdma_id;
974                 num_chipselect = 1;
975                 break;
976 #endif
977         default:
978                 return -EINVAL;
979         }
980
981         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
982         if (master == NULL) {
983                 dev_dbg(&pdev->dev, "master allocation failed\n");
984                 return -ENOMEM;
985         }
986
987         if (pdev->id != -1)
988                 master->bus_num = pdev->id;
989
990         master->setup = omap2_mcspi_setup;
991         master->transfer = omap2_mcspi_transfer;
992         master->cleanup = omap2_mcspi_cleanup;
993         master->num_chipselect = num_chipselect;
994
995         dev_set_drvdata(&pdev->dev, master);
996
997         mcspi = spi_master_get_devdata(master);
998         mcspi->master = master;
999
1000         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001         if (r == NULL) {
1002                 status = -ENODEV;
1003                 goto err1;
1004         }
1005         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1006                         dev_name(&pdev->dev))) {
1007                 status = -EBUSY;
1008                 goto err1;
1009         }
1010
1011         mcspi->phys = r->start;
1012         mcspi->base = ioremap(r->start, r->end - r->start + 1);
1013         if (!mcspi->base) {
1014                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1015                 status = -ENOMEM;
1016                 goto err1aa;
1017         }
1018
1019         INIT_WORK(&mcspi->work, omap2_mcspi_work);
1020
1021         spin_lock_init(&mcspi->lock);
1022         INIT_LIST_HEAD(&mcspi->msg_queue);
1023
1024         mcspi->ick = clk_get(&pdev->dev, "ick");
1025         if (IS_ERR(mcspi->ick)) {
1026                 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1027                 status = PTR_ERR(mcspi->ick);
1028                 goto err1a;
1029         }
1030         mcspi->fck = clk_get(&pdev->dev, "fck");
1031         if (IS_ERR(mcspi->fck)) {
1032                 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1033                 status = PTR_ERR(mcspi->fck);
1034                 goto err2;
1035         }
1036
1037         mcspi->dma_channels = kcalloc(master->num_chipselect,
1038                         sizeof(struct omap2_mcspi_dma),
1039                         GFP_KERNEL);
1040
1041         if (mcspi->dma_channels == NULL)
1042                 goto err3;
1043
1044         for (i = 0; i < num_chipselect; i++) {
1045                 mcspi->dma_channels[i].dma_rx_channel = -1;
1046                 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1047                 mcspi->dma_channels[i].dma_tx_channel = -1;
1048                 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1049         }
1050
1051         if (omap2_mcspi_reset(mcspi) < 0)
1052                 goto err4;
1053
1054         status = spi_register_master(master);
1055         if (status < 0)
1056                 goto err4;
1057
1058         return status;
1059
1060 err4:
1061         kfree(mcspi->dma_channels);
1062 err3:
1063         clk_put(mcspi->fck);
1064 err2:
1065         clk_put(mcspi->ick);
1066 err1a:
1067         iounmap(mcspi->base);
1068 err1aa:
1069         release_mem_region(r->start, (r->end - r->start) + 1);
1070 err1:
1071         spi_master_put(master);
1072         return status;
1073 }
1074
1075 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1076 {
1077         struct spi_master       *master;
1078         struct omap2_mcspi      *mcspi;
1079         struct omap2_mcspi_dma  *dma_channels;
1080         struct resource         *r;
1081         void __iomem *base;
1082
1083         master = dev_get_drvdata(&pdev->dev);
1084         mcspi = spi_master_get_devdata(master);
1085         dma_channels = mcspi->dma_channels;
1086
1087         clk_put(mcspi->fck);
1088         clk_put(mcspi->ick);
1089
1090         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1091         release_mem_region(r->start, (r->end - r->start) + 1);
1092
1093         base = mcspi->base;
1094         spi_unregister_master(master);
1095         iounmap(base);
1096         kfree(dma_channels);
1097
1098         return 0;
1099 }
1100
1101 /* work with hotplug and coldplug */
1102 MODULE_ALIAS("platform:omap2_mcspi");
1103
1104 static struct platform_driver omap2_mcspi_driver = {
1105         .driver = {
1106                 .name =         "omap2_mcspi",
1107                 .owner =        THIS_MODULE,
1108         },
1109         .remove =       __exit_p(omap2_mcspi_remove),
1110 };
1111
1112
1113 static int __init omap2_mcspi_init(void)
1114 {
1115         omap2_mcspi_wq = create_singlethread_workqueue(
1116                                 omap2_mcspi_driver.driver.name);
1117         if (omap2_mcspi_wq == NULL)
1118                 return -1;
1119         return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1120 }
1121 subsys_initcall(omap2_mcspi_init);
1122
1123 static void __exit omap2_mcspi_exit(void)
1124 {
1125         platform_driver_unregister(&omap2_mcspi_driver);
1126
1127         destroy_workqueue(omap2_mcspi_wq);
1128 }
1129 module_exit(omap2_mcspi_exit);
1130
1131 MODULE_LICENSE("GPL");