spi-imx: Add mx25 support
[linux-2.6.git] / drivers / spi / mpc52xx_psc_spi.c
1 /*
2  * MPC52xx PSC in SPI mode driver.
3  *
4  * Maintainer: Dragos Carp
5  *
6  * Copyright (C) 2006 TOPTICA Photonics AG.
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  */
13
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/errno.h>
18 #include <linux/interrupt.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_spi.h>
21 #include <linux/workqueue.h>
22 #include <linux/completion.h>
23 #include <linux/io.h>
24 #include <linux/delay.h>
25 #include <linux/spi/spi.h>
26 #include <linux/fsl_devices.h>
27
28 #include <asm/mpc52xx.h>
29 #include <asm/mpc52xx_psc.h>
30
31 #define MCLK 20000000 /* PSC port MClk in hz */
32
33 struct mpc52xx_psc_spi {
34         /* fsl_spi_platform data */
35         void (*cs_control)(struct spi_device *spi, bool on);
36         u32 sysclk;
37
38         /* driver internal data */
39         struct mpc52xx_psc __iomem *psc;
40         struct mpc52xx_psc_fifo __iomem *fifo;
41         unsigned int irq;
42         u8 bits_per_word;
43         u8 busy;
44
45         struct workqueue_struct *workqueue;
46         struct work_struct work;
47
48         struct list_head queue;
49         spinlock_t lock;
50
51         struct completion done;
52 };
53
54 /* controller state */
55 struct mpc52xx_psc_spi_cs {
56         int bits_per_word;
57         int speed_hz;
58 };
59
60 /* set clock freq, clock ramp, bits per work
61  * if t is NULL then reset the values to the default values
62  */
63 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
64                 struct spi_transfer *t)
65 {
66         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
67
68         cs->speed_hz = (t && t->speed_hz)
69                         ? t->speed_hz : spi->max_speed_hz;
70         cs->bits_per_word = (t && t->bits_per_word)
71                         ? t->bits_per_word : spi->bits_per_word;
72         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
73         return 0;
74 }
75
76 static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
77 {
78         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
79         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
80         struct mpc52xx_psc __iomem *psc = mps->psc;
81         u32 sicr;
82         u16 ccr;
83
84         sicr = in_be32(&psc->sicr);
85
86         /* Set clock phase and polarity */
87         if (spi->mode & SPI_CPHA)
88                 sicr |= 0x00001000;
89         else
90                 sicr &= ~0x00001000;
91         if (spi->mode & SPI_CPOL)
92                 sicr |= 0x00002000;
93         else
94                 sicr &= ~0x00002000;
95
96         if (spi->mode & SPI_LSB_FIRST)
97                 sicr |= 0x10000000;
98         else
99                 sicr &= ~0x10000000;
100         out_be32(&psc->sicr, sicr);
101
102         /* Set clock frequency and bits per word
103          * Because psc->ccr is defined as 16bit register instead of 32bit
104          * just set the lower byte of BitClkDiv
105          */
106         ccr = in_be16((u16 __iomem *)&psc->ccr);
107         ccr &= 0xFF00;
108         if (cs->speed_hz)
109                 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
110         else /* by default SPI Clk 1MHz */
111                 ccr |= (MCLK / 1000000 - 1) & 0xFF;
112         out_be16((u16 __iomem *)&psc->ccr, ccr);
113         mps->bits_per_word = cs->bits_per_word;
114
115         if (mps->cs_control)
116                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
117 }
118
119 static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
120 {
121         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
122
123         if (mps->cs_control)
124                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
125 }
126
127 #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
128 /* wake up when 80% fifo full */
129 #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
130
131 static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
132                                                 struct spi_transfer *t)
133 {
134         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
135         struct mpc52xx_psc __iomem *psc = mps->psc;
136         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
137         unsigned rb = 0;        /* number of bytes receieved */
138         unsigned sb = 0;        /* number of bytes sent */
139         unsigned char *rx_buf = (unsigned char *)t->rx_buf;
140         unsigned char *tx_buf = (unsigned char *)t->tx_buf;
141         unsigned rfalarm;
142         unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
143         unsigned recv_at_once;
144         int last_block = 0;
145
146         if (!t->tx_buf && !t->rx_buf && t->len)
147                 return -EINVAL;
148
149         /* enable transmiter/receiver */
150         out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
151         while (rb < t->len) {
152                 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
153                         rfalarm = MPC52xx_PSC_RFALARM;
154                         last_block = 0;
155                 } else {
156                         send_at_once = t->len - sb;
157                         rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
158                         last_block = 1;
159                 }
160
161                 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
162                 for (; send_at_once; sb++, send_at_once--) {
163                         /* set EOF flag before the last word is sent */
164                         if (send_at_once == 1 && last_block)
165                                 out_8(&psc->ircr2, 0x01);
166
167                         if (tx_buf)
168                                 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
169                         else
170                                 out_8(&psc->mpc52xx_psc_buffer_8, 0);
171                 }
172
173
174                 /* enable interrupts and wait for wake up
175                  * if just one byte is expected the Rx FIFO genererates no
176                  * FFULL interrupt, so activate the RxRDY interrupt
177                  */
178                 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
179                 if (t->len - rb == 1) {
180                         out_8(&psc->mode, 0);
181                 } else {
182                         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
183                         out_be16(&fifo->rfalarm, rfalarm);
184                 }
185                 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
186                 wait_for_completion(&mps->done);
187                 recv_at_once = in_be16(&fifo->rfnum);
188                 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
189
190                 send_at_once = recv_at_once;
191                 if (rx_buf) {
192                         for (; recv_at_once; rb++, recv_at_once--)
193                                 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
194                 } else {
195                         for (; recv_at_once; rb++, recv_at_once--)
196                                 in_8(&psc->mpc52xx_psc_buffer_8);
197                 }
198         }
199         /* disable transmiter/receiver */
200         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
201
202         return 0;
203 }
204
205 static void mpc52xx_psc_spi_work(struct work_struct *work)
206 {
207         struct mpc52xx_psc_spi *mps =
208                 container_of(work, struct mpc52xx_psc_spi, work);
209
210         spin_lock_irq(&mps->lock);
211         mps->busy = 1;
212         while (!list_empty(&mps->queue)) {
213                 struct spi_message *m;
214                 struct spi_device *spi;
215                 struct spi_transfer *t = NULL;
216                 unsigned cs_change;
217                 int status;
218
219                 m = container_of(mps->queue.next, struct spi_message, queue);
220                 list_del_init(&m->queue);
221                 spin_unlock_irq(&mps->lock);
222
223                 spi = m->spi;
224                 cs_change = 1;
225                 status = 0;
226                 list_for_each_entry (t, &m->transfers, transfer_list) {
227                         if (t->bits_per_word || t->speed_hz) {
228                                 status = mpc52xx_psc_spi_transfer_setup(spi, t);
229                                 if (status < 0)
230                                         break;
231                         }
232
233                         if (cs_change)
234                                 mpc52xx_psc_spi_activate_cs(spi);
235                         cs_change = t->cs_change;
236
237                         status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
238                         if (status)
239                                 break;
240                         m->actual_length += t->len;
241
242                         if (t->delay_usecs)
243                                 udelay(t->delay_usecs);
244
245                         if (cs_change)
246                                 mpc52xx_psc_spi_deactivate_cs(spi);
247                 }
248
249                 m->status = status;
250                 m->complete(m->context);
251
252                 if (status || !cs_change)
253                         mpc52xx_psc_spi_deactivate_cs(spi);
254
255                 mpc52xx_psc_spi_transfer_setup(spi, NULL);
256
257                 spin_lock_irq(&mps->lock);
258         }
259         mps->busy = 0;
260         spin_unlock_irq(&mps->lock);
261 }
262
263 static int mpc52xx_psc_spi_setup(struct spi_device *spi)
264 {
265         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
266         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
267         unsigned long flags;
268
269         if (spi->bits_per_word%8)
270                 return -EINVAL;
271
272         if (!cs) {
273                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
274                 if (!cs)
275                         return -ENOMEM;
276                 spi->controller_state = cs;
277         }
278
279         cs->bits_per_word = spi->bits_per_word;
280         cs->speed_hz = spi->max_speed_hz;
281
282         spin_lock_irqsave(&mps->lock, flags);
283         if (!mps->busy)
284                 mpc52xx_psc_spi_deactivate_cs(spi);
285         spin_unlock_irqrestore(&mps->lock, flags);
286
287         return 0;
288 }
289
290 static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
291                 struct spi_message *m)
292 {
293         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
294         unsigned long flags;
295
296         m->actual_length = 0;
297         m->status = -EINPROGRESS;
298
299         spin_lock_irqsave(&mps->lock, flags);
300         list_add_tail(&m->queue, &mps->queue);
301         queue_work(mps->workqueue, &mps->work);
302         spin_unlock_irqrestore(&mps->lock, flags);
303
304         return 0;
305 }
306
307 static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
308 {
309         kfree(spi->controller_state);
310 }
311
312 static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
313 {
314         struct mpc52xx_psc __iomem *psc = mps->psc;
315         struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
316         u32 mclken_div;
317         int ret;
318
319         /* default sysclk is 512MHz */
320         mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
321         ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
322         if (ret)
323                 return ret;
324
325         /* Reset the PSC into a known state */
326         out_8(&psc->command, MPC52xx_PSC_RST_RX);
327         out_8(&psc->command, MPC52xx_PSC_RST_TX);
328         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
329
330         /* Disable interrupts, interrupts are based on alarm level */
331         out_be16(&psc->mpc52xx_psc_imr, 0);
332         out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
333         out_8(&fifo->rfcntl, 0);
334         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
335
336         /* Configure 8bit codec mode as a SPI master and use EOF flags */
337         /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
338         out_be32(&psc->sicr, 0x0180C800);
339         out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
340
341         /* Set 2ms DTL delay */
342         out_8(&psc->ctur, 0x00);
343         out_8(&psc->ctlr, 0x84);
344
345         mps->bits_per_word = 8;
346
347         return 0;
348 }
349
350 static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
351 {
352         struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
353         struct mpc52xx_psc __iomem *psc = mps->psc;
354
355         /* disable interrupt and wake up the work queue */
356         if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
357                 out_be16(&psc->mpc52xx_psc_imr, 0);
358                 complete(&mps->done);
359                 return IRQ_HANDLED;
360         }
361         return IRQ_NONE;
362 }
363
364 /* bus_num is used only for the case dev->platform_data == NULL */
365 static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
366                                 u32 size, unsigned int irq, s16 bus_num)
367 {
368         struct fsl_spi_platform_data *pdata = dev->platform_data;
369         struct mpc52xx_psc_spi *mps;
370         struct spi_master *master;
371         int ret;
372
373         master = spi_alloc_master(dev, sizeof *mps);
374         if (master == NULL)
375                 return -ENOMEM;
376
377         dev_set_drvdata(dev, master);
378         mps = spi_master_get_devdata(master);
379
380         /* the spi->mode bits understood by this driver: */
381         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
382
383         mps->irq = irq;
384         if (pdata == NULL) {
385                 dev_warn(dev, "probe called without platform data, no "
386                                 "cs_control function will be called\n");
387                 mps->cs_control = NULL;
388                 mps->sysclk = 0;
389                 master->bus_num = bus_num;
390                 master->num_chipselect = 255;
391         } else {
392                 mps->cs_control = pdata->cs_control;
393                 mps->sysclk = pdata->sysclk;
394                 master->bus_num = pdata->bus_num;
395                 master->num_chipselect = pdata->max_chipselect;
396         }
397         master->setup = mpc52xx_psc_spi_setup;
398         master->transfer = mpc52xx_psc_spi_transfer;
399         master->cleanup = mpc52xx_psc_spi_cleanup;
400
401         mps->psc = ioremap(regaddr, size);
402         if (!mps->psc) {
403                 dev_err(dev, "could not ioremap I/O port range\n");
404                 ret = -EFAULT;
405                 goto free_master;
406         }
407         /* On the 5200, fifo regs are immediately ajacent to the psc regs */
408         mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
409
410         ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
411                                 mps);
412         if (ret)
413                 goto free_master;
414
415         ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
416         if (ret < 0) {
417                 dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
418                 goto free_irq;
419         }
420
421         spin_lock_init(&mps->lock);
422         init_completion(&mps->done);
423         INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
424         INIT_LIST_HEAD(&mps->queue);
425
426         mps->workqueue = create_singlethread_workqueue(
427                 dev_name(master->dev.parent));
428         if (mps->workqueue == NULL) {
429                 ret = -EBUSY;
430                 goto free_irq;
431         }
432
433         ret = spi_register_master(master);
434         if (ret < 0)
435                 goto unreg_master;
436
437         return ret;
438
439 unreg_master:
440         destroy_workqueue(mps->workqueue);
441 free_irq:
442         free_irq(mps->irq, mps);
443 free_master:
444         if (mps->psc)
445                 iounmap(mps->psc);
446         spi_master_put(master);
447
448         return ret;
449 }
450
451 static int __exit mpc52xx_psc_spi_do_remove(struct device *dev)
452 {
453         struct spi_master *master = dev_get_drvdata(dev);
454         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
455
456         flush_workqueue(mps->workqueue);
457         destroy_workqueue(mps->workqueue);
458         spi_unregister_master(master);
459         free_irq(mps->irq, mps);
460         if (mps->psc)
461                 iounmap(mps->psc);
462
463         return 0;
464 }
465
466 static int __init mpc52xx_psc_spi_of_probe(struct of_device *op,
467         const struct of_device_id *match)
468 {
469         const u32 *regaddr_p;
470         u64 regaddr64, size64;
471         s16 id = -1;
472         int rc;
473
474         regaddr_p = of_get_address(op->node, 0, &size64, NULL);
475         if (!regaddr_p) {
476                 dev_err(&op->dev, "Invalid PSC address\n");
477                 return -EINVAL;
478         }
479         regaddr64 = of_translate_address(op->node, regaddr_p);
480
481         /* get PSC id (1..6, used by port_config) */
482         if (op->dev.platform_data == NULL) {
483                 const u32 *psc_nump;
484
485                 psc_nump = of_get_property(op->node, "cell-index", NULL);
486                 if (!psc_nump || *psc_nump > 5) {
487                         dev_err(&op->dev, "Invalid cell-index property\n");
488                         return -EINVAL;
489                 }
490                 id = *psc_nump + 1;
491         }
492
493         rc = mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
494                                         irq_of_parse_and_map(op->node, 0), id);
495         if (rc == 0)
496                 of_register_spi_devices(dev_get_drvdata(&op->dev), op->node);
497
498         return rc;
499 }
500
501 static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op)
502 {
503         return mpc52xx_psc_spi_do_remove(&op->dev);
504 }
505
506 static struct of_device_id mpc52xx_psc_spi_of_match[] = {
507         { .compatible = "fsl,mpc5200-psc-spi", },
508         { .compatible = "mpc5200-psc-spi", }, /* old */
509         {}
510 };
511
512 MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
513
514 static struct of_platform_driver mpc52xx_psc_spi_of_driver = {
515         .owner = THIS_MODULE,
516         .name = "mpc52xx-psc-spi",
517         .match_table = mpc52xx_psc_spi_of_match,
518         .probe = mpc52xx_psc_spi_of_probe,
519         .remove = __exit_p(mpc52xx_psc_spi_of_remove),
520         .driver = {
521                 .name = "mpc52xx-psc-spi",
522                 .owner = THIS_MODULE,
523         },
524 };
525
526 static int __init mpc52xx_psc_spi_init(void)
527 {
528         return of_register_platform_driver(&mpc52xx_psc_spi_of_driver);
529 }
530 module_init(mpc52xx_psc_spi_init);
531
532 static void __exit mpc52xx_psc_spi_exit(void)
533 {
534         of_unregister_platform_driver(&mpc52xx_psc_spi_of_driver);
535 }
536 module_exit(mpc52xx_psc_spi_exit);
537
538 MODULE_AUTHOR("Dragos Carp");
539 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
540 MODULE_LICENSE("GPL");