[POWERPC] mpc5200: normalize compatible property bindings
[linux-2.6.git] / drivers / spi / mpc52xx_psc_spi.c
1 /*
2  * MPC52xx SPC in SPI mode driver.
3  *
4  * Maintainer: Dragos Carp
5  *
6  * Copyright (C) 2006 TOPTICA Photonics AG.
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  */
13
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/interrupt.h>
18
19 #if defined(CONFIG_PPC_MERGE)
20 #include <asm/of_platform.h>
21 #else
22 #include <linux/platform_device.h>
23 #endif
24
25 #include <linux/workqueue.h>
26 #include <linux/completion.h>
27 #include <linux/io.h>
28 #include <linux/delay.h>
29 #include <linux/spi/spi.h>
30 #include <linux/fsl_devices.h>
31
32 #include <asm/mpc52xx.h>
33 #include <asm/mpc52xx_psc.h>
34
35 #define MCLK 20000000 /* PSC port MClk in hz */
36
37 struct mpc52xx_psc_spi {
38         /* fsl_spi_platform data */
39         void (*activate_cs)(u8, u8);
40         void (*deactivate_cs)(u8, u8);
41         u32 sysclk;
42
43         /* driver internal data */
44         struct mpc52xx_psc __iomem *psc;
45         unsigned int irq;
46         u8 bits_per_word;
47         u8 busy;
48
49         struct workqueue_struct *workqueue;
50         struct work_struct work;
51
52         struct list_head queue;
53         spinlock_t lock;
54
55         struct completion done;
56 };
57
58 /* controller state */
59 struct mpc52xx_psc_spi_cs {
60         int bits_per_word;
61         int speed_hz;
62 };
63
64 /* set clock freq, clock ramp, bits per work
65  * if t is NULL then reset the values to the default values
66  */
67 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
68                 struct spi_transfer *t)
69 {
70         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
71
72         cs->speed_hz = (t && t->speed_hz)
73                         ? t->speed_hz : spi->max_speed_hz;
74         cs->bits_per_word = (t && t->bits_per_word)
75                         ? t->bits_per_word : spi->bits_per_word;
76         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
77         return 0;
78 }
79
80 static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
81 {
82         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
83         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
84         struct mpc52xx_psc __iomem *psc = mps->psc;
85         u32 sicr;
86         u16 ccr;
87
88         sicr = in_be32(&psc->sicr);
89
90         /* Set clock phase and polarity */
91         if (spi->mode & SPI_CPHA)
92                 sicr |= 0x00001000;
93         else
94                 sicr &= ~0x00001000;
95         if (spi->mode & SPI_CPOL)
96                 sicr |= 0x00002000;
97         else
98                 sicr &= ~0x00002000;
99
100         if (spi->mode & SPI_LSB_FIRST)
101                 sicr |= 0x10000000;
102         else
103                 sicr &= ~0x10000000;
104         out_be32(&psc->sicr, sicr);
105
106         /* Set clock frequency and bits per word
107          * Because psc->ccr is defined as 16bit register instead of 32bit
108          * just set the lower byte of BitClkDiv
109          */
110         ccr = in_be16(&psc->ccr);
111         ccr &= 0xFF00;
112         if (cs->speed_hz)
113                 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
114         else /* by default SPI Clk 1MHz */
115                 ccr |= (MCLK / 1000000 - 1) & 0xFF;
116         out_be16(&psc->ccr, ccr);
117         mps->bits_per_word = cs->bits_per_word;
118
119         if (mps->activate_cs)
120                 mps->activate_cs(spi->chip_select,
121                                 (spi->mode & SPI_CS_HIGH) ? 1 : 0);
122 }
123
124 static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
125 {
126         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
127
128         if (mps->deactivate_cs)
129                 mps->deactivate_cs(spi->chip_select,
130                                 (spi->mode & SPI_CS_HIGH) ? 1 : 0);
131 }
132
133 #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
134 /* wake up when 80% fifo full */
135 #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
136
137 static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
138                                                 struct spi_transfer *t)
139 {
140         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
141         struct mpc52xx_psc __iomem *psc = mps->psc;
142         unsigned rb = 0;        /* number of bytes receieved */
143         unsigned sb = 0;        /* number of bytes sent */
144         unsigned char *rx_buf = (unsigned char *)t->rx_buf;
145         unsigned char *tx_buf = (unsigned char *)t->tx_buf;
146         unsigned rfalarm;
147         unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
148         unsigned recv_at_once;
149         unsigned bpw = mps->bits_per_word / 8;
150
151         if (!t->tx_buf && !t->rx_buf && t->len)
152                 return -EINVAL;
153
154         /* enable transmiter/receiver */
155         out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
156         while (rb < t->len) {
157                 if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
158                         rfalarm = MPC52xx_PSC_RFALARM;
159                 } else {
160                         send_at_once = t->len - sb;
161                         rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
162                 }
163
164                 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
165                 if (tx_buf) {
166                         for (; send_at_once; sb++, send_at_once--) {
167                                 /* set EOF flag */
168                                 if (mps->bits_per_word
169                                                 && (sb + 1) % bpw == 0)
170                                         out_8(&psc->ircr2, 0x01);
171                                 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
172                         }
173                 } else {
174                         for (; send_at_once; sb++, send_at_once--) {
175                                 /* set EOF flag */
176                                 if (mps->bits_per_word
177                                                 && ((sb + 1) % bpw) == 0)
178                                         out_8(&psc->ircr2, 0x01);
179                                 out_8(&psc->mpc52xx_psc_buffer_8, 0);
180                         }
181                 }
182
183
184                 /* enable interrupts and wait for wake up
185                  * if just one byte is expected the Rx FIFO genererates no
186                  * FFULL interrupt, so activate the RxRDY interrupt
187                  */
188                 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
189                 if (t->len - rb == 1) {
190                         out_8(&psc->mode, 0);
191                 } else {
192                         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
193                         out_be16(&psc->rfalarm, rfalarm);
194                 }
195                 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
196                 wait_for_completion(&mps->done);
197                 recv_at_once = in_be16(&psc->rfnum);
198                 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
199
200                 send_at_once = recv_at_once;
201                 if (rx_buf) {
202                         for (; recv_at_once; rb++, recv_at_once--)
203                                 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
204                 } else {
205                         for (; recv_at_once; rb++, recv_at_once--)
206                                 in_8(&psc->mpc52xx_psc_buffer_8);
207                 }
208         }
209         /* disable transmiter/receiver */
210         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
211
212         return 0;
213 }
214
215 static void mpc52xx_psc_spi_work(struct work_struct *work)
216 {
217         struct mpc52xx_psc_spi *mps =
218                 container_of(work, struct mpc52xx_psc_spi, work);
219
220         spin_lock_irq(&mps->lock);
221         mps->busy = 1;
222         while (!list_empty(&mps->queue)) {
223                 struct spi_message *m;
224                 struct spi_device *spi;
225                 struct spi_transfer *t = NULL;
226                 unsigned cs_change;
227                 int status;
228
229                 m = container_of(mps->queue.next, struct spi_message, queue);
230                 list_del_init(&m->queue);
231                 spin_unlock_irq(&mps->lock);
232
233                 spi = m->spi;
234                 cs_change = 1;
235                 status = 0;
236                 list_for_each_entry (t, &m->transfers, transfer_list) {
237                         if (t->bits_per_word || t->speed_hz) {
238                                 status = mpc52xx_psc_spi_transfer_setup(spi, t);
239                                 if (status < 0)
240                                         break;
241                         }
242
243                         if (cs_change)
244                                 mpc52xx_psc_spi_activate_cs(spi);
245                         cs_change = t->cs_change;
246
247                         status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
248                         if (status)
249                                 break;
250                         m->actual_length += t->len;
251
252                         if (t->delay_usecs)
253                                 udelay(t->delay_usecs);
254
255                         if (cs_change)
256                                 mpc52xx_psc_spi_deactivate_cs(spi);
257                 }
258
259                 m->status = status;
260                 m->complete(m->context);
261
262                 if (status || !cs_change)
263                         mpc52xx_psc_spi_deactivate_cs(spi);
264
265                 mpc52xx_psc_spi_transfer_setup(spi, NULL);
266
267                 spin_lock_irq(&mps->lock);
268         }
269         mps->busy = 0;
270         spin_unlock_irq(&mps->lock);
271 }
272
273 /* the spi->mode bits understood by this driver: */
274 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
275
276 static int mpc52xx_psc_spi_setup(struct spi_device *spi)
277 {
278         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
279         struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
280         unsigned long flags;
281
282         if (spi->bits_per_word%8)
283                 return -EINVAL;
284
285         if (spi->mode & ~MODEBITS) {
286                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
287                         spi->mode & ~MODEBITS);
288                 return -EINVAL;
289         }
290
291         if (!cs) {
292                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
293                 if (!cs)
294                         return -ENOMEM;
295                 spi->controller_state = cs;
296         }
297
298         cs->bits_per_word = spi->bits_per_word;
299         cs->speed_hz = spi->max_speed_hz;
300
301         spin_lock_irqsave(&mps->lock, flags);
302         if (!mps->busy)
303                 mpc52xx_psc_spi_deactivate_cs(spi);
304         spin_unlock_irqrestore(&mps->lock, flags);
305
306         return 0;
307 }
308
309 static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
310                 struct spi_message *m)
311 {
312         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
313         unsigned long flags;
314
315         m->actual_length = 0;
316         m->status = -EINPROGRESS;
317
318         spin_lock_irqsave(&mps->lock, flags);
319         list_add_tail(&m->queue, &mps->queue);
320         queue_work(mps->workqueue, &mps->work);
321         spin_unlock_irqrestore(&mps->lock, flags);
322
323         return 0;
324 }
325
326 static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
327 {
328         kfree(spi->controller_state);
329 }
330
331 static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
332 {
333         struct device_node *np;
334         struct mpc52xx_cdm __iomem *cdm;
335         struct mpc52xx_gpio __iomem *gpio;
336         struct mpc52xx_psc __iomem *psc = mps->psc;
337         u32 ul;
338         u32 mclken_div;
339         int ret = 0;
340
341 #if defined(CONFIG_PPC_MERGE)
342         np = of_find_compatible_node(NULL, NULL, "mpc5200-cdm");
343         cdm = of_iomap(np, 0);
344         of_node_put(np);
345         np = of_find_compatible_node(NULL, NULL, "mpc5200-gpio");
346         gpio = of_iomap(np, 0);
347         of_node_put(np);
348 #else
349         cdm = ioremap(MPC52xx_PA(MPC52xx_CDM_OFFSET), MPC52xx_CDM_SIZE);
350         gpio = ioremap(MPC52xx_PA(MPC52xx_GPIO_OFFSET), MPC52xx_GPIO_SIZE);
351 #endif
352         if (!cdm || !gpio) {
353                 printk(KERN_ERR "Error mapping CDM/GPIO\n");
354                 ret = -EFAULT;
355                 goto unmap_regs;
356         }
357
358         /* default sysclk is 512MHz */
359         mclken_div = 0x8000 |
360                 (((mps->sysclk ? mps->sysclk : 512000000) / MCLK) & 0x1FF);
361
362         switch (psc_id) {
363         case 1:
364                 ul = in_be32(&gpio->port_config);
365                 ul &= 0xFFFFFFF8;
366                 ul |= 0x00000006;
367                 out_be32(&gpio->port_config, ul);
368                 out_be16(&cdm->mclken_div_psc1, mclken_div);
369                 ul = in_be32(&cdm->clk_enables);
370                 ul |= 0x00000020;
371                 out_be32(&cdm->clk_enables, ul);
372                 break;
373         case 2:
374                 ul = in_be32(&gpio->port_config);
375                 ul &= 0xFFFFFF8F;
376                 ul |= 0x00000060;
377                 out_be32(&gpio->port_config, ul);
378                 out_be16(&cdm->mclken_div_psc2, mclken_div);
379                 ul = in_be32(&cdm->clk_enables);
380                 ul |= 0x00000040;
381                 out_be32(&cdm->clk_enables, ul);
382                 break;
383         case 3:
384                 ul = in_be32(&gpio->port_config);
385                 ul &= 0xFFFFF0FF;
386                 ul |= 0x00000600;
387                 out_be32(&gpio->port_config, ul);
388                 out_be16(&cdm->mclken_div_psc3, mclken_div);
389                 ul = in_be32(&cdm->clk_enables);
390                 ul |= 0x00000080;
391                 out_be32(&cdm->clk_enables, ul);
392                 break;
393         case 6:
394                 ul = in_be32(&gpio->port_config);
395                 ul &= 0xFF8FFFFF;
396                 ul |= 0x00700000;
397                 out_be32(&gpio->port_config, ul);
398                 out_be16(&cdm->mclken_div_psc6, mclken_div);
399                 ul = in_be32(&cdm->clk_enables);
400                 ul |= 0x00000010;
401                 out_be32(&cdm->clk_enables, ul);
402                 break;
403         default:
404                 ret = -EINVAL;
405                 goto unmap_regs;
406         }
407
408         /* Reset the PSC into a known state */
409         out_8(&psc->command, MPC52xx_PSC_RST_RX);
410         out_8(&psc->command, MPC52xx_PSC_RST_TX);
411         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
412
413         /* Disable interrupts, interrupts are based on alarm level */
414         out_be16(&psc->mpc52xx_psc_imr, 0);
415         out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
416         out_8(&psc->rfcntl, 0);
417         out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
418
419         /* Configure 8bit codec mode as a SPI master and use EOF flags */
420         /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
421         out_be32(&psc->sicr, 0x0180C800);
422         out_be16(&psc->ccr, 0x070F); /* by default SPI Clk 1MHz */
423
424         /* Set 2ms DTL delay */
425         out_8(&psc->ctur, 0x00);
426         out_8(&psc->ctlr, 0x84);
427
428         mps->bits_per_word = 8;
429
430 unmap_regs:
431         if (cdm)
432                 iounmap(cdm);
433         if (gpio)
434                 iounmap(gpio);
435
436         return ret;
437 }
438
439 static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
440 {
441         struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
442         struct mpc52xx_psc __iomem *psc = mps->psc;
443
444         /* disable interrupt and wake up the work queue */
445         if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
446                 out_be16(&psc->mpc52xx_psc_imr, 0);
447                 complete(&mps->done);
448                 return IRQ_HANDLED;
449         }
450         return IRQ_NONE;
451 }
452
453 /* bus_num is used only for the case dev->platform_data == NULL */
454 static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
455                                 u32 size, unsigned int irq, s16 bus_num)
456 {
457         struct fsl_spi_platform_data *pdata = dev->platform_data;
458         struct mpc52xx_psc_spi *mps;
459         struct spi_master *master;
460         int ret;
461
462         master = spi_alloc_master(dev, sizeof *mps);
463         if (master == NULL)
464                 return -ENOMEM;
465
466         dev_set_drvdata(dev, master);
467         mps = spi_master_get_devdata(master);
468
469         mps->irq = irq;
470         if (pdata == NULL) {
471                 dev_warn(dev, "probe called without platform data, no "
472                                 "(de)activate_cs function will be called\n");
473                 mps->activate_cs = NULL;
474                 mps->deactivate_cs = NULL;
475                 mps->sysclk = 0;
476                 master->bus_num = bus_num;
477                 master->num_chipselect = 255;
478         } else {
479                 mps->activate_cs = pdata->activate_cs;
480                 mps->deactivate_cs = pdata->deactivate_cs;
481                 mps->sysclk = pdata->sysclk;
482                 master->bus_num = pdata->bus_num;
483                 master->num_chipselect = pdata->max_chipselect;
484         }
485         master->setup = mpc52xx_psc_spi_setup;
486         master->transfer = mpc52xx_psc_spi_transfer;
487         master->cleanup = mpc52xx_psc_spi_cleanup;
488
489         mps->psc = ioremap(regaddr, size);
490         if (!mps->psc) {
491                 dev_err(dev, "could not ioremap I/O port range\n");
492                 ret = -EFAULT;
493                 goto free_master;
494         }
495
496         ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
497                                 mps);
498         if (ret)
499                 goto free_master;
500
501         ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
502         if (ret < 0)
503                 goto free_irq;
504
505         spin_lock_init(&mps->lock);
506         init_completion(&mps->done);
507         INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
508         INIT_LIST_HEAD(&mps->queue);
509
510         mps->workqueue = create_singlethread_workqueue(
511                 master->dev.parent->bus_id);
512         if (mps->workqueue == NULL) {
513                 ret = -EBUSY;
514                 goto free_irq;
515         }
516
517         ret = spi_register_master(master);
518         if (ret < 0)
519                 goto unreg_master;
520
521         return ret;
522
523 unreg_master:
524         destroy_workqueue(mps->workqueue);
525 free_irq:
526         free_irq(mps->irq, mps);
527 free_master:
528         if (mps->psc)
529                 iounmap(mps->psc);
530         spi_master_put(master);
531
532         return ret;
533 }
534
535 static int __exit mpc52xx_psc_spi_do_remove(struct device *dev)
536 {
537         struct spi_master *master = dev_get_drvdata(dev);
538         struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
539
540         flush_workqueue(mps->workqueue);
541         destroy_workqueue(mps->workqueue);
542         spi_unregister_master(master);
543         free_irq(mps->irq, mps);
544         if (mps->psc)
545                 iounmap(mps->psc);
546
547         return 0;
548 }
549
550 #if !defined(CONFIG_PPC_MERGE)
551 static int __init mpc52xx_psc_spi_probe(struct platform_device *dev)
552 {
553         switch(dev->id) {
554         case 1:
555         case 2:
556         case 3:
557         case 6:
558                 return mpc52xx_psc_spi_do_probe(&dev->dev,
559                         MPC52xx_PA(MPC52xx_PSCx_OFFSET(dev->id)),
560                         MPC52xx_PSC_SIZE, platform_get_irq(dev, 0), dev->id);
561         default:
562                 return -EINVAL;
563         }
564 }
565
566 static int __exit mpc52xx_psc_spi_remove(struct platform_device *dev)
567 {
568         return mpc52xx_psc_spi_do_remove(&dev->dev);
569 }
570
571 static struct platform_driver mpc52xx_psc_spi_platform_driver = {
572         .remove = __exit_p(mpc52xx_psc_spi_remove),
573         .driver = {
574                 .name = "mpc52xx-psc-spi",
575                 .owner = THIS_MODULE,
576         },
577 };
578
579 static int __init mpc52xx_psc_spi_init(void)
580 {
581         return platform_driver_probe(&mpc52xx_psc_spi_platform_driver,
582                         mpc52xx_psc_spi_probe);
583 }
584 module_init(mpc52xx_psc_spi_init);
585
586 static void __exit mpc52xx_psc_spi_exit(void)
587 {
588         platform_driver_unregister(&mpc52xx_psc_spi_platform_driver);
589 }
590 module_exit(mpc52xx_psc_spi_exit);
591
592 #else   /* defined(CONFIG_PPC_MERGE) */
593
594 static int __init mpc52xx_psc_spi_of_probe(struct of_device *op,
595         const struct of_device_id *match)
596 {
597         const u32 *regaddr_p;
598         u64 regaddr64, size64;
599         s16 id = -1;
600
601         regaddr_p = of_get_address(op->node, 0, &size64, NULL);
602         if (!regaddr_p) {
603                 printk(KERN_ERR "Invalid PSC address\n");
604                 return -EINVAL;
605         }
606         regaddr64 = of_translate_address(op->node, regaddr_p);
607
608         /* get PSC id (1..6, used by port_config) */
609         if (op->dev.platform_data == NULL) {
610                 const u32 *psc_nump;
611
612                 psc_nump = of_get_property(op->node, "cell-index", NULL);
613                 if (!psc_nump || *psc_nump > 5) {
614                         printk(KERN_ERR "mpc52xx_psc_spi: Device node %s has invalid "
615                                         "cell-index property\n", op->node->full_name);
616                         return -EINVAL;
617                 }
618                 id = *psc_nump + 1;
619         }
620
621         return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
622                                         irq_of_parse_and_map(op->node, 0), id);
623 }
624
625 static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op)
626 {
627         return mpc52xx_psc_spi_do_remove(&op->dev);
628 }
629
630 static struct of_device_id mpc52xx_psc_spi_of_match[] = {
631         { .compatible = "fsl,mpc5200-psc-spi", },
632         { .compatible = "mpc5200-psc-spi", }, /* old */
633         {}
634 };
635
636 MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
637
638 static struct of_platform_driver mpc52xx_psc_spi_of_driver = {
639         .owner = THIS_MODULE,
640         .name = "mpc52xx-psc-spi",
641         .match_table = mpc52xx_psc_spi_of_match,
642         .probe = mpc52xx_psc_spi_of_probe,
643         .remove = __exit_p(mpc52xx_psc_spi_of_remove),
644         .driver = {
645                 .name = "mpc52xx-psc-spi",
646                 .owner = THIS_MODULE,
647         },
648 };
649
650 static int __init mpc52xx_psc_spi_init(void)
651 {
652         return of_register_platform_driver(&mpc52xx_psc_spi_of_driver);
653 }
654 module_init(mpc52xx_psc_spi_init);
655
656 static void __exit mpc52xx_psc_spi_exit(void)
657 {
658         of_unregister_platform_driver(&mpc52xx_psc_spi_of_driver);
659 }
660 module_exit(mpc52xx_psc_spi_exit);
661
662 #endif  /* defined(CONFIG_PPC_MERGE) */
663
664 MODULE_AUTHOR("Dragos Carp");
665 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
666 MODULE_LICENSE("GPL");