spi: davinci: do not store DMA channel information per chip select
[linux-2.6.git] / drivers / spi / davinci_spi.c
1 /*
2  * Copyright (C) 2009 Texas Instruments.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
17  */
18
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/err.h>
26 #include <linux/clk.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/slab.h>
31
32 #include <mach/spi.h>
33 #include <mach/edma.h>
34
35 #define SPI_NO_RESOURCE         ((resource_size_t)-1)
36
37 #define SPI_MAX_CHIPSELECT      2
38
39 #define CS_DEFAULT      0xFF
40
41 #define SPI_BUFSIZ      (SMP_CACHE_BYTES + 1)
42
43 #define SPIFMT_PHASE_MASK       BIT(16)
44 #define SPIFMT_POLARITY_MASK    BIT(17)
45 #define SPIFMT_DISTIMER_MASK    BIT(18)
46 #define SPIFMT_SHIFTDIR_MASK    BIT(20)
47 #define SPIFMT_WAITENA_MASK     BIT(21)
48 #define SPIFMT_PARITYENA_MASK   BIT(22)
49 #define SPIFMT_ODD_PARITY_MASK  BIT(23)
50 #define SPIFMT_WDELAY_MASK      0x3f000000u
51 #define SPIFMT_WDELAY_SHIFT     24
52 #define SPIFMT_PRESCALE_SHIFT   8
53
54
55 /* SPIPC0 */
56 #define SPIPC0_DIFUN_MASK       BIT(11)         /* MISO */
57 #define SPIPC0_DOFUN_MASK       BIT(10)         /* MOSI */
58 #define SPIPC0_CLKFUN_MASK      BIT(9)          /* CLK */
59 #define SPIPC0_SPIENA_MASK      BIT(8)          /* nREADY */
60
61 #define SPIINT_MASKALL          0x0101035F
62 #define SPIINT_MASKINT          0x0000015F
63 #define SPI_INTLVL_1            0x000001FF
64 #define SPI_INTLVL_0            0x00000000
65
66 /* SPIDAT1 (upper 16 bit defines) */
67 #define SPIDAT1_CSHOLD_MASK     BIT(12)
68
69 /* SPIGCR1 */
70 #define SPIGCR1_CLKMOD_MASK     BIT(1)
71 #define SPIGCR1_MASTER_MASK     BIT(0)
72 #define SPIGCR1_LOOPBACK_MASK   BIT(16)
73 #define SPIGCR1_SPIENA_MASK     BIT(24)
74
75 /* SPIBUF */
76 #define SPIBUF_TXFULL_MASK      BIT(29)
77 #define SPIBUF_RXEMPTY_MASK     BIT(31)
78
79 /* SPIDELAY */
80 #define SPIDELAY_C2TDELAY_SHIFT 24
81 #define SPIDELAY_C2TDELAY_MASK  (0xFF << SPIDELAY_C2TDELAY_SHIFT)
82 #define SPIDELAY_T2CDELAY_SHIFT 16
83 #define SPIDELAY_T2CDELAY_MASK  (0xFF << SPIDELAY_T2CDELAY_SHIFT)
84 #define SPIDELAY_T2EDELAY_SHIFT 8
85 #define SPIDELAY_T2EDELAY_MASK  (0xFF << SPIDELAY_T2EDELAY_SHIFT)
86 #define SPIDELAY_C2EDELAY_SHIFT 0
87 #define SPIDELAY_C2EDELAY_MASK  0xFF
88
89 /* Error Masks */
90 #define SPIFLG_DLEN_ERR_MASK            BIT(0)
91 #define SPIFLG_TIMEOUT_MASK             BIT(1)
92 #define SPIFLG_PARERR_MASK              BIT(2)
93 #define SPIFLG_DESYNC_MASK              BIT(3)
94 #define SPIFLG_BITERR_MASK              BIT(4)
95 #define SPIFLG_OVRRUN_MASK              BIT(6)
96 #define SPIFLG_BUF_INIT_ACTIVE_MASK     BIT(24)
97 #define SPIFLG_ERROR_MASK               (SPIFLG_DLEN_ERR_MASK \
98                                 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
99                                 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
100                                 | SPIFLG_OVRRUN_MASK)
101
102 #define SPIINT_DMA_REQ_EN       BIT(16)
103
104 /* SPI Controller registers */
105 #define SPIGCR0         0x00
106 #define SPIGCR1         0x04
107 #define SPIINT          0x08
108 #define SPILVL          0x0c
109 #define SPIFLG          0x10
110 #define SPIPC0          0x14
111 #define SPIDAT1         0x3c
112 #define SPIBUF          0x40
113 #define SPIDELAY        0x48
114 #define SPIDEF          0x4c
115 #define SPIFMT0         0x50
116
117 /* We have 2 DMA channels per CS, one for RX and one for TX */
118 struct davinci_spi_dma {
119         int                     dma_tx_channel;
120         int                     dma_rx_channel;
121         int                     dma_tx_sync_dev;
122         int                     dma_rx_sync_dev;
123         enum dma_event_q        eventq;
124
125         struct completion       dma_tx_completion;
126         struct completion       dma_rx_completion;
127 };
128
129 /* SPI Controller driver's private data. */
130 struct davinci_spi {
131         struct spi_bitbang      bitbang;
132         struct clk              *clk;
133
134         u8                      version;
135         resource_size_t         pbase;
136         void __iomem            *base;
137         size_t                  region_size;
138         u32                     irq;
139         struct completion       done;
140
141         const void              *tx;
142         void                    *rx;
143         u8                      *tmp_buf;
144         int                     rcount;
145         int                     wcount;
146         struct davinci_spi_dma  dma_channels;
147         struct davinci_spi_platform_data *pdata;
148
149         void                    (*get_rx)(u32 rx_data, struct davinci_spi *);
150         u32                     (*get_tx)(struct davinci_spi *);
151
152         u8                      bytes_per_word[SPI_MAX_CHIPSELECT];
153 };
154
155 static struct davinci_spi_config davinci_spi_default_cfg;
156
157 static unsigned use_dma;
158
159 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
160 {
161         if (davinci_spi->rx) {
162                 u8 *rx = davinci_spi->rx;
163                 *rx++ = (u8)data;
164                 davinci_spi->rx = rx;
165         }
166 }
167
168 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
169 {
170         if (davinci_spi->rx) {
171                 u16 *rx = davinci_spi->rx;
172                 *rx++ = (u16)data;
173                 davinci_spi->rx = rx;
174         }
175 }
176
177 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
178 {
179         u32 data = 0;
180         if (davinci_spi->tx) {
181                 const u8 *tx = davinci_spi->tx;
182                 data = *tx++;
183                 davinci_spi->tx = tx;
184         }
185         return data;
186 }
187
188 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
189 {
190         u32 data = 0;
191         if (davinci_spi->tx) {
192                 const u16 *tx = davinci_spi->tx;
193                 data = *tx++;
194                 davinci_spi->tx = tx;
195         }
196         return data;
197 }
198
199 static inline void set_io_bits(void __iomem *addr, u32 bits)
200 {
201         u32 v = ioread32(addr);
202
203         v |= bits;
204         iowrite32(v, addr);
205 }
206
207 static inline void clear_io_bits(void __iomem *addr, u32 bits)
208 {
209         u32 v = ioread32(addr);
210
211         v &= ~bits;
212         iowrite32(v, addr);
213 }
214
215 static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
216 {
217         struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
218
219         if (enable)
220                 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
221         else
222                 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
223 }
224
225 /*
226  * Interface to control the chip select signal
227  */
228 static void davinci_spi_chipselect(struct spi_device *spi, int value)
229 {
230         struct davinci_spi *davinci_spi;
231         struct davinci_spi_platform_data *pdata;
232         u8 chip_sel = spi->chip_select;
233         u16 spidat1_cfg = CS_DEFAULT;
234         bool gpio_chipsel = false;
235
236         davinci_spi = spi_master_get_devdata(spi->master);
237         pdata = davinci_spi->pdata;
238
239         if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
240                                 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
241                 gpio_chipsel = true;
242
243         /*
244          * Board specific chip select logic decides the polarity and cs
245          * line for the controller
246          */
247         if (gpio_chipsel) {
248                 if (value == BITBANG_CS_ACTIVE)
249                         gpio_set_value(pdata->chip_sel[chip_sel], 0);
250                 else
251                         gpio_set_value(pdata->chip_sel[chip_sel], 1);
252         } else {
253                 if (value == BITBANG_CS_ACTIVE) {
254                         spidat1_cfg |= SPIDAT1_CSHOLD_MASK;
255                         spidat1_cfg &= ~(0x1 << chip_sel);
256                 }
257
258                 iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2);
259         }
260 }
261
262 /**
263  * davinci_spi_get_prescale - Calculates the correct prescale value
264  * @maxspeed_hz: the maximum rate the SPI clock can run at
265  *
266  * This function calculates the prescale value that generates a clock rate
267  * less than or equal to the specified maximum.
268  *
269  * Returns: calculated prescale - 1 for easy programming into SPI registers
270  * or negative error number if valid prescalar cannot be updated.
271  */
272 static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi,
273                                                         u32 max_speed_hz)
274 {
275         int ret;
276
277         ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz);
278
279         if (ret < 3 || ret > 256)
280                 return -EINVAL;
281
282         return ret - 1;
283 }
284
285 /**
286  * davinci_spi_setup_transfer - This functions will determine transfer method
287  * @spi: spi device on which data transfer to be done
288  * @t: spi transfer in which transfer info is filled
289  *
290  * This function determines data transfer method (8/16/32 bit transfer).
291  * It will also set the SPI Clock Control register according to
292  * SPI slave device freq.
293  */
294 static int davinci_spi_setup_transfer(struct spi_device *spi,
295                 struct spi_transfer *t)
296 {
297
298         struct davinci_spi *davinci_spi;
299         struct davinci_spi_config *spicfg;
300         u8 bits_per_word = 0;
301         u32 hz = 0, spifmt = 0, prescale = 0;
302
303         davinci_spi = spi_master_get_devdata(spi->master);
304         spicfg = (struct davinci_spi_config *)spi->controller_data;
305         if (!spicfg)
306                 spicfg = &davinci_spi_default_cfg;
307
308         if (t) {
309                 bits_per_word = t->bits_per_word;
310                 hz = t->speed_hz;
311         }
312
313         /* if bits_per_word is not set then set it default */
314         if (!bits_per_word)
315                 bits_per_word = spi->bits_per_word;
316
317         /*
318          * Assign function pointer to appropriate transfer method
319          * 8bit, 16bit or 32bit transfer
320          */
321         if (bits_per_word <= 8 && bits_per_word >= 2) {
322                 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
323                 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
324                 davinci_spi->bytes_per_word[spi->chip_select] = 1;
325         } else if (bits_per_word <= 16 && bits_per_word >= 2) {
326                 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
327                 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
328                 davinci_spi->bytes_per_word[spi->chip_select] = 2;
329         } else
330                 return -EINVAL;
331
332         if (!hz)
333                 hz = spi->max_speed_hz;
334
335         /* Set up SPIFMTn register, unique to this chipselect. */
336
337         prescale = davinci_spi_get_prescale(davinci_spi, hz);
338         if (prescale < 0)
339                 return prescale;
340
341         spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
342
343         if (spi->mode & SPI_LSB_FIRST)
344                 spifmt |= SPIFMT_SHIFTDIR_MASK;
345
346         if (spi->mode & SPI_CPOL)
347                 spifmt |= SPIFMT_POLARITY_MASK;
348
349         if (!(spi->mode & SPI_CPHA))
350                 spifmt |= SPIFMT_PHASE_MASK;
351
352         /*
353          * Version 1 hardware supports two basic SPI modes:
354          *  - Standard SPI mode uses 4 pins, with chipselect
355          *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
356          *      (distinct from SPI_3WIRE, with just one data wire;
357          *      or similar variants without MOSI or without MISO)
358          *
359          * Version 2 hardware supports an optional handshaking signal,
360          * so it can support two more modes:
361          *  - 5 pin SPI variant is standard SPI plus SPI_READY
362          *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
363          */
364
365         if (davinci_spi->version == SPI_VERSION_2) {
366
367                 u32 delay = 0;
368
369                 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
370                                                         & SPIFMT_WDELAY_MASK);
371
372                 if (spicfg->odd_parity)
373                         spifmt |= SPIFMT_ODD_PARITY_MASK;
374
375                 if (spicfg->parity_enable)
376                         spifmt |= SPIFMT_PARITYENA_MASK;
377
378                 if (spicfg->timer_disable) {
379                         spifmt |= SPIFMT_DISTIMER_MASK;
380                 } else {
381                         delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
382                                                 & SPIDELAY_C2TDELAY_MASK;
383                         delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
384                                                 & SPIDELAY_T2CDELAY_MASK;
385                 }
386
387                 if (spi->mode & SPI_READY) {
388                         spifmt |= SPIFMT_WAITENA_MASK;
389                         delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
390                                                 & SPIDELAY_T2EDELAY_MASK;
391                         delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
392                                                 & SPIDELAY_C2EDELAY_MASK;
393                 }
394
395                 iowrite32(delay, davinci_spi->base + SPIDELAY);
396         }
397
398         iowrite32(spifmt, davinci_spi->base + SPIFMT0);
399
400         return 0;
401 }
402
403 static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
404 {
405         struct spi_device *spi = (struct spi_device *)data;
406         struct davinci_spi *davinci_spi;
407         struct davinci_spi_dma *davinci_spi_dma;
408
409         davinci_spi = spi_master_get_devdata(spi->master);
410         davinci_spi_dma = &davinci_spi->dma_channels;
411
412         if (ch_status == DMA_COMPLETE)
413                 edma_stop(davinci_spi_dma->dma_rx_channel);
414         else
415                 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
416
417         complete(&davinci_spi_dma->dma_rx_completion);
418         /* We must disable the DMA RX request */
419         davinci_spi_set_dma_req(spi, 0);
420 }
421
422 static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
423 {
424         struct spi_device *spi = (struct spi_device *)data;
425         struct davinci_spi *davinci_spi;
426         struct davinci_spi_dma *davinci_spi_dma;
427
428         davinci_spi = spi_master_get_devdata(spi->master);
429         davinci_spi_dma = &davinci_spi->dma_channels;
430
431         if (ch_status == DMA_COMPLETE)
432                 edma_stop(davinci_spi_dma->dma_tx_channel);
433         else
434                 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
435
436         complete(&davinci_spi_dma->dma_tx_completion);
437         /* We must disable the DMA TX request */
438         davinci_spi_set_dma_req(spi, 0);
439 }
440
441 static int davinci_spi_request_dma(struct spi_device *spi)
442 {
443         struct davinci_spi *davinci_spi;
444         struct davinci_spi_dma *davinci_spi_dma;
445         struct device *sdev;
446         int r;
447
448         davinci_spi = spi_master_get_devdata(spi->master);
449         davinci_spi_dma = &davinci_spi->dma_channels;
450         sdev = davinci_spi->bitbang.master->dev.parent;
451
452         r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
453                                 davinci_spi_dma_rx_callback, spi,
454                                 davinci_spi_dma->eventq);
455         if (r < 0) {
456                 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
457                 return -EAGAIN;
458         }
459         davinci_spi_dma->dma_rx_channel = r;
460         r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
461                                 davinci_spi_dma_tx_callback, spi,
462                                 davinci_spi_dma->eventq);
463         if (r < 0) {
464                 edma_free_channel(davinci_spi_dma->dma_rx_channel);
465                 davinci_spi_dma->dma_rx_channel = -1;
466                 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
467                 return -EAGAIN;
468         }
469         davinci_spi_dma->dma_tx_channel = r;
470
471         return 0;
472 }
473
474 /**
475  * davinci_spi_setup - This functions will set default transfer method
476  * @spi: spi device on which data transfer to be done
477  *
478  * This functions sets the default transfer method.
479  */
480 static int davinci_spi_setup(struct spi_device *spi)
481 {
482         int retval = 0;
483         struct davinci_spi *davinci_spi;
484         struct davinci_spi_dma *davinci_spi_dma;
485         struct davinci_spi_platform_data *pdata;
486
487         davinci_spi = spi_master_get_devdata(spi->master);
488         pdata = davinci_spi->pdata;
489
490         /* if bits per word length is zero then set it default 8 */
491         if (!spi->bits_per_word)
492                 spi->bits_per_word = 8;
493
494         if (!(spi->mode & SPI_NO_CS)) {
495                 if ((pdata->chip_sel == NULL) ||
496                     (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
497                         set_io_bits(davinci_spi->base + SPIPC0,
498                                         1 << spi->chip_select);
499
500         }
501
502         if (spi->mode & SPI_READY)
503                 set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK);
504
505         if (spi->mode & SPI_LOOP)
506                 set_io_bits(davinci_spi->base + SPIGCR1,
507                                 SPIGCR1_LOOPBACK_MASK);
508         else
509                 clear_io_bits(davinci_spi->base + SPIGCR1,
510                                 SPIGCR1_LOOPBACK_MASK);
511
512         if (use_dma) {
513                 davinci_spi_dma = &davinci_spi->dma_channels;
514
515                 if ((davinci_spi_dma->dma_rx_channel == -1) ||
516                     (davinci_spi_dma->dma_tx_channel == -1))
517                         retval = davinci_spi_request_dma(spi);
518         }
519
520         return retval;
521 }
522
523 static void davinci_spi_cleanup(struct spi_device *spi)
524 {
525         if (use_dma) {
526                 struct davinci_spi *davinci_spi =
527                                         spi_master_get_devdata(spi->master);
528                 struct davinci_spi_dma *davinci_spi_dma =
529                                         &davinci_spi->dma_channels;
530
531                 if ((davinci_spi_dma->dma_rx_channel != -1)
532                                 && (davinci_spi_dma->dma_tx_channel != -1)) {
533                         edma_free_channel(davinci_spi_dma->dma_tx_channel);
534                         edma_free_channel(davinci_spi_dma->dma_rx_channel);
535                 }
536         }
537 }
538
539 static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
540                                    int int_status)
541 {
542         struct device *sdev = davinci_spi->bitbang.master->dev.parent;
543
544         if (int_status & SPIFLG_TIMEOUT_MASK) {
545                 dev_dbg(sdev, "SPI Time-out Error\n");
546                 return -ETIMEDOUT;
547         }
548         if (int_status & SPIFLG_DESYNC_MASK) {
549                 dev_dbg(sdev, "SPI Desynchronization Error\n");
550                 return -EIO;
551         }
552         if (int_status & SPIFLG_BITERR_MASK) {
553                 dev_dbg(sdev, "SPI Bit error\n");
554                 return -EIO;
555         }
556
557         if (davinci_spi->version == SPI_VERSION_2) {
558                 if (int_status & SPIFLG_DLEN_ERR_MASK) {
559                         dev_dbg(sdev, "SPI Data Length Error\n");
560                         return -EIO;
561                 }
562                 if (int_status & SPIFLG_PARERR_MASK) {
563                         dev_dbg(sdev, "SPI Parity Error\n");
564                         return -EIO;
565                 }
566                 if (int_status & SPIFLG_OVRRUN_MASK) {
567                         dev_dbg(sdev, "SPI Data Overrun error\n");
568                         return -EIO;
569                 }
570                 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
571                         dev_dbg(sdev, "SPI Buffer Init Active\n");
572                         return -EBUSY;
573                 }
574         }
575
576         return 0;
577 }
578
579 /**
580  * davinci_spi_process_events - check for and handle any SPI controller events
581  * @davinci_spi: the controller data
582  *
583  * This function will check the SPIFLG register and handle any events that are
584  * detected there
585  */
586 static int davinci_spi_process_events(struct davinci_spi *davinci_spi)
587 {
588         u32 buf, status, errors = 0, data1_reg_val;
589
590         buf = ioread32(davinci_spi->base + SPIBUF);
591
592         if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
593                 davinci_spi->get_rx(buf & 0xFFFF, davinci_spi);
594                 davinci_spi->rcount--;
595         }
596
597         status = ioread32(davinci_spi->base + SPIFLG);
598
599         if (unlikely(status & SPIFLG_ERROR_MASK)) {
600                 errors = status & SPIFLG_ERROR_MASK;
601                 goto out;
602         }
603
604         if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
605                 data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
606                 davinci_spi->wcount--;
607                 data1_reg_val &= ~0xFFFF;
608                 data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi);
609                 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
610         }
611
612 out:
613         return errors;
614 }
615
616 /**
617  * davinci_spi_bufs - functions which will handle transfer data
618  * @spi: spi device on which data transfer to be done
619  * @t: spi transfer in which transfer info is filled
620  *
621  * This function will put data to be transferred into data register
622  * of SPI controller and then wait until the completion will be marked
623  * by the IRQ Handler.
624  */
625 static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
626 {
627         struct davinci_spi *davinci_spi;
628         int ret;
629         u32 tx_data, data1_reg_val;
630         u32 errors = 0;
631         struct davinci_spi_config *spicfg;
632         struct davinci_spi_platform_data *pdata;
633
634         davinci_spi = spi_master_get_devdata(spi->master);
635         pdata = davinci_spi->pdata;
636         spicfg = (struct davinci_spi_config *)spi->controller_data;
637         if (!spicfg)
638                 spicfg = &davinci_spi_default_cfg;
639
640         davinci_spi->tx = t->tx_buf;
641         davinci_spi->rx = t->rx_buf;
642         davinci_spi->wcount = t->len /
643                                 davinci_spi->bytes_per_word[spi->chip_select];
644         davinci_spi->rcount = davinci_spi->wcount;
645
646         data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
647
648         /* Enable SPI */
649         set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
650
651         if (spicfg->io_type == SPI_IO_TYPE_INTR) {
652                 set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
653                 INIT_COMPLETION(davinci_spi->done);
654         }
655
656         /* start the transfer */
657         davinci_spi->wcount--;
658         tx_data = davinci_spi->get_tx(davinci_spi);
659         data1_reg_val &= 0xFFFF0000;
660         data1_reg_val |= tx_data & 0xFFFF;
661         iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
662
663         /* Wait for the transfer to complete */
664         if (spicfg->io_type == SPI_IO_TYPE_INTR) {
665                 wait_for_completion_interruptible(&(davinci_spi->done));
666         } else {
667                 while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) {
668                         errors = davinci_spi_process_events(davinci_spi);
669                         if (errors)
670                                 break;
671                         cpu_relax();
672                 }
673         }
674
675         clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
676
677         /*
678          * Check for bit error, desync error,parity error,timeout error and
679          * receive overflow errors
680          */
681         if (errors) {
682                 ret = davinci_spi_check_error(davinci_spi, errors);
683                 WARN(!ret, "%s: error reported but no error found!\n",
684                                                         dev_name(&spi->dev));
685                 return ret;
686         }
687
688         return t->len;
689 }
690
691 /**
692  * davinci_spi_irq - Interrupt handler for SPI Master Controller
693  * @irq: IRQ number for this SPI Master
694  * @context_data: structure for SPI Master controller davinci_spi
695  *
696  * ISR will determine that interrupt arrives either for READ or WRITE command.
697  * According to command it will do the appropriate action. It will check
698  * transfer length and if it is not zero then dispatch transfer command again.
699  * If transfer length is zero then it will indicate the COMPLETION so that
700  * davinci_spi_bufs function can go ahead.
701  */
702 static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
703 {
704         struct davinci_spi *davinci_spi = context_data;
705         int status;
706
707         status = davinci_spi_process_events(davinci_spi);
708         if (unlikely(status != 0))
709                 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT);
710
711         if ((!davinci_spi->rcount && !davinci_spi->wcount) || status)
712                 complete(&davinci_spi->done);
713
714         return IRQ_HANDLED;
715 }
716
717 static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
718 {
719         struct davinci_spi *davinci_spi;
720         int int_status = 0;
721         int count, temp_count;
722         u32 data1_reg_val;
723         struct davinci_spi_dma *davinci_spi_dma;
724         int data_type, ret;
725         unsigned long tx_reg, rx_reg;
726         struct device *sdev;
727
728         davinci_spi = spi_master_get_devdata(spi->master);
729         sdev = davinci_spi->bitbang.master->dev.parent;
730
731         davinci_spi_dma = &davinci_spi->dma_channels;
732
733         tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
734         rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
735
736         davinci_spi->tx = t->tx_buf;
737         davinci_spi->rx = t->rx_buf;
738
739         /* convert len to words based on bits_per_word */
740         data_type = davinci_spi->bytes_per_word[spi->chip_select];
741
742         data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
743
744         init_completion(&davinci_spi_dma->dma_rx_completion);
745         init_completion(&davinci_spi_dma->dma_tx_completion);
746
747         count = t->len / data_type;     /* the number of elements */
748
749         /* disable all interrupts for dma transfers */
750         clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
751         /* Enable SPI */
752         set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
753
754         if (t->tx_buf) {
755                 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
756                                 DMA_TO_DEVICE);
757                 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
758                         dev_dbg(sdev, "Unable to DMA map a %d bytes"
759                                 " TX buffer\n", count);
760                         return -ENOMEM;
761                 }
762                 temp_count = count;
763         } else {
764                 /* We need TX clocking for RX transaction */
765                 t->tx_dma = dma_map_single(&spi->dev,
766                                 (void *)davinci_spi->tmp_buf, count + 1,
767                                 DMA_TO_DEVICE);
768                 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
769                         dev_dbg(sdev, "Unable to DMA map a %d bytes"
770                                 " TX tmp buffer\n", count);
771                         return -ENOMEM;
772                 }
773                 temp_count = count + 1;
774         }
775
776         edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
777                                         data_type, temp_count, 1, 0, ASYNC);
778         edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
779         edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
780         edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
781         edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
782
783         if (t->rx_buf) {
784                 /* initiate transaction */
785                 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
786
787                 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
788                                 DMA_FROM_DEVICE);
789                 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
790                         dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
791                                         count);
792                         if (t->tx_buf != NULL)
793                                 dma_unmap_single(NULL, t->tx_dma,
794                                                  count, DMA_TO_DEVICE);
795                         return -ENOMEM;
796                 }
797                 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
798                                 data_type, count, 1, 0, ASYNC);
799                 edma_set_src(davinci_spi_dma->dma_rx_channel,
800                                 rx_reg, INCR, W8BIT);
801                 edma_set_dest(davinci_spi_dma->dma_rx_channel,
802                                 t->rx_dma, INCR, W8BIT);
803                 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
804                 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
805                                 data_type, 0);
806         }
807
808         if ((t->tx_buf) || (t->rx_buf))
809                 edma_start(davinci_spi_dma->dma_tx_channel);
810
811         if (t->rx_buf)
812                 edma_start(davinci_spi_dma->dma_rx_channel);
813
814         if ((t->rx_buf) || (t->tx_buf))
815                 davinci_spi_set_dma_req(spi, 1);
816
817         if (t->tx_buf)
818                 wait_for_completion_interruptible(
819                                 &davinci_spi_dma->dma_tx_completion);
820
821         if (t->rx_buf)
822                 wait_for_completion_interruptible(
823                                 &davinci_spi_dma->dma_rx_completion);
824
825         dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
826
827         if (t->rx_buf)
828                 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
829
830         /*
831          * Check for bit error, desync error,parity error,timeout error and
832          * receive overflow errors
833          */
834         int_status = ioread32(davinci_spi->base + SPIFLG);
835
836         ret = davinci_spi_check_error(davinci_spi, int_status);
837         if (ret != 0)
838                 return ret;
839
840         return t->len;
841 }
842
843 /**
844  * davinci_spi_probe - probe function for SPI Master Controller
845  * @pdev: platform_device structure which contains plateform specific data
846  */
847 static int davinci_spi_probe(struct platform_device *pdev)
848 {
849         struct spi_master *master;
850         struct davinci_spi *davinci_spi;
851         struct davinci_spi_platform_data *pdata;
852         struct resource *r, *mem;
853         resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
854         resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
855         resource_size_t dma_eventq = SPI_NO_RESOURCE;
856         int i = 0, ret = 0;
857         u32 spipc0;
858
859         pdata = pdev->dev.platform_data;
860         if (pdata == NULL) {
861                 ret = -ENODEV;
862                 goto err;
863         }
864
865         master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
866         if (master == NULL) {
867                 ret = -ENOMEM;
868                 goto err;
869         }
870
871         dev_set_drvdata(&pdev->dev, master);
872
873         davinci_spi = spi_master_get_devdata(master);
874         if (davinci_spi == NULL) {
875                 ret = -ENOENT;
876                 goto free_master;
877         }
878
879         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
880         if (r == NULL) {
881                 ret = -ENOENT;
882                 goto free_master;
883         }
884
885         davinci_spi->pbase = r->start;
886         davinci_spi->region_size = resource_size(r);
887         davinci_spi->pdata = pdata;
888
889         mem = request_mem_region(r->start, davinci_spi->region_size,
890                                         pdev->name);
891         if (mem == NULL) {
892                 ret = -EBUSY;
893                 goto free_master;
894         }
895
896         davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
897         if (davinci_spi->base == NULL) {
898                 ret = -ENOMEM;
899                 goto release_region;
900         }
901
902         davinci_spi->irq = platform_get_irq(pdev, 0);
903         if (davinci_spi->irq <= 0) {
904                 ret = -EINVAL;
905                 goto unmap_io;
906         }
907
908         ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0,
909                                         dev_name(&pdev->dev), davinci_spi);
910         if (ret)
911                 goto unmap_io;
912
913         /* Allocate tmp_buf for tx_buf */
914         davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
915         if (davinci_spi->tmp_buf == NULL) {
916                 ret = -ENOMEM;
917                 goto irq_free;
918         }
919
920         davinci_spi->bitbang.master = spi_master_get(master);
921         if (davinci_spi->bitbang.master == NULL) {
922                 ret = -ENODEV;
923                 goto free_tmp_buf;
924         }
925
926         davinci_spi->clk = clk_get(&pdev->dev, NULL);
927         if (IS_ERR(davinci_spi->clk)) {
928                 ret = -ENODEV;
929                 goto put_master;
930         }
931         clk_enable(davinci_spi->clk);
932
933         master->bus_num = pdev->id;
934         master->num_chipselect = pdata->num_chipselect;
935         master->setup = davinci_spi_setup;
936         master->cleanup = davinci_spi_cleanup;
937
938         davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
939         davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
940
941         davinci_spi->version = pdata->version;
942         use_dma = pdata->use_dma;
943
944         davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
945         if (davinci_spi->version == SPI_VERSION_2)
946                 davinci_spi->bitbang.flags |= SPI_READY;
947
948         if (use_dma) {
949                 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
950                 if (r)
951                         dma_rx_chan = r->start;
952                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
953                 if (r)
954                         dma_tx_chan = r->start;
955                 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
956                 if (r)
957                         dma_eventq = r->start;
958         }
959
960         if (!use_dma ||
961             dma_rx_chan == SPI_NO_RESOURCE ||
962             dma_tx_chan == SPI_NO_RESOURCE ||
963             dma_eventq  == SPI_NO_RESOURCE) {
964                 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
965                 use_dma = 0;
966         } else {
967                 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
968
969                 davinci_spi->dma_channels.dma_rx_channel = -1;
970                 davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan;
971                 davinci_spi->dma_channels.dma_tx_channel = -1;
972                 davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan;
973                 davinci_spi->dma_channels.eventq = dma_eventq;
974
975                 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
976                                 "Using RX channel = %d , TX channel = %d and "
977                                 "event queue = %d", dma_rx_chan, dma_tx_chan,
978                                 dma_eventq);
979         }
980
981         davinci_spi->get_rx = davinci_spi_rx_buf_u8;
982         davinci_spi->get_tx = davinci_spi_tx_buf_u8;
983
984         init_completion(&davinci_spi->done);
985
986         /* Reset In/OUT SPI module */
987         iowrite32(0, davinci_spi->base + SPIGCR0);
988         udelay(100);
989         iowrite32(1, davinci_spi->base + SPIGCR0);
990
991         /* Set up SPIPC0.  CS and ENA init is done in davinci_spi_setup */
992         spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
993         iowrite32(spipc0, davinci_spi->base + SPIPC0);
994
995         /* initialize chip selects */
996         if (pdata->chip_sel) {
997                 for (i = 0; i < pdata->num_chipselect; i++) {
998                         if (pdata->chip_sel[i] != SPI_INTERN_CS)
999                                 gpio_direction_output(pdata->chip_sel[i], 1);
1000                 }
1001         }
1002
1003         /* Clock internal */
1004         if (davinci_spi->pdata->clk_internal)
1005                 set_io_bits(davinci_spi->base + SPIGCR1,
1006                                 SPIGCR1_CLKMOD_MASK);
1007         else
1008                 clear_io_bits(davinci_spi->base + SPIGCR1,
1009                                 SPIGCR1_CLKMOD_MASK);
1010
1011         if (pdata->intr_line)
1012                 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1013         else
1014                 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1015
1016         iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
1017
1018         /* master mode default */
1019         set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1020
1021         ret = spi_bitbang_start(&davinci_spi->bitbang);
1022         if (ret)
1023                 goto free_clk;
1024
1025         dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
1026
1027         return ret;
1028
1029 free_clk:
1030         clk_disable(davinci_spi->clk);
1031         clk_put(davinci_spi->clk);
1032 put_master:
1033         spi_master_put(master);
1034 free_tmp_buf:
1035         kfree(davinci_spi->tmp_buf);
1036 irq_free:
1037         free_irq(davinci_spi->irq, davinci_spi);
1038 unmap_io:
1039         iounmap(davinci_spi->base);
1040 release_region:
1041         release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1042 free_master:
1043         kfree(master);
1044 err:
1045         return ret;
1046 }
1047
1048 /**
1049  * davinci_spi_remove - remove function for SPI Master Controller
1050  * @pdev: platform_device structure which contains plateform specific data
1051  *
1052  * This function will do the reverse action of davinci_spi_probe function
1053  * It will free the IRQ and SPI controller's memory region.
1054  * It will also call spi_bitbang_stop to destroy the work queue which was
1055  * created by spi_bitbang_start.
1056  */
1057 static int __exit davinci_spi_remove(struct platform_device *pdev)
1058 {
1059         struct davinci_spi *davinci_spi;
1060         struct spi_master *master;
1061
1062         master = dev_get_drvdata(&pdev->dev);
1063         davinci_spi = spi_master_get_devdata(master);
1064
1065         spi_bitbang_stop(&davinci_spi->bitbang);
1066
1067         clk_disable(davinci_spi->clk);
1068         clk_put(davinci_spi->clk);
1069         spi_master_put(master);
1070         kfree(davinci_spi->tmp_buf);
1071         free_irq(davinci_spi->irq, davinci_spi);
1072         iounmap(davinci_spi->base);
1073         release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1074
1075         return 0;
1076 }
1077
1078 static struct platform_driver davinci_spi_driver = {
1079         .driver.name = "spi_davinci",
1080         .remove = __exit_p(davinci_spi_remove),
1081 };
1082
1083 static int __init davinci_spi_init(void)
1084 {
1085         return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1086 }
1087 module_init(davinci_spi_init);
1088
1089 static void __exit davinci_spi_exit(void)
1090 {
1091         platform_driver_unregister(&davinci_spi_driver);
1092 }
1093 module_exit(davinci_spi_exit);
1094
1095 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1096 MODULE_LICENSE("GPL");