Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6.git] / drivers / spi / au1550_spi.c
1 /*
2  * au1550_spi.c - au1550 psc spi controller driver
3  * may work also with au1200, au1210, au1250
4  * will not work on au1000, au1100 and au1500 (no full spi controller there)
5  *
6  * Copyright (c) 2006 ATRON electronic GmbH
7  * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22  */
23
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/errno.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/resource.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/spi_bitbang.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/completion.h>
34 #include <asm/mach-au1x00/au1000.h>
35 #include <asm/mach-au1x00/au1xxx_psc.h>
36 #include <asm/mach-au1x00/au1xxx_dbdma.h>
37
38 #include <asm/mach-au1x00/au1550_spi.h>
39
40 static unsigned usedma = 1;
41 module_param(usedma, uint, 0644);
42
43 /*
44 #define AU1550_SPI_DEBUG_LOOPBACK
45 */
46
47
48 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
49 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
50
51 struct au1550_spi {
52         struct spi_bitbang bitbang;
53
54         volatile psc_spi_t __iomem *regs;
55         int irq;
56         unsigned freq_max;
57         unsigned freq_min;
58
59         unsigned len;
60         unsigned tx_count;
61         unsigned rx_count;
62         const u8 *tx;
63         u8 *rx;
64
65         void (*rx_word)(struct au1550_spi *hw);
66         void (*tx_word)(struct au1550_spi *hw);
67         int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
68         irqreturn_t (*irq_callback)(struct au1550_spi *hw);
69
70         struct completion master_done;
71
72         unsigned usedma;
73         u32 dma_tx_id;
74         u32 dma_rx_id;
75         u32 dma_tx_ch;
76         u32 dma_rx_ch;
77
78         u8 *dma_rx_tmpbuf;
79         unsigned dma_rx_tmpbuf_size;
80         u32 dma_rx_tmpbuf_addr;
81
82         struct spi_master *master;
83         struct device *dev;
84         struct au1550_spi_info *pdata;
85         struct resource *ioarea;
86 };
87
88
89 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
90 static dbdev_tab_t au1550_spi_mem_dbdev =
91 {
92         .dev_id                 = DBDMA_MEM_CHAN,
93         .dev_flags              = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
94         .dev_tsize              = 0,
95         .dev_devwidth           = 8,
96         .dev_physaddr           = 0x00000000,
97         .dev_intlevel           = 0,
98         .dev_intpolarity        = 0
99 };
100
101 static int ddma_memid;  /* id to above mem dma device */
102
103 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
104
105
106 /*
107  *  compute BRG and DIV bits to setup spi clock based on main input clock rate
108  *  that was specified in platform data structure
109  *  according to au1550 datasheet:
110  *    psc_tempclk = psc_mainclk / (2 << DIV)
111  *    spiclk = psc_tempclk / (2 * (BRG + 1))
112  *    BRG valid range is 4..63
113  *    DIV valid range is 0..3
114  */
115 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
116 {
117         u32 mainclk_hz = hw->pdata->mainclk_hz;
118         u32 div, brg;
119
120         for (div = 0; div < 4; div++) {
121                 brg = mainclk_hz / speed_hz / (4 << div);
122                 /* now we have BRG+1 in brg, so count with that */
123                 if (brg < (4 + 1)) {
124                         brg = (4 + 1);  /* speed_hz too big */
125                         break;          /* set lowest brg (div is == 0) */
126                 }
127                 if (brg <= (63 + 1))
128                         break;          /* we have valid brg and div */
129         }
130         if (div == 4) {
131                 div = 3;                /* speed_hz too small */
132                 brg = (63 + 1);         /* set highest brg and div */
133         }
134         brg--;
135         return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
136 }
137
138 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
139 {
140         hw->regs->psc_spimsk =
141                   PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
142                 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
143                 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
144         au_sync();
145
146         hw->regs->psc_spievent =
147                   PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
148                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
149                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
150         au_sync();
151 }
152
153 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
154 {
155         u32 pcr;
156
157         hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
158         au_sync();
159         do {
160                 pcr = hw->regs->psc_spipcr;
161                 au_sync();
162         } while (pcr != 0);
163 }
164
165 /*
166  * dma transfers are used for the most common spi word size of 8-bits
167  * we cannot easily change already set up dma channels' width, so if we wanted
168  * dma support for more than 8-bit words (up to 24 bits), we would need to
169  * setup dma channels from scratch on each spi transfer, based on bits_per_word
170  * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
171  * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
172  * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
173  */
174 static void au1550_spi_chipsel(struct spi_device *spi, int value)
175 {
176         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
177         unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
178         u32 cfg, stat;
179
180         switch (value) {
181         case BITBANG_CS_INACTIVE:
182                 if (hw->pdata->deactivate_cs)
183                         hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
184                                         cspol);
185                 break;
186
187         case BITBANG_CS_ACTIVE:
188                 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
189
190                 cfg = hw->regs->psc_spicfg;
191                 au_sync();
192                 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
193                 au_sync();
194
195                 if (spi->mode & SPI_CPOL)
196                         cfg |= PSC_SPICFG_BI;
197                 else
198                         cfg &= ~PSC_SPICFG_BI;
199                 if (spi->mode & SPI_CPHA)
200                         cfg &= ~PSC_SPICFG_CDE;
201                 else
202                         cfg |= PSC_SPICFG_CDE;
203
204                 if (spi->mode & SPI_LSB_FIRST)
205                         cfg |= PSC_SPICFG_MLF;
206                 else
207                         cfg &= ~PSC_SPICFG_MLF;
208
209                 if (hw->usedma && spi->bits_per_word <= 8)
210                         cfg &= ~PSC_SPICFG_DD_DISABLE;
211                 else
212                         cfg |= PSC_SPICFG_DD_DISABLE;
213                 cfg = PSC_SPICFG_CLR_LEN(cfg);
214                 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
215
216                 cfg = PSC_SPICFG_CLR_BAUD(cfg);
217                 cfg &= ~PSC_SPICFG_SET_DIV(3);
218                 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
219
220                 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
221                 au_sync();
222                 do {
223                         stat = hw->regs->psc_spistat;
224                         au_sync();
225                 } while ((stat & PSC_SPISTAT_DR) == 0);
226
227                 if (hw->pdata->activate_cs)
228                         hw->pdata->activate_cs(hw->pdata, spi->chip_select,
229                                         cspol);
230                 break;
231         }
232 }
233
234 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
235 {
236         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
237         unsigned bpw, hz;
238         u32 cfg, stat;
239
240         bpw = spi->bits_per_word;
241         hz = spi->max_speed_hz;
242         if (t) {
243                 if (t->bits_per_word)
244                         bpw = t->bits_per_word;
245                 if (t->speed_hz)
246                         hz = t->speed_hz;
247         }
248
249         if (bpw < 4 || bpw > 24) {
250                 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
251                         bpw);
252                 return -EINVAL;
253         }
254         if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
255                 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
256                         hz);
257                 return -EINVAL;
258         }
259
260         au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
261
262         cfg = hw->regs->psc_spicfg;
263         au_sync();
264         hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
265         au_sync();
266
267         if (hw->usedma && bpw <= 8)
268                 cfg &= ~PSC_SPICFG_DD_DISABLE;
269         else
270                 cfg |= PSC_SPICFG_DD_DISABLE;
271         cfg = PSC_SPICFG_CLR_LEN(cfg);
272         cfg |= PSC_SPICFG_SET_LEN(bpw);
273
274         cfg = PSC_SPICFG_CLR_BAUD(cfg);
275         cfg &= ~PSC_SPICFG_SET_DIV(3);
276         cfg |= au1550_spi_baudcfg(hw, hz);
277
278         hw->regs->psc_spicfg = cfg;
279         au_sync();
280
281         if (cfg & PSC_SPICFG_DE_ENABLE) {
282                 do {
283                         stat = hw->regs->psc_spistat;
284                         au_sync();
285                 } while ((stat & PSC_SPISTAT_DR) == 0);
286         }
287
288         au1550_spi_reset_fifos(hw);
289         au1550_spi_mask_ack_all(hw);
290         return 0;
291 }
292
293 static int au1550_spi_setup(struct spi_device *spi)
294 {
295         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
296
297         if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
298                 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
299                         spi->bits_per_word);
300                 return -EINVAL;
301         }
302
303         if (spi->max_speed_hz == 0)
304                 spi->max_speed_hz = hw->freq_max;
305         if (spi->max_speed_hz > hw->freq_max
306                         || spi->max_speed_hz < hw->freq_min)
307                 return -EINVAL;
308         /*
309          * NOTE: cannot change speed and other hw settings immediately,
310          *       otherwise sharing of spi bus is not possible,
311          *       so do not call setupxfer(spi, NULL) here
312          */
313         return 0;
314 }
315
316 /*
317  * for dma spi transfers, we have to setup rx channel, otherwise there is
318  * no reliable way how to recognize that spi transfer is done
319  * dma complete callbacks are called before real spi transfer is finished
320  * and if only tx dma channel is set up (and rx fifo overflow event masked)
321  * spi master done event irq is not generated unless rx fifo is empty (emptied)
322  * so we need rx tmp buffer to use for rx dma if user does not provide one
323  */
324 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
325 {
326         hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
327         if (!hw->dma_rx_tmpbuf)
328                 return -ENOMEM;
329         hw->dma_rx_tmpbuf_size = size;
330         hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
331                         size, DMA_FROM_DEVICE);
332         if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
333                 kfree(hw->dma_rx_tmpbuf);
334                 hw->dma_rx_tmpbuf = 0;
335                 hw->dma_rx_tmpbuf_size = 0;
336                 return -EFAULT;
337         }
338         return 0;
339 }
340
341 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
342 {
343         dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
344                         hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
345         kfree(hw->dma_rx_tmpbuf);
346         hw->dma_rx_tmpbuf = 0;
347         hw->dma_rx_tmpbuf_size = 0;
348 }
349
350 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
351 {
352         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
353         dma_addr_t dma_tx_addr;
354         dma_addr_t dma_rx_addr;
355         u32 res;
356
357         hw->len = t->len;
358         hw->tx_count = 0;
359         hw->rx_count = 0;
360
361         hw->tx = t->tx_buf;
362         hw->rx = t->rx_buf;
363         dma_tx_addr = t->tx_dma;
364         dma_rx_addr = t->rx_dma;
365
366         /*
367          * check if buffers are already dma mapped, map them otherwise:
368          * - first map the TX buffer, so cache data gets written to memory
369          * - then map the RX buffer, so that cache entries (with
370          *   soon-to-be-stale data) get removed
371          * use rx buffer in place of tx if tx buffer was not provided
372          * use temp rx buffer (preallocated or realloc to fit) for rx dma
373          */
374         if (t->tx_buf) {
375                 if (t->tx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
376                         dma_tx_addr = dma_map_single(hw->dev,
377                                         (void *)t->tx_buf,
378                                         t->len, DMA_TO_DEVICE);
379                         if (dma_mapping_error(hw->dev, dma_tx_addr))
380                                 dev_err(hw->dev, "tx dma map error\n");
381                 }
382         }
383
384         if (t->rx_buf) {
385                 if (t->rx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
386                         dma_rx_addr = dma_map_single(hw->dev,
387                                         (void *)t->rx_buf,
388                                         t->len, DMA_FROM_DEVICE);
389                         if (dma_mapping_error(hw->dev, dma_rx_addr))
390                                 dev_err(hw->dev, "rx dma map error\n");
391                 }
392         } else {
393                 if (t->len > hw->dma_rx_tmpbuf_size) {
394                         int ret;
395
396                         au1550_spi_dma_rxtmp_free(hw);
397                         ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
398                                         AU1550_SPI_DMA_RXTMP_MINSIZE));
399                         if (ret < 0)
400                                 return ret;
401                 }
402                 hw->rx = hw->dma_rx_tmpbuf;
403                 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
404                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
405                         t->len, DMA_FROM_DEVICE);
406         }
407
408         if (!t->tx_buf) {
409                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
410                                 t->len, DMA_BIDIRECTIONAL);
411                 hw->tx = hw->rx;
412         }
413
414         /* put buffers on the ring */
415         res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
416                                     t->len, DDMA_FLAGS_IE);
417         if (!res)
418                 dev_err(hw->dev, "rx dma put dest error\n");
419
420         res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
421                                       t->len, DDMA_FLAGS_IE);
422         if (!res)
423                 dev_err(hw->dev, "tx dma put source error\n");
424
425         au1xxx_dbdma_start(hw->dma_rx_ch);
426         au1xxx_dbdma_start(hw->dma_tx_ch);
427
428         /* by default enable nearly all events interrupt */
429         hw->regs->psc_spimsk = PSC_SPIMSK_SD;
430         au_sync();
431
432         /* start the transfer */
433         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
434         au_sync();
435
436         wait_for_completion(&hw->master_done);
437
438         au1xxx_dbdma_stop(hw->dma_tx_ch);
439         au1xxx_dbdma_stop(hw->dma_rx_ch);
440
441         if (!t->rx_buf) {
442                 /* using the temporal preallocated and premapped buffer */
443                 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
444                         DMA_FROM_DEVICE);
445         }
446         /* unmap buffers if mapped above */
447         if (t->rx_buf && t->rx_dma == 0 )
448                 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
449                         DMA_FROM_DEVICE);
450         if (t->tx_buf && t->tx_dma == 0 )
451                 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
452                         DMA_TO_DEVICE);
453
454         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
455 }
456
457 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
458 {
459         u32 stat, evnt;
460
461         stat = hw->regs->psc_spistat;
462         evnt = hw->regs->psc_spievent;
463         au_sync();
464         if ((stat & PSC_SPISTAT_DI) == 0) {
465                 dev_err(hw->dev, "Unexpected IRQ!\n");
466                 return IRQ_NONE;
467         }
468
469         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
470                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
471                                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
472                         != 0) {
473                 /*
474                  * due to an spi error we consider transfer as done,
475                  * so mask all events until before next transfer start
476                  * and stop the possibly running dma immediatelly
477                  */
478                 au1550_spi_mask_ack_all(hw);
479                 au1xxx_dbdma_stop(hw->dma_rx_ch);
480                 au1xxx_dbdma_stop(hw->dma_tx_ch);
481
482                 /* get number of transfered bytes */
483                 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
484                 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
485
486                 au1xxx_dbdma_reset(hw->dma_rx_ch);
487                 au1xxx_dbdma_reset(hw->dma_tx_ch);
488                 au1550_spi_reset_fifos(hw);
489
490                 if (evnt == PSC_SPIEVNT_RO)
491                         dev_err(hw->dev,
492                                 "dma transfer: receive FIFO overflow!\n");
493                 else
494                         dev_err(hw->dev,
495                                 "dma transfer: unexpected SPI error "
496                                 "(event=0x%x stat=0x%x)!\n", evnt, stat);
497
498                 complete(&hw->master_done);
499                 return IRQ_HANDLED;
500         }
501
502         if ((evnt & PSC_SPIEVNT_MD) != 0) {
503                 /* transfer completed successfully */
504                 au1550_spi_mask_ack_all(hw);
505                 hw->rx_count = hw->len;
506                 hw->tx_count = hw->len;
507                 complete(&hw->master_done);
508         }
509         return IRQ_HANDLED;
510 }
511
512
513 /* routines to handle different word sizes in pio mode */
514 #define AU1550_SPI_RX_WORD(size, mask)                                  \
515 static void au1550_spi_rx_word_##size(struct au1550_spi *hw)            \
516 {                                                                       \
517         u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask);             \
518         au_sync();                                                      \
519         if (hw->rx) {                                                   \
520                 *(u##size *)hw->rx = (u##size)fifoword;                 \
521                 hw->rx += (size) / 8;                                   \
522         }                                                               \
523         hw->rx_count += (size) / 8;                                     \
524 }
525
526 #define AU1550_SPI_TX_WORD(size, mask)                                  \
527 static void au1550_spi_tx_word_##size(struct au1550_spi *hw)            \
528 {                                                                       \
529         u32 fifoword = 0;                                               \
530         if (hw->tx) {                                                   \
531                 fifoword = *(u##size *)hw->tx & (u32)(mask);            \
532                 hw->tx += (size) / 8;                                   \
533         }                                                               \
534         hw->tx_count += (size) / 8;                                     \
535         if (hw->tx_count >= hw->len)                                    \
536                 fifoword |= PSC_SPITXRX_LC;                             \
537         hw->regs->psc_spitxrx = fifoword;                               \
538         au_sync();                                                      \
539 }
540
541 AU1550_SPI_RX_WORD(8,0xff)
542 AU1550_SPI_RX_WORD(16,0xffff)
543 AU1550_SPI_RX_WORD(32,0xffffff)
544 AU1550_SPI_TX_WORD(8,0xff)
545 AU1550_SPI_TX_WORD(16,0xffff)
546 AU1550_SPI_TX_WORD(32,0xffffff)
547
548 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
549 {
550         u32 stat, mask;
551         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
552
553         hw->tx = t->tx_buf;
554         hw->rx = t->rx_buf;
555         hw->len = t->len;
556         hw->tx_count = 0;
557         hw->rx_count = 0;
558
559         /* by default enable nearly all events after filling tx fifo */
560         mask = PSC_SPIMSK_SD;
561
562         /* fill the transmit FIFO */
563         while (hw->tx_count < hw->len) {
564
565                 hw->tx_word(hw);
566
567                 if (hw->tx_count >= hw->len) {
568                         /* mask tx fifo request interrupt as we are done */
569                         mask |= PSC_SPIMSK_TR;
570                 }
571
572                 stat = hw->regs->psc_spistat;
573                 au_sync();
574                 if (stat & PSC_SPISTAT_TF)
575                         break;
576         }
577
578         /* enable event interrupts */
579         hw->regs->psc_spimsk = mask;
580         au_sync();
581
582         /* start the transfer */
583         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
584         au_sync();
585
586         wait_for_completion(&hw->master_done);
587
588         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
589 }
590
591 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
592 {
593         int busy;
594         u32 stat, evnt;
595
596         stat = hw->regs->psc_spistat;
597         evnt = hw->regs->psc_spievent;
598         au_sync();
599         if ((stat & PSC_SPISTAT_DI) == 0) {
600                 dev_err(hw->dev, "Unexpected IRQ!\n");
601                 return IRQ_NONE;
602         }
603
604         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
605                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
606                                 | PSC_SPIEVNT_SD))
607                         != 0) {
608                 /*
609                  * due to an error we consider transfer as done,
610                  * so mask all events until before next transfer start
611                  */
612                 au1550_spi_mask_ack_all(hw);
613                 au1550_spi_reset_fifos(hw);
614                 dev_err(hw->dev,
615                         "pio transfer: unexpected SPI error "
616                         "(event=0x%x stat=0x%x)!\n", evnt, stat);
617                 complete(&hw->master_done);
618                 return IRQ_HANDLED;
619         }
620
621         /*
622          * while there is something to read from rx fifo
623          * or there is a space to write to tx fifo:
624          */
625         do {
626                 busy = 0;
627                 stat = hw->regs->psc_spistat;
628                 au_sync();
629
630                 /*
631                  * Take care to not let the Rx FIFO overflow.
632                  *
633                  * We only write a byte if we have read one at least. Initially,
634                  * the write fifo is full, so we should read from the read fifo
635                  * first.
636                  * In case we miss a word from the read fifo, we should get a
637                  * RO event and should back out.
638                  */
639                 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
640                         hw->rx_word(hw);
641                         busy = 1;
642
643                         if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
644                                 hw->tx_word(hw);
645                 }
646         } while (busy);
647
648         hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
649         au_sync();
650
651         /*
652          * Restart the SPI transmission in case of a transmit underflow.
653          * This seems to work despite the notes in the Au1550 data book
654          * of Figure 8-4 with flowchart for SPI master operation:
655          *
656          * """Note 1: An XFR Error Interrupt occurs, unless masked,
657          * for any of the following events: Tx FIFO Underflow,
658          * Rx FIFO Overflow, or Multiple-master Error
659          *    Note 2: In case of a Tx Underflow Error, all zeroes are
660          * transmitted."""
661          *
662          * By simply restarting the spi transfer on Tx Underflow Error,
663          * we assume that spi transfer was paused instead of zeroes
664          * transmittion mentioned in the Note 2 of Au1550 data book.
665          */
666         if (evnt & PSC_SPIEVNT_TU) {
667                 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
668                 au_sync();
669                 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
670                 au_sync();
671         }
672
673         if (hw->rx_count >= hw->len) {
674                 /* transfer completed successfully */
675                 au1550_spi_mask_ack_all(hw);
676                 complete(&hw->master_done);
677         }
678         return IRQ_HANDLED;
679 }
680
681 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
682 {
683         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
684         return hw->txrx_bufs(spi, t);
685 }
686
687 static irqreturn_t au1550_spi_irq(int irq, void *dev)
688 {
689         struct au1550_spi *hw = dev;
690         return hw->irq_callback(hw);
691 }
692
693 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
694 {
695         if (bpw <= 8) {
696                 if (hw->usedma) {
697                         hw->txrx_bufs = &au1550_spi_dma_txrxb;
698                         hw->irq_callback = &au1550_spi_dma_irq_callback;
699                 } else {
700                         hw->rx_word = &au1550_spi_rx_word_8;
701                         hw->tx_word = &au1550_spi_tx_word_8;
702                         hw->txrx_bufs = &au1550_spi_pio_txrxb;
703                         hw->irq_callback = &au1550_spi_pio_irq_callback;
704                 }
705         } else if (bpw <= 16) {
706                 hw->rx_word = &au1550_spi_rx_word_16;
707                 hw->tx_word = &au1550_spi_tx_word_16;
708                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
709                 hw->irq_callback = &au1550_spi_pio_irq_callback;
710         } else {
711                 hw->rx_word = &au1550_spi_rx_word_32;
712                 hw->tx_word = &au1550_spi_tx_word_32;
713                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
714                 hw->irq_callback = &au1550_spi_pio_irq_callback;
715         }
716 }
717
718 static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
719 {
720         u32 stat, cfg;
721
722         /* set up the PSC for SPI mode */
723         hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
724         au_sync();
725         hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
726         au_sync();
727
728         hw->regs->psc_spicfg = 0;
729         au_sync();
730
731         hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
732         au_sync();
733
734         do {
735                 stat = hw->regs->psc_spistat;
736                 au_sync();
737         } while ((stat & PSC_SPISTAT_SR) == 0);
738
739
740         cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
741         cfg |= PSC_SPICFG_SET_LEN(8);
742         cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
743         /* use minimal allowed brg and div values as initial setting: */
744         cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
745
746 #ifdef AU1550_SPI_DEBUG_LOOPBACK
747         cfg |= PSC_SPICFG_LB;
748 #endif
749
750         hw->regs->psc_spicfg = cfg;
751         au_sync();
752
753         au1550_spi_mask_ack_all(hw);
754
755         hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
756         au_sync();
757
758         do {
759                 stat = hw->regs->psc_spistat;
760                 au_sync();
761         } while ((stat & PSC_SPISTAT_DR) == 0);
762
763         au1550_spi_reset_fifos(hw);
764 }
765
766
767 static int __init au1550_spi_probe(struct platform_device *pdev)
768 {
769         struct au1550_spi *hw;
770         struct spi_master *master;
771         struct resource *r;
772         int err = 0;
773
774         master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
775         if (master == NULL) {
776                 dev_err(&pdev->dev, "No memory for spi_master\n");
777                 err = -ENOMEM;
778                 goto err_nomem;
779         }
780
781         /* the spi->mode bits understood by this driver: */
782         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
783
784         hw = spi_master_get_devdata(master);
785
786         hw->master = spi_master_get(master);
787         hw->pdata = pdev->dev.platform_data;
788         hw->dev = &pdev->dev;
789
790         if (hw->pdata == NULL) {
791                 dev_err(&pdev->dev, "No platform data supplied\n");
792                 err = -ENOENT;
793                 goto err_no_pdata;
794         }
795
796         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
797         if (!r) {
798                 dev_err(&pdev->dev, "no IRQ\n");
799                 err = -ENODEV;
800                 goto err_no_iores;
801         }
802         hw->irq = r->start;
803
804         hw->usedma = 0;
805         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
806         if (r) {
807                 hw->dma_tx_id = r->start;
808                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
809                 if (r) {
810                         hw->dma_rx_id = r->start;
811                         if (usedma && ddma_memid) {
812                                 if (pdev->dev.dma_mask == NULL)
813                                         dev_warn(&pdev->dev, "no dma mask\n");
814                                 else
815                                         hw->usedma = 1;
816                         }
817                 }
818         }
819
820         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
821         if (!r) {
822                 dev_err(&pdev->dev, "no mmio resource\n");
823                 err = -ENODEV;
824                 goto err_no_iores;
825         }
826
827         hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
828                                         pdev->name);
829         if (!hw->ioarea) {
830                 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
831                 err = -ENXIO;
832                 goto err_no_iores;
833         }
834
835         hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
836         if (!hw->regs) {
837                 dev_err(&pdev->dev, "cannot ioremap\n");
838                 err = -ENXIO;
839                 goto err_ioremap;
840         }
841
842         platform_set_drvdata(pdev, hw);
843
844         init_completion(&hw->master_done);
845
846         hw->bitbang.master = hw->master;
847         hw->bitbang.setup_transfer = au1550_spi_setupxfer;
848         hw->bitbang.chipselect = au1550_spi_chipsel;
849         hw->bitbang.master->setup = au1550_spi_setup;
850         hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
851
852         if (hw->usedma) {
853                 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
854                         hw->dma_tx_id, NULL, (void *)hw);
855                 if (hw->dma_tx_ch == 0) {
856                         dev_err(&pdev->dev,
857                                 "Cannot allocate tx dma channel\n");
858                         err = -ENXIO;
859                         goto err_no_txdma;
860                 }
861                 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
862                 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
863                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
864                         dev_err(&pdev->dev,
865                                 "Cannot allocate tx dma descriptors\n");
866                         err = -ENXIO;
867                         goto err_no_txdma_descr;
868                 }
869
870
871                 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
872                         ddma_memid, NULL, (void *)hw);
873                 if (hw->dma_rx_ch == 0) {
874                         dev_err(&pdev->dev,
875                                 "Cannot allocate rx dma channel\n");
876                         err = -ENXIO;
877                         goto err_no_rxdma;
878                 }
879                 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
880                 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
881                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
882                         dev_err(&pdev->dev,
883                                 "Cannot allocate rx dma descriptors\n");
884                         err = -ENXIO;
885                         goto err_no_rxdma_descr;
886                 }
887
888                 err = au1550_spi_dma_rxtmp_alloc(hw,
889                         AU1550_SPI_DMA_RXTMP_MINSIZE);
890                 if (err < 0) {
891                         dev_err(&pdev->dev,
892                                 "Cannot allocate initial rx dma tmp buffer\n");
893                         goto err_dma_rxtmp_alloc;
894                 }
895         }
896
897         au1550_spi_bits_handlers_set(hw, 8);
898
899         err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
900         if (err) {
901                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
902                 goto err_no_irq;
903         }
904
905         master->bus_num = pdev->id;
906         master->num_chipselect = hw->pdata->num_chipselect;
907
908         /*
909          *  precompute valid range for spi freq - from au1550 datasheet:
910          *    psc_tempclk = psc_mainclk / (2 << DIV)
911          *    spiclk = psc_tempclk / (2 * (BRG + 1))
912          *    BRG valid range is 4..63
913          *    DIV valid range is 0..3
914          *  round the min and max frequencies to values that would still
915          *  produce valid brg and div
916          */
917         {
918                 int min_div = (2 << 0) * (2 * (4 + 1));
919                 int max_div = (2 << 3) * (2 * (63 + 1));
920                 hw->freq_max = hw->pdata->mainclk_hz / min_div;
921                 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
922         }
923
924         au1550_spi_setup_psc_as_spi(hw);
925
926         err = spi_bitbang_start(&hw->bitbang);
927         if (err) {
928                 dev_err(&pdev->dev, "Failed to register SPI master\n");
929                 goto err_register;
930         }
931
932         dev_info(&pdev->dev,
933                 "spi master registered: bus_num=%d num_chipselect=%d\n",
934                 master->bus_num, master->num_chipselect);
935
936         return 0;
937
938 err_register:
939         free_irq(hw->irq, hw);
940
941 err_no_irq:
942         au1550_spi_dma_rxtmp_free(hw);
943
944 err_dma_rxtmp_alloc:
945 err_no_rxdma_descr:
946         if (hw->usedma)
947                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
948
949 err_no_rxdma:
950 err_no_txdma_descr:
951         if (hw->usedma)
952                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
953
954 err_no_txdma:
955         iounmap((void __iomem *)hw->regs);
956
957 err_ioremap:
958         release_resource(hw->ioarea);
959         kfree(hw->ioarea);
960
961 err_no_iores:
962 err_no_pdata:
963         spi_master_put(hw->master);
964
965 err_nomem:
966         return err;
967 }
968
969 static int __exit au1550_spi_remove(struct platform_device *pdev)
970 {
971         struct au1550_spi *hw = platform_get_drvdata(pdev);
972
973         dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
974                 hw->master->bus_num);
975
976         spi_bitbang_stop(&hw->bitbang);
977         free_irq(hw->irq, hw);
978         iounmap((void __iomem *)hw->regs);
979         release_resource(hw->ioarea);
980         kfree(hw->ioarea);
981
982         if (hw->usedma) {
983                 au1550_spi_dma_rxtmp_free(hw);
984                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
985                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
986         }
987
988         platform_set_drvdata(pdev, NULL);
989
990         spi_master_put(hw->master);
991         return 0;
992 }
993
994 /* work with hotplug and coldplug */
995 MODULE_ALIAS("platform:au1550-spi");
996
997 static struct platform_driver au1550_spi_drv = {
998         .remove = __exit_p(au1550_spi_remove),
999         .driver = {
1000                 .name = "au1550-spi",
1001                 .owner = THIS_MODULE,
1002         },
1003 };
1004
1005 static int __init au1550_spi_init(void)
1006 {
1007         /*
1008          * create memory device with 8 bits dev_devwidth
1009          * needed for proper byte ordering to spi fifo
1010          */
1011         if (usedma) {
1012                 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
1013                 if (!ddma_memid)
1014                         printk(KERN_ERR "au1550-spi: cannot add memory"
1015                                         "dbdma device\n");
1016         }
1017         return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
1018 }
1019 module_init(au1550_spi_init);
1020
1021 static void __exit au1550_spi_exit(void)
1022 {
1023         if (usedma && ddma_memid)
1024                 au1xxx_ddma_del_device(ddma_memid);
1025         platform_driver_unregister(&au1550_spi_drv);
1026 }
1027 module_exit(au1550_spi_exit);
1028
1029 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
1030 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
1031 MODULE_LICENSE("GPL");