[PATCH] sh: sh-sci clock framework updates
[linux-2.6.git] / drivers / serial / sh-sci.c
1 /*
2  * drivers/serial/sh-sci.c
3  *
4  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
5  *
6  *  Copyright (C) 2002, 2003, 2004  Paul Mundt
7  *
8  * based off of the old drivers/char/sh-sci.c by:
9  *
10  *   Copyright (C) 1999, 2000  Niibe Yutaka
11  *   Copyright (C) 2000  Sugioka Toshinobu
12  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
13  *   Modified to support SecureEdge. David McCullough (2002)
14  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15  *
16  * This file is subject to the terms and conditions of the GNU General Public
17  * License.  See the file "COPYING" in the main directory of this archive
18  * for more details.
19  */
20
21 #undef DEBUG
22
23 #include <linux/config.h>
24 #include <linux/module.h>
25 #include <linux/errno.h>
26 #include <linux/signal.h>
27 #include <linux/sched.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/fcntl.h>
37 #include <linux/ptrace.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/slab.h>
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/console.h>
44 #include <linux/bitops.h>
45 #include <linux/generic_serial.h>
46
47 #ifdef CONFIG_CPU_FREQ
48 #include <linux/notifier.h>
49 #include <linux/cpufreq.h>
50 #endif
51
52 #include <asm/system.h>
53 #include <asm/io.h>
54 #include <asm/irq.h>
55 #include <asm/uaccess.h>
56
57 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
58 #include <asm/clock.h>
59 #endif
60
61 #ifdef CONFIG_SH_STANDARD_BIOS
62 #include <asm/sh_bios.h>
63 #endif
64
65 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
66 #define SUPPORT_SYSRQ
67 #endif
68
69 #include "sh-sci.h"
70
71 #ifdef CONFIG_SH_KGDB
72 #include <asm/kgdb.h>
73
74 static int kgdb_get_char(struct sci_port *port);
75 static void kgdb_put_char(struct sci_port *port, char c);
76 static void kgdb_handle_error(struct sci_port *port);
77 static struct sci_port *kgdb_sci_port;
78 #endif /* CONFIG_SH_KGDB */
79
80 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
81 static struct sci_port *serial_console_port = 0;
82 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
83
84 /* Function prototypes */
85 static void sci_stop_tx(struct uart_port *port);
86 static void sci_start_tx(struct uart_port *port);
87 static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
88 static void sci_stop_rx(struct uart_port *port);
89 static int sci_request_irq(struct sci_port *port);
90 static void sci_free_irq(struct sci_port *port);
91
92 static struct sci_port sci_ports[];
93 static struct uart_driver sci_uart_driver;
94
95 #define SCI_NPORTS sci_uart_driver.nr
96
97 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
98
99 static void handle_error(struct uart_port *port)
100 {                               /* Clear error flags */
101         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
102 }
103
104 static int get_char(struct uart_port *port)
105 {
106         unsigned long flags;
107         unsigned short status;
108         int c;
109
110         local_irq_save(flags);
111         do {
112                 status = sci_in(port, SCxSR);
113                 if (status & SCxSR_ERRORS(port)) {
114                         handle_error(port);
115                         continue;
116                 }
117         } while (!(status & SCxSR_RDxF(port)));
118         c = sci_in(port, SCxRDR);
119         sci_in(port, SCxSR);            /* Dummy read */
120         sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
121         local_irq_restore(flags);
122
123         return c;
124 }
125
126 /* Taken from sh-stub.c of GDB 4.18 */
127 static const char hexchars[] = "0123456789abcdef";
128
129 static __inline__ char highhex(int  x)
130 {
131         return hexchars[(x >> 4) & 0xf];
132 }
133
134 static __inline__ char lowhex(int  x)
135 {
136         return hexchars[x & 0xf];
137 }
138
139 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
140
141 /*
142  * Send the packet in buffer.  The host gets one chance to read it.
143  * This routine does not wait for a positive acknowledge.
144  */
145
146 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
147 static void put_char(struct uart_port *port, char c)
148 {
149         unsigned long flags;
150         unsigned short status;
151
152         local_irq_save(flags);
153
154         do {
155                 status = sci_in(port, SCxSR);
156         } while (!(status & SCxSR_TDxE(port)));
157
158         sci_out(port, SCxTDR, c);
159         sci_in(port, SCxSR);            /* Dummy read */
160         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
161
162         local_irq_restore(flags);
163 }
164
165 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
166 {
167         struct uart_port *port = &sci_port->port;
168         const unsigned char *p = buffer;
169         int i;
170
171 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
172         int checksum;
173         int usegdb=0;
174
175 #ifdef CONFIG_SH_STANDARD_BIOS
176         /* This call only does a trap the first time it is
177          * called, and so is safe to do here unconditionally
178          */
179         usegdb |= sh_bios_in_gdb_mode();
180 #endif
181 #ifdef CONFIG_SH_KGDB
182         usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
183 #endif
184
185         if (usegdb) {
186             /*  $<packet info>#<checksum>. */
187             do {
188                 unsigned char c;
189                 put_char(port, '$');
190                 put_char(port, 'O'); /* 'O'utput to console */
191                 checksum = 'O';
192
193                 for (i=0; i<count; i++) { /* Don't use run length encoding */
194                         int h, l;
195
196                         c = *p++;
197                         h = highhex(c);
198                         l = lowhex(c);
199                         put_char(port, h);
200                         put_char(port, l);
201                         checksum += h + l;
202                 }
203                 put_char(port, '#');
204                 put_char(port, highhex(checksum));
205                 put_char(port, lowhex(checksum));
206             } while  (get_char(port) != '+');
207         } else
208 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
209         for (i=0; i<count; i++) {
210                 if (*p == 10)
211                         put_char(port, '\r');
212                 put_char(port, *p++);
213         }
214 }
215 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
216
217
218 #ifdef CONFIG_SH_KGDB
219
220 /* Is the SCI ready, ie is there a char waiting? */
221 static int kgdb_is_char_ready(struct sci_port *port)
222 {
223         unsigned short status = sci_in(port, SCxSR);
224
225         if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
226                 kgdb_handle_error(port);
227
228         return (status & SCxSR_RDxF(port));
229 }
230
231 /* Write a char */
232 static void kgdb_put_char(struct sci_port *port, char c)
233 {
234         unsigned short status;
235
236         do
237                 status = sci_in(port, SCxSR);
238         while (!(status & SCxSR_TDxE(port)));
239
240         sci_out(port, SCxTDR, c);
241         sci_in(port, SCxSR);    /* Dummy read */
242         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
243 }
244
245 /* Get a char if there is one, else ret -1 */
246 static int kgdb_get_char(struct sci_port *port)
247 {
248         int c;
249
250         if (kgdb_is_char_ready(port) == 0)
251                 c = -1;
252         else {
253                 c = sci_in(port, SCxRDR);
254                 sci_in(port, SCxSR);    /* Dummy read */
255                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
256         }
257
258         return c;
259 }
260
261 /* Called from kgdbstub.c to get a character, i.e. is blocking */
262 static int kgdb_sci_getchar(void)
263 {
264         volatile int c;
265
266         /* Keep trying to read a character, this could be neater */
267         while ((c = kgdb_get_char(kgdb_sci_port)) < 0);
268
269         return c;
270 }
271
272 /* Called from kgdbstub.c to put a character, just a wrapper */
273 static void kgdb_sci_putchar(int c)
274 {
275
276         kgdb_put_char(kgdb_sci_port, c);
277 }
278
279 /* Clear any errors on the SCI */
280 static void kgdb_handle_error(struct sci_port *port)
281 {
282         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));  /* Clear error flags */
283 }
284
285 /* Breakpoint if there's a break sent on the serial port */
286 static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
287 {
288         struct sci_port *port = ptr;
289         unsigned short status = sci_in(port, SCxSR);
290
291         if (status & SCxSR_BRK(port)) {
292
293                 /* Break into the debugger if a break is detected */
294                 BREAKPOINT();
295
296                 /* Clear */
297                 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
298         }
299 }
300
301 #endif /* CONFIG_SH_KGDB */
302
303 #if defined(__H8300S__)
304 enum { sci_disable, sci_enable };
305
306 static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
307 {
308         volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
309         int ch = (port->mapbase  - SMR0) >> 3;
310         unsigned char mask = 1 << (ch+1);
311
312         if (ctrl == sci_disable) {
313                 *mstpcrl |= mask;
314         } else {
315                 *mstpcrl &= ~mask;
316         }
317 }
318 #endif
319
320 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF)
321 #if defined(__H8300H__) || defined(__H8300S__)
322 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
323 {
324         int ch = (port->mapbase - SMR0) >> 3;
325
326         /* set DDR regs */
327         H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT);
328         H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT);
329         /* tx mark output*/
330         H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
331 }
332 #endif
333 #endif
334
335 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
336 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
337 /* SH7300 doesn't use RTS/CTS */
338 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
339 {
340         sci_out(port, SCFCR, 0);
341 }
342 #elif defined(CONFIG_CPU_SH3)
343 /* For SH7705, SH7707, SH7709, SH7709A, SH7729 */
344 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
345 {
346         unsigned int fcr_val = 0;
347         unsigned short data;
348
349         /* We need to set SCPCR to enable RTS/CTS */
350         data = ctrl_inw(SCPCR);
351         /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
352         ctrl_outw(data & 0x0fcf, SCPCR);
353
354         if (cflag & CRTSCTS)
355                 fcr_val |= SCFCR_MCE;
356         else {
357                 /* We need to set SCPCR to enable RTS/CTS */
358                 data = ctrl_inw(SCPCR);
359                 /* Clear out SCP7MD1,0, SCP4MD1,0,
360                    Set SCP6MD1,0 = {01} (output)  */
361                 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
362
363                 data = ctrl_inb(SCPDR);
364                 /* Set /RTS2 (bit6) = 0 */
365                 ctrl_outb(data & 0xbf, SCPDR);
366         }
367
368         sci_out(port, SCFCR, fcr_val);
369 }
370
371 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
372 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
373 {
374         unsigned int fcr_val = 0;
375
376         if (cflag & CRTSCTS)
377                 fcr_val |= SCFCR_MCE;
378
379         sci_out(port, SCFCR, fcr_val);
380 }
381 #endif
382 #else
383
384 /* For SH7750 */
385 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
386 {
387         unsigned int fcr_val = 0;
388
389         if (cflag & CRTSCTS) {
390                 fcr_val |= SCFCR_MCE;
391         } else {
392 #ifdef CONFIG_CPU_SUBTYPE_SH7780
393                 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
394 #else
395                 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
396 #endif
397         }
398         sci_out(port, SCFCR, fcr_val);
399 }
400
401 #endif
402 #endif /* SCIF_ONLY || SCI_AND_SCIF */
403
404 /* ********************************************************************** *
405  *                   the interrupt related routines                       *
406  * ********************************************************************** */
407
408 static void sci_transmit_chars(struct uart_port *port)
409 {
410         struct circ_buf *xmit = &port->info->xmit;
411         unsigned int stopped = uart_tx_stopped(port);
412         unsigned long flags;
413         unsigned short status;
414         unsigned short ctrl;
415         int count, txroom;
416
417         status = sci_in(port, SCxSR);
418         if (!(status & SCxSR_TDxE(port))) {
419                 local_irq_save(flags);
420                 ctrl = sci_in(port, SCSCR);
421                 if (uart_circ_empty(xmit)) {
422                         ctrl &= ~SCI_CTRL_FLAGS_TIE;
423                 } else {
424                         ctrl |= SCI_CTRL_FLAGS_TIE;
425                 }
426                 sci_out(port, SCSCR, ctrl);
427                 local_irq_restore(flags);
428                 return;
429         }
430
431 #if !defined(SCI_ONLY)
432         if (port->type == PORT_SCIF) {
433 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
434                 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
435 #else
436                 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
437 #endif
438         } else {
439                 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
440         }
441 #else
442         txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
443 #endif
444
445         count = txroom;
446
447         do {
448                 unsigned char c;
449
450                 if (port->x_char) {
451                         c = port->x_char;
452                         port->x_char = 0;
453                 } else if (!uart_circ_empty(xmit) && !stopped) {
454                         c = xmit->buf[xmit->tail];
455                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
456                 } else {
457                         break;
458                 }
459
460                 sci_out(port, SCxTDR, c);
461
462                 port->icount.tx++;
463         } while (--count > 0);
464
465         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
466
467         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
468                 uart_write_wakeup(port);
469         if (uart_circ_empty(xmit)) {
470                 sci_stop_tx(port);
471         } else {
472                 local_irq_save(flags);
473                 ctrl = sci_in(port, SCSCR);
474
475 #if !defined(SCI_ONLY)
476                 if (port->type == PORT_SCIF) {
477                         sci_in(port, SCxSR); /* Dummy read */
478                         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
479                 }
480 #endif
481
482                 ctrl |= SCI_CTRL_FLAGS_TIE;
483                 sci_out(port, SCSCR, ctrl);
484                 local_irq_restore(flags);
485         }
486 }
487
488 /* On SH3, SCIF may read end-of-break as a space->mark char */
489 #define STEPFN(c)  ({int __c=(c); (((__c-1)|(__c)) == -1); })
490
491 static inline void sci_receive_chars(struct uart_port *port,
492                                      struct pt_regs *regs)
493 {
494         struct tty_struct *tty = port->info->tty;
495         int i, count, copied = 0;
496         unsigned short status;
497         unsigned char flag;
498
499         status = sci_in(port, SCxSR);
500         if (!(status & SCxSR_RDxF(port)))
501                 return;
502
503         while (1) {
504 #if !defined(SCI_ONLY)
505                 if (port->type == PORT_SCIF) {
506 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
507                         count = sci_in(port, SCRFDR) & 0x7f;
508 #else
509                         count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
510 #endif
511                 } else {
512                         count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
513                 }
514 #else
515                 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
516 #endif
517
518                 /* Don't copy more bytes than there is room for in the buffer */
519                 count = tty_buffer_request_room(tty, count);
520
521                 /* If for any reason we can't copy more data, we're done! */
522                 if (count == 0)
523                         break;
524
525                 if (port->type == PORT_SCI) {
526                         char c = sci_in(port, SCxRDR);
527                        if(((struct sci_port *)port)->break_flag
528                             || uart_handle_sysrq_char(port, c, regs)) {
529                                 count = 0;
530                         } else {
531                             tty_insert_flip_char(tty, c, TTY_NORMAL);
532                         }
533                 } else {
534                         for (i=0; i<count; i++) {
535                                 char c = sci_in(port, SCxRDR);
536                                 status = sci_in(port, SCxSR);
537 #if defined(CONFIG_CPU_SH3)
538                                 /* Skip "chars" during break */
539                                 if (((struct sci_port *)port)->break_flag) {
540                                         if ((c == 0) &&
541                                             (status & SCxSR_FER(port))) {
542                                                 count--; i--;
543                                                 continue;
544                                         }
545                                         /* Nonzero => end-of-break */
546                                         pr_debug("scif: debounce<%02x>\n", c);
547                                         ((struct sci_port *)port)->break_flag = 0;
548                                         if (STEPFN(c)) {
549                                                 count--; i--;
550                                                 continue;
551                                         }
552                                 }
553 #endif /* CONFIG_CPU_SH3 */
554                                 if (uart_handle_sysrq_char(port, c, regs)) {
555                                         count--; i--;
556                                         continue;
557                                 }
558
559                                 /* Store data and status */
560                                 if (status&SCxSR_FER(port)) {
561                                         flag = TTY_FRAME;
562                                         pr_debug("sci: frame error\n");
563                                 } else if (status&SCxSR_PER(port)) {
564                                         flag = TTY_PARITY;
565                                         pr_debug("sci: parity error\n");
566                                 } else
567                                         flag = TTY_NORMAL;
568                                 tty_insert_flip_char(tty, c, flag);
569                         }
570                 }
571
572                 sci_in(port, SCxSR); /* dummy read */
573                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
574
575                 copied += count;
576                 port->icount.rx += count;
577         }
578
579         if (copied) {
580                 /* Tell the rest of the system the news. New characters! */
581                 tty_flip_buffer_push(tty);
582         } else {
583                 sci_in(port, SCxSR); /* dummy read */
584                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
585         }
586 }
587
588 #define SCI_BREAK_JIFFIES (HZ/20)
589 /* The sci generates interrupts during the break,
590  * 1 per millisecond or so during the break period, for 9600 baud.
591  * So dont bother disabling interrupts.
592  * But dont want more than 1 break event.
593  * Use a kernel timer to periodically poll the rx line until
594  * the break is finished.
595  */
596 static void sci_schedule_break_timer(struct sci_port *port)
597 {
598         port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
599         add_timer(&port->break_timer);
600 }
601 /* Ensure that two consecutive samples find the break over. */
602 static void sci_break_timer(unsigned long data)
603 {
604     struct sci_port * port = (struct sci_port *)data;
605         if(sci_rxd_in(&port->port) == 0) {
606                 port->break_flag = 1;
607             sci_schedule_break_timer(port);
608         } else if(port->break_flag == 1){
609                 /* break is over. */
610                 port->break_flag = 2;
611             sci_schedule_break_timer(port);
612         } else port->break_flag = 0;
613 }
614
615 static inline int sci_handle_errors(struct uart_port *port)
616 {
617         int copied = 0;
618         unsigned short status = sci_in(port, SCxSR);
619         struct tty_struct *tty = port->info->tty;
620
621         if (status&SCxSR_ORER(port)) {
622                 /* overrun error */
623                 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN))
624                         copied++;
625                 pr_debug("sci: overrun error\n");
626         }
627
628         if (status&SCxSR_FER(port)) {
629                 if (sci_rxd_in(port) == 0) {
630                         /* Notify of BREAK */
631                         struct sci_port * sci_port = (struct sci_port *)port;
632                         if(!sci_port->break_flag) {
633                                 sci_port->break_flag = 1;
634                                 sci_schedule_break_timer((struct sci_port *)port);
635                                 /* Do sysrq handling. */
636                                 if(uart_handle_break(port))
637                                         return 0;
638                                 pr_debug("sci: BREAK detected\n");
639                                 if(tty_insert_flip_char(tty, 0, TTY_BREAK))
640                                         copied++;
641                        }
642                 }
643                 else {
644                         /* frame error */
645                         if(tty_insert_flip_char(tty, 0, TTY_FRAME))
646                                 copied++;
647                         pr_debug("sci: frame error\n");
648                 }
649         }
650
651         if (status&SCxSR_PER(port)) {
652                 if(tty_insert_flip_char(tty, 0, TTY_PARITY))
653                         copied++;
654                 /* parity error */
655                 pr_debug("sci: parity error\n");
656         }
657
658         if (copied)
659                 tty_flip_buffer_push(tty);
660
661         return copied;
662 }
663
664 static inline int sci_handle_breaks(struct uart_port *port)
665 {
666         int copied = 0;
667         unsigned short status = sci_in(port, SCxSR);
668         struct tty_struct *tty = port->info->tty;
669         struct sci_port *s = &sci_ports[port->line];
670
671         if (!s->break_flag && status & SCxSR_BRK(port)) {
672 #if defined(CONFIG_CPU_SH3)
673                 /* Debounce break */
674                 s->break_flag = 1;
675 #endif
676                 /* Notify of BREAK */
677                 if(tty_insert_flip_char(tty, 0, TTY_BREAK))
678                         copied++;
679                 pr_debug("sci: BREAK detected\n");
680         }
681
682 #if defined(SCIF_ORER)
683         /* XXX: Handle SCIF overrun error */
684         if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
685                 sci_out(port, SCLSR, 0);
686                 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
687                         copied++;
688                         pr_debug("sci: overrun error\n");
689                 }
690         }
691 #endif
692
693         if (copied)
694                 tty_flip_buffer_push(tty);
695         return copied;
696 }
697
698 static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs)
699 {
700         struct uart_port *port = ptr;
701
702         /* I think sci_receive_chars has to be called irrespective
703          * of whether the I_IXOFF is set, otherwise, how is the interrupt
704          * to be disabled?
705          */
706         sci_receive_chars(port, regs);
707
708         return IRQ_HANDLED;
709 }
710
711 static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
712 {
713         struct uart_port *port = ptr;
714
715         sci_transmit_chars(port);
716
717         return IRQ_HANDLED;
718 }
719
720 static irqreturn_t sci_er_interrupt(int irq, void *ptr, struct pt_regs *regs)
721 {
722         struct uart_port *port = ptr;
723
724         /* Handle errors */
725         if (port->type == PORT_SCI) {
726                 if (sci_handle_errors(port)) {
727                         /* discard character in rx buffer */
728                         sci_in(port, SCxSR);
729                         sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
730                 }
731         } else {
732 #if defined(SCIF_ORER)
733                 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
734                         struct tty_struct *tty = port->info->tty;
735
736                         sci_out(port, SCLSR, 0);
737                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
738                         tty_flip_buffer_push(tty);
739                         pr_debug("scif: overrun error\n");
740                 }
741 #endif
742                 sci_rx_interrupt(irq, ptr, regs);
743         }
744
745         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
746
747         /* Kick the transmission */
748         sci_tx_interrupt(irq, ptr, regs);
749
750         return IRQ_HANDLED;
751 }
752
753 static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
754 {
755         struct uart_port *port = ptr;
756
757         /* Handle BREAKs */
758         sci_handle_breaks(port);
759         sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
760
761         return IRQ_HANDLED;
762 }
763
764 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
765 {
766         unsigned short ssr_status, scr_status;
767         struct uart_port *port = ptr;
768
769         ssr_status = sci_in(port,SCxSR);
770         scr_status = sci_in(port,SCSCR);
771
772         /* Tx Interrupt */
773         if ((ssr_status&0x0020) && (scr_status&0x0080))
774                 sci_tx_interrupt(irq, ptr, regs);
775         /* Rx Interrupt */
776         if ((ssr_status&0x0002) && (scr_status&0x0040))
777                 sci_rx_interrupt(irq, ptr, regs);
778         /* Error Interrupt */
779         if ((ssr_status&0x0080) && (scr_status&0x0400))
780                 sci_er_interrupt(irq, ptr, regs);
781         /* Break Interrupt */
782         if ((ssr_status&0x0010) && (scr_status&0x0200))
783                 sci_br_interrupt(irq, ptr, regs);
784
785         return IRQ_HANDLED;
786 }
787
788 #ifdef CONFIG_CPU_FREQ
789 /*
790  * Here we define a transistion notifier so that we can update all of our
791  * ports' baud rate when the peripheral clock changes.
792  */
793 static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p)
794 {
795         struct cpufreq_freqs *freqs = p;
796         int i;
797
798         if ((phase == CPUFREQ_POSTCHANGE) ||
799             (phase == CPUFREQ_RESUMECHANGE)){
800                 for (i = 0; i < SCI_NPORTS; i++) {
801                         struct uart_port *port = &sci_ports[i].port;
802                         struct clk *clk;
803
804                         /*
805                          * Update the uartclk per-port if frequency has
806                          * changed, since it will no longer necessarily be
807                          * consistent with the old frequency.
808                          *
809                          * Really we want to be able to do something like
810                          * uart_change_speed() or something along those lines
811                          * here to implicitly reset the per-port baud rate..
812                          *
813                          * Clean this up later..
814                          */
815                         clk = clk_get("module_clk");
816                         port->uartclk = clk_get_rate(clk) * 16;
817                         clk_put(clk);
818                 }
819
820                 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
821                                 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
822         }
823
824         return NOTIFY_OK;
825 }
826
827 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
828 #endif /* CONFIG_CPU_FREQ */
829
830 static int sci_request_irq(struct sci_port *port)
831 {
832         int i;
833         irqreturn_t (*handlers[4])(int irq, void *ptr, struct pt_regs *regs) = {
834                 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
835                 sci_br_interrupt,
836         };
837         const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
838                                "SCI Transmit Data Empty", "SCI Break" };
839
840         if (port->irqs[0] == port->irqs[1]) {
841                 if (!port->irqs[0]) {
842                         printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
843                         return -ENODEV;
844                 }
845                 if (request_irq(port->irqs[0], sci_mpxed_interrupt, SA_INTERRUPT,
846                                 "sci", port)) {
847                         printk(KERN_ERR "sci: Cannot allocate irq.\n");
848                         return -ENODEV;
849                 }
850         } else {
851                 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
852                         if (!port->irqs[i])
853                                 continue;
854                         if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT,
855                                         desc[i], port)) {
856                                 printk(KERN_ERR "sci: Cannot allocate irq.\n");
857                                 return -ENODEV;
858                         }
859                 }
860         }
861
862         return 0;
863 }
864
865 static void sci_free_irq(struct sci_port *port)
866 {
867         int i;
868
869         if (port->irqs[0] == port->irqs[1]) {
870                 if (!port->irqs[0])
871                         printk("sci: sci_free_irq error\n");
872                 else
873                         free_irq(port->irqs[0], port);
874         } else {
875                 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
876                         if (!port->irqs[i])
877                                 continue;
878
879                         free_irq(port->irqs[i], port);
880                 }
881         }
882 }
883
884 static unsigned int sci_tx_empty(struct uart_port *port)
885 {
886         /* Can't detect */
887         return TIOCSER_TEMT;
888 }
889
890 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
891 {
892         /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
893         /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
894         /* If you have signals for DTR and DCD, please implement here. */
895 }
896
897 static unsigned int sci_get_mctrl(struct uart_port *port)
898 {
899         /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
900            and CTS/RTS */
901
902         return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
903 }
904
905 static void sci_start_tx(struct uart_port *port)
906 {
907         struct sci_port *s = &sci_ports[port->line];
908
909         disable_irq(s->irqs[SCIx_TXI_IRQ]);
910         sci_transmit_chars(port);
911         enable_irq(s->irqs[SCIx_TXI_IRQ]);
912 }
913
914 static void sci_stop_tx(struct uart_port *port)
915 {
916         unsigned long flags;
917         unsigned short ctrl;
918
919         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
920         local_irq_save(flags);
921         ctrl = sci_in(port, SCSCR);
922         ctrl &= ~SCI_CTRL_FLAGS_TIE;
923         sci_out(port, SCSCR, ctrl);
924         local_irq_restore(flags);
925 }
926
927 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
928 {
929         unsigned long flags;
930         unsigned short ctrl;
931
932         /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
933         local_irq_save(flags);
934         ctrl = sci_in(port, SCSCR);
935         ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
936         sci_out(port, SCSCR, ctrl);
937         local_irq_restore(flags);
938 }
939
940 static void sci_stop_rx(struct uart_port *port)
941 {
942         unsigned long flags;
943         unsigned short ctrl;
944
945         /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
946         local_irq_save(flags);
947         ctrl = sci_in(port, SCSCR);
948         ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
949         sci_out(port, SCSCR, ctrl);
950         local_irq_restore(flags);
951 }
952
953 static void sci_enable_ms(struct uart_port *port)
954 {
955         /* Nothing here yet .. */
956 }
957
958 static void sci_break_ctl(struct uart_port *port, int break_state)
959 {
960         /* Nothing here yet .. */
961 }
962
963 static int sci_startup(struct uart_port *port)
964 {
965         struct sci_port *s = &sci_ports[port->line];
966
967 #if defined(__H8300S__)
968         h8300_sci_enable(port, sci_enable);
969 #endif
970
971         sci_request_irq(s);
972         sci_start_tx(port);
973         sci_start_rx(port, 1);
974
975         return 0;
976 }
977
978 static void sci_shutdown(struct uart_port *port)
979 {
980         struct sci_port *s = &sci_ports[port->line];
981
982         sci_stop_rx(port);
983         sci_stop_tx(port);
984         sci_free_irq(s);
985
986 #if defined(__H8300S__)
987         h8300_sci_enable(port, sci_disable);
988 #endif
989 }
990
991 static void sci_set_termios(struct uart_port *port, struct termios *termios,
992                             struct termios *old)
993 {
994         struct sci_port *s = &sci_ports[port->line];
995         unsigned int status, baud, smr_val;
996         unsigned long flags;
997         int t;
998
999         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1000
1001         spin_lock_irqsave(&port->lock, flags);
1002
1003         do {
1004                 status = sci_in(port, SCxSR);
1005         } while (!(status & SCxSR_TEND(port)));
1006
1007         sci_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
1008
1009 #if !defined(SCI_ONLY)
1010         if (port->type == PORT_SCIF) {
1011                 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1012         }
1013 #endif
1014
1015         smr_val = sci_in(port, SCSMR) & 3;
1016         if ((termios->c_cflag & CSIZE) == CS7)
1017                 smr_val |= 0x40;
1018         if (termios->c_cflag & PARENB)
1019                 smr_val |= 0x20;
1020         if (termios->c_cflag & PARODD)
1021                 smr_val |= 0x30;
1022         if (termios->c_cflag & CSTOPB)
1023                 smr_val |= 0x08;
1024
1025         uart_update_timeout(port, termios->c_cflag, baud);
1026
1027         sci_out(port, SCSMR, smr_val);
1028
1029         switch (baud) {
1030                 case 0:
1031                         t = -1;
1032                         break;
1033                 default:
1034                 {
1035 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
1036                         struct clk *clk = clk_get("module_clk");
1037                         t = SCBRR_VALUE(baud, clk_get_rate(clk));
1038                         clk_put(clk);
1039 #else
1040                         t = SCBRR_VALUE(baud);
1041 #endif
1042                 }
1043                         break;
1044         }
1045
1046         if (t > 0) {
1047                 if(t >= 256) {
1048                         sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1049                         t >>= 2;
1050                 } else {
1051                         sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1052                 }
1053                 sci_out(port, SCBRR, t);
1054                 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1055         }
1056
1057         if (likely(s->init_pins))
1058                 s->init_pins(port, termios->c_cflag);
1059
1060         sci_out(port, SCSCR, SCSCR_INIT(port));
1061
1062         if ((termios->c_cflag & CREAD) != 0)
1063               sci_start_rx(port,0);
1064
1065         spin_unlock_irqrestore(&port->lock, flags);
1066 }
1067
1068 static const char *sci_type(struct uart_port *port)
1069 {
1070         switch (port->type) {
1071                 case PORT_SCI:  return "sci";
1072                 case PORT_SCIF: return "scif";
1073                 case PORT_IRDA: return "irda";
1074         }
1075
1076         return 0;
1077 }
1078
1079 static void sci_release_port(struct uart_port *port)
1080 {
1081         /* Nothing here yet .. */
1082 }
1083
1084 static int sci_request_port(struct uart_port *port)
1085 {
1086         /* Nothing here yet .. */
1087         return 0;
1088 }
1089
1090 static void sci_config_port(struct uart_port *port, int flags)
1091 {
1092         struct sci_port *s = &sci_ports[port->line];
1093
1094         port->type = s->type;
1095
1096 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1097         if (port->mapbase == 0)
1098                 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1099
1100         port->membase = (void *)port->mapbase;
1101 #endif
1102 }
1103
1104 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1105 {
1106         struct sci_port *s = &sci_ports[port->line];
1107
1108         if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1109                 return -EINVAL;
1110         if (ser->baud_base < 2400)
1111                 /* No paper tape reader for Mitch.. */
1112                 return -EINVAL;
1113
1114         return 0;
1115 }
1116
1117 static struct uart_ops sci_uart_ops = {
1118         .tx_empty       = sci_tx_empty,
1119         .set_mctrl      = sci_set_mctrl,
1120         .get_mctrl      = sci_get_mctrl,
1121         .start_tx       = sci_start_tx,
1122         .stop_tx        = sci_stop_tx,
1123         .stop_rx        = sci_stop_rx,
1124         .enable_ms      = sci_enable_ms,
1125         .break_ctl      = sci_break_ctl,
1126         .startup        = sci_startup,
1127         .shutdown       = sci_shutdown,
1128         .set_termios    = sci_set_termios,
1129         .type           = sci_type,
1130         .release_port   = sci_release_port,
1131         .request_port   = sci_request_port,
1132         .config_port    = sci_config_port,
1133         .verify_port    = sci_verify_port,
1134 };
1135
1136 static struct sci_port sci_ports[] = {
1137 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
1138         {
1139                 .port   = {
1140                         .membase        = (void *)0xfffffe80,
1141                         .mapbase        = 0xfffffe80,
1142                         .iotype         = UPIO_MEM,
1143                         .irq            = 25,
1144                         .ops            = &sci_uart_ops,
1145                         .flags          = UPF_BOOT_AUTOCONF,
1146                         .line           = 0,
1147                 },
1148                 .type           = PORT_SCI,
1149                 .irqs           = SCI_IRQS,
1150         },
1151 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
1152         {
1153                 .port   = {
1154                         .membase        = (void *)SCIF0,
1155                         .mapbase        = SCIF0,
1156                         .iotype         = UPIO_MEM,
1157                         .irq            = 55,
1158                         .ops            = &sci_uart_ops,
1159                         .flags          = UPF_BOOT_AUTOCONF,
1160                         .line           = 0,
1161                 },
1162                 .type           = PORT_SCIF,
1163                 .irqs           = SH3_IRDA_IRQS,
1164                 .init_pins      = sci_init_pins_scif,
1165         },
1166         {
1167                 .port   = {
1168                         .membase        = (void *)SCIF2,
1169                         .mapbase        = SCIF2,
1170                         .iotype         = UPIO_MEM,
1171                         .irq            = 59,
1172                         .ops            = &sci_uart_ops,
1173                         .flags          = UPF_BOOT_AUTOCONF,
1174                         .line           = 1,
1175                 },
1176                 .type           = PORT_SCIF,
1177                 .irqs           = SH3_SCIF_IRQS,
1178                 .init_pins      = sci_init_pins_scif,
1179         }
1180 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1181         {
1182                 .port   = {
1183                         .membase        = (void *)0xfffffe80,
1184                         .mapbase        = 0xfffffe80,
1185                         .iotype         = UPIO_MEM,
1186                         .irq            = 25,
1187                         .ops            = &sci_uart_ops,
1188                         .flags          = UPF_BOOT_AUTOCONF,
1189                         .line           = 0,
1190                 },
1191                 .type           = PORT_SCI,
1192                 .irqs           = SCI_IRQS,
1193         },
1194         {
1195                 .port   = {
1196                         .membase        = (void *)0xa4000150,
1197                         .mapbase        = 0xa4000150,
1198                         .iotype         = UPIO_MEM,
1199                         .irq            = 59,
1200                         .ops            = &sci_uart_ops,
1201                         .flags          = UPF_BOOT_AUTOCONF,
1202                         .line           = 1,
1203                 },
1204                 .type           = PORT_SCIF,
1205                 .irqs           = SH3_SCIF_IRQS,
1206                 .init_pins      = sci_init_pins_scif,
1207         },
1208         {
1209                 .port   = {
1210                         .membase        = (void *)0xa4000140,
1211                         .mapbase        = 0xa4000140,
1212                         .iotype         = UPIO_MEM,
1213                         .irq            = 55,
1214                         .ops            = &sci_uart_ops,
1215                         .flags          = UPF_BOOT_AUTOCONF,
1216                         .line           = 2,
1217                 },
1218                 .type           = PORT_IRDA,
1219                 .irqs           = SH3_IRDA_IRQS,
1220                 .init_pins      = sci_init_pins_irda,
1221         }
1222 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1223         {
1224                 .port   = {
1225                         .membase        = (void *)0xA4430000,
1226                         .mapbase        = 0xA4430000,
1227                         .iotype         = UPIO_MEM,
1228                         .irq            = 25,
1229                         .ops            = &sci_uart_ops,
1230                         .flags          = UPF_BOOT_AUTOCONF,
1231                         .line           = 0,
1232                 },
1233                 .type           = PORT_SCIF,
1234                 .irqs           = SH7300_SCIF0_IRQS,
1235                 .init_pins      = sci_init_pins_scif,
1236         },
1237 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1238         {
1239                 .port   = {
1240                         .membase        = (void *)0xffe00000,
1241                         .mapbase        = 0xffe00000,
1242                         .iotype         = UPIO_MEM,
1243                         .irq            = 25,
1244                         .ops            = &sci_uart_ops,
1245                         .flags          = UPF_BOOT_AUTOCONF,
1246                         .line           = 0,
1247                 },
1248                 .type           = PORT_SCIF,
1249                 .irqs           = SH73180_SCIF_IRQS,
1250                 .init_pins      = sci_init_pins_scif,
1251         },
1252 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1253         {
1254                 .port   = {
1255                         .membase        = (void *)0xffe80000,
1256                         .mapbase        = 0xffe80000,
1257                         .iotype         = UPIO_MEM,
1258                         .irq            = 43,
1259                         .ops            = &sci_uart_ops,
1260                         .flags          = UPF_BOOT_AUTOCONF,
1261                         .line           = 0,
1262                 },
1263                 .type           = PORT_SCIF,
1264                 .irqs           = SH4_SCIF_IRQS,
1265                 .init_pins      = sci_init_pins_scif,
1266         },
1267 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1268         {
1269                 .port   = {
1270                         .membase        = (void *)0xffe00000,
1271                         .mapbase        = 0xffe00000,
1272                         .iotype         = UPIO_MEM,
1273                         .irq            = 25,
1274                         .ops            = &sci_uart_ops,
1275                         .flags          = UPF_BOOT_AUTOCONF,
1276                         .line           = 0,
1277                 },
1278                 .type           = PORT_SCI,
1279                 .irqs           = SCI_IRQS,
1280         },
1281         {
1282                 .port   = {
1283                         .membase        = (void *)0xffe80000,
1284                         .mapbase        = 0xffe80000,
1285                         .iotype         = UPIO_MEM,
1286                         .irq            = 43,
1287                         .ops            = &sci_uart_ops,
1288                         .flags          = UPF_BOOT_AUTOCONF,
1289                         .line           = 1,
1290                 },
1291                 .type           = PORT_SCIF,
1292                 .irqs           = SH4_SCIF_IRQS,
1293                 .init_pins      = sci_init_pins_scif,
1294         },
1295 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1296         {
1297                 .port   = {
1298                         .membase        = (void *)0xfe600000,
1299                         .mapbase        = 0xfe600000,
1300                         .iotype         = UPIO_MEM,
1301                         .irq            = 55,
1302                         .ops            = &sci_uart_ops,
1303                         .flags          = UPF_BOOT_AUTOCONF,
1304                         .line           = 0,
1305                 },
1306                 .type           = PORT_SCIF,
1307                 .irqs           = SH7760_SCIF0_IRQS,
1308                 .init_pins      = sci_init_pins_scif,
1309         },
1310         {
1311                 .port   = {
1312                         .membase        = (void *)0xfe610000,
1313                         .mapbase        = 0xfe610000,
1314                         .iotype         = UPIO_MEM,
1315                         .irq            = 75,
1316                         .ops            = &sci_uart_ops,
1317                         .flags          = UPF_BOOT_AUTOCONF,
1318                         .line           = 1,
1319                 },
1320                 .type           = PORT_SCIF,
1321                 .irqs           = SH7760_SCIF1_IRQS,
1322                 .init_pins      = sci_init_pins_scif,
1323         },
1324         {
1325                 .port   = {
1326                         .membase        = (void *)0xfe620000,
1327                         .mapbase        = 0xfe620000,
1328                         .iotype         = UPIO_MEM,
1329                         .irq            = 79,
1330                         .ops            = &sci_uart_ops,
1331                         .flags          = UPF_BOOT_AUTOCONF,
1332                         .line           = 2,
1333                 },
1334                 .type           = PORT_SCIF,
1335                 .irqs           = SH7760_SCIF2_IRQS,
1336                 .init_pins      = sci_init_pins_scif,
1337         },
1338 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1339         {
1340                 .port   = {
1341                         .membase        = (void *)0xffe00000,
1342                         .mapbase        = 0xffe00000,
1343                         .iotype         = UPIO_MEM,
1344                         .irq            = 26,
1345                         .ops            = &sci_uart_ops,
1346                         .flags          = UPF_BOOT_AUTOCONF,
1347                         .line           = 0,
1348                 },
1349                 .type           = PORT_SCIF,
1350                 .irqs           = STB1_SCIF1_IRQS,
1351                 .init_pins      = sci_init_pins_scif,
1352         },
1353         {
1354                 .port   = {
1355                         .membase        = (void *)0xffe80000,
1356                         .mapbase        = 0xffe80000,
1357                         .iotype         = UPIO_MEM,
1358                         .irq            = 43,
1359                         .ops            = &sci_uart_ops,
1360                         .flags          = UPF_BOOT_AUTOCONF,
1361                         .line           = 1,
1362                 },
1363                 .type           = PORT_SCIF,
1364                 .irqs           = SH4_SCIF_IRQS,
1365                 .init_pins      = sci_init_pins_scif,
1366         },
1367 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1368         {
1369                 .port   = {
1370                         .iotype         = UPIO_MEM,
1371                         .irq            = 42,
1372                         .ops            = &sci_uart_ops,
1373                         .flags          = UPF_BOOT_AUTOCONF,
1374                         .line           = 0,
1375                 },
1376                 .type           = PORT_SCIF,
1377                 .irqs           = SH5_SCIF_IRQS,
1378                 .init_pins      = sci_init_pins_scif,
1379         },
1380 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1381         {
1382                 .port   = {
1383                         .membase        = (void *)0x00ffffb0,
1384                         .mapbase        = 0x00ffffb0,
1385                         .iotype         = UPIO_MEM,
1386                         .irq            = 54,
1387                         .ops            = &sci_uart_ops,
1388                         .flags          = UPF_BOOT_AUTOCONF,
1389                         .line           = 0,
1390                 },
1391                 .type           = PORT_SCI,
1392                 .irqs           = H8300H_SCI_IRQS0,
1393                 .init_pins      = sci_init_pins_sci,
1394         },
1395         {
1396                 .port   = {
1397                         .membase        = (void *)0x00ffffb8,
1398                         .mapbase        = 0x00ffffb8,
1399                         .iotype         = UPIO_MEM,
1400                         .irq            = 58,
1401                         .ops            = &sci_uart_ops,
1402                         .flags          = UPF_BOOT_AUTOCONF,
1403                         .line           = 1,
1404                 },
1405                 .type           = PORT_SCI,
1406                 .irqs           = H8300H_SCI_IRQS1,
1407                 .init_pins      = sci_init_pins_sci,
1408         },
1409         {
1410                 .port   = {
1411                         .membase        = (void *)0x00ffffc0,
1412                         .mapbase        = 0x00ffffc0,
1413                         .iotype         = UPIO_MEM,
1414                         .irq            = 62,
1415                         .ops            = &sci_uart_ops,
1416                         .flags          = UPF_BOOT_AUTOCONF,
1417                         .line           = 2,
1418                 },
1419                 .type           = PORT_SCI,
1420                 .irqs           = H8300H_SCI_IRQS2,
1421                 .init_pins      = sci_init_pins_sci,
1422         },
1423 #elif defined(CONFIG_H8S2678)
1424         {
1425                 .port   = {
1426                         .membase        = (void *)0x00ffff78,
1427                         .mapbase        = 0x00ffff78,
1428                         .iotype         = UPIO_MEM,
1429                         .irq            = 90,
1430                         .ops            = &sci_uart_ops,
1431                         .flags          = UPF_BOOT_AUTOCONF,
1432                         .line           = 0,
1433                 },
1434                 .type           = PORT_SCI,
1435                 .irqs           = H8S_SCI_IRQS0,
1436                 .init_pins      = sci_init_pins_sci,
1437         },
1438         {
1439                 .port   = {
1440                         .membase        = (void *)0x00ffff80,
1441                         .mapbase        = 0x00ffff80,
1442                         .iotype         = UPIO_MEM,
1443                         .irq            = 94,
1444                         .ops            = &sci_uart_ops,
1445                         .flags          = UPF_BOOT_AUTOCONF,
1446                         .line           = 1,
1447                 },
1448                 .type           = PORT_SCI,
1449                 .irqs           = H8S_SCI_IRQS1,
1450                 .init_pins      = sci_init_pins_sci,
1451         },
1452         {
1453                 .port   = {
1454                         .membase        = (void *)0x00ffff88,
1455                         .mapbase        = 0x00ffff88,
1456                         .iotype         = UPIO_MEM,
1457                         .irq            = 98,
1458                         .ops            = &sci_uart_ops,
1459                         .flags          = UPF_BOOT_AUTOCONF,
1460                         .line           = 2,
1461                 },
1462                 .type           = PORT_SCI,
1463                 .irqs           = H8S_SCI_IRQS2,
1464                 .init_pins      = sci_init_pins_sci,
1465         },
1466 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
1467         {
1468                 .port   = {
1469                         .membase        = (void *)0xff923000,
1470                         .mapbase        = 0xff923000,
1471                         .iotype         = SERIAL_IO_MEM,
1472                         .irq            = 61,
1473                         .ops            = &sci_uart_ops,
1474                         .flags          = ASYNC_BOOT_AUTOCONF,
1475                         .line           = 0,
1476                 },
1477                 .type           = PORT_SCIF,
1478                 .irqs           = SH7770_SCIF0_IRQS,
1479                 .init_pins      = sci_init_pins_scif,
1480         },
1481         {
1482                 .port   = {
1483                         .membase        = (void *)0xff924000,
1484                         .mapbase        = 0xff924000,
1485                         .iotype         = SERIAL_IO_MEM,
1486                         .irq            = 62,
1487                         .ops            = &sci_uart_ops,
1488                         .flags          = ASYNC_BOOT_AUTOCONF,
1489                         .line           = 1,
1490                 },
1491                 .type           = PORT_SCIF,
1492                 .irqs           = SH7770_SCIF1_IRQS,
1493                 .init_pins      = sci_init_pins_scif,
1494         },
1495         {
1496                 .port   = {
1497                         .membase        = (void *)0xff925000,
1498                         .mapbase        = 0xff925000,
1499                         .iotype         = SERIAL_IO_MEM,
1500                         .irq            = 63,
1501                         .ops            = &sci_uart_ops,
1502                         .flags          = ASYNC_BOOT_AUTOCONF,
1503                         .line           = 2,
1504                 },
1505                 .type           = PORT_SCIF,
1506                 .irqs           = SH7770_SCIF2_IRQS,
1507                 .init_pins      = sci_init_pins_scif,
1508         },
1509 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
1510         {
1511                 .port   = {
1512                         .membase        = (void *)0xffe00000,
1513                         .mapbase        = 0xffe00000,
1514                         .iotype         = SERIAL_IO_MEM,
1515                         .irq            = 43,
1516                         .ops            = &sci_uart_ops,
1517                         .flags          = ASYNC_BOOT_AUTOCONF,
1518                         .line           = 0,
1519                 },
1520                 .type           = PORT_SCIF,
1521                 .irqs           = SH7780_SCIF0_IRQS,
1522                 .init_pins      = sci_init_pins_scif,
1523         },
1524         {
1525                 .port   = {
1526                         .membase        = (void *)0xffe10000,
1527                         .mapbase        = 0xffe10000,
1528                         .iotype         = SERIAL_IO_MEM,
1529                         .irq            = 79,
1530                         .ops            = &sci_uart_ops,
1531                         .flags          = ASYNC_BOOT_AUTOCONF,
1532                         .line           = 1,
1533                 },
1534                 .type           = PORT_SCIF,
1535                 .irqs           = SH7780_SCIF1_IRQS,
1536                 .init_pins      = sci_init_pins_scif,
1537         },
1538 #else
1539 #error "CPU subtype not defined"
1540 #endif
1541 };
1542
1543 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1544 /*
1545  *      Print a string to the serial port trying not to disturb
1546  *      any possible real use of the port...
1547  */
1548 static void serial_console_write(struct console *co, const char *s,
1549                                  unsigned count)
1550 {
1551         put_string(serial_console_port, s, count);
1552 }
1553
1554 static int __init serial_console_setup(struct console *co, char *options)
1555 {
1556         struct uart_port *port;
1557         int baud = 115200;
1558         int bits = 8;
1559         int parity = 'n';
1560         int flow = 'n';
1561         int ret;
1562
1563         serial_console_port = &sci_ports[co->index];
1564         port = &serial_console_port->port;
1565         port->type = serial_console_port->type;
1566
1567 #ifdef CONFIG_SUPERH64
1568         /* This is especially needed on sh64 to remap the SCIF */
1569         sci_config_port(port, 0);
1570 #endif
1571
1572         /*
1573          * We need to set the initial uartclk here, since otherwise it will
1574          * only ever be setup at sci_init() time.
1575          */
1576 #if defined(__H8300H__) || defined(__H8300S__)
1577         port->uartclk = CONFIG_CPU_CLOCK;
1578
1579 #if defined(__H8300S__)
1580         h8300_sci_enable(port, sci_enable);
1581 #endif
1582 #elif defined(CONFIG_SUPERH64)
1583         port->uartclk = current_cpu_info.module_clock * 16;
1584 #else
1585         {
1586                 struct clk *clk = clk_get("module_clk");
1587                 port->uartclk = clk_get_rate(clk) * 16;
1588                 clk_put(clk);
1589         }
1590 #endif
1591         if (options)
1592                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1593
1594         ret = uart_set_options(port, co, baud, parity, bits, flow);
1595 #if defined(__H8300H__) || defined(__H8300S__)
1596         /* disable rx interrupt */
1597         if (ret == 0)
1598                 sci_stop_rx(port);
1599 #endif
1600         return ret;
1601 }
1602
1603 static struct console serial_console = {
1604         .name           = "ttySC",
1605         .device         = uart_console_device,
1606         .write          = serial_console_write,
1607         .setup          = serial_console_setup,
1608         .flags          = CON_PRINTBUFFER,
1609         .index          = -1,
1610         .data           = &sci_uart_driver,
1611 };
1612
1613 static int __init sci_console_init(void)
1614 {
1615         register_console(&serial_console);
1616         return 0;
1617 }
1618
1619 console_initcall(sci_console_init);
1620 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1621
1622 #ifdef CONFIG_SH_KGDB
1623 /*
1624  * FIXME: Most of this can go away.. at the moment, we rely on
1625  * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1626  * most of that can easily be done here instead.
1627  *
1628  * For the time being, just accept the values that were parsed earlier..
1629  */
1630 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1631                                             int *parity, int *bits)
1632 {
1633         *baud = kgdb_baud;
1634         *parity = tolower(kgdb_parity);
1635         *bits = kgdb_bits - '0';
1636 }
1637
1638 /*
1639  * The naming here is somewhat misleading, since kgdb_console_setup() takes
1640  * care of the early-on initialization for kgdb, regardless of whether we
1641  * actually use kgdb as a console or not.
1642  *
1643  * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1644  */
1645 int __init kgdb_console_setup(struct console *co, char *options)
1646 {
1647         struct uart_port *port = &sci_ports[kgdb_portnum].port;
1648         int baud = 38400;
1649         int bits = 8;
1650         int parity = 'n';
1651         int flow = 'n';
1652
1653         if (co->index != kgdb_portnum)
1654                 co->index = kgdb_portnum;
1655
1656         if (options)
1657                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1658         else
1659                 kgdb_console_get_options(port, &baud, &parity, &bits);
1660
1661         kgdb_getchar = kgdb_sci_getchar;
1662         kgdb_putchar = kgdb_sci_putchar;
1663
1664         return uart_set_options(port, co, baud, parity, bits, flow);
1665 }
1666 #endif /* CONFIG_SH_KGDB */
1667
1668 #ifdef CONFIG_SH_KGDB_CONSOLE
1669 static struct console kgdb_console = {
1670         .name           = "ttySC",
1671         .write          = kgdb_console_write,
1672         .setup          = kgdb_console_setup,
1673         .flags          = CON_PRINTBUFFER | CON_ENABLED,
1674         .index          = -1,
1675         .data           = &sci_uart_driver,
1676 };
1677
1678 /* Register the KGDB console so we get messages (d'oh!) */
1679 static int __init kgdb_console_init(void)
1680 {
1681         register_console(&kgdb_console);
1682         return 0;
1683 }
1684
1685 console_initcall(kgdb_console_init);
1686 #endif /* CONFIG_SH_KGDB_CONSOLE */
1687
1688 #if defined(CONFIG_SH_KGDB_CONSOLE)
1689 #define SCI_CONSOLE     &kgdb_console
1690 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1691 #define SCI_CONSOLE     &serial_console
1692 #else
1693 #define SCI_CONSOLE     0
1694 #endif
1695
1696 static char banner[] __initdata =
1697         KERN_INFO "SuperH SCI(F) driver initialized\n";
1698
1699 static struct uart_driver sci_uart_driver = {
1700         .owner          = THIS_MODULE,
1701         .driver_name    = "sci",
1702 #ifdef CONFIG_DEVFS_FS
1703         .devfs_name     = "ttsc/",
1704 #endif
1705         .dev_name       = "ttySC",
1706         .major          = SCI_MAJOR,
1707         .minor          = SCI_MINOR_START,
1708         .cons           = SCI_CONSOLE,
1709 };
1710
1711 static int __init sci_init(void)
1712 {
1713         int chan, ret;
1714
1715         printk("%s", banner);
1716
1717         sci_uart_driver.nr = ARRAY_SIZE(sci_ports);
1718
1719         ret = uart_register_driver(&sci_uart_driver);
1720         if (ret == 0) {
1721                 for (chan = 0; chan < SCI_NPORTS; chan++) {
1722                         struct sci_port *sciport = &sci_ports[chan];
1723
1724 #if defined(__H8300H__) || defined(__H8300S__)
1725                         sciport->port.uartclk = CONFIG_CPU_CLOCK;
1726 #elif defined(CONFIG_SUPERH64)
1727                         sciport->port.uartclk = current_cpu_info.module_clock * 16;
1728 #else
1729                         struct clk *clk = clk_get("module_clk");
1730                         sciport->port.uartclk = clk_get_rate(clk) * 16;
1731                         clk_put(clk);
1732 #endif
1733                         uart_add_one_port(&sci_uart_driver, &sciport->port);
1734                         sciport->break_timer.data = (unsigned long)sciport;
1735                         sciport->break_timer.function = sci_break_timer;
1736                         init_timer(&sciport->break_timer);
1737                 }
1738         }
1739
1740 #ifdef CONFIG_CPU_FREQ
1741         cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1742         printk("sci: CPU frequency notifier registered\n");
1743 #endif
1744
1745 #ifdef CONFIG_SH_STANDARD_BIOS
1746         sh_bios_gdb_detach();
1747 #endif
1748
1749         return ret;
1750 }
1751
1752 static void __exit sci_exit(void)
1753 {
1754         int chan;
1755
1756         for (chan = 0; chan < SCI_NPORTS; chan++)
1757                 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port);
1758
1759         uart_unregister_driver(&sci_uart_driver);
1760 }
1761
1762 module_init(sci_init);
1763 module_exit(sci_exit);
1764