[SERIAL] Clean up and fix tty transmission start/stoping
[linux-2.6.git] / drivers / serial / sh-sci.c
1 /*
2  * drivers/serial/sh-sci.c
3  *
4  * SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
5  *
6  *  Copyright (C) 2002, 2003, 2004  Paul Mundt
7  *
8  * based off of the old drivers/char/sh-sci.c by:
9  *
10  *   Copyright (C) 1999, 2000  Niibe Yutaka
11  *   Copyright (C) 2000  Sugioka Toshinobu
12  *   Modified to support multiple serial ports. Stuart Menefy (May 2000).
13  *   Modified to support SecureEdge. David McCullough (2002)
14  *   Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15  *
16  * This file is subject to the terms and conditions of the GNU General Public
17  * License.  See the file "COPYING" in the main directory of this archive
18  * for more details.
19  */
20
21 #undef DEBUG
22
23 #include <linux/config.h>
24 #include <linux/module.h>
25 #include <linux/errno.h>
26 #include <linux/signal.h>
27 #include <linux/sched.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/fcntl.h>
37 #include <linux/ptrace.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/slab.h>
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/console.h>
44 #include <linux/bitops.h>
45
46 #ifdef CONFIG_CPU_FREQ
47 #include <linux/notifier.h>
48 #include <linux/cpufreq.h>
49 #endif
50
51 #include <asm/system.h>
52 #include <asm/io.h>
53 #include <asm/irq.h>
54 #include <asm/uaccess.h>
55
56 #include <linux/generic_serial.h>
57
58 #ifdef CONFIG_SH_STANDARD_BIOS
59 #include <asm/sh_bios.h>
60 #endif
61
62 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
63 #define SUPPORT_SYSRQ
64 #endif
65
66 #include "sh-sci.h"
67
68 #ifdef CONFIG_SH_KGDB
69 #include <asm/kgdb.h>
70
71 static int kgdb_get_char(struct sci_port *port);
72 static void kgdb_put_char(struct sci_port *port, char c);
73 static void kgdb_handle_error(struct sci_port *port);
74 static struct sci_port *kgdb_sci_port;
75 #endif /* CONFIG_SH_KGDB */
76
77 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
78 static struct sci_port *serial_console_port = 0;
79 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
80
81 /* Function prototypes */
82 static void sci_stop_tx(struct uart_port *port);
83 static void sci_start_tx(struct uart_port *port);
84 static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
85 static void sci_stop_rx(struct uart_port *port);
86 static int sci_request_irq(struct sci_port *port);
87 static void sci_free_irq(struct sci_port *port);
88
89 static struct sci_port sci_ports[SCI_NPORTS];
90 static struct uart_driver sci_uart_driver;
91
92 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
93
94 static void handle_error(struct uart_port *port)
95 {                               /* Clear error flags */
96         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
97 }
98
99 static int get_char(struct uart_port *port)
100 {
101         unsigned long flags;
102         unsigned short status;
103         int c;
104
105         local_irq_save(flags);
106         do {
107                 status = sci_in(port, SCxSR);
108                 if (status & SCxSR_ERRORS(port)) {
109                         handle_error(port);
110                         continue;
111                 }
112         } while (!(status & SCxSR_RDxF(port)));
113         c = sci_in(port, SCxRDR);
114         sci_in(port, SCxSR);            /* Dummy read */
115         sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
116         local_irq_restore(flags);
117
118         return c;
119 }
120
121 /* Taken from sh-stub.c of GDB 4.18 */
122 static const char hexchars[] = "0123456789abcdef";
123
124 static __inline__ char highhex(int  x)
125 {
126         return hexchars[(x >> 4) & 0xf];
127 }
128
129 static __inline__ char lowhex(int  x)
130 {
131         return hexchars[x & 0xf];
132 }
133
134 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
135
136 /*
137  * Send the packet in buffer.  The host gets one chance to read it.
138  * This routine does not wait for a positive acknowledge.
139  */
140
141 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
142 static void put_char(struct uart_port *port, char c)
143 {
144         unsigned long flags;
145         unsigned short status;
146
147         local_irq_save(flags);
148
149         do {
150                 status = sci_in(port, SCxSR);
151         } while (!(status & SCxSR_TDxE(port)));
152
153         sci_out(port, SCxTDR, c);
154         sci_in(port, SCxSR);            /* Dummy read */
155         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
156
157         local_irq_restore(flags);
158 }
159
160 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
161 {
162         struct uart_port *port = &sci_port->port;
163         const unsigned char *p = buffer;
164         int i;
165
166 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
167         int checksum;
168         int usegdb=0;
169
170 #ifdef CONFIG_SH_STANDARD_BIOS
171         /* This call only does a trap the first time it is
172          * called, and so is safe to do here unconditionally
173          */
174         usegdb |= sh_bios_in_gdb_mode();
175 #endif
176 #ifdef CONFIG_SH_KGDB
177         usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
178 #endif
179
180         if (usegdb) {
181             /*  $<packet info>#<checksum>. */
182             do {
183                 unsigned char c;
184                 put_char(port, '$');
185                 put_char(port, 'O'); /* 'O'utput to console */
186                 checksum = 'O';
187
188                 for (i=0; i<count; i++) { /* Don't use run length encoding */
189                         int h, l;
190
191                         c = *p++;
192                         h = highhex(c);
193                         l = lowhex(c);
194                         put_char(port, h);
195                         put_char(port, l);
196                         checksum += h + l;
197                 }
198                 put_char(port, '#');
199                 put_char(port, highhex(checksum));
200                 put_char(port, lowhex(checksum));
201             } while  (get_char(port) != '+');
202         } else
203 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
204         for (i=0; i<count; i++) {
205                 if (*p == 10)
206                         put_char(port, '\r');
207                 put_char(port, *p++);
208         }
209 }
210 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
211
212
213 #ifdef CONFIG_SH_KGDB
214
215 /* Is the SCI ready, ie is there a char waiting? */
216 static int kgdb_is_char_ready(struct sci_port *port)
217 {
218         unsigned short status = sci_in(port, SCxSR);
219
220         if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
221                 kgdb_handle_error(port);
222
223         return (status & SCxSR_RDxF(port));
224 }
225
226 /* Write a char */
227 static void kgdb_put_char(struct sci_port *port, char c)
228 {
229         unsigned short status;
230
231         do
232                 status = sci_in(port, SCxSR);
233         while (!(status & SCxSR_TDxE(port)));
234
235         sci_out(port, SCxTDR, c);
236         sci_in(port, SCxSR);    /* Dummy read */
237         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
238 }
239
240 /* Get a char if there is one, else ret -1 */
241 static int kgdb_get_char(struct sci_port *port)
242 {
243         int c;
244
245         if (kgdb_is_char_ready(port) == 0)
246                 c = -1;
247         else {
248                 c = sci_in(port, SCxRDR);
249                 sci_in(port, SCxSR);    /* Dummy read */
250                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
251         }
252
253         return c;
254 }
255
256 /* Called from kgdbstub.c to get a character, i.e. is blocking */
257 static int kgdb_sci_getchar(void)
258 {
259         volatile int c;
260
261         /* Keep trying to read a character, this could be neater */
262         while ((c = kgdb_get_char(kgdb_sci_port)) < 0);
263
264         return c;
265 }
266
267 /* Called from kgdbstub.c to put a character, just a wrapper */
268 static void kgdb_sci_putchar(int c)
269 {
270
271         kgdb_put_char(kgdb_sci_port, c);
272 }
273
274 /* Clear any errors on the SCI */
275 static void kgdb_handle_error(struct sci_port *port)
276 {
277         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));  /* Clear error flags */
278 }
279
280 /* Breakpoint if there's a break sent on the serial port */
281 static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
282 {
283         struct sci_port *port = ptr;
284         unsigned short status = sci_in(port, SCxSR);
285
286         if (status & SCxSR_BRK(port)) {
287
288                 /* Break into the debugger if a break is detected */
289                 BREAKPOINT();
290
291                 /* Clear */
292                 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
293         }
294 }
295
296 #endif /* CONFIG_SH_KGDB */
297
298 #if defined(__H8300S__)
299 enum { sci_disable, sci_enable };
300
301 static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
302 {
303         volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
304         int ch = (port->mapbase  - SMR0) >> 3;
305         unsigned char mask = 1 << (ch+1);
306
307         if (ctrl == sci_disable) {
308                 *mstpcrl |= mask;
309         } else {
310                 *mstpcrl &= ~mask;
311         }
312 }
313 #endif
314
315 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF)
316 #if defined(__H8300H__) || defined(__H8300S__)
317 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
318 {
319         int ch = (port->mapbase - SMR0) >> 3;
320
321         /* set DDR regs */
322         H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT);
323         H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT);
324         /* tx mark output*/
325         H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
326 }
327 #else
328 static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
329 {
330 }
331 #endif
332 #endif
333
334 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
335 #if defined(CONFIG_CPU_SH3)
336 /* For SH7705, SH7707, SH7709, SH7709A, SH7729, SH7300*/
337 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
338 {
339         unsigned int fcr_val = 0;
340 #if !defined(CONFIG_CPU_SUBTYPE_SH7300) /* SH7300 doesn't use RTS/CTS */
341         {
342                 unsigned short data;
343
344                 /* We need to set SCPCR to enable RTS/CTS */
345                 data = ctrl_inw(SCPCR);
346                 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
347                 ctrl_outw(data&0x0fcf, SCPCR);
348         }
349         if (cflag & CRTSCTS)
350                 fcr_val |= SCFCR_MCE;
351         else {
352                 unsigned short data;
353
354                 /* We need to set SCPCR to enable RTS/CTS */
355                 data = ctrl_inw(SCPCR);
356                 /* Clear out SCP7MD1,0, SCP4MD1,0,
357                    Set SCP6MD1,0 = {01} (output)  */
358                 ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
359
360                 data = ctrl_inb(SCPDR);
361                 /* Set /RTS2 (bit6) = 0 */
362                 ctrl_outb(data&0xbf, SCPDR);
363         }
364 #endif
365         sci_out(port, SCFCR, fcr_val);
366 }
367
368 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
369 {
370         unsigned int fcr_val = 0;
371
372         if (cflag & CRTSCTS)
373                 fcr_val |= SCFCR_MCE;
374
375         sci_out(port, SCFCR, fcr_val);
376 }
377
378 #else
379
380 /* For SH7750 */
381 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
382 {
383         unsigned int fcr_val = 0;
384
385         if (cflag & CRTSCTS) {
386                 fcr_val |= SCFCR_MCE;
387         } else {
388                 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
389         }
390         sci_out(port, SCFCR, fcr_val);
391 }
392
393 #endif
394 #endif /* SCIF_ONLY || SCI_AND_SCIF */
395
396 /* ********************************************************************** *
397  *                   the interrupt related routines                       *
398  * ********************************************************************** */
399
400 static void sci_transmit_chars(struct uart_port *port)
401 {
402         struct circ_buf *xmit = &port->info->xmit;
403         unsigned int stopped = uart_tx_stopped(port);
404         unsigned long flags;
405         unsigned short status;
406         unsigned short ctrl;
407         int count, txroom;
408
409         status = sci_in(port, SCxSR);
410         if (!(status & SCxSR_TDxE(port))) {
411                 local_irq_save(flags);
412                 ctrl = sci_in(port, SCSCR);
413                 if (uart_circ_empty(xmit)) {
414                         ctrl &= ~SCI_CTRL_FLAGS_TIE;
415                 } else {
416                         ctrl |= SCI_CTRL_FLAGS_TIE;
417                 }
418                 sci_out(port, SCSCR, ctrl);
419                 local_irq_restore(flags);
420                 return;
421         }
422
423 #if !defined(SCI_ONLY)
424         if (port->type == PORT_SCIF) {
425                 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
426         } else {
427                 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
428         }
429 #else
430         txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
431 #endif
432
433         count = txroom;
434
435         do {
436                 unsigned char c;
437
438                 if (port->x_char) {
439                         c = port->x_char;
440                         port->x_char = 0;
441                 } else if (!uart_circ_empty(xmit) && !stopped) {
442                         c = xmit->buf[xmit->tail];
443                         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
444                 } else {
445                         break;
446                 }
447
448                 sci_out(port, SCxTDR, c);
449
450                 port->icount.tx++;
451         } while (--count > 0);
452
453         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
454
455         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456                 uart_write_wakeup(port);
457         if (uart_circ_empty(xmit)) {
458                 sci_stop_tx(port);
459         } else {
460                 local_irq_save(flags);
461                 ctrl = sci_in(port, SCSCR);
462
463 #if !defined(SCI_ONLY)
464                 if (port->type == PORT_SCIF) {
465                         sci_in(port, SCxSR); /* Dummy read */
466                         sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
467                 }
468 #endif
469
470                 ctrl |= SCI_CTRL_FLAGS_TIE;
471                 sci_out(port, SCSCR, ctrl);
472                 local_irq_restore(flags);
473         }
474 }
475
476 /* On SH3, SCIF may read end-of-break as a space->mark char */
477 #define STEPFN(c)  ({int __c=(c); (((__c-1)|(__c)) == -1); })
478
479 static inline void sci_receive_chars(struct uart_port *port,
480                                      struct pt_regs *regs)
481 {
482         struct tty_struct *tty = port->info->tty;
483         int i, count, copied = 0;
484         unsigned short status;
485
486         status = sci_in(port, SCxSR);
487         if (!(status & SCxSR_RDxF(port)))
488                 return;
489
490         while (1) {
491 #if !defined(SCI_ONLY)
492                 if (port->type == PORT_SCIF) {
493                         count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
494                 } else {
495                         count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
496                 }
497 #else
498                 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
499 #endif
500
501                 /* Don't copy more bytes than there is room for in the buffer */
502                 if (tty->flip.count + count > TTY_FLIPBUF_SIZE)
503                         count = TTY_FLIPBUF_SIZE - tty->flip.count;
504
505                 /* If for any reason we can't copy more data, we're done! */
506                 if (count == 0)
507                         break;
508
509                 if (port->type == PORT_SCI) {
510                         char c = sci_in(port, SCxRDR);
511                        if(((struct sci_port *)port)->break_flag
512                             || uart_handle_sysrq_char(port, c, regs)) {
513                                 count = 0;
514                         } else {
515                             tty->flip.char_buf_ptr[0] = c;
516                             tty->flip.flag_buf_ptr[0] = TTY_NORMAL;
517                         }
518                 } else {
519                         for (i=0; i<count; i++) {
520                                 char c = sci_in(port, SCxRDR);
521                                 status = sci_in(port, SCxSR);
522 #if defined(CONFIG_CPU_SH3)
523                                 /* Skip "chars" during break */
524                                 if (((struct sci_port *)port)->break_flag) {
525                                         if ((c == 0) &&
526                                             (status & SCxSR_FER(port))) {
527                                                 count--; i--;
528                                                 continue;
529                                         }
530                                         /* Nonzero => end-of-break */
531                                         pr_debug("scif: debounce<%02x>\n", c);
532                                         ((struct sci_port *)port)->break_flag = 0;
533                                         if (STEPFN(c)) {
534                                                 count--; i--;
535                                                 continue;
536                                         }
537                                 }
538 #endif /* CONFIG_CPU_SH3 */
539                                 if (uart_handle_sysrq_char(port, c, regs)) {
540                                         count--; i--;
541                                         continue;
542                                 }
543
544                                 /* Store data and status */
545                                 tty->flip.char_buf_ptr[i] = c;
546                                 if (status&SCxSR_FER(port)) {
547                                         tty->flip.flag_buf_ptr[i] = TTY_FRAME;
548                                         pr_debug("sci: frame error\n");
549                                 } else if (status&SCxSR_PER(port)) {
550                                         tty->flip.flag_buf_ptr[i] = TTY_PARITY;
551                                         pr_debug("sci: parity error\n");
552                                 } else {
553                                         tty->flip.flag_buf_ptr[i] = TTY_NORMAL;
554                                 }
555                         }
556                 }
557
558                 sci_in(port, SCxSR); /* dummy read */
559                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
560
561                 /* Update the kernel buffer end */
562                 tty->flip.count += count;
563                 tty->flip.char_buf_ptr += count;
564                 tty->flip.flag_buf_ptr += count;
565                 copied += count;
566                 port->icount.rx += count;
567         }
568
569         if (copied) {
570                 /* Tell the rest of the system the news. New characters! */
571                 tty_flip_buffer_push(tty);
572         } else {
573                 sci_in(port, SCxSR); /* dummy read */
574                 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
575         }
576 }
577
578 #define SCI_BREAK_JIFFIES (HZ/20)
579 /* The sci generates interrupts during the break,
580  * 1 per millisecond or so during the break period, for 9600 baud.
581  * So dont bother disabling interrupts.
582  * But dont want more than 1 break event.
583  * Use a kernel timer to periodically poll the rx line until
584  * the break is finished.
585  */
586 static void sci_schedule_break_timer(struct sci_port *port)
587 {
588         port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
589         add_timer(&port->break_timer);
590 }
591 /* Ensure that two consecutive samples find the break over. */
592 static void sci_break_timer(unsigned long data)
593 {
594     struct sci_port * port = (struct sci_port *)data;
595         if(sci_rxd_in(&port->port) == 0) {
596                 port->break_flag = 1;
597             sci_schedule_break_timer(port);
598         } else if(port->break_flag == 1){
599                 /* break is over. */
600                 port->break_flag = 2;
601             sci_schedule_break_timer(port);
602         } else port->break_flag = 0;
603 }
604
605 static inline int sci_handle_errors(struct uart_port *port)
606 {
607         int copied = 0;
608         unsigned short status = sci_in(port, SCxSR);
609         struct tty_struct *tty = port->info->tty;
610
611         if (status&SCxSR_ORER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
612                 /* overrun error */
613                 copied++;
614                 *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
615                 pr_debug("sci: overrun error\n");
616         }
617
618         if (status&SCxSR_FER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
619                 if (sci_rxd_in(port) == 0) {
620                         /* Notify of BREAK */
621                         struct sci_port * sci_port = (struct sci_port *)port;
622                        if(!sci_port->break_flag) {
623                                 sci_port->break_flag = 1;
624                                sci_schedule_break_timer((struct sci_port *)port);
625                                 /* Do sysrq handling. */
626                                 if(uart_handle_break(port)) {
627                                         return 0;
628                                 }
629                                 pr_debug("sci: BREAK detected\n");
630                                 copied++;
631                                 *tty->flip.flag_buf_ptr++ = TTY_BREAK;
632                        }
633                 }
634                 else {
635                         /* frame error */
636                         copied++;
637                         *tty->flip.flag_buf_ptr++ = TTY_FRAME;
638                         pr_debug("sci: frame error\n");
639                 }
640         }
641
642         if (status&SCxSR_PER(port) && tty->flip.count<TTY_FLIPBUF_SIZE) {
643                 /* parity error */
644                 copied++;
645                 *tty->flip.flag_buf_ptr++ = TTY_PARITY;
646                 pr_debug("sci: parity error\n");
647         }
648
649         if (copied) {
650                 tty->flip.count += copied;
651                 tty_flip_buffer_push(tty);
652         }
653
654         return copied;
655 }
656
657 static inline int sci_handle_breaks(struct uart_port *port)
658 {
659         int copied = 0;
660         unsigned short status = sci_in(port, SCxSR);
661         struct tty_struct *tty = port->info->tty;
662         struct sci_port *s = &sci_ports[port->line];
663
664         if (!s->break_flag && status & SCxSR_BRK(port) &&
665             tty->flip.count < TTY_FLIPBUF_SIZE) {
666 #if defined(CONFIG_CPU_SH3)
667                 /* Debounce break */
668                 s->break_flag = 1;
669 #endif
670                 /* Notify of BREAK */
671                 copied++;
672                 *tty->flip.flag_buf_ptr++ = TTY_BREAK;
673                 pr_debug("sci: BREAK detected\n");
674         }
675
676 #if defined(SCIF_ORER)
677         /* XXX: Handle SCIF overrun error */
678         if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
679                 sci_out(port, SCLSR, 0);
680                 if(tty->flip.count<TTY_FLIPBUF_SIZE) {
681                         copied++;
682                         *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
683                         pr_debug("sci: overrun error\n");
684                 }
685         }
686 #endif
687
688         if (copied) {
689                 tty->flip.count += copied;
690                 tty_flip_buffer_push(tty);
691         }
692
693         return copied;
694 }
695
696 static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs)
697 {
698         struct uart_port *port = ptr;
699
700         /* I think sci_receive_chars has to be called irrespective
701          * of whether the I_IXOFF is set, otherwise, how is the interrupt
702          * to be disabled?
703          */
704         sci_receive_chars(port, regs);
705
706         return IRQ_HANDLED;
707 }
708
709 static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
710 {
711         struct uart_port *port = ptr;
712
713         sci_transmit_chars(port);
714
715         return IRQ_HANDLED;
716 }
717
718 static irqreturn_t sci_er_interrupt(int irq, void *ptr, struct pt_regs *regs)
719 {
720         struct uart_port *port = ptr;
721
722         /* Handle errors */
723         if (port->type == PORT_SCI) {
724                 if (sci_handle_errors(port)) {
725                         /* discard character in rx buffer */
726                         sci_in(port, SCxSR);
727                         sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
728                 }
729         } else {
730 #if defined(SCIF_ORER)
731                 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
732                         struct tty_struct *tty = port->info->tty;
733
734                         sci_out(port, SCLSR, 0);
735                         if(tty->flip.count<TTY_FLIPBUF_SIZE) {
736                                 *tty->flip.flag_buf_ptr++ = TTY_OVERRUN;
737                                 tty->flip.count++;
738                                 tty_flip_buffer_push(tty);
739                                 pr_debug("scif: overrun error\n");
740                         }
741                 }
742 #endif
743                 sci_rx_interrupt(irq, ptr, regs);
744         }
745
746         sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
747
748         /* Kick the transmission */
749         sci_tx_interrupt(irq, ptr, regs);
750
751         return IRQ_HANDLED;
752 }
753
754 static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
755 {
756         struct uart_port *port = ptr;
757
758         /* Handle BREAKs */
759         sci_handle_breaks(port);
760         sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
761
762         return IRQ_HANDLED;
763 }
764
765 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
766 {
767         unsigned short ssr_status, scr_status;
768         struct uart_port *port = ptr;
769
770         ssr_status = sci_in(port,SCxSR);
771         scr_status = sci_in(port,SCSCR);
772
773         /* Tx Interrupt */
774         if ((ssr_status&0x0020) && (scr_status&0x0080))
775                 sci_tx_interrupt(irq, ptr, regs);
776         /* Rx Interrupt */
777         if ((ssr_status&0x0002) && (scr_status&0x0040))
778                 sci_rx_interrupt(irq, ptr, regs);
779         /* Error Interrupt */
780         if ((ssr_status&0x0080) && (scr_status&0x0400))
781                 sci_er_interrupt(irq, ptr, regs);
782         /* Break Interrupt */
783         if ((ssr_status&0x0010) && (scr_status&0x0200))
784                 sci_br_interrupt(irq, ptr, regs);
785
786         return IRQ_HANDLED;
787 }
788
789 #ifdef CONFIG_CPU_FREQ
790 /*
791  * Here we define a transistion notifier so that we can update all of our
792  * ports' baud rate when the peripheral clock changes.
793  */
794 static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p)
795 {
796         struct cpufreq_freqs *freqs = p;
797         int i;
798
799         if ((phase == CPUFREQ_POSTCHANGE) ||
800             (phase == CPUFREQ_RESUMECHANGE)){
801                 for (i = 0; i < SCI_NPORTS; i++) {
802                         struct uart_port *port = &sci_ports[i].port;
803
804                         /*
805                          * Update the uartclk per-port if frequency has
806                          * changed, since it will no longer necessarily be
807                          * consistent with the old frequency.
808                          *
809                          * Really we want to be able to do something like
810                          * uart_change_speed() or something along those lines
811                          * here to implicitly reset the per-port baud rate..
812                          *
813                          * Clean this up later..
814                          */
815                         port->uartclk = current_cpu_data.module_clock * 16;
816                 }
817
818                 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
819                                 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
820         }
821
822         return NOTIFY_OK;
823 }
824
825 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
826 #endif /* CONFIG_CPU_FREQ */
827
828 static int sci_request_irq(struct sci_port *port)
829 {
830         int i;
831         irqreturn_t (*handlers[4])(int irq, void *ptr, struct pt_regs *regs) = {
832                 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
833                 sci_br_interrupt,
834         };
835         const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
836                                "SCI Transmit Data Empty", "SCI Break" };
837
838         if (port->irqs[0] == port->irqs[1]) {
839                 if (!port->irqs[0]) {
840                         printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
841                         return -ENODEV;
842                 }
843                 if (request_irq(port->irqs[0], sci_mpxed_interrupt, SA_INTERRUPT,
844                                 "sci", port)) {
845                         printk(KERN_ERR "sci: Cannot allocate irq.\n");
846                         return -ENODEV;
847                 }
848         } else {
849                 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
850                         if (!port->irqs[i])
851                                 continue;
852                         if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT,
853                                         desc[i], port)) {
854                                 printk(KERN_ERR "sci: Cannot allocate irq.\n");
855                                 return -ENODEV;
856                         }
857                 }
858         }
859
860         return 0;
861 }
862
863 static void sci_free_irq(struct sci_port *port)
864 {
865         int i;
866
867         if (port->irqs[0] == port->irqs[1]) {
868                 if (!port->irqs[0])
869                         printk("sci: sci_free_irq error\n");
870                 else
871                         free_irq(port->irqs[0], port);
872         } else {
873                 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
874                         if (!port->irqs[i])
875                                 continue;
876
877                         free_irq(port->irqs[i], port);
878                 }
879         }
880 }
881
882 static unsigned int sci_tx_empty(struct uart_port *port)
883 {
884         /* Can't detect */
885         return TIOCSER_TEMT;
886 }
887
888 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
889 {
890         /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
891         /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
892         /* If you have signals for DTR and DCD, please implement here. */
893 }
894
895 static unsigned int sci_get_mctrl(struct uart_port *port)
896 {
897         /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
898            and CTS/RTS */
899
900         return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
901 }
902
903 static void sci_start_tx(struct uart_port *port)
904 {
905         struct sci_port *s = &sci_ports[port->line];
906
907         disable_irq(s->irqs[SCIx_TXI_IRQ]);
908         sci_transmit_chars(port);
909         enable_irq(s->irqs[SCIx_TXI_IRQ]);
910 }
911
912 static void sci_stop_tx(struct uart_port *port)
913 {
914         unsigned long flags;
915         unsigned short ctrl;
916
917         /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
918         local_irq_save(flags);
919         ctrl = sci_in(port, SCSCR);
920         ctrl &= ~SCI_CTRL_FLAGS_TIE;
921         sci_out(port, SCSCR, ctrl);
922         local_irq_restore(flags);
923 }
924
925 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
926 {
927         unsigned long flags;
928         unsigned short ctrl;
929
930         /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
931         local_irq_save(flags);
932         ctrl = sci_in(port, SCSCR);
933         ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
934         sci_out(port, SCSCR, ctrl);
935         local_irq_restore(flags);
936 }
937
938 static void sci_stop_rx(struct uart_port *port)
939 {
940         unsigned long flags;
941         unsigned short ctrl;
942
943         /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
944         local_irq_save(flags);
945         ctrl = sci_in(port, SCSCR);
946         ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
947         sci_out(port, SCSCR, ctrl);
948         local_irq_restore(flags);
949 }
950
951 static void sci_enable_ms(struct uart_port *port)
952 {
953         /* Nothing here yet .. */
954 }
955
956 static void sci_break_ctl(struct uart_port *port, int break_state)
957 {
958         /* Nothing here yet .. */
959 }
960
961 static int sci_startup(struct uart_port *port)
962 {
963         struct sci_port *s = &sci_ports[port->line];
964
965 #if defined(__H8300S__)
966         h8300_sci_enable(port, sci_enable);
967 #endif
968
969         sci_request_irq(s);
970         sci_start_tx(port, 1);
971         sci_start_rx(port, 1);
972
973         return 0;
974 }
975
976 static void sci_shutdown(struct uart_port *port)
977 {
978         struct sci_port *s = &sci_ports[port->line];
979
980         sci_stop_rx(port);
981         sci_stop_tx(port);
982         sci_free_irq(s);
983
984 #if defined(__H8300S__)
985         h8300_sci_enable(port, sci_disable);
986 #endif
987 }
988
989 static void sci_set_termios(struct uart_port *port, struct termios *termios,
990                             struct termios *old)
991 {
992         struct sci_port *s = &sci_ports[port->line];
993         unsigned int status, baud, smr_val;
994         unsigned long flags;
995         int t;
996
997         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
998
999         spin_lock_irqsave(&port->lock, flags);
1000
1001         do {
1002                 status = sci_in(port, SCxSR);
1003         } while (!(status & SCxSR_TEND(port)));
1004
1005         sci_out(port, SCSCR, 0x00);     /* TE=0, RE=0, CKE1=0 */
1006
1007 #if !defined(SCI_ONLY)
1008         if (port->type == PORT_SCIF) {
1009                 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1010         }
1011 #endif
1012
1013         smr_val = sci_in(port, SCSMR) & 3;
1014         if ((termios->c_cflag & CSIZE) == CS7)
1015                 smr_val |= 0x40;
1016         if (termios->c_cflag & PARENB)
1017                 smr_val |= 0x20;
1018         if (termios->c_cflag & PARODD)
1019                 smr_val |= 0x30;
1020         if (termios->c_cflag & CSTOPB)
1021                 smr_val |= 0x08;
1022
1023         uart_update_timeout(port, termios->c_cflag, baud);
1024
1025         sci_out(port, SCSMR, smr_val);
1026
1027         switch (baud) {
1028                 case 0:         t = -1;         break;
1029                 case 2400:      t = BPS_2400;   break;
1030                 case 4800:      t = BPS_4800;   break;
1031                 case 9600:      t = BPS_9600;   break;
1032                 case 19200:     t = BPS_19200;  break;
1033                 case 38400:     t = BPS_38400;  break;
1034                 case 57600:     t = BPS_57600;  break;
1035                 case 115200:    t = BPS_115200; break;
1036                 default:        t = SCBRR_VALUE(baud); break;
1037         }
1038
1039         if (t > 0) {
1040                 if(t >= 256) {
1041                         sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1042                         t >>= 2;
1043                 } else {
1044                         sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1045                 }
1046                 sci_out(port, SCBRR, t);
1047                 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1048         }
1049
1050         s->init_pins(port, termios->c_cflag);
1051         sci_out(port, SCSCR, SCSCR_INIT(port));
1052
1053         if ((termios->c_cflag & CREAD) != 0)
1054               sci_start_rx(port,0);
1055
1056         spin_unlock_irqrestore(&port->lock, flags);
1057 }
1058
1059 static const char *sci_type(struct uart_port *port)
1060 {
1061         switch (port->type) {
1062                 case PORT_SCI:  return "sci";
1063                 case PORT_SCIF: return "scif";
1064                 case PORT_IRDA: return "irda";
1065         }
1066
1067         return 0;
1068 }
1069
1070 static void sci_release_port(struct uart_port *port)
1071 {
1072         /* Nothing here yet .. */
1073 }
1074
1075 static int sci_request_port(struct uart_port *port)
1076 {
1077         /* Nothing here yet .. */
1078         return 0;
1079 }
1080
1081 static void sci_config_port(struct uart_port *port, int flags)
1082 {
1083         struct sci_port *s = &sci_ports[port->line];
1084
1085         port->type = s->type;
1086
1087 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1088         if (port->mapbase == 0)
1089                 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1090
1091         port->membase = (void *)port->mapbase;
1092 #endif
1093 }
1094
1095 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1096 {
1097         struct sci_port *s = &sci_ports[port->line];
1098
1099         if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1100                 return -EINVAL;
1101         if (ser->baud_base < 2400)
1102                 /* No paper tape reader for Mitch.. */
1103                 return -EINVAL;
1104
1105         return 0;
1106 }
1107
1108 static struct uart_ops sci_uart_ops = {
1109         .tx_empty       = sci_tx_empty,
1110         .set_mctrl      = sci_set_mctrl,
1111         .get_mctrl      = sci_get_mctrl,
1112         .start_tx       = sci_start_tx,
1113         .stop_tx        = sci_stop_tx,
1114         .stop_rx        = sci_stop_rx,
1115         .enable_ms      = sci_enable_ms,
1116         .break_ctl      = sci_break_ctl,
1117         .startup        = sci_startup,
1118         .shutdown       = sci_shutdown,
1119         .set_termios    = sci_set_termios,
1120         .type           = sci_type,
1121         .release_port   = sci_release_port,
1122         .request_port   = sci_request_port,
1123         .config_port    = sci_config_port,
1124         .verify_port    = sci_verify_port,
1125 };
1126
1127 static struct sci_port sci_ports[SCI_NPORTS] = {
1128 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
1129         {
1130                 .port   = {
1131                         .membase        = (void *)0xfffffe80,
1132                         .mapbase        = 0xfffffe80,
1133                         .iotype         = SERIAL_IO_MEM,
1134                         .irq            = 25,
1135                         .ops            = &sci_uart_ops,
1136                         .flags          = ASYNC_BOOT_AUTOCONF,
1137                         .line           = 0,
1138                 },
1139                 .type           = PORT_SCI,
1140                 .irqs           = SCI_IRQS,
1141                 .init_pins      = sci_init_pins_sci,
1142         },
1143 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
1144         {
1145                 .port   = {
1146                         .membase        = (void *)SCIF0,
1147                         .mapbase        = SCIF0,
1148                         .iotype         = SERIAL_IO_MEM,
1149                         .irq            = 55,
1150                         .ops            = &sci_uart_ops,
1151                         .flags          = ASYNC_BOOT_AUTOCONF,
1152                         .line           = 0,
1153                 },
1154                 .type           = PORT_SCIF,
1155                 .irqs           = SH3_IRDA_IRQS,
1156                 .init_pins      = sci_init_pins_scif,
1157         },
1158         {
1159                 .port   = {
1160                         .membase        = (void *)SCIF2,
1161                         .mapbase        = SCIF2,
1162                         .iotype         = SERIAL_IO_MEM,
1163                         .irq            = 59,
1164                         .ops            = &sci_uart_ops,
1165                         .flags          = ASYNC_BOOT_AUTOCONF,
1166                         .line           = 1,
1167                 },
1168                 .type           = PORT_SCIF,
1169                 .irqs           = SH3_SCIF_IRQS,
1170                 .init_pins      = sci_init_pins_scif,
1171         }
1172 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1173         {
1174                 .port   = {
1175                         .membase        = (void *)0xfffffe80,
1176                         .mapbase        = 0xfffffe80,
1177                         .iotype         = SERIAL_IO_MEM,
1178                         .irq            = 25,
1179                         .ops            = &sci_uart_ops,
1180                         .flags          = ASYNC_BOOT_AUTOCONF,
1181                         .line           = 0,
1182                 },
1183                 .type           = PORT_SCI,
1184                 .irqs           = SCI_IRQS,
1185                 .init_pins      = sci_init_pins_sci,
1186         },
1187         {
1188                 .port   = {
1189                         .membase        = (void *)0xa4000150,
1190                         .mapbase        = 0xa4000150,
1191                         .iotype         = SERIAL_IO_MEM,
1192                         .irq            = 59,
1193                         .ops            = &sci_uart_ops,
1194                         .flags          = ASYNC_BOOT_AUTOCONF,
1195                         .line           = 1,
1196                 },
1197                 .type           = PORT_SCIF,
1198                 .irqs           = SH3_SCIF_IRQS,
1199                 .init_pins      = sci_init_pins_scif,
1200         },
1201         {
1202                 .port   = {
1203                         .membase        = (void *)0xa4000140,
1204                         .mapbase        = 0xa4000140,
1205                         .iotype         = SERIAL_IO_MEM,
1206                         .irq            = 55,
1207                         .ops            = &sci_uart_ops,
1208                         .flags          = ASYNC_BOOT_AUTOCONF,
1209                         .line           = 2,
1210                 },
1211                 .type           = PORT_IRDA,
1212                 .irqs           = SH3_IRDA_IRQS,
1213                 .init_pins      = sci_init_pins_irda,
1214         }
1215 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1216         {
1217                 .port   = {
1218                         .membase        = (void *)0xA4430000,
1219                         .mapbase        = 0xA4430000,
1220                         .iotype         = SERIAL_IO_MEM,
1221                         .irq            = 25,
1222                         .ops            = &sci_uart_ops,
1223                         .flags          = ASYNC_BOOT_AUTOCONF,
1224                         .line           = 0,
1225                 },
1226                 .type           = PORT_SCIF,
1227                 .irqs           = SH7300_SCIF0_IRQS,
1228                 .init_pins      = sci_init_pins_scif,
1229         },
1230 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1231         {
1232                 .port   = {
1233                         .membase        = (void *)0xffe00000,
1234                         .mapbase        = 0xffe00000,
1235                         .iotype         = SERIAL_IO_MEM,
1236                         .irq            = 25,
1237                         .ops            = &sci_uart_ops,
1238                         .flags          = ASYNC_BOOT_AUTOCONF,
1239                         .line           = 0,
1240                 },
1241                 .type           = PORT_SCIF,
1242                 .irqs           = SH73180_SCIF_IRQS,
1243                 .init_pins      = sci_init_pins_scif,
1244         },
1245 #elif defined(CONFIG_SH_RTS7751R2D)
1246         {
1247                 .port   = {
1248                         .membase        = (void *)0xffe80000,
1249                         .mapbase        = 0xffe80000,
1250                         .iotype         = SERIAL_IO_MEM,
1251                         .irq            = 43,
1252                         .ops            = &sci_uart_ops,
1253                         .flags          = ASYNC_BOOT_AUTOCONF,
1254                         .line           = 0,
1255                 },
1256                 .type           = PORT_SCIF,
1257                 .irqs           = SH4_SCIF_IRQS,
1258                 .init_pins      = sci_init_pins_scif,
1259         },
1260 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1261         {
1262                 .port   = {
1263                         .membase        = (void *)0xffe00000,
1264                         .mapbase        = 0xffe00000,
1265                         .iotype         = SERIAL_IO_MEM,
1266                         .irq            = 25,
1267                         .ops            = &sci_uart_ops,
1268                         .flags          = ASYNC_BOOT_AUTOCONF,
1269                         .line           = 0,
1270                 },
1271                 .type           = PORT_SCI,
1272                 .irqs           = SCI_IRQS,
1273                 .init_pins      = sci_init_pins_sci,
1274         },
1275         {
1276                 .port   = {
1277                         .membase        = (void *)0xffe80000,
1278                         .mapbase        = 0xffe80000,
1279                         .iotype         = SERIAL_IO_MEM,
1280                         .irq            = 43,
1281                         .ops            = &sci_uart_ops,
1282                         .flags          = ASYNC_BOOT_AUTOCONF,
1283                         .line           = 1,
1284                 },
1285                 .type           = PORT_SCIF,
1286                 .irqs           = SH4_SCIF_IRQS,
1287                 .init_pins      = sci_init_pins_scif,
1288         },
1289 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1290         {
1291                 .port   = {
1292                         .membase        = (void *)0xfe600000,
1293                         .mapbase        = 0xfe600000,
1294                         .iotype         = SERIAL_IO_MEM,
1295                         .irq            = 55,
1296                         .ops            = &sci_uart_ops,
1297                         .flags          = ASYNC_BOOT_AUTOCONF,
1298                         .line           = 0,
1299                 },
1300                 .type           = PORT_SCIF,
1301                 .irqs           = SH7760_SCIF0_IRQS,
1302                 .init_pins      = sci_init_pins_scif,
1303         },
1304         {
1305                 .port   = {
1306                         .membase        = (void *)0xfe610000,
1307                         .mapbase        = 0xfe610000,
1308                         .iotype         = SERIAL_IO_MEM,
1309                         .irq            = 75,
1310                         .ops            = &sci_uart_ops,
1311                         .flags          = ASYNC_BOOT_AUTOCONF,
1312                         .line           = 1,
1313                 },
1314                 .type           = PORT_SCIF,
1315                 .irqs           = SH7760_SCIF1_IRQS,
1316                 .init_pins      = sci_init_pins_scif,
1317         },
1318         {
1319                 .port   = {
1320                         .membase        = (void *)0xfe620000,
1321                         .mapbase        = 0xfe620000,
1322                         .iotype         = SERIAL_IO_MEM,
1323                         .irq            = 79,
1324                         .ops            = &sci_uart_ops,
1325                         .flags          = ASYNC_BOOT_AUTOCONF,
1326                         .line           = 2,
1327                 },
1328                 .type           = PORT_SCIF,
1329                 .irqs           = SH7760_SCIF2_IRQS,
1330                 .init_pins      = sci_init_pins_scif,
1331         },
1332 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1333         {
1334                 .port   = {
1335                         .membase        = (void *)0xffe80000,
1336                         .mapbase        = 0xffe80000,
1337                         .iotype         = SERIAL_IO_MEM,
1338                         .irq            = 43,
1339                         .ops            = &sci_uart_ops,
1340                         .flags          = ASYNC_BOOT_AUTOCONF,
1341                         .line           = 0,
1342                 },
1343                 .type           = PORT_SCIF,
1344                 .irqs           = SH4_SCIF_IRQS,
1345                 .init_pins      = sci_init_pins_scif,
1346         },
1347 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1348         {
1349                 .port   = {
1350                         .membase        = (void *)0xffe00000,
1351                         .mapbase        = 0xffe00000,
1352                         .iotype         = SERIAL_IO_MEM,
1353                         .irq            = 26,
1354                         .ops            = &sci_uart_ops,
1355                         .flags          = ASYNC_BOOT_AUTOCONF,
1356                         .line           = 0,
1357                 },
1358                 .type           = PORT_SCIF,
1359                 .irqs           = STB1_SCIF1_IRQS,
1360                 .init_pins      = sci_init_pins_scif,
1361         },
1362         {
1363                 .port   = {
1364                         .membase        = (void *)0xffe80000,
1365                         .mapbase        = 0xffe80000,
1366                         .iotype         = SERIAL_IO_MEM,
1367                         .irq            = 43,
1368                         .ops            = &sci_uart_ops,
1369                         .flags          = ASYNC_BOOT_AUTOCONF,
1370                         .line           = 1,
1371                 },
1372                 .type           = PORT_SCIF,
1373                 .irqs           = SH4_SCIF_IRQS,
1374                 .init_pins      = sci_init_pins_scif,
1375         },
1376 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1377         {
1378                 .port   = {
1379                         .iotype         = SERIAL_IO_MEM,
1380                         .irq            = 42,
1381                         .ops            = &sci_uart_ops,
1382                         .flags          = ASYNC_BOOT_AUTOCONF,
1383                         .line           = 0,
1384                 },
1385                 .type           = PORT_SCIF,
1386                 .irqs           = SH5_SCIF_IRQS,
1387                 .init_pins      = sci_init_pins_scif,
1388         },
1389 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1390         {
1391                 .port   = {
1392                         .membase        = (void *)0x00ffffb0,
1393                         .mapbase        = 0x00ffffb0,
1394                         .iotype         = SERIAL_IO_MEM,
1395                         .irq            = 54,
1396                         .ops            = &sci_uart_ops,
1397                         .flags          = ASYNC_BOOT_AUTOCONF,
1398                         .line           = 0,
1399                 },
1400                 .type           = PORT_SCI,
1401                 .irqs           = H8300H_SCI_IRQS0,
1402                 .init_pins      = sci_init_pins_sci,
1403         },
1404         {
1405                 .port   = {
1406                         .membase        = (void *)0x00ffffb8,
1407                         .mapbase        = 0x00ffffb8,
1408                         .iotype         = SERIAL_IO_MEM,
1409                         .irq            = 58,
1410                         .ops            = &sci_uart_ops,
1411                         .flags          = ASYNC_BOOT_AUTOCONF,
1412                         .line           = 1,
1413                 },
1414                 .type           = PORT_SCI,
1415                 .irqs           = H8300H_SCI_IRQS1,
1416                 .init_pins      = sci_init_pins_sci,
1417         },
1418         {
1419                 .port   = {
1420                         .membase        = (void *)0x00ffffc0,
1421                         .mapbase        = 0x00ffffc0,
1422                         .iotype         = SERIAL_IO_MEM,
1423                         .irq            = 62,
1424                         .ops            = &sci_uart_ops,
1425                         .flags          = ASYNC_BOOT_AUTOCONF,
1426                         .line           = 2,
1427                 },
1428                 .type           = PORT_SCI,
1429                 .irqs           = H8300H_SCI_IRQS2,
1430                 .init_pins      = sci_init_pins_sci,
1431         },
1432 #elif defined(CONFIG_H8S2678)
1433         {
1434                 .port   = {
1435                         .membase        = (void *)0x00ffff78,
1436                         .mapbase        = 0x00ffff78,
1437                         .iotype         = SERIAL_IO_MEM,
1438                         .irq            = 90,
1439                         .ops            = &sci_uart_ops,
1440                         .flags          = ASYNC_BOOT_AUTOCONF,
1441                         .line           = 0,
1442                 },
1443                 .type           = PORT_SCI,
1444                 .irqs           = H8S_SCI_IRQS0,
1445                 .init_pins      = sci_init_pins_sci,
1446         },
1447         {
1448                 .port   = {
1449                         .membase        = (void *)0x00ffff80,
1450                         .mapbase        = 0x00ffff80,
1451                         .iotype         = SERIAL_IO_MEM,
1452                         .irq            = 94,
1453                         .ops            = &sci_uart_ops,
1454                         .flags          = ASYNC_BOOT_AUTOCONF,
1455                         .line           = 1,
1456                 },
1457                 .type           = PORT_SCI,
1458                 .irqs           = H8S_SCI_IRQS1,
1459                 .init_pins      = sci_init_pins_sci,
1460         },
1461         {
1462                 .port   = {
1463                         .membase        = (void *)0x00ffff88,
1464                         .mapbase        = 0x00ffff88,
1465                         .iotype         = SERIAL_IO_MEM,
1466                         .irq            = 98,
1467                         .ops            = &sci_uart_ops,
1468                         .flags          = ASYNC_BOOT_AUTOCONF,
1469                         .line           = 2,
1470                 },
1471                 .type           = PORT_SCI,
1472                 .irqs           = H8S_SCI_IRQS2,
1473                 .init_pins      = sci_init_pins_sci,
1474         },
1475 #else
1476 #error "CPU subtype not defined"
1477 #endif
1478 };
1479
1480 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1481 /*
1482  *      Print a string to the serial port trying not to disturb
1483  *      any possible real use of the port...
1484  */
1485 static void serial_console_write(struct console *co, const char *s,
1486                                  unsigned count)
1487 {
1488         put_string(serial_console_port, s, count);
1489 }
1490
1491 static int __init serial_console_setup(struct console *co, char *options)
1492 {
1493         struct uart_port *port;
1494         int baud = 115200;
1495         int bits = 8;
1496         int parity = 'n';
1497         int flow = 'n';
1498         int ret;
1499
1500         if (co->index >= SCI_NPORTS)
1501                 co->index = 0;
1502
1503         serial_console_port = &sci_ports[co->index];
1504         port = &serial_console_port->port;
1505         port->type = serial_console_port->type;
1506
1507 #ifdef CONFIG_SUPERH64
1508         /* This is especially needed on sh64 to remap the SCIF */
1509         sci_config_port(port, 0);
1510 #endif
1511
1512         /*
1513          * We need to set the initial uartclk here, since otherwise it will
1514          * only ever be setup at sci_init() time.
1515          */
1516 #if !defined(__H8300H__) && !defined(__H8300S__)
1517         port->uartclk = current_cpu_data.module_clock * 16;
1518 #else
1519         port->uartclk = CONFIG_CPU_CLOCK;
1520 #endif
1521 #if defined(__H8300S__)
1522         h8300_sci_enable(port, sci_enable);
1523 #endif
1524         if (options)
1525                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1526
1527         ret = uart_set_options(port, co, baud, parity, bits, flow);
1528 #if defined(__H8300H__) || defined(__H8300S__)
1529         /* disable rx interrupt */
1530         if (ret == 0)
1531                 sci_stop_rx(port);
1532 #endif
1533         return ret;
1534 }
1535
1536 static struct console serial_console = {
1537         .name           = "ttySC",
1538         .device         = uart_console_device,
1539         .write          = serial_console_write,
1540         .setup          = serial_console_setup,
1541         .flags          = CON_PRINTBUFFER,
1542         .index          = -1,
1543         .data           = &sci_uart_driver,
1544 };
1545
1546 static int __init sci_console_init(void)
1547 {
1548         register_console(&serial_console);
1549         return 0;
1550 }
1551
1552 console_initcall(sci_console_init);
1553 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1554
1555 #ifdef CONFIG_SH_KGDB
1556 /*
1557  * FIXME: Most of this can go away.. at the moment, we rely on
1558  * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1559  * most of that can easily be done here instead.
1560  *
1561  * For the time being, just accept the values that were parsed earlier..
1562  */
1563 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1564                                             int *parity, int *bits)
1565 {
1566         *baud = kgdb_baud;
1567         *parity = tolower(kgdb_parity);
1568         *bits = kgdb_bits - '0';
1569 }
1570
1571 /*
1572  * The naming here is somewhat misleading, since kgdb_console_setup() takes
1573  * care of the early-on initialization for kgdb, regardless of whether we
1574  * actually use kgdb as a console or not.
1575  *
1576  * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1577  */
1578 int __init kgdb_console_setup(struct console *co, char *options)
1579 {
1580         struct uart_port *port = &sci_ports[kgdb_portnum].port;
1581         int baud = 38400;
1582         int bits = 8;
1583         int parity = 'n';
1584         int flow = 'n';
1585
1586         if (co->index >= SCI_NPORTS || co->index != kgdb_portnum)
1587                 co->index = kgdb_portnum;
1588
1589         if (options)
1590                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1591         else
1592                 kgdb_console_get_options(port, &baud, &parity, &bits);
1593
1594         kgdb_getchar = kgdb_sci_getchar;
1595         kgdb_putchar = kgdb_sci_putchar;
1596
1597         return uart_set_options(port, co, baud, parity, bits, flow);
1598 }
1599 #endif /* CONFIG_SH_KGDB */
1600
1601 #ifdef CONFIG_SH_KGDB_CONSOLE
1602 static struct console kgdb_console = {
1603         .name           = "ttySC",
1604         .write          = kgdb_console_write,
1605         .setup          = kgdb_console_setup,
1606         .flags          = CON_PRINTBUFFER | CON_ENABLED,
1607         .index          = -1,
1608         .data           = &sci_uart_driver,
1609 };
1610
1611 /* Register the KGDB console so we get messages (d'oh!) */
1612 static int __init kgdb_console_init(void)
1613 {
1614         register_console(&kgdb_console);
1615         return 0;
1616 }
1617
1618 console_initcall(kgdb_console_init);
1619 #endif /* CONFIG_SH_KGDB_CONSOLE */
1620
1621 #if defined(CONFIG_SH_KGDB_CONSOLE)
1622 #define SCI_CONSOLE     &kgdb_console
1623 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1624 #define SCI_CONSOLE     &serial_console
1625 #else
1626 #define SCI_CONSOLE     0
1627 #endif
1628
1629 static char banner[] __initdata =
1630         KERN_INFO "SuperH SCI(F) driver initialized\n";
1631
1632 static struct uart_driver sci_uart_driver = {
1633         .owner          = THIS_MODULE,
1634         .driver_name    = "sci",
1635 #ifdef CONFIG_DEVFS_FS
1636         .devfs_name     = "ttsc/",
1637 #endif
1638         .dev_name       = "ttySC",
1639         .major          = SCI_MAJOR,
1640         .minor          = SCI_MINOR_START,
1641         .nr             = SCI_NPORTS,
1642         .cons           = SCI_CONSOLE,
1643 };
1644
1645 static int __init sci_init(void)
1646 {
1647         int chan, ret;
1648
1649         printk("%s", banner);
1650
1651         ret = uart_register_driver(&sci_uart_driver);
1652         if (ret == 0) {
1653                 for (chan = 0; chan < SCI_NPORTS; chan++) {
1654                         struct sci_port *sciport = &sci_ports[chan];
1655
1656 #if !defined(__H8300H__) && !defined(__H8300S__)
1657                         sciport->port.uartclk = (current_cpu_data.module_clock * 16);
1658 #else
1659                         sciport->port.uartclk = CONFIG_CPU_CLOCK;
1660 #endif
1661                         uart_add_one_port(&sci_uart_driver, &sciport->port);
1662                         sciport->break_timer.data = (unsigned long)sciport;
1663                         sciport->break_timer.function = sci_break_timer;
1664                         init_timer(&sciport->break_timer);
1665                 }
1666         }
1667
1668 #ifdef CONFIG_CPU_FREQ
1669         cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1670         printk("sci: CPU frequency notifier registered\n");
1671 #endif
1672
1673 #ifdef CONFIG_SH_STANDARD_BIOS
1674         sh_bios_gdb_detach();
1675 #endif
1676
1677         return ret;
1678 }
1679
1680 static void __exit sci_exit(void)
1681 {
1682         int chan;
1683
1684         for (chan = 0; chan < SCI_NPORTS; chan++)
1685                 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port);
1686
1687         uart_unregister_driver(&sci_uart_driver);
1688 }
1689
1690 module_init(sci_init);
1691 module_exit(sci_exit);
1692