[SCSI] qla2xxx: Add Flash Layout Table support.
[linux-2.6.git] / drivers / scsi / qla2xxx / qla_sup.c
1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c)  2003-2008 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
12
13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
14 static void qla2x00_nv_deselect(scsi_qla_host_t *);
15 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
16
17 /*
18  * NVRAM support routines
19  */
20
21 /**
22  * qla2x00_lock_nvram_access() -
23  * @ha: HA context
24  */
25 static void
26 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
27 {
28         uint16_t data;
29         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
30
31         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
32                 data = RD_REG_WORD(&reg->nvram);
33                 while (data & NVR_BUSY) {
34                         udelay(100);
35                         data = RD_REG_WORD(&reg->nvram);
36                 }
37
38                 /* Lock resource */
39                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
40                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
41                 udelay(5);
42                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
43                 while ((data & BIT_0) == 0) {
44                         /* Lock failed */
45                         udelay(100);
46                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
47                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
48                         udelay(5);
49                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
50                 }
51         }
52 }
53
54 /**
55  * qla2x00_unlock_nvram_access() -
56  * @ha: HA context
57  */
58 static void
59 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
60 {
61         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
62
63         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
64                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
65                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
66         }
67 }
68
69 /**
70  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
71  *      request routine to get the word from NVRAM.
72  * @ha: HA context
73  * @addr: Address in NVRAM to read
74  *
75  * Returns the word read from nvram @addr.
76  */
77 static uint16_t
78 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
79 {
80         uint16_t        data;
81         uint32_t        nv_cmd;
82
83         nv_cmd = addr << 16;
84         nv_cmd |= NV_READ_OP;
85         data = qla2x00_nvram_request(ha, nv_cmd);
86
87         return (data);
88 }
89
90 /**
91  * qla2x00_write_nvram_word() - Write NVRAM data.
92  * @ha: HA context
93  * @addr: Address in NVRAM to write
94  * @data: word to program
95  */
96 static void
97 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
98 {
99         int count;
100         uint16_t word;
101         uint32_t nv_cmd, wait_cnt;
102         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
103
104         qla2x00_nv_write(ha, NVR_DATA_OUT);
105         qla2x00_nv_write(ha, 0);
106         qla2x00_nv_write(ha, 0);
107
108         for (word = 0; word < 8; word++)
109                 qla2x00_nv_write(ha, NVR_DATA_OUT);
110
111         qla2x00_nv_deselect(ha);
112
113         /* Write data */
114         nv_cmd = (addr << 16) | NV_WRITE_OP;
115         nv_cmd |= data;
116         nv_cmd <<= 5;
117         for (count = 0; count < 27; count++) {
118                 if (nv_cmd & BIT_31)
119                         qla2x00_nv_write(ha, NVR_DATA_OUT);
120                 else
121                         qla2x00_nv_write(ha, 0);
122
123                 nv_cmd <<= 1;
124         }
125
126         qla2x00_nv_deselect(ha);
127
128         /* Wait for NVRAM to become ready */
129         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
131         wait_cnt = NVR_WAIT_CNT;
132         do {
133                 if (!--wait_cnt) {
134                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
135                             __func__, ha->host_no));
136                         break;
137                 }
138                 NVRAM_DELAY();
139                 word = RD_REG_WORD(&reg->nvram);
140         } while ((word & NVR_DATA_IN) == 0);
141
142         qla2x00_nv_deselect(ha);
143
144         /* Disable writes */
145         qla2x00_nv_write(ha, NVR_DATA_OUT);
146         for (count = 0; count < 10; count++)
147                 qla2x00_nv_write(ha, 0);
148
149         qla2x00_nv_deselect(ha);
150 }
151
152 static int
153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
154     uint32_t tmo)
155 {
156         int ret, count;
157         uint16_t word;
158         uint32_t nv_cmd;
159         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
160
161         ret = QLA_SUCCESS;
162
163         qla2x00_nv_write(ha, NVR_DATA_OUT);
164         qla2x00_nv_write(ha, 0);
165         qla2x00_nv_write(ha, 0);
166
167         for (word = 0; word < 8; word++)
168                 qla2x00_nv_write(ha, NVR_DATA_OUT);
169
170         qla2x00_nv_deselect(ha);
171
172         /* Write data */
173         nv_cmd = (addr << 16) | NV_WRITE_OP;
174         nv_cmd |= data;
175         nv_cmd <<= 5;
176         for (count = 0; count < 27; count++) {
177                 if (nv_cmd & BIT_31)
178                         qla2x00_nv_write(ha, NVR_DATA_OUT);
179                 else
180                         qla2x00_nv_write(ha, 0);
181
182                 nv_cmd <<= 1;
183         }
184
185         qla2x00_nv_deselect(ha);
186
187         /* Wait for NVRAM to become ready */
188         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
189         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
190         do {
191                 NVRAM_DELAY();
192                 word = RD_REG_WORD(&reg->nvram);
193                 if (!--tmo) {
194                         ret = QLA_FUNCTION_FAILED;
195                         break;
196                 }
197         } while ((word & NVR_DATA_IN) == 0);
198
199         qla2x00_nv_deselect(ha);
200
201         /* Disable writes */
202         qla2x00_nv_write(ha, NVR_DATA_OUT);
203         for (count = 0; count < 10; count++)
204                 qla2x00_nv_write(ha, 0);
205
206         qla2x00_nv_deselect(ha);
207
208         return ret;
209 }
210
211 /**
212  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
213  *      NVRAM.
214  * @ha: HA context
215  * @nv_cmd: NVRAM command
216  *
217  * Bit definitions for NVRAM command:
218  *
219  *      Bit 26     = start bit
220  *      Bit 25, 24 = opcode
221  *      Bit 23-16  = address
222  *      Bit 15-0   = write data
223  *
224  * Returns the word read from nvram @addr.
225  */
226 static uint16_t
227 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
228 {
229         uint8_t         cnt;
230         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
231         uint16_t        data = 0;
232         uint16_t        reg_data;
233
234         /* Send command to NVRAM. */
235         nv_cmd <<= 5;
236         for (cnt = 0; cnt < 11; cnt++) {
237                 if (nv_cmd & BIT_31)
238                         qla2x00_nv_write(ha, NVR_DATA_OUT);
239                 else
240                         qla2x00_nv_write(ha, 0);
241                 nv_cmd <<= 1;
242         }
243
244         /* Read data from NVRAM. */
245         for (cnt = 0; cnt < 16; cnt++) {
246                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
247                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
248                 NVRAM_DELAY();
249                 data <<= 1;
250                 reg_data = RD_REG_WORD(&reg->nvram);
251                 if (reg_data & NVR_DATA_IN)
252                         data |= BIT_0;
253                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
254                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
255                 NVRAM_DELAY();
256         }
257
258         /* Deselect chip. */
259         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
260         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
261         NVRAM_DELAY();
262
263         return (data);
264 }
265
266 /**
267  * qla2x00_nv_write() - Clean NVRAM operations.
268  * @ha: HA context
269  */
270 static void
271 qla2x00_nv_deselect(scsi_qla_host_t *ha)
272 {
273         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
274
275         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
276         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
277         NVRAM_DELAY();
278 }
279
280 /**
281  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
282  * @ha: HA context
283  * @data: Serial interface selector
284  */
285 static void
286 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
287 {
288         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
289
290         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
291         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
292         NVRAM_DELAY();
293         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
294             NVR_WRT_ENABLE);
295         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
296         NVRAM_DELAY();
297         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
298         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
299         NVRAM_DELAY();
300 }
301
302 /**
303  * qla2x00_clear_nvram_protection() -
304  * @ha: HA context
305  */
306 static int
307 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
308 {
309         int ret, stat;
310         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
311         uint32_t word, wait_cnt;
312         uint16_t wprot, wprot_old;
313
314         /* Clear NVRAM write protection. */
315         ret = QLA_FUNCTION_FAILED;
316
317         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
319             __constant_cpu_to_le16(0x1234), 100000);
320         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321         if (stat != QLA_SUCCESS || wprot != 0x1234) {
322                 /* Write enable. */
323                 qla2x00_nv_write(ha, NVR_DATA_OUT);
324                 qla2x00_nv_write(ha, 0);
325                 qla2x00_nv_write(ha, 0);
326                 for (word = 0; word < 8; word++)
327                         qla2x00_nv_write(ha, NVR_DATA_OUT);
328
329                 qla2x00_nv_deselect(ha);
330
331                 /* Enable protection register. */
332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335                 for (word = 0; word < 8; word++)
336                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337
338                 qla2x00_nv_deselect(ha);
339
340                 /* Clear protection register (ffff is cleared). */
341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344                 for (word = 0; word < 8; word++)
345                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346
347                 qla2x00_nv_deselect(ha);
348
349                 /* Wait for NVRAM to become ready. */
350                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
351                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
352                 wait_cnt = NVR_WAIT_CNT;
353                 do {
354                         if (!--wait_cnt) {
355                                 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
356                                     "ready...\n", __func__,
357                                     ha->host_no));
358                                 break;
359                         }
360                         NVRAM_DELAY();
361                         word = RD_REG_WORD(&reg->nvram);
362                 } while ((word & NVR_DATA_IN) == 0);
363
364                 if (wait_cnt)
365                         ret = QLA_SUCCESS;
366         } else
367                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
368
369         return ret;
370 }
371
372 static void
373 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
374 {
375         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
376         uint32_t word, wait_cnt;
377
378         if (stat != QLA_SUCCESS)
379                 return;
380
381         /* Set NVRAM write protection. */
382         /* Write enable. */
383         qla2x00_nv_write(ha, NVR_DATA_OUT);
384         qla2x00_nv_write(ha, 0);
385         qla2x00_nv_write(ha, 0);
386         for (word = 0; word < 8; word++)
387                 qla2x00_nv_write(ha, NVR_DATA_OUT);
388
389         qla2x00_nv_deselect(ha);
390
391         /* Enable protection register. */
392         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393         qla2x00_nv_write(ha, NVR_PR_ENABLE);
394         qla2x00_nv_write(ha, NVR_PR_ENABLE);
395         for (word = 0; word < 8; word++)
396                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397
398         qla2x00_nv_deselect(ha);
399
400         /* Enable protection register. */
401         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402         qla2x00_nv_write(ha, NVR_PR_ENABLE);
403         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404         for (word = 0; word < 8; word++)
405                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406
407         qla2x00_nv_deselect(ha);
408
409         /* Wait for NVRAM to become ready. */
410         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
411         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
412         wait_cnt = NVR_WAIT_CNT;
413         do {
414                 if (!--wait_cnt) {
415                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
416                             __func__, ha->host_no));
417                         break;
418                 }
419                 NVRAM_DELAY();
420                 word = RD_REG_WORD(&reg->nvram);
421         } while ((word & NVR_DATA_IN) == 0);
422 }
423
424
425 /*****************************************************************************/
426 /* Flash Manipulation Routines                                               */
427 /*****************************************************************************/
428
429 #define OPTROM_BURST_SIZE       0x1000
430 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
431
432 static inline uint32_t
433 flash_conf_to_access_addr(uint32_t faddr)
434 {
435         return FARX_ACCESS_FLASH_CONF | faddr;
436 }
437
438 static inline uint32_t
439 flash_data_to_access_addr(uint32_t faddr)
440 {
441         return FARX_ACCESS_FLASH_DATA | faddr;
442 }
443
444 static inline uint32_t
445 nvram_conf_to_access_addr(uint32_t naddr)
446 {
447         return FARX_ACCESS_NVRAM_CONF | naddr;
448 }
449
450 static inline uint32_t
451 nvram_data_to_access_addr(uint32_t naddr)
452 {
453         return FARX_ACCESS_NVRAM_DATA | naddr;
454 }
455
456 static uint32_t
457 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
458 {
459         int rval;
460         uint32_t cnt, data;
461         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
462
463         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
464         /* Wait for READ cycle to complete. */
465         rval = QLA_SUCCESS;
466         for (cnt = 3000;
467             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
468             rval == QLA_SUCCESS; cnt--) {
469                 if (cnt)
470                         udelay(10);
471                 else
472                         rval = QLA_FUNCTION_TIMEOUT;
473                 cond_resched();
474         }
475
476         /* TODO: What happens if we time out? */
477         data = 0xDEADDEAD;
478         if (rval == QLA_SUCCESS)
479                 data = RD_REG_DWORD(&reg->flash_data);
480
481         return data;
482 }
483
484 uint32_t *
485 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
486     uint32_t dwords)
487 {
488         uint32_t i;
489
490         /* Dword reads to flash. */
491         for (i = 0; i < dwords; i++, faddr++)
492                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
493                     flash_data_to_access_addr(faddr)));
494
495         return dwptr;
496 }
497
498 static int
499 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
500 {
501         int rval;
502         uint32_t cnt;
503         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
504
505         WRT_REG_DWORD(&reg->flash_data, data);
506         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
507         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
508         /* Wait for Write cycle to complete. */
509         rval = QLA_SUCCESS;
510         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
511             rval == QLA_SUCCESS; cnt--) {
512                 if (cnt)
513                         udelay(10);
514                 else
515                         rval = QLA_FUNCTION_TIMEOUT;
516                 cond_resched();
517         }
518         return rval;
519 }
520
521 static void
522 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
523     uint8_t *flash_id)
524 {
525         uint32_t ids;
526
527         ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
528         *man_id = LSB(ids);
529         *flash_id = MSB(ids);
530
531         /* Check if man_id and flash_id are valid. */
532         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
533                 /* Read information using 0x9f opcode
534                  * Device ID, Mfg ID would be read in the format:
535                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
536                  * Example: ATMEL 0x00 01 45 1F
537                  * Extract MFG and Dev ID from last two bytes.
538                  */
539                 ids = qla24xx_read_flash_dword(ha,
540                     flash_data_to_access_addr(0xd009f));
541                 *man_id = LSB(ids);
542                 *flash_id = MSB(ids);
543         }
544 }
545
546 static int
547 qla2xxx_find_flt_start(scsi_qla_host_t *ha, uint32_t *start)
548 {
549         const char *loc, *locations[] = { "DEF", "PCI" };
550         uint32_t pcihdr, pcids;
551         uint32_t *dcode;
552         uint8_t *buf, *bcode, last_image;
553         uint16_t cnt, chksum, *wptr;
554         struct qla_flt_location *fltl;
555
556         /*
557          * FLT-location structure resides after the last PCI region.
558          */
559
560         /* Begin with sane defaults. */
561         loc = locations[0];
562         *start = IS_QLA24XX_TYPE(ha) ? FA_FLASH_LAYOUT_ADDR_24:
563             FA_FLASH_LAYOUT_ADDR;
564
565         /* Begin with first PCI expansion ROM header. */
566         buf = (uint8_t *)ha->request_ring;
567         dcode = (uint32_t *)ha->request_ring;
568         pcihdr = 0;
569         last_image = 1;
570         do {
571                 /* Verify PCI expansion ROM header. */
572                 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
573                 bcode = buf + (pcihdr % 4);
574                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
575                         goto end;
576
577                 /* Locate PCI data structure. */
578                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
579                 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
580                 bcode = buf + (pcihdr % 4);
581
582                 /* Validate signature of PCI data structure. */
583                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
584                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
585                         goto end;
586
587                 last_image = bcode[0x15] & BIT_7;
588
589                 /* Locate next PCI expansion ROM. */
590                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
591         } while (!last_image);
592
593         /* Now verify FLT-location structure. */
594         fltl = (struct qla_flt_location *)ha->request_ring;
595         qla24xx_read_flash_data(ha, dcode, pcihdr >> 2,
596             sizeof(struct qla_flt_location) >> 2);
597         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
598             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
599                 goto end;
600
601         wptr = (uint16_t *)ha->request_ring;
602         cnt = sizeof(struct qla_flt_location) >> 1;
603         for (chksum = 0; cnt; cnt--)
604                 chksum += le16_to_cpu(*wptr++);
605         if (chksum) {
606                 qla_printk(KERN_ERR, ha,
607                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
608                 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
609                 return QLA_FUNCTION_FAILED;
610         }
611
612         /* Good data.  Use specified location. */
613         loc = locations[1];
614         *start = le16_to_cpu(fltl->start_hi) << 16 |
615             le16_to_cpu(fltl->start_lo);
616 end:
617         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
618         return QLA_SUCCESS;
619 }
620
621 static void
622 qla2xxx_get_flt_info(scsi_qla_host_t *ha, uint32_t flt_addr)
623 {
624         const char *loc, *locations[] = { "DEF", "FLT" };
625         uint16_t *wptr;
626         uint16_t cnt, chksum;
627         uint32_t start;
628         struct qla_flt_header *flt;
629         struct qla_flt_region *region;
630
631         ha->flt_region_flt = flt_addr;
632         wptr = (uint16_t *)ha->request_ring;
633         flt = (struct qla_flt_header *)ha->request_ring;
634         region = (struct qla_flt_region *)&flt[1];
635         ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring,
636             flt_addr << 2, OPTROM_BURST_SIZE);
637         if (*wptr == __constant_cpu_to_le16(0xffff))
638                 goto no_flash_data;
639         if (flt->version != __constant_cpu_to_le16(1)) {
640                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
641                     "version=0x%x length=0x%x checksum=0x%x.\n",
642                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
643                     le16_to_cpu(flt->checksum)));
644                 goto no_flash_data;
645         }
646
647         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
648         for (chksum = 0; cnt; cnt--)
649                 chksum += le16_to_cpu(*wptr++);
650         if (chksum) {
651                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
652                     "version=0x%x length=0x%x checksum=0x%x.\n",
653                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
654                     chksum));
655                 goto no_flash_data;
656         }
657
658         loc = locations[1];
659         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
660         for ( ; cnt; cnt--, region++) {
661                 /* Store addresses as DWORD offsets. */
662                 start = le32_to_cpu(region->start) >> 2;
663
664                 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
665                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
666                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
667
668                 switch (le32_to_cpu(region->code)) {
669                 case FLT_REG_FW:
670                         ha->flt_region_fw = start;
671                         break;
672                 case FLT_REG_BOOT_CODE:
673                         ha->flt_region_boot = start;
674                         break;
675                 case FLT_REG_VPD_0:
676                         ha->flt_region_vpd_nvram = start;
677                         break;
678                 case FLT_REG_FDT:
679                         ha->flt_region_fdt = start;
680                         break;
681                 case FLT_REG_HW_EVENT_0:
682                         if (!PCI_FUNC(ha->pdev->devfn))
683                                 ha->flt_region_hw_event = start;
684                         break;
685                 case FLT_REG_HW_EVENT_1:
686                         if (PCI_FUNC(ha->pdev->devfn))
687                                 ha->flt_region_hw_event = start;
688                         break;
689                 }
690         }
691         goto done;
692
693 no_flash_data:
694         /* Use hardcoded defaults. */
695         loc = locations[0];
696         ha->flt_region_fw = FA_RISC_CODE_ADDR;
697         ha->flt_region_boot = FA_BOOT_CODE_ADDR;
698         ha->flt_region_vpd_nvram = FA_VPD_NVRAM_ADDR;
699         ha->flt_region_fdt = IS_QLA24XX_TYPE(ha) ? FA_FLASH_DESCR_ADDR_24:
700             FA_FLASH_DESCR_ADDR;
701         ha->flt_region_hw_event = !PCI_FUNC(ha->pdev->devfn) ?
702             FA_HW_EVENT0_ADDR: FA_HW_EVENT1_ADDR;
703 done:
704         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
705             "vpd_nvram=0x%x fdt=0x%x flt=0x%x hwe=0x%x.\n", loc,
706             ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
707             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_hw_event));
708 }
709
710 static void
711 qla2xxx_get_fdt_info(scsi_qla_host_t *ha)
712 {
713 #define FLASH_BLK_SIZE_32K      0x8000
714 #define FLASH_BLK_SIZE_64K      0x10000
715         const char *loc, *locations[] = { "MID", "FDT" };
716         uint16_t cnt, chksum;
717         uint16_t *wptr;
718         struct qla_fdt_layout *fdt;
719         uint8_t man_id, flash_id;
720         uint16_t mid, fid;
721
722         wptr = (uint16_t *)ha->request_ring;
723         fdt = (struct qla_fdt_layout *)ha->request_ring;
724         ha->isp_ops->read_optrom(ha, (uint8_t *)ha->request_ring,
725             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
726         if (*wptr == __constant_cpu_to_le16(0xffff))
727                 goto no_flash_data;
728         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
729             fdt->sig[3] != 'D')
730                 goto no_flash_data;
731
732         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
733             cnt++)
734                 chksum += le16_to_cpu(*wptr++);
735         if (chksum) {
736                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
737                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
738                     le16_to_cpu(fdt->version)));
739                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
740                 goto no_flash_data;
741         }
742
743         loc = locations[1];
744         mid = le16_to_cpu(fdt->man_id);
745         fid = le16_to_cpu(fdt->id);
746         ha->fdt_odd_index = mid == 0x1f;
747         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
748         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0300 | fdt->erase_cmd);
749         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
750         if (fdt->unprotect_sec_cmd) {
751                 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0300 |
752                     fdt->unprotect_sec_cmd);
753                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
754                     flash_conf_to_access_addr(0x0300 | fdt->protect_sec_cmd):
755                     flash_conf_to_access_addr(0x0336);
756         }
757         goto done;
758 no_flash_data:
759         loc = locations[0];
760         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
761         mid = man_id;
762         fid = flash_id;
763         ha->fdt_wrt_disable = 0x9c;
764         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x03d8);
765         switch (man_id) {
766         case 0xbf: /* STT flash. */
767                 if (flash_id == 0x8e)
768                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
769                 else
770                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
771
772                 if (flash_id == 0x80)
773                         ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0352);
774                 break;
775         case 0x13: /* ST M25P80. */
776                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
777                 break;
778         case 0x1f: /* Atmel 26DF081A. */
779                 ha->fdt_odd_index = 1;
780                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
781                 ha->fdt_erase_cmd = flash_conf_to_access_addr(0x0320);
782                 ha->fdt_unprotect_sec_cmd = flash_conf_to_access_addr(0x0339);
783                 ha->fdt_protect_sec_cmd = flash_conf_to_access_addr(0x0336);
784                 break;
785         default:
786                 /* Default to 64 kb sector size. */
787                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
788                 break;
789         }
790 done:
791         DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
792             "pro=%x upro=%x idx=%d wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
793             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
794             ha->fdt_unprotect_sec_cmd, ha->fdt_odd_index, ha->fdt_wrt_disable,
795             ha->fdt_block_size));
796 }
797
798 int
799 qla2xxx_get_flash_info(scsi_qla_host_t *ha)
800 {
801         int ret;
802         uint32_t flt_addr;
803
804         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
805                 return QLA_SUCCESS;
806
807         ret = qla2xxx_find_flt_start(ha, &flt_addr);
808         if (ret != QLA_SUCCESS)
809                 return ret;
810
811         qla2xxx_get_flt_info(ha, flt_addr);
812         qla2xxx_get_fdt_info(ha);
813
814         return QLA_SUCCESS;
815 }
816
817 static void
818 qla24xx_unprotect_flash(scsi_qla_host_t *ha)
819 {
820         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
821
822         /* Enable flash write. */
823         WRT_REG_DWORD(&reg->ctrl_status,
824             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
825         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
826
827         if (!ha->fdt_wrt_disable)
828                 return;
829
830         /* Disable flash write-protection. */
831         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
832         /* Some flash parts need an additional zero-write to clear bits.*/
833         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
834 }
835
836 static void
837 qla24xx_protect_flash(scsi_qla_host_t *ha)
838 {
839         uint32_t cnt;
840         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
841
842         if (!ha->fdt_wrt_disable)
843                 goto skip_wrt_protect;
844
845         /* Enable flash write-protection and wait for completion. */
846         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101),
847             ha->fdt_wrt_disable);
848         for (cnt = 300; cnt &&
849             qla24xx_read_flash_dword(ha,
850                     flash_conf_to_access_addr(0x005)) & BIT_0;
851             cnt--) {
852                 udelay(10);
853         }
854
855 skip_wrt_protect:
856         /* Disable flash write. */
857         WRT_REG_DWORD(&reg->ctrl_status,
858             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
859         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
860 }
861
862 static int
863 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
864     uint32_t dwords)
865 {
866         int ret;
867         uint32_t liter, miter;
868         uint32_t sec_mask, rest_addr;
869         uint32_t fdata, findex;
870         dma_addr_t optrom_dma;
871         void *optrom = NULL;
872         uint32_t *s, *d;
873
874         ret = QLA_SUCCESS;
875
876         /* Prepare burst-capable write on supported ISPs. */
877         if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
878             dwords > OPTROM_BURST_DWORDS) {
879                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
880                     &optrom_dma, GFP_KERNEL);
881                 if (!optrom) {
882                         qla_printk(KERN_DEBUG, ha,
883                             "Unable to allocate memory for optrom burst write "
884                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
885                 }
886         }
887
888         rest_addr = (ha->fdt_block_size >> 2) - 1;
889         sec_mask = 0x80000 - (ha->fdt_block_size >> 2);
890
891         qla24xx_unprotect_flash(ha);
892
893         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
894                 if (ha->fdt_odd_index) {
895                         findex = faddr << 2;
896                         fdata = findex & sec_mask;
897                 } else {
898                         findex = faddr;
899                         fdata = (findex & sec_mask) << 2;
900                 }
901
902                 /* Are we at the beginning of a sector? */
903                 if ((findex & rest_addr) == 0) {
904                         /* Do sector unprotect. */
905                         if (ha->fdt_unprotect_sec_cmd)
906                                 qla24xx_write_flash_dword(ha,
907                                     ha->fdt_unprotect_sec_cmd,
908                                     (fdata & 0xff00) | ((fdata << 16) &
909                                     0xff0000) | ((fdata >> 16) & 0xff));
910                         ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
911                             (fdata & 0xff00) |((fdata << 16) &
912                             0xff0000) | ((fdata >> 16) & 0xff));
913                         if (ret != QLA_SUCCESS) {
914                                 DEBUG9(printk("%s(%ld) Unable to flash "
915                                     "sector: address=%x.\n", __func__,
916                                     ha->host_no, faddr));
917                                 break;
918                         }
919                 }
920
921                 /* Go with burst-write. */
922                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
923                         /* Copy data to DMA'ble buffer. */
924                         for (miter = 0, s = optrom, d = dwptr;
925                             miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
926                                 *s = cpu_to_le32(*d);
927
928                         ret = qla2x00_load_ram(ha, optrom_dma,
929                             flash_data_to_access_addr(faddr),
930                             OPTROM_BURST_DWORDS);
931                         if (ret != QLA_SUCCESS) {
932                                 qla_printk(KERN_WARNING, ha,
933                                     "Unable to burst-write optrom segment "
934                                     "(%x/%x/%llx).\n", ret,
935                                     flash_data_to_access_addr(faddr),
936                                     (unsigned long long)optrom_dma);
937                                 qla_printk(KERN_WARNING, ha,
938                                     "Reverting to slow-write.\n");
939
940                                 dma_free_coherent(&ha->pdev->dev,
941                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
942                                 optrom = NULL;
943                         } else {
944                                 liter += OPTROM_BURST_DWORDS - 1;
945                                 faddr += OPTROM_BURST_DWORDS - 1;
946                                 dwptr += OPTROM_BURST_DWORDS - 1;
947                                 continue;
948                         }
949                 }
950
951                 ret = qla24xx_write_flash_dword(ha,
952                     flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
953                 if (ret != QLA_SUCCESS) {
954                         DEBUG9(printk("%s(%ld) Unable to program flash "
955                             "address=%x data=%x.\n", __func__,
956                             ha->host_no, faddr, *dwptr));
957                         break;
958                 }
959
960                 /* Do sector protect. */
961                 if (ha->fdt_unprotect_sec_cmd &&
962                     ((faddr & rest_addr) == rest_addr))
963                         qla24xx_write_flash_dword(ha,
964                             ha->fdt_protect_sec_cmd,
965                             (fdata & 0xff00) | ((fdata << 16) &
966                             0xff0000) | ((fdata >> 16) & 0xff));
967         }
968
969         qla24xx_protect_flash(ha);
970
971         if (optrom)
972                 dma_free_coherent(&ha->pdev->dev,
973                     OPTROM_BURST_SIZE, optrom, optrom_dma);
974
975         return ret;
976 }
977
978 uint8_t *
979 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
980     uint32_t bytes)
981 {
982         uint32_t i;
983         uint16_t *wptr;
984
985         /* Word reads to NVRAM via registers. */
986         wptr = (uint16_t *)buf;
987         qla2x00_lock_nvram_access(ha);
988         for (i = 0; i < bytes >> 1; i++, naddr++)
989                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
990                     naddr));
991         qla2x00_unlock_nvram_access(ha);
992
993         return buf;
994 }
995
996 uint8_t *
997 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
998     uint32_t bytes)
999 {
1000         uint32_t i;
1001         uint32_t *dwptr;
1002
1003         /* Dword reads to flash. */
1004         dwptr = (uint32_t *)buf;
1005         for (i = 0; i < bytes >> 2; i++, naddr++)
1006                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1007                     nvram_data_to_access_addr(naddr)));
1008
1009         return buf;
1010 }
1011
1012 int
1013 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1014     uint32_t bytes)
1015 {
1016         int ret, stat;
1017         uint32_t i;
1018         uint16_t *wptr;
1019         unsigned long flags;
1020
1021         ret = QLA_SUCCESS;
1022
1023         spin_lock_irqsave(&ha->hardware_lock, flags);
1024         qla2x00_lock_nvram_access(ha);
1025
1026         /* Disable NVRAM write-protection. */
1027         stat = qla2x00_clear_nvram_protection(ha);
1028
1029         wptr = (uint16_t *)buf;
1030         for (i = 0; i < bytes >> 1; i++, naddr++) {
1031                 qla2x00_write_nvram_word(ha, naddr,
1032                     cpu_to_le16(*wptr));
1033                 wptr++;
1034         }
1035
1036         /* Enable NVRAM write-protection. */
1037         qla2x00_set_nvram_protection(ha, stat);
1038
1039         qla2x00_unlock_nvram_access(ha);
1040         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1041
1042         return ret;
1043 }
1044
1045 int
1046 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1047     uint32_t bytes)
1048 {
1049         int ret;
1050         uint32_t i;
1051         uint32_t *dwptr;
1052         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1053
1054         ret = QLA_SUCCESS;
1055
1056         /* Enable flash write. */
1057         WRT_REG_DWORD(&reg->ctrl_status,
1058             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1059         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1060
1061         /* Disable NVRAM write-protection. */
1062         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1063             0);
1064         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1065             0);
1066
1067         /* Dword writes to flash. */
1068         dwptr = (uint32_t *)buf;
1069         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1070                 ret = qla24xx_write_flash_dword(ha,
1071                     nvram_data_to_access_addr(naddr),
1072                     cpu_to_le32(*dwptr));
1073                 if (ret != QLA_SUCCESS) {
1074                         DEBUG9(printk("%s(%ld) Unable to program "
1075                             "nvram address=%x data=%x.\n", __func__,
1076                             ha->host_no, naddr, *dwptr));
1077                         break;
1078                 }
1079         }
1080
1081         /* Enable NVRAM write-protection. */
1082         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
1083             0x8c);
1084
1085         /* Disable flash write. */
1086         WRT_REG_DWORD(&reg->ctrl_status,
1087             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1088         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1089
1090         return ret;
1091 }
1092
1093 uint8_t *
1094 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1095     uint32_t bytes)
1096 {
1097         uint32_t i;
1098         uint32_t *dwptr;
1099
1100         /* Dword reads to flash. */
1101         dwptr = (uint32_t *)buf;
1102         for (i = 0; i < bytes >> 2; i++, naddr++)
1103                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1104                     flash_data_to_access_addr(ha->flt_region_vpd_nvram |
1105                     naddr)));
1106
1107         return buf;
1108 }
1109
1110 int
1111 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
1112     uint32_t bytes)
1113 {
1114 #define RMW_BUFFER_SIZE (64 * 1024)
1115         uint8_t *dbuf;
1116
1117         dbuf = vmalloc(RMW_BUFFER_SIZE);
1118         if (!dbuf)
1119                 return QLA_MEMORY_ALLOC_FAILED;
1120         ha->isp_ops->read_optrom(ha, dbuf, ha->flt_region_vpd_nvram << 2,
1121             RMW_BUFFER_SIZE);
1122         memcpy(dbuf + (naddr << 2), buf, bytes);
1123         ha->isp_ops->write_optrom(ha, dbuf, ha->flt_region_vpd_nvram << 2,
1124             RMW_BUFFER_SIZE);
1125         vfree(dbuf);
1126
1127         return QLA_SUCCESS;
1128 }
1129
1130 static inline void
1131 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1132 {
1133         if (IS_QLA2322(ha)) {
1134                 /* Flip all colors. */
1135                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1136                         /* Turn off. */
1137                         ha->beacon_color_state = 0;
1138                         *pflags = GPIO_LED_ALL_OFF;
1139                 } else {
1140                         /* Turn on. */
1141                         ha->beacon_color_state = QLA_LED_ALL_ON;
1142                         *pflags = GPIO_LED_RGA_ON;
1143                 }
1144         } else {
1145                 /* Flip green led only. */
1146                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1147                         /* Turn off. */
1148                         ha->beacon_color_state = 0;
1149                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1150                 } else {
1151                         /* Turn on. */
1152                         ha->beacon_color_state = QLA_LED_GRN_ON;
1153                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1154                 }
1155         }
1156 }
1157
1158 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1159
1160 void
1161 qla2x00_beacon_blink(struct scsi_qla_host *ha)
1162 {
1163         uint16_t gpio_enable;
1164         uint16_t gpio_data;
1165         uint16_t led_color = 0;
1166         unsigned long flags;
1167         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1168
1169         spin_lock_irqsave(&ha->hardware_lock, flags);
1170
1171         /* Save the Original GPIOE. */
1172         if (ha->pio_address) {
1173                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1174                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1175         } else {
1176                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1177                 gpio_data = RD_REG_WORD(&reg->gpiod);
1178         }
1179
1180         /* Set the modified gpio_enable values */
1181         gpio_enable |= GPIO_LED_MASK;
1182
1183         if (ha->pio_address) {
1184                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1185         } else {
1186                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1187                 RD_REG_WORD(&reg->gpioe);
1188         }
1189
1190         qla2x00_flip_colors(ha, &led_color);
1191
1192         /* Clear out any previously set LED color. */
1193         gpio_data &= ~GPIO_LED_MASK;
1194
1195         /* Set the new input LED color to GPIOD. */
1196         gpio_data |= led_color;
1197
1198         /* Set the modified gpio_data values */
1199         if (ha->pio_address) {
1200                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1201         } else {
1202                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1203                 RD_REG_WORD(&reg->gpiod);
1204         }
1205
1206         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1207 }
1208
1209 int
1210 qla2x00_beacon_on(struct scsi_qla_host *ha)
1211 {
1212         uint16_t gpio_enable;
1213         uint16_t gpio_data;
1214         unsigned long flags;
1215         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1216
1217         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1218         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1219
1220         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1221                 qla_printk(KERN_WARNING, ha,
1222                     "Unable to update fw options (beacon on).\n");
1223                 return QLA_FUNCTION_FAILED;
1224         }
1225
1226         /* Turn off LEDs. */
1227         spin_lock_irqsave(&ha->hardware_lock, flags);
1228         if (ha->pio_address) {
1229                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1230                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1231         } else {
1232                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1233                 gpio_data = RD_REG_WORD(&reg->gpiod);
1234         }
1235         gpio_enable |= GPIO_LED_MASK;
1236
1237         /* Set the modified gpio_enable values. */
1238         if (ha->pio_address) {
1239                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1240         } else {
1241                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1242                 RD_REG_WORD(&reg->gpioe);
1243         }
1244
1245         /* Clear out previously set LED colour. */
1246         gpio_data &= ~GPIO_LED_MASK;
1247         if (ha->pio_address) {
1248                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1249         } else {
1250                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1251                 RD_REG_WORD(&reg->gpiod);
1252         }
1253         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1254
1255         /*
1256          * Let the per HBA timer kick off the blinking process based on
1257          * the following flags. No need to do anything else now.
1258          */
1259         ha->beacon_blink_led = 1;
1260         ha->beacon_color_state = 0;
1261
1262         return QLA_SUCCESS;
1263 }
1264
1265 int
1266 qla2x00_beacon_off(struct scsi_qla_host *ha)
1267 {
1268         int rval = QLA_SUCCESS;
1269
1270         ha->beacon_blink_led = 0;
1271
1272         /* Set the on flag so when it gets flipped it will be off. */
1273         if (IS_QLA2322(ha))
1274                 ha->beacon_color_state = QLA_LED_ALL_ON;
1275         else
1276                 ha->beacon_color_state = QLA_LED_GRN_ON;
1277
1278         ha->isp_ops->beacon_blink(ha);  /* This turns green LED off */
1279
1280         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1281         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1282
1283         rval = qla2x00_set_fw_options(ha, ha->fw_options);
1284         if (rval != QLA_SUCCESS)
1285                 qla_printk(KERN_WARNING, ha,
1286                     "Unable to update fw options (beacon off).\n");
1287         return rval;
1288 }
1289
1290
1291 static inline void
1292 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1293 {
1294         /* Flip all colors. */
1295         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1296                 /* Turn off. */
1297                 ha->beacon_color_state = 0;
1298                 *pflags = 0;
1299         } else {
1300                 /* Turn on. */
1301                 ha->beacon_color_state = QLA_LED_ALL_ON;
1302                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1303         }
1304 }
1305
1306 void
1307 qla24xx_beacon_blink(struct scsi_qla_host *ha)
1308 {
1309         uint16_t led_color = 0;
1310         uint32_t gpio_data;
1311         unsigned long flags;
1312         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1313
1314         /* Save the Original GPIOD. */
1315         spin_lock_irqsave(&ha->hardware_lock, flags);
1316         gpio_data = RD_REG_DWORD(&reg->gpiod);
1317
1318         /* Enable the gpio_data reg for update. */
1319         gpio_data |= GPDX_LED_UPDATE_MASK;
1320
1321         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1322         gpio_data = RD_REG_DWORD(&reg->gpiod);
1323
1324         /* Set the color bits. */
1325         qla24xx_flip_colors(ha, &led_color);
1326
1327         /* Clear out any previously set LED color. */
1328         gpio_data &= ~GPDX_LED_COLOR_MASK;
1329
1330         /* Set the new input LED color to GPIOD. */
1331         gpio_data |= led_color;
1332
1333         /* Set the modified gpio_data values. */
1334         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1335         gpio_data = RD_REG_DWORD(&reg->gpiod);
1336         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1337 }
1338
1339 int
1340 qla24xx_beacon_on(struct scsi_qla_host *ha)
1341 {
1342         uint32_t gpio_data;
1343         unsigned long flags;
1344         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1345
1346         if (ha->beacon_blink_led == 0) {
1347                 /* Enable firmware for update */
1348                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1349
1350                 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
1351                         return QLA_FUNCTION_FAILED;
1352
1353                 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
1354                     QLA_SUCCESS) {
1355                         qla_printk(KERN_WARNING, ha,
1356                             "Unable to update fw options (beacon on).\n");
1357                         return QLA_FUNCTION_FAILED;
1358                 }
1359
1360                 spin_lock_irqsave(&ha->hardware_lock, flags);
1361                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1362
1363                 /* Enable the gpio_data reg for update. */
1364                 gpio_data |= GPDX_LED_UPDATE_MASK;
1365                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1366                 RD_REG_DWORD(&reg->gpiod);
1367
1368                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1369         }
1370
1371         /* So all colors blink together. */
1372         ha->beacon_color_state = 0;
1373
1374         /* Let the per HBA timer kick off the blinking process. */
1375         ha->beacon_blink_led = 1;
1376
1377         return QLA_SUCCESS;
1378 }
1379
1380 int
1381 qla24xx_beacon_off(struct scsi_qla_host *ha)
1382 {
1383         uint32_t gpio_data;
1384         unsigned long flags;
1385         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1386
1387         ha->beacon_blink_led = 0;
1388         ha->beacon_color_state = QLA_LED_ALL_ON;
1389
1390         ha->isp_ops->beacon_blink(ha);  /* Will flip to all off. */
1391
1392         /* Give control back to firmware. */
1393         spin_lock_irqsave(&ha->hardware_lock, flags);
1394         gpio_data = RD_REG_DWORD(&reg->gpiod);
1395
1396         /* Disable the gpio_data reg for update. */
1397         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1398         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1399         RD_REG_DWORD(&reg->gpiod);
1400         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1401
1402         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1403
1404         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1405                 qla_printk(KERN_WARNING, ha,
1406                     "Unable to update fw options (beacon off).\n");
1407                 return QLA_FUNCTION_FAILED;
1408         }
1409
1410         if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1411                 qla_printk(KERN_WARNING, ha,
1412                     "Unable to get fw options (beacon off).\n");
1413                 return QLA_FUNCTION_FAILED;
1414         }
1415
1416         return QLA_SUCCESS;
1417 }
1418
1419
1420 /*
1421  * Flash support routines
1422  */
1423
1424 /**
1425  * qla2x00_flash_enable() - Setup flash for reading and writing.
1426  * @ha: HA context
1427  */
1428 static void
1429 qla2x00_flash_enable(scsi_qla_host_t *ha)
1430 {
1431         uint16_t data;
1432         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1433
1434         data = RD_REG_WORD(&reg->ctrl_status);
1435         data |= CSR_FLASH_ENABLE;
1436         WRT_REG_WORD(&reg->ctrl_status, data);
1437         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1438 }
1439
1440 /**
1441  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1442  * @ha: HA context
1443  */
1444 static void
1445 qla2x00_flash_disable(scsi_qla_host_t *ha)
1446 {
1447         uint16_t data;
1448         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1449
1450         data = RD_REG_WORD(&reg->ctrl_status);
1451         data &= ~(CSR_FLASH_ENABLE);
1452         WRT_REG_WORD(&reg->ctrl_status, data);
1453         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1454 }
1455
1456 /**
1457  * qla2x00_read_flash_byte() - Reads a byte from flash
1458  * @ha: HA context
1459  * @addr: Address in flash to read
1460  *
1461  * A word is read from the chip, but, only the lower byte is valid.
1462  *
1463  * Returns the byte read from flash @addr.
1464  */
1465 static uint8_t
1466 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1467 {
1468         uint16_t data;
1469         uint16_t bank_select;
1470         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1471
1472         bank_select = RD_REG_WORD(&reg->ctrl_status);
1473
1474         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1475                 /* Specify 64K address range: */
1476                 /*  clear out Module Select and Flash Address bits [19:16]. */
1477                 bank_select &= ~0xf8;
1478                 bank_select |= addr >> 12 & 0xf0;
1479                 bank_select |= CSR_FLASH_64K_BANK;
1480                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1481                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1482
1483                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1484                 data = RD_REG_WORD(&reg->flash_data);
1485
1486                 return (uint8_t)data;
1487         }
1488
1489         /* Setup bit 16 of flash address. */
1490         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1491                 bank_select |= CSR_FLASH_64K_BANK;
1492                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1493                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1494         } else if (((addr & BIT_16) == 0) &&
1495             (bank_select & CSR_FLASH_64K_BANK)) {
1496                 bank_select &= ~(CSR_FLASH_64K_BANK);
1497                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1498                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1499         }
1500
1501         /* Always perform IO mapped accesses to the FLASH registers. */
1502         if (ha->pio_address) {
1503                 uint16_t data2;
1504
1505                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1506                 do {
1507                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1508                         barrier();
1509                         cpu_relax();
1510                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1511                 } while (data != data2);
1512         } else {
1513                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1514                 data = qla2x00_debounce_register(&reg->flash_data);
1515         }
1516
1517         return (uint8_t)data;
1518 }
1519
1520 /**
1521  * qla2x00_write_flash_byte() - Write a byte to flash
1522  * @ha: HA context
1523  * @addr: Address in flash to write
1524  * @data: Data to write
1525  */
1526 static void
1527 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1528 {
1529         uint16_t bank_select;
1530         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1531
1532         bank_select = RD_REG_WORD(&reg->ctrl_status);
1533         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1534                 /* Specify 64K address range: */
1535                 /*  clear out Module Select and Flash Address bits [19:16]. */
1536                 bank_select &= ~0xf8;
1537                 bank_select |= addr >> 12 & 0xf0;
1538                 bank_select |= CSR_FLASH_64K_BANK;
1539                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1540                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1541
1542                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1543                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1544                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1545                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1546
1547                 return;
1548         }
1549
1550         /* Setup bit 16 of flash address. */
1551         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1552                 bank_select |= CSR_FLASH_64K_BANK;
1553                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1554                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1555         } else if (((addr & BIT_16) == 0) &&
1556             (bank_select & CSR_FLASH_64K_BANK)) {
1557                 bank_select &= ~(CSR_FLASH_64K_BANK);
1558                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1559                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1560         }
1561
1562         /* Always perform IO mapped accesses to the FLASH registers. */
1563         if (ha->pio_address) {
1564                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1565                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1566         } else {
1567                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1568                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1569                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1570                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1571         }
1572 }
1573
1574 /**
1575  * qla2x00_poll_flash() - Polls flash for completion.
1576  * @ha: HA context
1577  * @addr: Address in flash to poll
1578  * @poll_data: Data to be polled
1579  * @man_id: Flash manufacturer ID
1580  * @flash_id: Flash ID
1581  *
1582  * This function polls the device until bit 7 of what is read matches data
1583  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1584  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1585  * reading bit 5 as a 1.
1586  *
1587  * Returns 0 on success, else non-zero.
1588  */
1589 static int
1590 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1591     uint8_t man_id, uint8_t flash_id)
1592 {
1593         int status;
1594         uint8_t flash_data;
1595         uint32_t cnt;
1596
1597         status = 1;
1598
1599         /* Wait for 30 seconds for command to finish. */
1600         poll_data &= BIT_7;
1601         for (cnt = 3000000; cnt; cnt--) {
1602                 flash_data = qla2x00_read_flash_byte(ha, addr);
1603                 if ((flash_data & BIT_7) == poll_data) {
1604                         status = 0;
1605                         break;
1606                 }
1607
1608                 if (man_id != 0x40 && man_id != 0xda) {
1609                         if ((flash_data & BIT_5) && cnt > 2)
1610                                 cnt = 2;
1611                 }
1612                 udelay(10);
1613                 barrier();
1614                 cond_resched();
1615         }
1616         return status;
1617 }
1618
1619 /**
1620  * qla2x00_program_flash_address() - Programs a flash address
1621  * @ha: HA context
1622  * @addr: Address in flash to program
1623  * @data: Data to be written in flash
1624  * @man_id: Flash manufacturer ID
1625  * @flash_id: Flash ID
1626  *
1627  * Returns 0 on success, else non-zero.
1628  */
1629 static int
1630 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1631     uint8_t man_id, uint8_t flash_id)
1632 {
1633         /* Write Program Command Sequence. */
1634         if (IS_OEM_001(ha)) {
1635                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1636                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1637                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1638                 qla2x00_write_flash_byte(ha, addr, data);
1639         } else {
1640                 if (man_id == 0xda && flash_id == 0xc1) {
1641                         qla2x00_write_flash_byte(ha, addr, data);
1642                         if (addr & 0x7e)
1643                                 return 0;
1644                 } else {
1645                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1646                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1647                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1648                         qla2x00_write_flash_byte(ha, addr, data);
1649                 }
1650         }
1651
1652         udelay(150);
1653
1654         /* Wait for write to complete. */
1655         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1656 }
1657
1658 /**
1659  * qla2x00_erase_flash() - Erase the flash.
1660  * @ha: HA context
1661  * @man_id: Flash manufacturer ID
1662  * @flash_id: Flash ID
1663  *
1664  * Returns 0 on success, else non-zero.
1665  */
1666 static int
1667 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1668 {
1669         /* Individual Sector Erase Command Sequence */
1670         if (IS_OEM_001(ha)) {
1671                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1672                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1673                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1674                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1675                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1676                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1677         } else {
1678                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1679                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1680                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1681                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1682                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1683                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1684         }
1685
1686         udelay(150);
1687
1688         /* Wait for erase to complete. */
1689         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1690 }
1691
1692 /**
1693  * qla2x00_erase_flash_sector() - Erase a flash sector.
1694  * @ha: HA context
1695  * @addr: Flash sector to erase
1696  * @sec_mask: Sector address mask
1697  * @man_id: Flash manufacturer ID
1698  * @flash_id: Flash ID
1699  *
1700  * Returns 0 on success, else non-zero.
1701  */
1702 static int
1703 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1704     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1705 {
1706         /* Individual Sector Erase Command Sequence */
1707         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1708         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1709         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1710         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1711         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1712         if (man_id == 0x1f && flash_id == 0x13)
1713                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1714         else
1715                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1716
1717         udelay(150);
1718
1719         /* Wait for erase to complete. */
1720         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1721 }
1722
1723 /**
1724  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1725  * @man_id: Flash manufacturer ID
1726  * @flash_id: Flash ID
1727  */
1728 static void
1729 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1730     uint8_t *flash_id)
1731 {
1732         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1733         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1734         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1735         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1736         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1737         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1738         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1739         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1740 }
1741
1742 static void
1743 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1744         uint32_t length)
1745 {
1746         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1747         uint32_t midpoint, ilength;
1748         uint8_t data;
1749
1750         midpoint = length / 2;
1751
1752         WRT_REG_WORD(&reg->nvram, 0);
1753         RD_REG_WORD(&reg->nvram);
1754         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1755                 if (ilength == midpoint) {
1756                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1757                         RD_REG_WORD(&reg->nvram);
1758                 }
1759                 data = qla2x00_read_flash_byte(ha, saddr);
1760                 if (saddr % 100)
1761                         udelay(10);
1762                 *tmp_buf = data;
1763                 cond_resched();
1764         }
1765 }
1766
1767 static inline void
1768 qla2x00_suspend_hba(struct scsi_qla_host *ha)
1769 {
1770         int cnt;
1771         unsigned long flags;
1772         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1773
1774         /* Suspend HBA. */
1775         scsi_block_requests(ha->host);
1776         ha->isp_ops->disable_intrs(ha);
1777         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1778
1779         /* Pause RISC. */
1780         spin_lock_irqsave(&ha->hardware_lock, flags);
1781         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1782         RD_REG_WORD(&reg->hccr);
1783         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1784                 for (cnt = 0; cnt < 30000; cnt++) {
1785                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1786                                 break;
1787                         udelay(100);
1788                 }
1789         } else {
1790                 udelay(10);
1791         }
1792         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1793 }
1794
1795 static inline void
1796 qla2x00_resume_hba(struct scsi_qla_host *ha)
1797 {
1798         /* Resume HBA. */
1799         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1800         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1801         qla2xxx_wake_dpc(ha);
1802         qla2x00_wait_for_hba_online(ha);
1803         scsi_unblock_requests(ha->host);
1804 }
1805
1806 uint8_t *
1807 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1808     uint32_t offset, uint32_t length)
1809 {
1810         uint32_t addr, midpoint;
1811         uint8_t *data;
1812         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1813
1814         /* Suspend HBA. */
1815         qla2x00_suspend_hba(ha);
1816
1817         /* Go with read. */
1818         midpoint = ha->optrom_size / 2;
1819
1820         qla2x00_flash_enable(ha);
1821         WRT_REG_WORD(&reg->nvram, 0);
1822         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
1823         for (addr = offset, data = buf; addr < length; addr++, data++) {
1824                 if (addr == midpoint) {
1825                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1826                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
1827                 }
1828
1829                 *data = qla2x00_read_flash_byte(ha, addr);
1830         }
1831         qla2x00_flash_disable(ha);
1832
1833         /* Resume HBA. */
1834         qla2x00_resume_hba(ha);
1835
1836         return buf;
1837 }
1838
1839 int
1840 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1841     uint32_t offset, uint32_t length)
1842 {
1843
1844         int rval;
1845         uint8_t man_id, flash_id, sec_number, data;
1846         uint16_t wd;
1847         uint32_t addr, liter, sec_mask, rest_addr;
1848         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1849
1850         /* Suspend HBA. */
1851         qla2x00_suspend_hba(ha);
1852
1853         rval = QLA_SUCCESS;
1854         sec_number = 0;
1855
1856         /* Reset ISP chip. */
1857         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1858         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1859
1860         /* Go with write. */
1861         qla2x00_flash_enable(ha);
1862         do {    /* Loop once to provide quick error exit */
1863                 /* Structure of flash memory based on manufacturer */
1864                 if (IS_OEM_001(ha)) {
1865                         /* OEM variant with special flash part. */
1866                         man_id = flash_id = 0;
1867                         rest_addr = 0xffff;
1868                         sec_mask   = 0x10000;
1869                         goto update_flash;
1870                 }
1871                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1872                 switch (man_id) {
1873                 case 0x20: /* ST flash. */
1874                         if (flash_id == 0xd2 || flash_id == 0xe3) {
1875                                 /*
1876                                  * ST m29w008at part - 64kb sector size with
1877                                  * 32kb,8kb,8kb,16kb sectors at memory address
1878                                  * 0xf0000.
1879                                  */
1880                                 rest_addr = 0xffff;
1881                                 sec_mask = 0x10000;
1882                                 break;   
1883                         }
1884                         /*
1885                          * ST m29w010b part - 16kb sector size
1886                          * Default to 16kb sectors
1887                          */
1888                         rest_addr = 0x3fff;
1889                         sec_mask = 0x1c000;
1890                         break;
1891                 case 0x40: /* Mostel flash. */
1892                         /* Mostel v29c51001 part - 512 byte sector size. */
1893                         rest_addr = 0x1ff;
1894                         sec_mask = 0x1fe00;
1895                         break;
1896                 case 0xbf: /* SST flash. */
1897                         /* SST39sf10 part - 4kb sector size. */
1898                         rest_addr = 0xfff;
1899                         sec_mask = 0x1f000;
1900                         break;
1901                 case 0xda: /* Winbond flash. */
1902                         /* Winbond W29EE011 part - 256 byte sector size. */
1903                         rest_addr = 0x7f;
1904                         sec_mask = 0x1ff80;
1905                         break;
1906                 case 0xc2: /* Macronix flash. */
1907                         /* 64k sector size. */
1908                         if (flash_id == 0x38 || flash_id == 0x4f) {
1909                                 rest_addr = 0xffff;
1910                                 sec_mask = 0x10000;
1911                                 break;
1912                         }
1913                         /* Fall through... */
1914
1915                 case 0x1f: /* Atmel flash. */
1916                         /* 512k sector size. */
1917                         if (flash_id == 0x13) {
1918                                 rest_addr = 0x7fffffff;
1919                                 sec_mask =   0x80000000;
1920                                 break;
1921                         }
1922                         /* Fall through... */
1923
1924                 case 0x01: /* AMD flash. */
1925                         if (flash_id == 0x38 || flash_id == 0x40 ||
1926                             flash_id == 0x4f) {
1927                                 /* Am29LV081 part - 64kb sector size. */
1928                                 /* Am29LV002BT part - 64kb sector size. */
1929                                 rest_addr = 0xffff;
1930                                 sec_mask = 0x10000;
1931                                 break;
1932                         } else if (flash_id == 0x3e) {
1933                                 /*
1934                                  * Am29LV008b part - 64kb sector size with
1935                                  * 32kb,8kb,8kb,16kb sector at memory address
1936                                  * h0xf0000.
1937                                  */
1938                                 rest_addr = 0xffff;
1939                                 sec_mask = 0x10000;
1940                                 break;
1941                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
1942                                 /*
1943                                  * Am29LV010 part or AM29f010 - 16kb sector
1944                                  * size.
1945                                  */
1946                                 rest_addr = 0x3fff;
1947                                 sec_mask = 0x1c000;
1948                                 break;
1949                         } else if (flash_id == 0x6d) {
1950                                 /* Am29LV001 part - 8kb sector size. */
1951                                 rest_addr = 0x1fff;
1952                                 sec_mask = 0x1e000;
1953                                 break;
1954                         }
1955                 default:
1956                         /* Default to 16 kb sector size. */
1957                         rest_addr = 0x3fff;
1958                         sec_mask = 0x1c000;
1959                         break;
1960                 }
1961
1962 update_flash:
1963                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1964                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1965                                 rval = QLA_FUNCTION_FAILED;
1966                                 break;
1967                         }
1968                 }
1969
1970                 for (addr = offset, liter = 0; liter < length; liter++,
1971                     addr++) {
1972                         data = buf[liter];
1973                         /* Are we at the beginning of a sector? */
1974                         if ((addr & rest_addr) == 0) {
1975                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1976                                         if (addr >= 0x10000UL) {
1977                                                 if (((addr >> 12) & 0xf0) &&
1978                                                     ((man_id == 0x01 &&
1979                                                         flash_id == 0x3e) ||
1980                                                      (man_id == 0x20 &&
1981                                                          flash_id == 0xd2))) {
1982                                                         sec_number++;
1983                                                         if (sec_number == 1) {
1984                                                                 rest_addr =
1985                                                                     0x7fff;
1986                                                                 sec_mask =
1987                                                                     0x18000;
1988                                                         } else if (
1989                                                             sec_number == 2 ||
1990                                                             sec_number == 3) {
1991                                                                 rest_addr =
1992                                                                     0x1fff;
1993                                                                 sec_mask =
1994                                                                     0x1e000;
1995                                                         } else if (
1996                                                             sec_number == 4) {
1997                                                                 rest_addr =
1998                                                                     0x3fff;
1999                                                                 sec_mask =
2000                                                                     0x1c000;
2001                                                         }
2002                                                 }
2003                                         }
2004                                 } else if (addr == ha->optrom_size / 2) {
2005                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2006                                         RD_REG_WORD(&reg->nvram);
2007                                 }
2008
2009                                 if (flash_id == 0xda && man_id == 0xc1) {
2010                                         qla2x00_write_flash_byte(ha, 0x5555,
2011                                             0xaa);
2012                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2013                                             0x55);
2014                                         qla2x00_write_flash_byte(ha, 0x5555,
2015                                             0xa0);
2016                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2017                                         /* Then erase it */
2018                                         if (qla2x00_erase_flash_sector(ha,
2019                                             addr, sec_mask, man_id,
2020                                             flash_id)) {
2021                                                 rval = QLA_FUNCTION_FAILED;
2022                                                 break;
2023                                         }
2024                                         if (man_id == 0x01 && flash_id == 0x6d)
2025                                                 sec_number++;
2026                                 }
2027                         }
2028
2029                         if (man_id == 0x01 && flash_id == 0x6d) {
2030                                 if (sec_number == 1 &&
2031                                     addr == (rest_addr - 1)) {
2032                                         rest_addr = 0x0fff;
2033                                         sec_mask   = 0x1f000;
2034                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2035                                         rest_addr = 0x3fff;
2036                                         sec_mask   = 0x1c000;
2037                                 }
2038                         }
2039
2040                         if (qla2x00_program_flash_address(ha, addr, data,
2041                             man_id, flash_id)) {
2042                                 rval = QLA_FUNCTION_FAILED;
2043                                 break;
2044                         }
2045                         cond_resched();
2046                 }
2047         } while (0);
2048         qla2x00_flash_disable(ha);
2049
2050         /* Resume HBA. */
2051         qla2x00_resume_hba(ha);
2052
2053         return rval;
2054 }
2055
2056 uint8_t *
2057 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2058     uint32_t offset, uint32_t length)
2059 {
2060         /* Suspend HBA. */
2061         scsi_block_requests(ha->host);
2062         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2063
2064         /* Go with read. */
2065         qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
2066
2067         /* Resume HBA. */
2068         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2069         scsi_unblock_requests(ha->host);
2070
2071         return buf;
2072 }
2073
2074 int
2075 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2076     uint32_t offset, uint32_t length)
2077 {
2078         int rval;
2079
2080         /* Suspend HBA. */
2081         scsi_block_requests(ha->host);
2082         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2083
2084         /* Go with write. */
2085         rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
2086             length >> 2);
2087
2088         /* Resume HBA -- RISC reset needed. */
2089         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2090         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
2091         qla2xxx_wake_dpc(ha);
2092         qla2x00_wait_for_hba_online(ha);
2093         scsi_unblock_requests(ha->host);
2094
2095         return rval;
2096 }
2097
2098 uint8_t *
2099 qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2100     uint32_t offset, uint32_t length)
2101 {
2102         int rval;
2103         dma_addr_t optrom_dma;
2104         void *optrom;
2105         uint8_t *pbuf;
2106         uint32_t faddr, left, burst;
2107
2108         if (offset & 0xfff)
2109                 goto slow_read;
2110         if (length < OPTROM_BURST_SIZE)
2111                 goto slow_read;
2112
2113         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2114             &optrom_dma, GFP_KERNEL);
2115         if (!optrom) {
2116                 qla_printk(KERN_DEBUG, ha,
2117                     "Unable to allocate memory for optrom burst read "
2118                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2119
2120                 goto slow_read;
2121         }
2122
2123         pbuf = buf;
2124         faddr = offset >> 2;
2125         left = length >> 2;
2126         burst = OPTROM_BURST_DWORDS;
2127         while (left != 0) {
2128                 if (burst > left)
2129                         burst = left;
2130
2131                 rval = qla2x00_dump_ram(ha, optrom_dma,
2132                     flash_data_to_access_addr(faddr), burst);
2133                 if (rval) {
2134                         qla_printk(KERN_WARNING, ha,
2135                             "Unable to burst-read optrom segment "
2136                             "(%x/%x/%llx).\n", rval,
2137                             flash_data_to_access_addr(faddr),
2138                             (unsigned long long)optrom_dma);
2139                         qla_printk(KERN_WARNING, ha,
2140                             "Reverting to slow-read.\n");
2141
2142                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2143                             optrom, optrom_dma);
2144                         goto slow_read;
2145                 }
2146
2147                 memcpy(pbuf, optrom, burst * 4);
2148
2149                 left -= burst;
2150                 faddr += burst;
2151                 pbuf += burst * 4;
2152         }
2153
2154         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2155             optrom_dma);
2156
2157         return buf;
2158
2159 slow_read:
2160     return qla24xx_read_optrom_data(ha, buf, offset, length);
2161 }
2162
2163 /**
2164  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2165  * @ha: HA context
2166  * @pcids: Pointer to the FCODE PCI data structure
2167  *
2168  * The process of retrieving the FCODE version information is at best
2169  * described as interesting.
2170  *
2171  * Within the first 100h bytes of the image an ASCII string is present
2172  * which contains several pieces of information including the FCODE
2173  * version.  Unfortunately it seems the only reliable way to retrieve
2174  * the version is by scanning for another sentinel within the string,
2175  * the FCODE build date:
2176  *
2177  *      ... 2.00.02 10/17/02 ...
2178  *
2179  * Returns QLA_SUCCESS on successful retrieval of version.
2180  */
2181 static void
2182 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
2183 {
2184         int ret = QLA_FUNCTION_FAILED;
2185         uint32_t istart, iend, iter, vend;
2186         uint8_t do_next, rbyte, *vbyte;
2187
2188         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2189
2190         /* Skip the PCI data structure. */
2191         istart = pcids +
2192             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2193                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2194         iend = istart + 0x100;
2195         do {
2196                 /* Scan for the sentinel date string...eeewww. */
2197                 do_next = 0;
2198                 iter = istart;
2199                 while ((iter < iend) && !do_next) {
2200                         iter++;
2201                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2202                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2203                                     '/')
2204                                         do_next++;
2205                                 else if (qla2x00_read_flash_byte(ha,
2206                                     iter + 3) == '/')
2207                                         do_next++;
2208                         }
2209                 }
2210                 if (!do_next)
2211                         break;
2212
2213                 /* Backtrack to previous ' ' (space). */
2214                 do_next = 0;
2215                 while ((iter > istart) && !do_next) {
2216                         iter--;
2217                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2218                                 do_next++;
2219                 }
2220                 if (!do_next)
2221                         break;
2222
2223                 /*
2224                  * Mark end of version tag, and find previous ' ' (space) or
2225                  * string length (recent FCODE images -- major hack ahead!!!).
2226                  */
2227                 vend = iter - 1;
2228                 do_next = 0;
2229                 while ((iter > istart) && !do_next) {
2230                         iter--;
2231                         rbyte = qla2x00_read_flash_byte(ha, iter);
2232                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2233                                 do_next++;
2234                 }
2235                 if (!do_next)
2236                         break;
2237
2238                 /* Mark beginning of version tag, and copy data. */
2239                 iter++;
2240                 if ((vend - iter) &&
2241                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2242                         vbyte = ha->fcode_revision;
2243                         while (iter <= vend) {
2244                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2245                                 iter++;
2246                         }
2247                         ret = QLA_SUCCESS;
2248                 }
2249         } while (0);
2250
2251         if (ret != QLA_SUCCESS)
2252                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2253 }
2254
2255 int
2256 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2257 {
2258         int ret = QLA_SUCCESS;
2259         uint8_t code_type, last_image;
2260         uint32_t pcihdr, pcids;
2261         uint8_t *dbyte;
2262         uint16_t *dcode;
2263
2264         if (!ha->pio_address || !mbuf)
2265                 return QLA_FUNCTION_FAILED;
2266
2267         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2268         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2269         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2270         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2271
2272         qla2x00_flash_enable(ha);
2273
2274         /* Begin with first PCI expansion ROM header. */
2275         pcihdr = 0;
2276         last_image = 1;
2277         do {
2278                 /* Verify PCI expansion ROM header. */
2279                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2280                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2281                         /* No signature */
2282                         DEBUG2(printk("scsi(%ld): No matching ROM "
2283                             "signature.\n", ha->host_no));
2284                         ret = QLA_FUNCTION_FAILED;
2285                         break;
2286                 }
2287
2288                 /* Locate PCI data structure. */
2289                 pcids = pcihdr +
2290                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2291                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2292
2293                 /* Validate signature of PCI data structure. */
2294                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2295                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2296                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2297                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2298                         /* Incorrect header. */
2299                         DEBUG2(printk("%s(): PCI data struct not found "
2300                             "pcir_adr=%x.\n", __func__, pcids));
2301                         ret = QLA_FUNCTION_FAILED;
2302                         break;
2303                 }
2304
2305                 /* Read version */
2306                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2307                 switch (code_type) {
2308                 case ROM_CODE_TYPE_BIOS:
2309                         /* Intel x86, PC-AT compatible. */
2310                         ha->bios_revision[0] =
2311                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2312                         ha->bios_revision[1] =
2313                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2314                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2315                             ha->bios_revision[1], ha->bios_revision[0]));
2316                         break;
2317                 case ROM_CODE_TYPE_FCODE:
2318                         /* Open Firmware standard for PCI (FCode). */
2319                         /* Eeeewww... */
2320                         qla2x00_get_fcode_version(ha, pcids);
2321                         break;
2322                 case ROM_CODE_TYPE_EFI:
2323                         /* Extensible Firmware Interface (EFI). */
2324                         ha->efi_revision[0] =
2325                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2326                         ha->efi_revision[1] =
2327                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2328                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2329                             ha->efi_revision[1], ha->efi_revision[0]));
2330                         break;
2331                 default:
2332                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2333                             "pcids %x.\n", __func__, code_type, pcids));
2334                         break;
2335                 }
2336
2337                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2338
2339                 /* Locate next PCI expansion ROM. */
2340                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2341                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2342         } while (!last_image);
2343
2344         if (IS_QLA2322(ha)) {
2345                 /* Read firmware image information. */
2346                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2347                 dbyte = mbuf;
2348                 memset(dbyte, 0, 8);
2349                 dcode = (uint16_t *)dbyte;
2350
2351                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2352                     8);
2353                 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2354                     __func__, ha->host_no));
2355                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2356
2357                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2358                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2359                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2360                     dcode[3] == 0)) {
2361                         DEBUG2(printk("%s(): Unrecognized fw revision at "
2362                             "%x.\n", __func__, ha->flt_region_fw * 4));
2363                 } else {
2364                         /* values are in big endian */
2365                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2366                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2367                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2368                 }
2369         }
2370
2371         qla2x00_flash_disable(ha);
2372
2373         return ret;
2374 }
2375
2376 int
2377 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2378 {
2379         int ret = QLA_SUCCESS;
2380         uint32_t pcihdr, pcids;
2381         uint32_t *dcode;
2382         uint8_t *bcode;
2383         uint8_t code_type, last_image;
2384         int i;
2385
2386         if (!mbuf)
2387                 return QLA_FUNCTION_FAILED;
2388
2389         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2390         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2391         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2392         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2393
2394         dcode = mbuf;
2395
2396         /* Begin with first PCI expansion ROM header. */
2397         pcihdr = ha->flt_region_boot;
2398         last_image = 1;
2399         do {
2400                 /* Verify PCI expansion ROM header. */
2401                 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
2402                 bcode = mbuf + (pcihdr % 4);
2403                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2404                         /* No signature */
2405                         DEBUG2(printk("scsi(%ld): No matching ROM "
2406                             "signature.\n", ha->host_no));
2407                         ret = QLA_FUNCTION_FAILED;
2408                         break;
2409                 }
2410
2411                 /* Locate PCI data structure. */
2412                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2413
2414                 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2415                 bcode = mbuf + (pcihdr % 4);
2416
2417                 /* Validate signature of PCI data structure. */
2418                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2419                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2420                         /* Incorrect header. */
2421                         DEBUG2(printk("%s(): PCI data struct not found "
2422                             "pcir_adr=%x.\n", __func__, pcids));
2423                         ret = QLA_FUNCTION_FAILED;
2424                         break;
2425                 }
2426
2427                 /* Read version */
2428                 code_type = bcode[0x14];
2429                 switch (code_type) {
2430                 case ROM_CODE_TYPE_BIOS:
2431                         /* Intel x86, PC-AT compatible. */
2432                         ha->bios_revision[0] = bcode[0x12];
2433                         ha->bios_revision[1] = bcode[0x13];
2434                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2435                             ha->bios_revision[1], ha->bios_revision[0]));
2436                         break;
2437                 case ROM_CODE_TYPE_FCODE:
2438                         /* Open Firmware standard for PCI (FCode). */
2439                         ha->fcode_revision[0] = bcode[0x12];
2440                         ha->fcode_revision[1] = bcode[0x13];
2441                         DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2442                             ha->fcode_revision[1], ha->fcode_revision[0]));
2443                         break;
2444                 case ROM_CODE_TYPE_EFI:
2445                         /* Extensible Firmware Interface (EFI). */
2446                         ha->efi_revision[0] = bcode[0x12];
2447                         ha->efi_revision[1] = bcode[0x13];
2448                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2449                             ha->efi_revision[1], ha->efi_revision[0]));
2450                         break;
2451                 default:
2452                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2453                             "pcids %x.\n", __func__, code_type, pcids));
2454                         break;
2455                 }
2456
2457                 last_image = bcode[0x15] & BIT_7;
2458
2459                 /* Locate next PCI expansion ROM. */
2460                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2461         } while (!last_image);
2462
2463         /* Read firmware image information. */
2464         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2465         dcode = mbuf;
2466
2467         qla24xx_read_flash_data(ha, dcode, ha->flt_region_fw + 4, 4);
2468         for (i = 0; i < 4; i++)
2469                 dcode[i] = be32_to_cpu(dcode[i]);
2470
2471         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2472             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2473             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2474             dcode[3] == 0)) {
2475                 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2476                     __func__, ha->flt_region_fw));
2477         } else {
2478                 ha->fw_revision[0] = dcode[0];
2479                 ha->fw_revision[1] = dcode[1];
2480                 ha->fw_revision[2] = dcode[2];
2481                 ha->fw_revision[3] = dcode[3];
2482         }
2483
2484         return ret;
2485 }
2486
2487 static int
2488 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2489 {
2490         if (pos >= end || *pos != 0x82)
2491                 return 0;
2492
2493         pos += 3 + pos[1];
2494         if (pos >= end || *pos != 0x90)
2495                 return 0;
2496
2497         pos += 3 + pos[1];
2498         if (pos >= end || *pos != 0x78)
2499                 return 0;
2500
2501         return 1;
2502 }
2503
2504 int
2505 qla2xxx_get_vpd_field(scsi_qla_host_t *ha, char *key, char *str, size_t size)
2506 {
2507         uint8_t *pos = ha->vpd;
2508         uint8_t *end = pos + ha->vpd_size;
2509         int len = 0;
2510
2511         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2512                 return 0;
2513
2514         while (pos < end && *pos != 0x78) {
2515                 len = (*pos == 0x82) ? pos[1] : pos[2];
2516
2517                 if (!strncmp(pos, key, strlen(key)))
2518                         break;
2519
2520                 if (*pos != 0x90 && *pos != 0x91)
2521                         pos += len;
2522
2523                 pos += 3;
2524         }
2525
2526         if (pos < end - len && *pos != 0x78)
2527                 return snprintf(str, size, "%.*s", len, pos + 3);
2528
2529         return 0;
2530 }
2531
2532 static int
2533 qla2xxx_hw_event_store(scsi_qla_host_t *ha, uint32_t *fdata)
2534 {
2535         uint32_t d[2], faddr;
2536
2537         /* Locate first empty entry. */
2538         for (;;) {
2539                 if (ha->hw_event_ptr >=
2540                     ha->flt_region_hw_event + FA_HW_EVENT_SIZE) {
2541                         DEBUG2(qla_printk(KERN_WARNING, ha,
2542                             "HW event -- Log Full!\n"));
2543                         return QLA_MEMORY_ALLOC_FAILED;
2544                 }
2545
2546                 qla24xx_read_flash_data(ha, d, ha->hw_event_ptr, 2);
2547                 faddr = flash_data_to_access_addr(ha->hw_event_ptr);
2548                 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2549                 if (d[0] == __constant_cpu_to_le32(0xffffffff) &&
2550                     d[1] == __constant_cpu_to_le32(0xffffffff)) {
2551                         qla24xx_unprotect_flash(ha);
2552
2553                         qla24xx_write_flash_dword(ha, faddr++,
2554                             cpu_to_le32(jiffies));
2555                         qla24xx_write_flash_dword(ha, faddr++, 0);
2556                         qla24xx_write_flash_dword(ha, faddr++, *fdata++);
2557                         qla24xx_write_flash_dword(ha, faddr++, *fdata);
2558
2559                         qla24xx_protect_flash(ha);
2560                         break;
2561                 }
2562         }
2563         return QLA_SUCCESS;
2564 }
2565
2566 int
2567 qla2xxx_hw_event_log(scsi_qla_host_t *ha, uint16_t code, uint16_t d1,
2568     uint16_t d2, uint16_t d3)
2569 {
2570 #define QMARK(a, b, c, d) \
2571     cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
2572
2573         int rval;
2574         uint32_t marker[2], fdata[4];
2575
2576         if (ha->flt_region_hw_event == 0)
2577                 return QLA_FUNCTION_FAILED;
2578
2579         DEBUG2(qla_printk(KERN_WARNING, ha,
2580             "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3));
2581
2582         /* If marker not already found, locate or write.  */
2583         if (!ha->flags.hw_event_marker_found) {
2584                 /* Create marker. */
2585                 marker[0] = QMARK('L', ha->fw_major_version,
2586                     ha->fw_minor_version, ha->fw_subminor_version);
2587                 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER,
2588                     QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER);
2589
2590                 /* Locate marker. */
2591                 ha->hw_event_ptr = ha->flt_region_hw_event;
2592                 for (;;) {
2593                         qla24xx_read_flash_data(ha, fdata, ha->hw_event_ptr,
2594                             4);
2595                         if (fdata[0] == __constant_cpu_to_le32(0xffffffff) &&
2596                             fdata[1] == __constant_cpu_to_le32(0xffffffff))
2597                                 break;
2598                         ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2599                         if (ha->hw_event_ptr >=
2600                             ha->flt_region_hw_event + FA_HW_EVENT_SIZE) {
2601                                 DEBUG2(qla_printk(KERN_WARNING, ha,
2602                                     "HW event -- Log Full!\n"));
2603                                 return QLA_MEMORY_ALLOC_FAILED;
2604                         }
2605                         if (fdata[2] == marker[0] && fdata[3] == marker[1]) {
2606                                 ha->flags.hw_event_marker_found = 1;
2607                                 break;
2608                         }
2609                 }
2610                 /* No marker, write it. */
2611                 if (!ha->flags.hw_event_marker_found) {
2612                         rval = qla2xxx_hw_event_store(ha, marker);
2613                         if (rval != QLA_SUCCESS) {
2614                                 DEBUG2(qla_printk(KERN_WARNING, ha,
2615                                     "HW event -- Failed marker write=%x.!\n",
2616                                     rval));
2617                                 return rval;
2618                         }
2619                         ha->flags.hw_event_marker_found = 1;
2620                 }
2621         }
2622
2623         /* Store error.  */
2624         fdata[0] = cpu_to_le32(code << 16 | d1);
2625         fdata[1] = cpu_to_le32(d2 << 16 | d3);
2626         rval = qla2xxx_hw_event_store(ha, fdata);
2627         if (rval != QLA_SUCCESS) {
2628                 DEBUG2(qla_printk(KERN_WARNING, ha,
2629                     "HW event -- Failed error write=%x.!\n",
2630                     rval));
2631         }
2632
2633         return rval;
2634 }