[SCSI] qla2xxx: Update copyright banner.
[linux-2.6.git] / drivers / scsi / qla2xxx / qla_sup.c
1 /******************************************************************************
2  *                  QLOGIC LINUX SOFTWARE
3  *
4  * QLogic ISP2x00 device driver for Linux 2.6.x
5  * Copyright (C) 2003-2005 QLogic Corporation
6  * (www.qlogic.com)
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License as published by the
10  * Free Software Foundation; either version 2, or (at your option) any
11  * later version.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  ******************************************************************************/
19
20 #include "qla_def.h"
21
22 #include <linux/delay.h>
23 #include <asm/uaccess.h>
24
25 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
26 static void qla2x00_nv_deselect(scsi_qla_host_t *);
27 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
28
29 /*
30  * NVRAM support routines
31  */
32
33 /**
34  * qla2x00_lock_nvram_access() -
35  * @ha: HA context
36  */
37 void
38 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
39 {
40         uint16_t data;
41         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
42
43         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
44                 data = RD_REG_WORD(&reg->nvram);
45                 while (data & NVR_BUSY) {
46                         udelay(100);
47                         data = RD_REG_WORD(&reg->nvram);
48                 }
49
50                 /* Lock resource */
51                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
52                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
53                 udelay(5);
54                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
55                 while ((data & BIT_0) == 0) {
56                         /* Lock failed */
57                         udelay(100);
58                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
59                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
60                         udelay(5);
61                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62                 }
63         }
64 }
65
66 /**
67  * qla2x00_unlock_nvram_access() -
68  * @ha: HA context
69  */
70 void
71 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
72 {
73         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
76                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
77                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
78         }
79 }
80
81 /**
82  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
83  *      request routine to get the word from NVRAM.
84  * @ha: HA context
85  * @addr: Address in NVRAM to read
86  *
87  * Returns the word read from nvram @addr.
88  */
89 uint16_t
90 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
91 {
92         uint16_t        data;
93         uint32_t        nv_cmd;
94
95         nv_cmd = addr << 16;
96         nv_cmd |= NV_READ_OP;
97         data = qla2x00_nvram_request(ha, nv_cmd);
98
99         return (data);
100 }
101
102 /**
103  * qla2x00_write_nvram_word() - Write NVRAM data.
104  * @ha: HA context
105  * @addr: Address in NVRAM to write
106  * @data: word to program
107  */
108 void
109 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
110 {
111         int count;
112         uint16_t word;
113         uint32_t nv_cmd;
114         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
115
116         qla2x00_nv_write(ha, NVR_DATA_OUT);
117         qla2x00_nv_write(ha, 0);
118         qla2x00_nv_write(ha, 0);
119
120         for (word = 0; word < 8; word++)
121                 qla2x00_nv_write(ha, NVR_DATA_OUT);
122
123         qla2x00_nv_deselect(ha);
124
125         /* Write data */
126         nv_cmd = (addr << 16) | NV_WRITE_OP;
127         nv_cmd |= data;
128         nv_cmd <<= 5;
129         for (count = 0; count < 27; count++) {
130                 if (nv_cmd & BIT_31)
131                         qla2x00_nv_write(ha, NVR_DATA_OUT);
132                 else
133                         qla2x00_nv_write(ha, 0);
134
135                 nv_cmd <<= 1;
136         }
137
138         qla2x00_nv_deselect(ha);
139
140         /* Wait for NVRAM to become ready */
141         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
142         do {
143                 NVRAM_DELAY();
144                 word = RD_REG_WORD(&reg->nvram);
145         } while ((word & NVR_DATA_IN) == 0);
146
147         qla2x00_nv_deselect(ha);
148
149         /* Disable writes */
150         qla2x00_nv_write(ha, NVR_DATA_OUT);
151         for (count = 0; count < 10; count++)
152                 qla2x00_nv_write(ha, 0);
153
154         qla2x00_nv_deselect(ha);
155 }
156
157 static int
158 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
159     uint32_t tmo)
160 {
161         int ret, count;
162         uint16_t word;
163         uint32_t nv_cmd;
164         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
165
166         ret = QLA_SUCCESS;
167
168         qla2x00_nv_write(ha, NVR_DATA_OUT);
169         qla2x00_nv_write(ha, 0);
170         qla2x00_nv_write(ha, 0);
171
172         for (word = 0; word < 8; word++)
173                 qla2x00_nv_write(ha, NVR_DATA_OUT);
174
175         qla2x00_nv_deselect(ha);
176
177         /* Write data */
178         nv_cmd = (addr << 16) | NV_WRITE_OP;
179         nv_cmd |= data;
180         nv_cmd <<= 5;
181         for (count = 0; count < 27; count++) {
182                 if (nv_cmd & BIT_31)
183                         qla2x00_nv_write(ha, NVR_DATA_OUT);
184                 else
185                         qla2x00_nv_write(ha, 0);
186
187                 nv_cmd <<= 1;
188         }
189
190         qla2x00_nv_deselect(ha);
191
192         /* Wait for NVRAM to become ready */
193         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
194         do {
195                 NVRAM_DELAY();
196                 word = RD_REG_WORD(&reg->nvram);
197                 if (!--tmo) {
198                         ret = QLA_FUNCTION_FAILED;
199                         break;
200                 }
201         } while ((word & NVR_DATA_IN) == 0);
202
203         qla2x00_nv_deselect(ha);
204
205         /* Disable writes */
206         qla2x00_nv_write(ha, NVR_DATA_OUT);
207         for (count = 0; count < 10; count++)
208                 qla2x00_nv_write(ha, 0);
209
210         qla2x00_nv_deselect(ha);
211
212         return ret;
213 }
214
215 /**
216  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
217  *      NVRAM.
218  * @ha: HA context
219  * @nv_cmd: NVRAM command
220  *
221  * Bit definitions for NVRAM command:
222  *
223  *      Bit 26     = start bit
224  *      Bit 25, 24 = opcode
225  *      Bit 23-16  = address
226  *      Bit 15-0   = write data
227  *
228  * Returns the word read from nvram @addr.
229  */
230 static uint16_t
231 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
232 {
233         uint8_t         cnt;
234         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
235         uint16_t        data = 0;
236         uint16_t        reg_data;
237
238         /* Send command to NVRAM. */
239         nv_cmd <<= 5;
240         for (cnt = 0; cnt < 11; cnt++) {
241                 if (nv_cmd & BIT_31)
242                         qla2x00_nv_write(ha, NVR_DATA_OUT);
243                 else
244                         qla2x00_nv_write(ha, 0);
245                 nv_cmd <<= 1;
246         }
247
248         /* Read data from NVRAM. */
249         for (cnt = 0; cnt < 16; cnt++) {
250                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
251                 NVRAM_DELAY();
252                 data <<= 1;
253                 reg_data = RD_REG_WORD(&reg->nvram);
254                 if (reg_data & NVR_DATA_IN)
255                         data |= BIT_0;
256                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
257                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
258                 NVRAM_DELAY();
259         }
260
261         /* Deselect chip. */
262         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
263         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
264         NVRAM_DELAY();
265
266         return (data);
267 }
268
269 /**
270  * qla2x00_nv_write() - Clean NVRAM operations.
271  * @ha: HA context
272  */
273 static void
274 qla2x00_nv_deselect(scsi_qla_host_t *ha)
275 {
276         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
277
278         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
279         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
280         NVRAM_DELAY();
281 }
282
283 /**
284  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
285  * @ha: HA context
286  * @data: Serial interface selector
287  */
288 static void
289 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
290 {
291         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
292
293         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
294         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
295         NVRAM_DELAY();
296         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
297             NVR_WRT_ENABLE);
298         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
299         NVRAM_DELAY();
300         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
301         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
302         NVRAM_DELAY();
303 }
304
305 /**
306  * qla2x00_clear_nvram_protection() -
307  * @ha: HA context
308  */
309 static int
310 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
311 {
312         int ret, stat;
313         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
314         uint32_t word;
315         uint16_t wprot, wprot_old;
316
317         /* Clear NVRAM write protection. */
318         ret = QLA_FUNCTION_FAILED;
319         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
320         stat = qla2x00_write_nvram_word_tmo(ha, 0,
321             __constant_cpu_to_le16(0x1234), 100000);
322         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
323         if (stat != QLA_SUCCESS || wprot != __constant_cpu_to_le16(0x1234)) {
324                 /* Write enable. */
325                 qla2x00_nv_write(ha, NVR_DATA_OUT);
326                 qla2x00_nv_write(ha, 0);
327                 qla2x00_nv_write(ha, 0);
328                 for (word = 0; word < 8; word++)
329                         qla2x00_nv_write(ha, NVR_DATA_OUT);
330
331                 qla2x00_nv_deselect(ha);
332
333                 /* Enable protection register. */
334                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
335                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
336                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
337                 for (word = 0; word < 8; word++)
338                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
339
340                 qla2x00_nv_deselect(ha);
341
342                 /* Clear protection register (ffff is cleared). */
343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
345                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
346                 for (word = 0; word < 8; word++)
347                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
348
349                 qla2x00_nv_deselect(ha);
350
351                 /* Wait for NVRAM to become ready. */
352                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
353                 do {
354                         NVRAM_DELAY();
355                         word = RD_REG_WORD(&reg->nvram);
356                 } while ((word & NVR_DATA_IN) == 0);
357
358                 ret = QLA_SUCCESS;
359         } else
360                 qla2x00_write_nvram_word(ha, 0, wprot_old);
361
362         return ret;
363 }
364
365 static void
366 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
367 {
368         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
369         uint32_t word;
370
371         if (stat != QLA_SUCCESS)
372                 return;
373
374         /* Set NVRAM write protection. */
375         /* Write enable. */
376         qla2x00_nv_write(ha, NVR_DATA_OUT);
377         qla2x00_nv_write(ha, 0);
378         qla2x00_nv_write(ha, 0);
379         for (word = 0; word < 8; word++)
380                 qla2x00_nv_write(ha, NVR_DATA_OUT);
381
382         qla2x00_nv_deselect(ha);
383
384         /* Enable protection register. */
385         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
386         qla2x00_nv_write(ha, NVR_PR_ENABLE);
387         qla2x00_nv_write(ha, NVR_PR_ENABLE);
388         for (word = 0; word < 8; word++)
389                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
390
391         qla2x00_nv_deselect(ha);
392
393         /* Enable protection register. */
394         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
395         qla2x00_nv_write(ha, NVR_PR_ENABLE);
396         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
397         for (word = 0; word < 8; word++)
398                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399
400         qla2x00_nv_deselect(ha);
401
402         /* Wait for NVRAM to become ready. */
403         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
404         do {
405                 NVRAM_DELAY();
406                 word = RD_REG_WORD(&reg->nvram);
407         } while ((word & NVR_DATA_IN) == 0);
408 }
409
410
411 /*****************************************************************************/
412 /* Flash Manipulation Routines                                               */
413 /*****************************************************************************/
414
415 static inline uint32_t
416 flash_conf_to_access_addr(uint32_t faddr)
417 {
418         return FARX_ACCESS_FLASH_CONF | faddr;
419 }
420
421 static inline uint32_t
422 flash_data_to_access_addr(uint32_t faddr)
423 {
424         return FARX_ACCESS_FLASH_DATA | faddr;
425 }
426
427 static inline uint32_t
428 nvram_conf_to_access_addr(uint32_t naddr)
429 {
430         return FARX_ACCESS_NVRAM_CONF | naddr;
431 }
432
433 static inline uint32_t
434 nvram_data_to_access_addr(uint32_t naddr)
435 {
436         return FARX_ACCESS_NVRAM_DATA | naddr;
437 }
438
439 uint32_t
440 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
441 {
442         int rval;
443         uint32_t cnt, data;
444         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
445
446         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
447         /* Wait for READ cycle to complete. */
448         rval = QLA_SUCCESS;
449         for (cnt = 3000;
450             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
451             rval == QLA_SUCCESS; cnt--) {
452                 if (cnt)
453                         udelay(10);
454                 else
455                         rval = QLA_FUNCTION_TIMEOUT;
456         }
457
458         /* TODO: What happens if we time out? */
459         data = 0xDEADDEAD;
460         if (rval == QLA_SUCCESS)
461                 data = RD_REG_DWORD(&reg->flash_data);
462
463         return data;
464 }
465
466 uint32_t *
467 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
468     uint32_t dwords)
469 {
470         uint32_t i;
471         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
472
473         /* Pause RISC. */
474         WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
475         RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
476
477         /* Dword reads to flash. */
478         for (i = 0; i < dwords; i++, faddr++)
479                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
480                     flash_data_to_access_addr(faddr)));
481
482         /* Release RISC pause. */
483         WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
484         RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
485
486         return dwptr;
487 }
488
489 int
490 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
491 {
492         int rval;
493         uint32_t cnt;
494         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
495
496         WRT_REG_DWORD(&reg->flash_data, data);
497         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
498         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
499         /* Wait for Write cycle to complete. */
500         rval = QLA_SUCCESS;
501         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
502             rval == QLA_SUCCESS; cnt--) {
503                 if (cnt)
504                         udelay(10);
505                 else
506                         rval = QLA_FUNCTION_TIMEOUT;
507         }
508         return rval;
509 }
510
511 void
512 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
513     uint8_t *flash_id)
514 {
515         uint32_t ids;
516
517         ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
518         *man_id = LSB(ids);
519         *flash_id = MSB(ids);
520 }
521
522 int
523 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
524     uint32_t dwords)
525 {
526         int ret;
527         uint32_t liter;
528         uint32_t sec_mask, rest_addr, conf_addr;
529         uint32_t fdata;
530         uint8_t man_id, flash_id;
531         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
532
533         ret = QLA_SUCCESS;
534
535         /* Pause RISC. */
536         WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
537         RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
538
539         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
540         DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
541             ha->host_no, man_id, flash_id));
542
543         conf_addr = flash_conf_to_access_addr(0x03d8);
544         switch (man_id) {
545         case 0xbf: /* STT flash. */
546                 rest_addr = 0x1fff;
547                 sec_mask = 0x3e000;
548                 if (flash_id == 0x80)
549                         conf_addr = flash_conf_to_access_addr(0x0352);
550                 break;
551         case 0x13: /* ST M25P80. */
552                 rest_addr = 0x3fff;
553                 sec_mask = 0x3c000;
554                 break;
555         default:
556                 /* Default to 64 kb sector size. */
557                 rest_addr = 0x3fff;
558                 sec_mask = 0x3c000;
559                 break;
560         }
561
562         /* Enable flash write. */
563         WRT_REG_DWORD(&reg->ctrl_status,
564             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
565         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
566
567         /* Disable flash write-protection. */
568         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
569
570         do {    /* Loop once to provide quick error exit. */
571                 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
572                         /* Are we at the beginning of a sector? */
573                         if ((faddr & rest_addr) == 0) {
574                                 fdata = (faddr & sec_mask) << 2;
575                                 ret = qla24xx_write_flash_dword(ha, conf_addr,
576                                     (fdata & 0xff00) |((fdata << 16) &
577                                     0xff0000) | ((fdata >> 16) & 0xff));
578                                 if (ret != QLA_SUCCESS) {
579                                         DEBUG9(printk("%s(%ld) Unable to flash "
580                                             "sector: address=%x.\n", __func__,
581                                             ha->host_no, faddr));
582                                         break;
583                                 }
584                         }
585                         ret = qla24xx_write_flash_dword(ha,
586                             flash_data_to_access_addr(faddr),
587                             cpu_to_le32(*dwptr));
588                         if (ret != QLA_SUCCESS) {
589                                 DEBUG9(printk("%s(%ld) Unable to program flash "
590                                     "address=%x data=%x.\n", __func__,
591                                     ha->host_no, faddr, *dwptr));
592                                 break;
593                         }
594                 }
595         } while (0);
596
597         /* Disable flash write. */
598         WRT_REG_DWORD(&reg->ctrl_status,
599             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
600         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
601
602         /* Release RISC pause. */
603         WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
604         RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
605
606         return ret;
607 }
608
609 uint8_t *
610 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
611     uint32_t bytes)
612 {
613         uint32_t i;
614         uint16_t *wptr;
615
616         /* Word reads to NVRAM via registers. */
617         wptr = (uint16_t *)buf;
618         qla2x00_lock_nvram_access(ha);
619         for (i = 0; i < bytes >> 1; i++, naddr++)
620                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
621                     naddr));
622         qla2x00_unlock_nvram_access(ha);
623
624         return buf;
625 }
626
627 uint8_t *
628 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
629     uint32_t bytes)
630 {
631         uint32_t i;
632         uint32_t *dwptr;
633         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
634
635         /* Pause RISC. */
636         WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
637         RD_REG_DWORD(&reg->hccr);       /* PCI Posting. */
638
639         /* Dword reads to flash. */
640         dwptr = (uint32_t *)buf;
641         for (i = 0; i < bytes >> 2; i++, naddr++)
642                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
643                     nvram_data_to_access_addr(naddr)));
644
645         /* Release RISC pause. */
646         WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
647         RD_REG_DWORD(&reg->hccr);       /* PCI Posting. */
648
649         return buf;
650 }
651
652 int
653 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
654     uint32_t bytes)
655 {
656         int ret, stat;
657         uint32_t i;
658         uint16_t *wptr;
659
660         ret = QLA_SUCCESS;
661
662         qla2x00_lock_nvram_access(ha);
663
664         /* Disable NVRAM write-protection. */
665         stat = qla2x00_clear_nvram_protection(ha);
666
667         wptr = (uint16_t *)buf;
668         for (i = 0; i < bytes >> 1; i++, naddr++) {
669                 qla2x00_write_nvram_word(ha, naddr,
670                     cpu_to_le16(*wptr));
671                 wptr++;
672         }
673
674         /* Enable NVRAM write-protection. */
675         qla2x00_set_nvram_protection(ha, stat);
676
677         qla2x00_unlock_nvram_access(ha);
678
679         return ret;
680 }
681
682 int
683 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
684     uint32_t bytes)
685 {
686         int ret;
687         uint32_t i;
688         uint32_t *dwptr;
689         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
690
691         ret = QLA_SUCCESS;
692
693         /* Pause RISC. */
694         WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
695         RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
696
697         /* Enable flash write. */
698         WRT_REG_DWORD(&reg->ctrl_status,
699             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
700         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
701
702         /* Disable NVRAM write-protection. */
703         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
704             0);
705         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
706             0);
707
708         /* Dword writes to flash. */
709         dwptr = (uint32_t *)buf;
710         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
711                 ret = qla24xx_write_flash_dword(ha,
712                     nvram_data_to_access_addr(naddr),
713                     cpu_to_le32(*dwptr));
714                 if (ret != QLA_SUCCESS) {
715                         DEBUG9(printk("%s(%ld) Unable to program "
716                             "nvram address=%x data=%x.\n", __func__,
717                             ha->host_no, naddr, *dwptr));
718                         break;
719                 }
720         }
721
722         /* Enable NVRAM write-protection. */
723         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
724             0x8c);
725
726         /* Disable flash write. */
727         WRT_REG_DWORD(&reg->ctrl_status,
728             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
729         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
730
731         /* Release RISC pause. */
732         WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
733         RD_REG_DWORD(&reg->hccr);               /* PCI Posting. */
734
735         return ret;
736 }