[SCSI] qla2xxx: Add ISP81XX support.
[linux-2.6.git] / drivers / scsi / qla2xxx / qla_sup.c
1 /*
2  * QLogic Fibre Channel HBA Driver
3  * Copyright (c)  2003-2008 QLogic Corporation
4  *
5  * See LICENSE.qla2xxx for copyright and licensing details.
6  */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
12
13 /*
14  * NVRAM support routines
15  */
16
17 /**
18  * qla2x00_lock_nvram_access() -
19  * @ha: HA context
20  */
21 static void
22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
23 {
24         uint16_t data;
25         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
26
27         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28                 data = RD_REG_WORD(&reg->nvram);
29                 while (data & NVR_BUSY) {
30                         udelay(100);
31                         data = RD_REG_WORD(&reg->nvram);
32                 }
33
34                 /* Lock resource */
35                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37                 udelay(5);
38                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39                 while ((data & BIT_0) == 0) {
40                         /* Lock failed */
41                         udelay(100);
42                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44                         udelay(5);
45                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46                 }
47         }
48 }
49
50 /**
51  * qla2x00_unlock_nvram_access() -
52  * @ha: HA context
53  */
54 static void
55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
56 {
57         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
58
59         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62         }
63 }
64
65 /**
66  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67  * @ha: HA context
68  * @data: Serial interface selector
69  */
70 static void
71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72 {
73         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
77         NVRAM_DELAY();
78         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79             NVR_WRT_ENABLE);
80         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
81         NVRAM_DELAY();
82         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
84         NVRAM_DELAY();
85 }
86
87 /**
88  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89  *      NVRAM.
90  * @ha: HA context
91  * @nv_cmd: NVRAM command
92  *
93  * Bit definitions for NVRAM command:
94  *
95  *      Bit 26     = start bit
96  *      Bit 25, 24 = opcode
97  *      Bit 23-16  = address
98  *      Bit 15-0   = write data
99  *
100  * Returns the word read from nvram @addr.
101  */
102 static uint16_t
103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104 {
105         uint8_t         cnt;
106         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107         uint16_t        data = 0;
108         uint16_t        reg_data;
109
110         /* Send command to NVRAM. */
111         nv_cmd <<= 5;
112         for (cnt = 0; cnt < 11; cnt++) {
113                 if (nv_cmd & BIT_31)
114                         qla2x00_nv_write(ha, NVR_DATA_OUT);
115                 else
116                         qla2x00_nv_write(ha, 0);
117                 nv_cmd <<= 1;
118         }
119
120         /* Read data from NVRAM. */
121         for (cnt = 0; cnt < 16; cnt++) {
122                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
124                 NVRAM_DELAY();
125                 data <<= 1;
126                 reg_data = RD_REG_WORD(&reg->nvram);
127                 if (reg_data & NVR_DATA_IN)
128                         data |= BIT_0;
129                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
131                 NVRAM_DELAY();
132         }
133
134         /* Deselect chip. */
135         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
137         NVRAM_DELAY();
138
139         return data;
140 }
141
142
143 /**
144  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145  *      request routine to get the word from NVRAM.
146  * @ha: HA context
147  * @addr: Address in NVRAM to read
148  *
149  * Returns the word read from nvram @addr.
150  */
151 static uint16_t
152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
153 {
154         uint16_t        data;
155         uint32_t        nv_cmd;
156
157         nv_cmd = addr << 16;
158         nv_cmd |= NV_READ_OP;
159         data = qla2x00_nvram_request(ha, nv_cmd);
160
161         return (data);
162 }
163
164 /**
165  * qla2x00_nv_deselect() - Deselect NVRAM operations.
166  * @ha: HA context
167  */
168 static void
169 qla2x00_nv_deselect(struct qla_hw_data *ha)
170 {
171         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
175         NVRAM_DELAY();
176 }
177
178 /**
179  * qla2x00_write_nvram_word() - Write NVRAM data.
180  * @ha: HA context
181  * @addr: Address in NVRAM to write
182  * @data: word to program
183  */
184 static void
185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
186 {
187         int count;
188         uint16_t word;
189         uint32_t nv_cmd, wait_cnt;
190         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
191
192         qla2x00_nv_write(ha, NVR_DATA_OUT);
193         qla2x00_nv_write(ha, 0);
194         qla2x00_nv_write(ha, 0);
195
196         for (word = 0; word < 8; word++)
197                 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199         qla2x00_nv_deselect(ha);
200
201         /* Write data */
202         nv_cmd = (addr << 16) | NV_WRITE_OP;
203         nv_cmd |= data;
204         nv_cmd <<= 5;
205         for (count = 0; count < 27; count++) {
206                 if (nv_cmd & BIT_31)
207                         qla2x00_nv_write(ha, NVR_DATA_OUT);
208                 else
209                         qla2x00_nv_write(ha, 0);
210
211                 nv_cmd <<= 1;
212         }
213
214         qla2x00_nv_deselect(ha);
215
216         /* Wait for NVRAM to become ready */
217         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
218         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
219         wait_cnt = NVR_WAIT_CNT;
220         do {
221                 if (!--wait_cnt) {
222                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
223                             __func__, vha->host_no));
224                         break;
225                 }
226                 NVRAM_DELAY();
227                 word = RD_REG_WORD(&reg->nvram);
228         } while ((word & NVR_DATA_IN) == 0);
229
230         qla2x00_nv_deselect(ha);
231
232         /* Disable writes */
233         qla2x00_nv_write(ha, NVR_DATA_OUT);
234         for (count = 0; count < 10; count++)
235                 qla2x00_nv_write(ha, 0);
236
237         qla2x00_nv_deselect(ha);
238 }
239
240 static int
241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242         uint16_t data, uint32_t tmo)
243 {
244         int ret, count;
245         uint16_t word;
246         uint32_t nv_cmd;
247         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249         ret = QLA_SUCCESS;
250
251         qla2x00_nv_write(ha, NVR_DATA_OUT);
252         qla2x00_nv_write(ha, 0);
253         qla2x00_nv_write(ha, 0);
254
255         for (word = 0; word < 8; word++)
256                 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258         qla2x00_nv_deselect(ha);
259
260         /* Write data */
261         nv_cmd = (addr << 16) | NV_WRITE_OP;
262         nv_cmd |= data;
263         nv_cmd <<= 5;
264         for (count = 0; count < 27; count++) {
265                 if (nv_cmd & BIT_31)
266                         qla2x00_nv_write(ha, NVR_DATA_OUT);
267                 else
268                         qla2x00_nv_write(ha, 0);
269
270                 nv_cmd <<= 1;
271         }
272
273         qla2x00_nv_deselect(ha);
274
275         /* Wait for NVRAM to become ready */
276         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
277         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
278         do {
279                 NVRAM_DELAY();
280                 word = RD_REG_WORD(&reg->nvram);
281                 if (!--tmo) {
282                         ret = QLA_FUNCTION_FAILED;
283                         break;
284                 }
285         } while ((word & NVR_DATA_IN) == 0);
286
287         qla2x00_nv_deselect(ha);
288
289         /* Disable writes */
290         qla2x00_nv_write(ha, NVR_DATA_OUT);
291         for (count = 0; count < 10; count++)
292                 qla2x00_nv_write(ha, 0);
293
294         qla2x00_nv_deselect(ha);
295
296         return ret;
297 }
298
299 /**
300  * qla2x00_clear_nvram_protection() -
301  * @ha: HA context
302  */
303 static int
304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
305 {
306         int ret, stat;
307         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
308         uint32_t word, wait_cnt;
309         uint16_t wprot, wprot_old;
310
311         /* Clear NVRAM write protection. */
312         ret = QLA_FUNCTION_FAILED;
313
314         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
316             __constant_cpu_to_le16(0x1234), 100000);
317         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318         if (stat != QLA_SUCCESS || wprot != 0x1234) {
319                 /* Write enable. */
320                 qla2x00_nv_write(ha, NVR_DATA_OUT);
321                 qla2x00_nv_write(ha, 0);
322                 qla2x00_nv_write(ha, 0);
323                 for (word = 0; word < 8; word++)
324                         qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326                 qla2x00_nv_deselect(ha);
327
328                 /* Enable protection register. */
329                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332                 for (word = 0; word < 8; word++)
333                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335                 qla2x00_nv_deselect(ha);
336
337                 /* Clear protection register (ffff is cleared). */
338                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341                 for (word = 0; word < 8; word++)
342                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344                 qla2x00_nv_deselect(ha);
345
346                 /* Wait for NVRAM to become ready. */
347                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
348                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
349                 wait_cnt = NVR_WAIT_CNT;
350                 do {
351                         if (!--wait_cnt) {
352                                 DEBUG9_10(qla_printk(
353                                     "NVRAM didn't go ready...\n"));
354                                 break;
355                         }
356                         NVRAM_DELAY();
357                         word = RD_REG_WORD(&reg->nvram);
358                 } while ((word & NVR_DATA_IN) == 0);
359
360                 if (wait_cnt)
361                         ret = QLA_SUCCESS;
362         } else
363                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
364
365         return ret;
366 }
367
368 static void
369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
370 {
371         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
372         uint32_t word, wait_cnt;
373
374         if (stat != QLA_SUCCESS)
375                 return;
376
377         /* Set NVRAM write protection. */
378         /* Write enable. */
379         qla2x00_nv_write(ha, NVR_DATA_OUT);
380         qla2x00_nv_write(ha, 0);
381         qla2x00_nv_write(ha, 0);
382         for (word = 0; word < 8; word++)
383                 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385         qla2x00_nv_deselect(ha);
386
387         /* Enable protection register. */
388         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389         qla2x00_nv_write(ha, NVR_PR_ENABLE);
390         qla2x00_nv_write(ha, NVR_PR_ENABLE);
391         for (word = 0; word < 8; word++)
392                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394         qla2x00_nv_deselect(ha);
395
396         /* Enable protection register. */
397         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398         qla2x00_nv_write(ha, NVR_PR_ENABLE);
399         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400         for (word = 0; word < 8; word++)
401                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403         qla2x00_nv_deselect(ha);
404
405         /* Wait for NVRAM to become ready. */
406         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
407         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
408         wait_cnt = NVR_WAIT_CNT;
409         do {
410                 if (!--wait_cnt) {
411                         DEBUG9_10(qla_printk("NVRAM didn't go ready...\n"));
412                         break;
413                 }
414                 NVRAM_DELAY();
415                 word = RD_REG_WORD(&reg->nvram);
416         } while ((word & NVR_DATA_IN) == 0);
417 }
418
419
420 /*****************************************************************************/
421 /* Flash Manipulation Routines                                               */
422 /*****************************************************************************/
423
424 #define OPTROM_BURST_SIZE       0x1000
425 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
426
427 static inline uint32_t
428 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
429 {
430         return ha->flash_conf_off | faddr;
431 }
432
433 static inline uint32_t
434 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
435 {
436         return ha->flash_data_off | faddr;
437 }
438
439 static inline uint32_t
440 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
441 {
442         return ha->nvram_conf_off | naddr;
443 }
444
445 static inline uint32_t
446 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
447 {
448         return ha->nvram_data_off | naddr;
449 }
450
451 static uint32_t
452 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
453 {
454         int rval;
455         uint32_t cnt, data;
456         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
457
458         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
459         /* Wait for READ cycle to complete. */
460         rval = QLA_SUCCESS;
461         for (cnt = 3000;
462             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
463             rval == QLA_SUCCESS; cnt--) {
464                 if (cnt)
465                         udelay(10);
466                 else
467                         rval = QLA_FUNCTION_TIMEOUT;
468                 cond_resched();
469         }
470
471         /* TODO: What happens if we time out? */
472         data = 0xDEADDEAD;
473         if (rval == QLA_SUCCESS)
474                 data = RD_REG_DWORD(&reg->flash_data);
475
476         return data;
477 }
478
479 uint32_t *
480 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
481     uint32_t dwords)
482 {
483         uint32_t i;
484         struct qla_hw_data *ha = vha->hw;
485
486         /* Dword reads to flash. */
487         for (i = 0; i < dwords; i++, faddr++)
488                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
489                     flash_data_addr(ha, faddr)));
490
491         return dwptr;
492 }
493
494 static int
495 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
496 {
497         int rval;
498         uint32_t cnt;
499         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
500
501         WRT_REG_DWORD(&reg->flash_data, data);
502         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
503         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
504         /* Wait for Write cycle to complete. */
505         rval = QLA_SUCCESS;
506         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
507             rval == QLA_SUCCESS; cnt--) {
508                 if (cnt)
509                         udelay(10);
510                 else
511                         rval = QLA_FUNCTION_TIMEOUT;
512                 cond_resched();
513         }
514         return rval;
515 }
516
517 static void
518 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
519     uint8_t *flash_id)
520 {
521         uint32_t ids;
522
523         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
524         *man_id = LSB(ids);
525         *flash_id = MSB(ids);
526
527         /* Check if man_id and flash_id are valid. */
528         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
529                 /* Read information using 0x9f opcode
530                  * Device ID, Mfg ID would be read in the format:
531                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
532                  * Example: ATMEL 0x00 01 45 1F
533                  * Extract MFG and Dev ID from last two bytes.
534                  */
535                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
536                 *man_id = LSB(ids);
537                 *flash_id = MSB(ids);
538         }
539 }
540
541 static int
542 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
543 {
544         const char *loc, *locations[] = { "DEF", "PCI" };
545         uint32_t pcihdr, pcids;
546         uint32_t *dcode;
547         uint8_t *buf, *bcode, last_image;
548         uint16_t cnt, chksum, *wptr;
549         struct qla_flt_location *fltl;
550         struct qla_hw_data *ha = vha->hw;
551         struct req_que *req = ha->req_q_map[0];
552
553         /*
554          * FLT-location structure resides after the last PCI region.
555          */
556
557         /* Begin with sane defaults. */
558         loc = locations[0];
559         *start = 0;
560         if (IS_QLA24XX_TYPE(ha))
561                 *start = FA_FLASH_LAYOUT_ADDR_24;
562         else if (IS_QLA25XX(ha))
563                 *start = FA_FLASH_LAYOUT_ADDR;
564         else if (IS_QLA81XX(ha))
565                 *start = FA_FLASH_LAYOUT_ADDR_81;
566         /* Begin with first PCI expansion ROM header. */
567         buf = (uint8_t *)req->ring;
568         dcode = (uint32_t *)req->ring;
569         pcihdr = 0;
570         last_image = 1;
571         do {
572                 /* Verify PCI expansion ROM header. */
573                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
574                 bcode = buf + (pcihdr % 4);
575                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
576                         goto end;
577
578                 /* Locate PCI data structure. */
579                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
580                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
581                 bcode = buf + (pcihdr % 4);
582
583                 /* Validate signature of PCI data structure. */
584                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
585                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
586                         goto end;
587
588                 last_image = bcode[0x15] & BIT_7;
589
590                 /* Locate next PCI expansion ROM. */
591                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
592         } while (!last_image);
593
594         /* Now verify FLT-location structure. */
595         fltl = (struct qla_flt_location *)req->ring;
596         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
597             sizeof(struct qla_flt_location) >> 2);
598         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
599             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
600                 goto end;
601
602         wptr = (uint16_t *)req->ring;
603         cnt = sizeof(struct qla_flt_location) >> 1;
604         for (chksum = 0; cnt; cnt--)
605                 chksum += le16_to_cpu(*wptr++);
606         if (chksum) {
607                 qla_printk(KERN_ERR, ha,
608                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
609                 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
610                 return QLA_FUNCTION_FAILED;
611         }
612
613         /* Good data.  Use specified location. */
614         loc = locations[1];
615         *start = le16_to_cpu(fltl->start_hi) << 16 |
616             le16_to_cpu(fltl->start_lo);
617 end:
618         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
619         return QLA_SUCCESS;
620 }
621
622 static void
623 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
624 {
625         const char *loc, *locations[] = { "DEF", "FLT" };
626         const uint32_t def_fw[] =
627                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
628         const uint32_t def_boot[] =
629                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
630         const uint32_t def_vpd_nvram[] =
631                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
632         const uint32_t def_fdt[] =
633                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
634                         FA_FLASH_DESCR_ADDR_81 };
635         const uint32_t def_npiv_conf0[] =
636                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
637                         FA_NPIV_CONF0_ADDR_81 };
638         const uint32_t def_npiv_conf1[] =
639                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
640                         FA_NPIV_CONF1_ADDR_81 };
641         uint32_t def;
642         uint16_t *wptr;
643         uint16_t cnt, chksum;
644         uint32_t start;
645         struct qla_flt_header *flt;
646         struct qla_flt_region *region;
647         struct qla_hw_data *ha = vha->hw;
648         struct req_que *req = ha->req_q_map[0];
649
650         ha->flt_region_flt = flt_addr;
651         wptr = (uint16_t *)req->ring;
652         flt = (struct qla_flt_header *)req->ring;
653         region = (struct qla_flt_region *)&flt[1];
654         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
655             flt_addr << 2, OPTROM_BURST_SIZE);
656         if (*wptr == __constant_cpu_to_le16(0xffff))
657                 goto no_flash_data;
658         if (flt->version != __constant_cpu_to_le16(1)) {
659                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
660                     "version=0x%x length=0x%x checksum=0x%x.\n",
661                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
662                     le16_to_cpu(flt->checksum)));
663                 goto no_flash_data;
664         }
665
666         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
667         for (chksum = 0; cnt; cnt--)
668                 chksum += le16_to_cpu(*wptr++);
669         if (chksum) {
670                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
671                     "version=0x%x length=0x%x checksum=0x%x.\n",
672                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
673                     chksum));
674                 goto no_flash_data;
675         }
676
677         loc = locations[1];
678         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
679         for ( ; cnt; cnt--, region++) {
680                 /* Store addresses as DWORD offsets. */
681                 start = le32_to_cpu(region->start) >> 2;
682
683                 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
684                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
685                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
686
687                 switch (le32_to_cpu(region->code)) {
688                 case FLT_REG_FW:
689                         ha->flt_region_fw = start;
690                         break;
691                 case FLT_REG_BOOT_CODE:
692                         ha->flt_region_boot = start;
693                         break;
694                 case FLT_REG_VPD_0:
695                         ha->flt_region_vpd_nvram = start;
696                         break;
697                 case FLT_REG_FDT:
698                         ha->flt_region_fdt = start;
699                         break;
700                 case FLT_REG_NPIV_CONF_0:
701                         if (!(PCI_FUNC(ha->pdev->devfn) & 1))
702                                 ha->flt_region_npiv_conf = start;
703                         break;
704                 case FLT_REG_NPIV_CONF_1:
705                         if (PCI_FUNC(ha->pdev->devfn) & 1)
706                                 ha->flt_region_npiv_conf = start;
707                         break;
708                 }
709         }
710         goto done;
711
712 no_flash_data:
713         /* Use hardcoded defaults. */
714         loc = locations[0];
715         def = 0;
716         if (IS_QLA24XX_TYPE(ha))
717                 def = 0;
718         else if (IS_QLA25XX(ha))
719                 def = 1;
720         else if (IS_QLA81XX(ha))
721                 def = 2;
722         ha->flt_region_fw = def_fw[def];
723         ha->flt_region_boot = def_boot[def];
724         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
725         ha->flt_region_fdt = def_fdt[def];
726         ha->flt_region_npiv_conf = !(PCI_FUNC(ha->pdev->devfn) & 1) ?
727             def_npiv_conf0[def]: def_npiv_conf1[def];
728 done:
729         DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
730             "vpd_nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x.\n", loc,
731             ha->flt_region_boot, ha->flt_region_fw, ha->flt_region_vpd_nvram,
732             ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
733 }
734
735 static void
736 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
737 {
738 #define FLASH_BLK_SIZE_4K       0x1000
739 #define FLASH_BLK_SIZE_32K      0x8000
740 #define FLASH_BLK_SIZE_64K      0x10000
741         const char *loc, *locations[] = { "MID", "FDT" };
742         uint16_t cnt, chksum;
743         uint16_t *wptr;
744         struct qla_fdt_layout *fdt;
745         uint8_t man_id, flash_id;
746         uint16_t mid, fid;
747         struct qla_hw_data *ha = vha->hw;
748         struct req_que *req = ha->req_q_map[0];
749
750         wptr = (uint16_t *)req->ring;
751         fdt = (struct qla_fdt_layout *)req->ring;
752         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
753             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
754         if (*wptr == __constant_cpu_to_le16(0xffff))
755                 goto no_flash_data;
756         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
757             fdt->sig[3] != 'D')
758                 goto no_flash_data;
759
760         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
761             cnt++)
762                 chksum += le16_to_cpu(*wptr++);
763         if (chksum) {
764                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
765                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
766                     le16_to_cpu(fdt->version)));
767                 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
768                 goto no_flash_data;
769         }
770
771         loc = locations[1];
772         mid = le16_to_cpu(fdt->man_id);
773         fid = le16_to_cpu(fdt->id);
774         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
775         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
776         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
777         if (fdt->unprotect_sec_cmd) {
778                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
779                     fdt->unprotect_sec_cmd);
780                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
781                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
782                     flash_conf_addr(ha, 0x0336);
783         }
784         goto done;
785 no_flash_data:
786         loc = locations[0];
787         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
788         mid = man_id;
789         fid = flash_id;
790         ha->fdt_wrt_disable = 0x9c;
791         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
792         switch (man_id) {
793         case 0xbf: /* STT flash. */
794                 if (flash_id == 0x8e)
795                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
796                 else
797                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
798
799                 if (flash_id == 0x80)
800                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
801                 break;
802         case 0x13: /* ST M25P80. */
803                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
804                 break;
805         case 0x1f: /* Atmel 26DF081A. */
806                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
807                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
808                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
809                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
810                 break;
811         default:
812                 /* Default to 64 kb sector size. */
813                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
814                 break;
815         }
816 done:
817         DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
818             "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
819             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
820             ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
821             ha->fdt_block_size));
822 }
823
824 int
825 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
826 {
827         int ret;
828         uint32_t flt_addr;
829         struct qla_hw_data *ha = vha->hw;
830
831         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
832                 return QLA_SUCCESS;
833
834         ret = qla2xxx_find_flt_start(vha, &flt_addr);
835         if (ret != QLA_SUCCESS)
836                 return ret;
837
838         qla2xxx_get_flt_info(vha, flt_addr);
839         qla2xxx_get_fdt_info(vha);
840
841         return QLA_SUCCESS;
842 }
843
844 void
845 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
846 {
847 #define NPIV_CONFIG_SIZE        (16*1024)
848         void *data;
849         uint16_t *wptr;
850         uint16_t cnt, chksum;
851         int i;
852         struct qla_npiv_header hdr;
853         struct qla_npiv_entry *entry;
854         struct qla_hw_data *ha = vha->hw;
855
856         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
857                 return;
858
859         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
860             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
861         if (hdr.version == __constant_cpu_to_le16(0xffff))
862                 return;
863         if (hdr.version != __constant_cpu_to_le16(1)) {
864                 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
865                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
866                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
867                     le16_to_cpu(hdr.checksum)));
868                 return;
869         }
870
871         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
872         if (!data) {
873                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
874                     "allocate memory.\n"));
875                 return;
876         }
877
878         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
879             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
880
881         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
882             sizeof(struct qla_npiv_entry)) >> 1;
883         for (wptr = data, chksum = 0; cnt; cnt--)
884                 chksum += le16_to_cpu(*wptr++);
885         if (chksum) {
886                 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
887                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
888                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
889                     chksum));
890                 goto done;
891         }
892
893         entry = data + sizeof(struct qla_npiv_header);
894         cnt = le16_to_cpu(hdr.entries);
895         for (i = 0; cnt; cnt--, entry++, i++) {
896                 uint16_t flags;
897                 struct fc_vport_identifiers vid;
898                 struct fc_vport *vport;
899
900                 flags = le16_to_cpu(entry->flags);
901                 if (flags == 0xffff)
902                         continue;
903                 if ((flags & BIT_0) == 0)
904                         continue;
905
906                 memset(&vid, 0, sizeof(vid));
907                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
908                 vid.vport_type = FC_PORTTYPE_NPIV;
909                 vid.disable = false;
910                 vid.port_name = wwn_to_u64(entry->port_name);
911                 vid.node_name = wwn_to_u64(entry->node_name);
912
913                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
914
915                 DEBUG2(qla_printk(KERN_DEBUG, ha, "NPIV[%02x]: wwpn=%llx "
916                         "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
917                         vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
918                         entry->q_qos, entry->f_qos));
919
920                 if (i < QLA_PRECONFIG_VPORTS) {
921                         vport = fc_vport_create(vha->host, 0, &vid);
922                         if (!vport)
923                                 qla_printk(KERN_INFO, ha,
924                                 "NPIV-Config: Failed to create vport [%02x]: "
925                                 "wwpn=%llx wwnn=%llx.\n", cnt,
926                                 vid.port_name, vid.node_name);
927                 }
928         }
929 done:
930         kfree(data);
931         ha->npiv_info = NULL;
932 }
933
934 static void
935 qla24xx_unprotect_flash(struct qla_hw_data *ha)
936 {
937         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
938
939         /* Enable flash write. */
940         WRT_REG_DWORD(&reg->ctrl_status,
941             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
942         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
943
944         if (!ha->fdt_wrt_disable)
945                 return;
946
947         /* Disable flash write-protection. */
948         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
949         /* Some flash parts need an additional zero-write to clear bits.*/
950         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
951 }
952
953 static void
954 qla24xx_protect_flash(struct qla_hw_data *ha)
955 {
956         uint32_t cnt;
957         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
958
959         if (!ha->fdt_wrt_disable)
960                 goto skip_wrt_protect;
961
962         /* Enable flash write-protection and wait for completion. */
963         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
964             ha->fdt_wrt_disable);
965         for (cnt = 300; cnt &&
966             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
967             cnt--) {
968                 udelay(10);
969         }
970
971 skip_wrt_protect:
972         /* Disable flash write. */
973         WRT_REG_DWORD(&reg->ctrl_status,
974             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
975         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
976 }
977
978 static int
979 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
980     uint32_t dwords)
981 {
982         int ret;
983         uint32_t liter, miter;
984         uint32_t sec_mask, rest_addr;
985         uint32_t fdata, findex;
986         dma_addr_t optrom_dma;
987         void *optrom = NULL;
988         uint32_t *s, *d;
989         struct qla_hw_data *ha = vha->hw;
990
991         ret = QLA_SUCCESS;
992
993         /* Prepare burst-capable write on supported ISPs. */
994         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
995             dwords > OPTROM_BURST_DWORDS) {
996                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
997                     &optrom_dma, GFP_KERNEL);
998                 if (!optrom) {
999                         qla_printk(KERN_DEBUG, ha,
1000                             "Unable to allocate memory for optrom burst write "
1001                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1002                 }
1003         }
1004
1005         rest_addr = (ha->fdt_block_size >> 2) - 1;
1006         sec_mask = (ha->optrom_size >> 2) - (ha->fdt_block_size >> 2);
1007
1008         qla24xx_unprotect_flash(ha);
1009
1010         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1011
1012                 findex = faddr;
1013                 fdata = (findex & sec_mask) << 2;
1014
1015                 /* Are we at the beginning of a sector? */
1016                 if ((findex & rest_addr) == 0) {
1017                         /* Do sector unprotect. */
1018                         if (ha->fdt_unprotect_sec_cmd)
1019                                 qla24xx_write_flash_dword(ha,
1020                                     ha->fdt_unprotect_sec_cmd,
1021                                     (fdata & 0xff00) | ((fdata << 16) &
1022                                     0xff0000) | ((fdata >> 16) & 0xff));
1023                         ret = qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1024                             (fdata & 0xff00) |((fdata << 16) &
1025                             0xff0000) | ((fdata >> 16) & 0xff));
1026                         if (ret != QLA_SUCCESS) {
1027                                 DEBUG9(qla_printk("Unable to flash sector: "
1028                                     "address=%x.\n", faddr));
1029                                 break;
1030                         }
1031                 }
1032
1033                 /* Go with burst-write. */
1034                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1035                         /* Copy data to DMA'ble buffer. */
1036                         for (miter = 0, s = optrom, d = dwptr;
1037                             miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
1038                                 *s = cpu_to_le32(*d);
1039
1040                         ret = qla2x00_load_ram(vha, optrom_dma,
1041                             flash_data_addr(ha, faddr),
1042                             OPTROM_BURST_DWORDS);
1043                         if (ret != QLA_SUCCESS) {
1044                                 qla_printk(KERN_WARNING, ha,
1045                                     "Unable to burst-write optrom segment "
1046                                     "(%x/%x/%llx).\n", ret,
1047                                     flash_data_addr(ha, faddr),
1048                                     (unsigned long long)optrom_dma);
1049                                 qla_printk(KERN_WARNING, ha,
1050                                     "Reverting to slow-write.\n");
1051
1052                                 dma_free_coherent(&ha->pdev->dev,
1053                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1054                                 optrom = NULL;
1055                         } else {
1056                                 liter += OPTROM_BURST_DWORDS - 1;
1057                                 faddr += OPTROM_BURST_DWORDS - 1;
1058                                 dwptr += OPTROM_BURST_DWORDS - 1;
1059                                 continue;
1060                         }
1061                 }
1062
1063                 ret = qla24xx_write_flash_dword(ha,
1064                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1065                 if (ret != QLA_SUCCESS) {
1066                         DEBUG9(printk("%s(%ld) Unable to program flash "
1067                             "address=%x data=%x.\n", __func__,
1068                             vha->host_no, faddr, *dwptr));
1069                         break;
1070                 }
1071
1072                 /* Do sector protect. */
1073                 if (ha->fdt_unprotect_sec_cmd &&
1074                     ((faddr & rest_addr) == rest_addr))
1075                         qla24xx_write_flash_dword(ha,
1076                             ha->fdt_protect_sec_cmd,
1077                             (fdata & 0xff00) | ((fdata << 16) &
1078                             0xff0000) | ((fdata >> 16) & 0xff));
1079         }
1080
1081         qla24xx_protect_flash(ha);
1082
1083         if (optrom)
1084                 dma_free_coherent(&ha->pdev->dev,
1085                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1086
1087         return ret;
1088 }
1089
1090 uint8_t *
1091 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1092     uint32_t bytes)
1093 {
1094         uint32_t i;
1095         uint16_t *wptr;
1096         struct qla_hw_data *ha = vha->hw;
1097
1098         /* Word reads to NVRAM via registers. */
1099         wptr = (uint16_t *)buf;
1100         qla2x00_lock_nvram_access(ha);
1101         for (i = 0; i < bytes >> 1; i++, naddr++)
1102                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1103                     naddr));
1104         qla2x00_unlock_nvram_access(ha);
1105
1106         return buf;
1107 }
1108
1109 uint8_t *
1110 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1111     uint32_t bytes)
1112 {
1113         uint32_t i;
1114         uint32_t *dwptr;
1115         struct qla_hw_data *ha = vha->hw;
1116
1117         /* Dword reads to flash. */
1118         dwptr = (uint32_t *)buf;
1119         for (i = 0; i < bytes >> 2; i++, naddr++)
1120                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1121                     nvram_data_addr(ha, naddr)));
1122
1123         return buf;
1124 }
1125
1126 int
1127 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1128     uint32_t bytes)
1129 {
1130         int ret, stat;
1131         uint32_t i;
1132         uint16_t *wptr;
1133         unsigned long flags;
1134         struct qla_hw_data *ha = vha->hw;
1135
1136         ret = QLA_SUCCESS;
1137
1138         spin_lock_irqsave(&ha->hardware_lock, flags);
1139         qla2x00_lock_nvram_access(ha);
1140
1141         /* Disable NVRAM write-protection. */
1142         stat = qla2x00_clear_nvram_protection(ha);
1143
1144         wptr = (uint16_t *)buf;
1145         for (i = 0; i < bytes >> 1; i++, naddr++) {
1146                 qla2x00_write_nvram_word(ha, naddr,
1147                     cpu_to_le16(*wptr));
1148                 wptr++;
1149         }
1150
1151         /* Enable NVRAM write-protection. */
1152         qla2x00_set_nvram_protection(ha, stat);
1153
1154         qla2x00_unlock_nvram_access(ha);
1155         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1156
1157         return ret;
1158 }
1159
1160 int
1161 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1162     uint32_t bytes)
1163 {
1164         int ret;
1165         uint32_t i;
1166         uint32_t *dwptr;
1167         struct qla_hw_data *ha = vha->hw;
1168         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1169
1170         ret = QLA_SUCCESS;
1171
1172         /* Enable flash write. */
1173         WRT_REG_DWORD(&reg->ctrl_status,
1174             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1175         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1176
1177         /* Disable NVRAM write-protection. */
1178         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1179         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1180
1181         /* Dword writes to flash. */
1182         dwptr = (uint32_t *)buf;
1183         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1184                 ret = qla24xx_write_flash_dword(ha,
1185                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1186                 if (ret != QLA_SUCCESS) {
1187                         DEBUG9(qla_printk("Unable to program nvram address=%x "
1188                             "data=%x.\n", naddr, *dwptr));
1189                         break;
1190                 }
1191         }
1192
1193         /* Enable NVRAM write-protection. */
1194         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1195
1196         /* Disable flash write. */
1197         WRT_REG_DWORD(&reg->ctrl_status,
1198             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1199         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1200
1201         return ret;
1202 }
1203
1204 uint8_t *
1205 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1206     uint32_t bytes)
1207 {
1208         uint32_t i;
1209         uint32_t *dwptr;
1210         struct qla_hw_data *ha = vha->hw;
1211
1212         /* Dword reads to flash. */
1213         dwptr = (uint32_t *)buf;
1214         for (i = 0; i < bytes >> 2; i++, naddr++)
1215                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1216                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1217
1218         return buf;
1219 }
1220
1221 int
1222 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1223     uint32_t bytes)
1224 {
1225         struct qla_hw_data *ha = vha->hw;
1226 #define RMW_BUFFER_SIZE (64 * 1024)
1227         uint8_t *dbuf;
1228
1229         dbuf = vmalloc(RMW_BUFFER_SIZE);
1230         if (!dbuf)
1231                 return QLA_MEMORY_ALLOC_FAILED;
1232         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1233             RMW_BUFFER_SIZE);
1234         memcpy(dbuf + (naddr << 2), buf, bytes);
1235         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1236             RMW_BUFFER_SIZE);
1237         vfree(dbuf);
1238
1239         return QLA_SUCCESS;
1240 }
1241
1242 static inline void
1243 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1244 {
1245         if (IS_QLA2322(ha)) {
1246                 /* Flip all colors. */
1247                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1248                         /* Turn off. */
1249                         ha->beacon_color_state = 0;
1250                         *pflags = GPIO_LED_ALL_OFF;
1251                 } else {
1252                         /* Turn on. */
1253                         ha->beacon_color_state = QLA_LED_ALL_ON;
1254                         *pflags = GPIO_LED_RGA_ON;
1255                 }
1256         } else {
1257                 /* Flip green led only. */
1258                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1259                         /* Turn off. */
1260                         ha->beacon_color_state = 0;
1261                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1262                 } else {
1263                         /* Turn on. */
1264                         ha->beacon_color_state = QLA_LED_GRN_ON;
1265                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1266                 }
1267         }
1268 }
1269
1270 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1271
1272 void
1273 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1274 {
1275         uint16_t gpio_enable;
1276         uint16_t gpio_data;
1277         uint16_t led_color = 0;
1278         unsigned long flags;
1279         struct qla_hw_data *ha = vha->hw;
1280         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1281
1282         spin_lock_irqsave(&ha->hardware_lock, flags);
1283
1284         /* Save the Original GPIOE. */
1285         if (ha->pio_address) {
1286                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1287                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1288         } else {
1289                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1290                 gpio_data = RD_REG_WORD(&reg->gpiod);
1291         }
1292
1293         /* Set the modified gpio_enable values */
1294         gpio_enable |= GPIO_LED_MASK;
1295
1296         if (ha->pio_address) {
1297                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1298         } else {
1299                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1300                 RD_REG_WORD(&reg->gpioe);
1301         }
1302
1303         qla2x00_flip_colors(ha, &led_color);
1304
1305         /* Clear out any previously set LED color. */
1306         gpio_data &= ~GPIO_LED_MASK;
1307
1308         /* Set the new input LED color to GPIOD. */
1309         gpio_data |= led_color;
1310
1311         /* Set the modified gpio_data values */
1312         if (ha->pio_address) {
1313                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1314         } else {
1315                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1316                 RD_REG_WORD(&reg->gpiod);
1317         }
1318
1319         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1320 }
1321
1322 int
1323 qla2x00_beacon_on(struct scsi_qla_host *vha)
1324 {
1325         uint16_t gpio_enable;
1326         uint16_t gpio_data;
1327         unsigned long flags;
1328         struct qla_hw_data *ha = vha->hw;
1329         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1330
1331         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1332         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1333
1334         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1335                 qla_printk(KERN_WARNING, ha,
1336                     "Unable to update fw options (beacon on).\n");
1337                 return QLA_FUNCTION_FAILED;
1338         }
1339
1340         /* Turn off LEDs. */
1341         spin_lock_irqsave(&ha->hardware_lock, flags);
1342         if (ha->pio_address) {
1343                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1344                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1345         } else {
1346                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1347                 gpio_data = RD_REG_WORD(&reg->gpiod);
1348         }
1349         gpio_enable |= GPIO_LED_MASK;
1350
1351         /* Set the modified gpio_enable values. */
1352         if (ha->pio_address) {
1353                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1354         } else {
1355                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1356                 RD_REG_WORD(&reg->gpioe);
1357         }
1358
1359         /* Clear out previously set LED colour. */
1360         gpio_data &= ~GPIO_LED_MASK;
1361         if (ha->pio_address) {
1362                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1363         } else {
1364                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1365                 RD_REG_WORD(&reg->gpiod);
1366         }
1367         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1368
1369         /*
1370          * Let the per HBA timer kick off the blinking process based on
1371          * the following flags. No need to do anything else now.
1372          */
1373         ha->beacon_blink_led = 1;
1374         ha->beacon_color_state = 0;
1375
1376         return QLA_SUCCESS;
1377 }
1378
1379 int
1380 qla2x00_beacon_off(struct scsi_qla_host *vha)
1381 {
1382         int rval = QLA_SUCCESS;
1383         struct qla_hw_data *ha = vha->hw;
1384
1385         ha->beacon_blink_led = 0;
1386
1387         /* Set the on flag so when it gets flipped it will be off. */
1388         if (IS_QLA2322(ha))
1389                 ha->beacon_color_state = QLA_LED_ALL_ON;
1390         else
1391                 ha->beacon_color_state = QLA_LED_GRN_ON;
1392
1393         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1394
1395         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1396         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1397
1398         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1399         if (rval != QLA_SUCCESS)
1400                 qla_printk(KERN_WARNING, ha,
1401                     "Unable to update fw options (beacon off).\n");
1402         return rval;
1403 }
1404
1405
1406 static inline void
1407 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1408 {
1409         /* Flip all colors. */
1410         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1411                 /* Turn off. */
1412                 ha->beacon_color_state = 0;
1413                 *pflags = 0;
1414         } else {
1415                 /* Turn on. */
1416                 ha->beacon_color_state = QLA_LED_ALL_ON;
1417                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1418         }
1419 }
1420
1421 void
1422 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1423 {
1424         uint16_t led_color = 0;
1425         uint32_t gpio_data;
1426         unsigned long flags;
1427         struct qla_hw_data *ha = vha->hw;
1428         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1429
1430         /* Save the Original GPIOD. */
1431         spin_lock_irqsave(&ha->hardware_lock, flags);
1432         gpio_data = RD_REG_DWORD(&reg->gpiod);
1433
1434         /* Enable the gpio_data reg for update. */
1435         gpio_data |= GPDX_LED_UPDATE_MASK;
1436
1437         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1438         gpio_data = RD_REG_DWORD(&reg->gpiod);
1439
1440         /* Set the color bits. */
1441         qla24xx_flip_colors(ha, &led_color);
1442
1443         /* Clear out any previously set LED color. */
1444         gpio_data &= ~GPDX_LED_COLOR_MASK;
1445
1446         /* Set the new input LED color to GPIOD. */
1447         gpio_data |= led_color;
1448
1449         /* Set the modified gpio_data values. */
1450         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1451         gpio_data = RD_REG_DWORD(&reg->gpiod);
1452         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1453 }
1454
1455 int
1456 qla24xx_beacon_on(struct scsi_qla_host *vha)
1457 {
1458         uint32_t gpio_data;
1459         unsigned long flags;
1460         struct qla_hw_data *ha = vha->hw;
1461         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1462
1463         if (ha->beacon_blink_led == 0) {
1464                 /* Enable firmware for update */
1465                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1466
1467                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1468                         return QLA_FUNCTION_FAILED;
1469
1470                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1471                     QLA_SUCCESS) {
1472                         qla_printk(KERN_WARNING, ha,
1473                             "Unable to update fw options (beacon on).\n");
1474                         return QLA_FUNCTION_FAILED;
1475                 }
1476
1477                 spin_lock_irqsave(&ha->hardware_lock, flags);
1478                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1479
1480                 /* Enable the gpio_data reg for update. */
1481                 gpio_data |= GPDX_LED_UPDATE_MASK;
1482                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1483                 RD_REG_DWORD(&reg->gpiod);
1484
1485                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1486         }
1487
1488         /* So all colors blink together. */
1489         ha->beacon_color_state = 0;
1490
1491         /* Let the per HBA timer kick off the blinking process. */
1492         ha->beacon_blink_led = 1;
1493
1494         return QLA_SUCCESS;
1495 }
1496
1497 int
1498 qla24xx_beacon_off(struct scsi_qla_host *vha)
1499 {
1500         uint32_t gpio_data;
1501         unsigned long flags;
1502         struct qla_hw_data *ha = vha->hw;
1503         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1504
1505         ha->beacon_blink_led = 0;
1506         ha->beacon_color_state = QLA_LED_ALL_ON;
1507
1508         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1509
1510         /* Give control back to firmware. */
1511         spin_lock_irqsave(&ha->hardware_lock, flags);
1512         gpio_data = RD_REG_DWORD(&reg->gpiod);
1513
1514         /* Disable the gpio_data reg for update. */
1515         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1516         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1517         RD_REG_DWORD(&reg->gpiod);
1518         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1519
1520         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1521
1522         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1523                 qla_printk(KERN_WARNING, ha,
1524                     "Unable to update fw options (beacon off).\n");
1525                 return QLA_FUNCTION_FAILED;
1526         }
1527
1528         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1529                 qla_printk(KERN_WARNING, ha,
1530                     "Unable to get fw options (beacon off).\n");
1531                 return QLA_FUNCTION_FAILED;
1532         }
1533
1534         return QLA_SUCCESS;
1535 }
1536
1537
1538 /*
1539  * Flash support routines
1540  */
1541
1542 /**
1543  * qla2x00_flash_enable() - Setup flash for reading and writing.
1544  * @ha: HA context
1545  */
1546 static void
1547 qla2x00_flash_enable(struct qla_hw_data *ha)
1548 {
1549         uint16_t data;
1550         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1551
1552         data = RD_REG_WORD(&reg->ctrl_status);
1553         data |= CSR_FLASH_ENABLE;
1554         WRT_REG_WORD(&reg->ctrl_status, data);
1555         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1556 }
1557
1558 /**
1559  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1560  * @ha: HA context
1561  */
1562 static void
1563 qla2x00_flash_disable(struct qla_hw_data *ha)
1564 {
1565         uint16_t data;
1566         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1567
1568         data = RD_REG_WORD(&reg->ctrl_status);
1569         data &= ~(CSR_FLASH_ENABLE);
1570         WRT_REG_WORD(&reg->ctrl_status, data);
1571         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1572 }
1573
1574 /**
1575  * qla2x00_read_flash_byte() - Reads a byte from flash
1576  * @ha: HA context
1577  * @addr: Address in flash to read
1578  *
1579  * A word is read from the chip, but, only the lower byte is valid.
1580  *
1581  * Returns the byte read from flash @addr.
1582  */
1583 static uint8_t
1584 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1585 {
1586         uint16_t data;
1587         uint16_t bank_select;
1588         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1589
1590         bank_select = RD_REG_WORD(&reg->ctrl_status);
1591
1592         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1593                 /* Specify 64K address range: */
1594                 /*  clear out Module Select and Flash Address bits [19:16]. */
1595                 bank_select &= ~0xf8;
1596                 bank_select |= addr >> 12 & 0xf0;
1597                 bank_select |= CSR_FLASH_64K_BANK;
1598                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1599                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1600
1601                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1602                 data = RD_REG_WORD(&reg->flash_data);
1603
1604                 return (uint8_t)data;
1605         }
1606
1607         /* Setup bit 16 of flash address. */
1608         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1609                 bank_select |= CSR_FLASH_64K_BANK;
1610                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1611                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1612         } else if (((addr & BIT_16) == 0) &&
1613             (bank_select & CSR_FLASH_64K_BANK)) {
1614                 bank_select &= ~(CSR_FLASH_64K_BANK);
1615                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1616                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1617         }
1618
1619         /* Always perform IO mapped accesses to the FLASH registers. */
1620         if (ha->pio_address) {
1621                 uint16_t data2;
1622
1623                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1624                 do {
1625                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1626                         barrier();
1627                         cpu_relax();
1628                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1629                 } while (data != data2);
1630         } else {
1631                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1632                 data = qla2x00_debounce_register(&reg->flash_data);
1633         }
1634
1635         return (uint8_t)data;
1636 }
1637
1638 /**
1639  * qla2x00_write_flash_byte() - Write a byte to flash
1640  * @ha: HA context
1641  * @addr: Address in flash to write
1642  * @data: Data to write
1643  */
1644 static void
1645 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1646 {
1647         uint16_t bank_select;
1648         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1649
1650         bank_select = RD_REG_WORD(&reg->ctrl_status);
1651         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1652                 /* Specify 64K address range: */
1653                 /*  clear out Module Select and Flash Address bits [19:16]. */
1654                 bank_select &= ~0xf8;
1655                 bank_select |= addr >> 12 & 0xf0;
1656                 bank_select |= CSR_FLASH_64K_BANK;
1657                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1658                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1659
1660                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1661                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1662                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1663                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1664
1665                 return;
1666         }
1667
1668         /* Setup bit 16 of flash address. */
1669         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1670                 bank_select |= CSR_FLASH_64K_BANK;
1671                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1672                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1673         } else if (((addr & BIT_16) == 0) &&
1674             (bank_select & CSR_FLASH_64K_BANK)) {
1675                 bank_select &= ~(CSR_FLASH_64K_BANK);
1676                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1677                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1678         }
1679
1680         /* Always perform IO mapped accesses to the FLASH registers. */
1681         if (ha->pio_address) {
1682                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1683                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1684         } else {
1685                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1686                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1687                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1688                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1689         }
1690 }
1691
1692 /**
1693  * qla2x00_poll_flash() - Polls flash for completion.
1694  * @ha: HA context
1695  * @addr: Address in flash to poll
1696  * @poll_data: Data to be polled
1697  * @man_id: Flash manufacturer ID
1698  * @flash_id: Flash ID
1699  *
1700  * This function polls the device until bit 7 of what is read matches data
1701  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1702  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1703  * reading bit 5 as a 1.
1704  *
1705  * Returns 0 on success, else non-zero.
1706  */
1707 static int
1708 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1709     uint8_t man_id, uint8_t flash_id)
1710 {
1711         int status;
1712         uint8_t flash_data;
1713         uint32_t cnt;
1714
1715         status = 1;
1716
1717         /* Wait for 30 seconds for command to finish. */
1718         poll_data &= BIT_7;
1719         for (cnt = 3000000; cnt; cnt--) {
1720                 flash_data = qla2x00_read_flash_byte(ha, addr);
1721                 if ((flash_data & BIT_7) == poll_data) {
1722                         status = 0;
1723                         break;
1724                 }
1725
1726                 if (man_id != 0x40 && man_id != 0xda) {
1727                         if ((flash_data & BIT_5) && cnt > 2)
1728                                 cnt = 2;
1729                 }
1730                 udelay(10);
1731                 barrier();
1732                 cond_resched();
1733         }
1734         return status;
1735 }
1736
1737 /**
1738  * qla2x00_program_flash_address() - Programs a flash address
1739  * @ha: HA context
1740  * @addr: Address in flash to program
1741  * @data: Data to be written in flash
1742  * @man_id: Flash manufacturer ID
1743  * @flash_id: Flash ID
1744  *
1745  * Returns 0 on success, else non-zero.
1746  */
1747 static int
1748 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1749     uint8_t data, uint8_t man_id, uint8_t flash_id)
1750 {
1751         /* Write Program Command Sequence. */
1752         if (IS_OEM_001(ha)) {
1753                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1754                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1755                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1756                 qla2x00_write_flash_byte(ha, addr, data);
1757         } else {
1758                 if (man_id == 0xda && flash_id == 0xc1) {
1759                         qla2x00_write_flash_byte(ha, addr, data);
1760                         if (addr & 0x7e)
1761                                 return 0;
1762                 } else {
1763                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1764                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1765                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1766                         qla2x00_write_flash_byte(ha, addr, data);
1767                 }
1768         }
1769
1770         udelay(150);
1771
1772         /* Wait for write to complete. */
1773         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1774 }
1775
1776 /**
1777  * qla2x00_erase_flash() - Erase the flash.
1778  * @ha: HA context
1779  * @man_id: Flash manufacturer ID
1780  * @flash_id: Flash ID
1781  *
1782  * Returns 0 on success, else non-zero.
1783  */
1784 static int
1785 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1786 {
1787         /* Individual Sector Erase Command Sequence */
1788         if (IS_OEM_001(ha)) {
1789                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1790                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1791                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1792                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1793                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1794                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1795         } else {
1796                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1797                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1798                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1799                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1800                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1801                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1802         }
1803
1804         udelay(150);
1805
1806         /* Wait for erase to complete. */
1807         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1808 }
1809
1810 /**
1811  * qla2x00_erase_flash_sector() - Erase a flash sector.
1812  * @ha: HA context
1813  * @addr: Flash sector to erase
1814  * @sec_mask: Sector address mask
1815  * @man_id: Flash manufacturer ID
1816  * @flash_id: Flash ID
1817  *
1818  * Returns 0 on success, else non-zero.
1819  */
1820 static int
1821 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1822     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1823 {
1824         /* Individual Sector Erase Command Sequence */
1825         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1826         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1827         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1828         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1829         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1830         if (man_id == 0x1f && flash_id == 0x13)
1831                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1832         else
1833                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1834
1835         udelay(150);
1836
1837         /* Wait for erase to complete. */
1838         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1839 }
1840
1841 /**
1842  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1843  * @man_id: Flash manufacturer ID
1844  * @flash_id: Flash ID
1845  */
1846 static void
1847 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1848     uint8_t *flash_id)
1849 {
1850         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1851         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1852         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1853         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1854         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1855         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1856         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1857         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1858 }
1859
1860 static void
1861 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1862         uint32_t saddr, uint32_t length)
1863 {
1864         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1865         uint32_t midpoint, ilength;
1866         uint8_t data;
1867
1868         midpoint = length / 2;
1869
1870         WRT_REG_WORD(&reg->nvram, 0);
1871         RD_REG_WORD(&reg->nvram);
1872         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1873                 if (ilength == midpoint) {
1874                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1875                         RD_REG_WORD(&reg->nvram);
1876                 }
1877                 data = qla2x00_read_flash_byte(ha, saddr);
1878                 if (saddr % 100)
1879                         udelay(10);
1880                 *tmp_buf = data;
1881                 cond_resched();
1882         }
1883 }
1884
1885 static inline void
1886 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1887 {
1888         int cnt;
1889         unsigned long flags;
1890         struct qla_hw_data *ha = vha->hw;
1891         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1892
1893         /* Suspend HBA. */
1894         scsi_block_requests(vha->host);
1895         ha->isp_ops->disable_intrs(ha);
1896         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1897
1898         /* Pause RISC. */
1899         spin_lock_irqsave(&ha->hardware_lock, flags);
1900         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1901         RD_REG_WORD(&reg->hccr);
1902         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1903                 for (cnt = 0; cnt < 30000; cnt++) {
1904                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1905                                 break;
1906                         udelay(100);
1907                 }
1908         } else {
1909                 udelay(10);
1910         }
1911         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1912 }
1913
1914 static inline void
1915 qla2x00_resume_hba(struct scsi_qla_host *vha)
1916 {
1917         struct qla_hw_data *ha = vha->hw;
1918
1919         /* Resume HBA. */
1920         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1921         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1922         qla2xxx_wake_dpc(vha);
1923         qla2x00_wait_for_hba_online(vha);
1924         scsi_unblock_requests(vha->host);
1925 }
1926
1927 uint8_t *
1928 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1929     uint32_t offset, uint32_t length)
1930 {
1931         uint32_t addr, midpoint;
1932         uint8_t *data;
1933         struct qla_hw_data *ha = vha->hw;
1934         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1935
1936         /* Suspend HBA. */
1937         qla2x00_suspend_hba(vha);
1938
1939         /* Go with read. */
1940         midpoint = ha->optrom_size / 2;
1941
1942         qla2x00_flash_enable(ha);
1943         WRT_REG_WORD(&reg->nvram, 0);
1944         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
1945         for (addr = offset, data = buf; addr < length; addr++, data++) {
1946                 if (addr == midpoint) {
1947                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1948                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
1949                 }
1950
1951                 *data = qla2x00_read_flash_byte(ha, addr);
1952         }
1953         qla2x00_flash_disable(ha);
1954
1955         /* Resume HBA. */
1956         qla2x00_resume_hba(vha);
1957
1958         return buf;
1959 }
1960
1961 int
1962 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1963     uint32_t offset, uint32_t length)
1964 {
1965
1966         int rval;
1967         uint8_t man_id, flash_id, sec_number, data;
1968         uint16_t wd;
1969         uint32_t addr, liter, sec_mask, rest_addr;
1970         struct qla_hw_data *ha = vha->hw;
1971         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1972
1973         /* Suspend HBA. */
1974         qla2x00_suspend_hba(vha);
1975
1976         rval = QLA_SUCCESS;
1977         sec_number = 0;
1978
1979         /* Reset ISP chip. */
1980         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1981         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1982
1983         /* Go with write. */
1984         qla2x00_flash_enable(ha);
1985         do {    /* Loop once to provide quick error exit */
1986                 /* Structure of flash memory based on manufacturer */
1987                 if (IS_OEM_001(ha)) {
1988                         /* OEM variant with special flash part. */
1989                         man_id = flash_id = 0;
1990                         rest_addr = 0xffff;
1991                         sec_mask   = 0x10000;
1992                         goto update_flash;
1993                 }
1994                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1995                 switch (man_id) {
1996                 case 0x20: /* ST flash. */
1997                         if (flash_id == 0xd2 || flash_id == 0xe3) {
1998                                 /*
1999                                  * ST m29w008at part - 64kb sector size with
2000                                  * 32kb,8kb,8kb,16kb sectors at memory address
2001                                  * 0xf0000.
2002                                  */
2003                                 rest_addr = 0xffff;
2004                                 sec_mask = 0x10000;
2005                                 break;   
2006                         }
2007                         /*
2008                          * ST m29w010b part - 16kb sector size
2009                          * Default to 16kb sectors
2010                          */
2011                         rest_addr = 0x3fff;
2012                         sec_mask = 0x1c000;
2013                         break;
2014                 case 0x40: /* Mostel flash. */
2015                         /* Mostel v29c51001 part - 512 byte sector size. */
2016                         rest_addr = 0x1ff;
2017                         sec_mask = 0x1fe00;
2018                         break;
2019                 case 0xbf: /* SST flash. */
2020                         /* SST39sf10 part - 4kb sector size. */
2021                         rest_addr = 0xfff;
2022                         sec_mask = 0x1f000;
2023                         break;
2024                 case 0xda: /* Winbond flash. */
2025                         /* Winbond W29EE011 part - 256 byte sector size. */
2026                         rest_addr = 0x7f;
2027                         sec_mask = 0x1ff80;
2028                         break;
2029                 case 0xc2: /* Macronix flash. */
2030                         /* 64k sector size. */
2031                         if (flash_id == 0x38 || flash_id == 0x4f) {
2032                                 rest_addr = 0xffff;
2033                                 sec_mask = 0x10000;
2034                                 break;
2035                         }
2036                         /* Fall through... */
2037
2038                 case 0x1f: /* Atmel flash. */
2039                         /* 512k sector size. */
2040                         if (flash_id == 0x13) {
2041                                 rest_addr = 0x7fffffff;
2042                                 sec_mask =   0x80000000;
2043                                 break;
2044                         }
2045                         /* Fall through... */
2046
2047                 case 0x01: /* AMD flash. */
2048                         if (flash_id == 0x38 || flash_id == 0x40 ||
2049                             flash_id == 0x4f) {
2050                                 /* Am29LV081 part - 64kb sector size. */
2051                                 /* Am29LV002BT part - 64kb sector size. */
2052                                 rest_addr = 0xffff;
2053                                 sec_mask = 0x10000;
2054                                 break;
2055                         } else if (flash_id == 0x3e) {
2056                                 /*
2057                                  * Am29LV008b part - 64kb sector size with
2058                                  * 32kb,8kb,8kb,16kb sector at memory address
2059                                  * h0xf0000.
2060                                  */
2061                                 rest_addr = 0xffff;
2062                                 sec_mask = 0x10000;
2063                                 break;
2064                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2065                                 /*
2066                                  * Am29LV010 part or AM29f010 - 16kb sector
2067                                  * size.
2068                                  */
2069                                 rest_addr = 0x3fff;
2070                                 sec_mask = 0x1c000;
2071                                 break;
2072                         } else if (flash_id == 0x6d) {
2073                                 /* Am29LV001 part - 8kb sector size. */
2074                                 rest_addr = 0x1fff;
2075                                 sec_mask = 0x1e000;
2076                                 break;
2077                         }
2078                 default:
2079                         /* Default to 16 kb sector size. */
2080                         rest_addr = 0x3fff;
2081                         sec_mask = 0x1c000;
2082                         break;
2083                 }
2084
2085 update_flash:
2086                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2087                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2088                                 rval = QLA_FUNCTION_FAILED;
2089                                 break;
2090                         }
2091                 }
2092
2093                 for (addr = offset, liter = 0; liter < length; liter++,
2094                     addr++) {
2095                         data = buf[liter];
2096                         /* Are we at the beginning of a sector? */
2097                         if ((addr & rest_addr) == 0) {
2098                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2099                                         if (addr >= 0x10000UL) {
2100                                                 if (((addr >> 12) & 0xf0) &&
2101                                                     ((man_id == 0x01 &&
2102                                                         flash_id == 0x3e) ||
2103                                                      (man_id == 0x20 &&
2104                                                          flash_id == 0xd2))) {
2105                                                         sec_number++;
2106                                                         if (sec_number == 1) {
2107                                                                 rest_addr =
2108                                                                     0x7fff;
2109                                                                 sec_mask =
2110                                                                     0x18000;
2111                                                         } else if (
2112                                                             sec_number == 2 ||
2113                                                             sec_number == 3) {
2114                                                                 rest_addr =
2115                                                                     0x1fff;
2116                                                                 sec_mask =
2117                                                                     0x1e000;
2118                                                         } else if (
2119                                                             sec_number == 4) {
2120                                                                 rest_addr =
2121                                                                     0x3fff;
2122                                                                 sec_mask =
2123                                                                     0x1c000;
2124                                                         }
2125                                                 }
2126                                         }
2127                                 } else if (addr == ha->optrom_size / 2) {
2128                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2129                                         RD_REG_WORD(&reg->nvram);
2130                                 }
2131
2132                                 if (flash_id == 0xda && man_id == 0xc1) {
2133                                         qla2x00_write_flash_byte(ha, 0x5555,
2134                                             0xaa);
2135                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2136                                             0x55);
2137                                         qla2x00_write_flash_byte(ha, 0x5555,
2138                                             0xa0);
2139                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2140                                         /* Then erase it */
2141                                         if (qla2x00_erase_flash_sector(ha,
2142                                             addr, sec_mask, man_id,
2143                                             flash_id)) {
2144                                                 rval = QLA_FUNCTION_FAILED;
2145                                                 break;
2146                                         }
2147                                         if (man_id == 0x01 && flash_id == 0x6d)
2148                                                 sec_number++;
2149                                 }
2150                         }
2151
2152                         if (man_id == 0x01 && flash_id == 0x6d) {
2153                                 if (sec_number == 1 &&
2154                                     addr == (rest_addr - 1)) {
2155                                         rest_addr = 0x0fff;
2156                                         sec_mask   = 0x1f000;
2157                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2158                                         rest_addr = 0x3fff;
2159                                         sec_mask   = 0x1c000;
2160                                 }
2161                         }
2162
2163                         if (qla2x00_program_flash_address(ha, addr, data,
2164                             man_id, flash_id)) {
2165                                 rval = QLA_FUNCTION_FAILED;
2166                                 break;
2167                         }
2168                         cond_resched();
2169                 }
2170         } while (0);
2171         qla2x00_flash_disable(ha);
2172
2173         /* Resume HBA. */
2174         qla2x00_resume_hba(vha);
2175
2176         return rval;
2177 }
2178
2179 uint8_t *
2180 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2181     uint32_t offset, uint32_t length)
2182 {
2183         struct qla_hw_data *ha = vha->hw;
2184
2185         /* Suspend HBA. */
2186         scsi_block_requests(vha->host);
2187         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2188
2189         /* Go with read. */
2190         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2191
2192         /* Resume HBA. */
2193         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2194         scsi_unblock_requests(vha->host);
2195
2196         return buf;
2197 }
2198
2199 int
2200 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2201     uint32_t offset, uint32_t length)
2202 {
2203         int rval;
2204         struct qla_hw_data *ha = vha->hw;
2205
2206         /* Suspend HBA. */
2207         scsi_block_requests(vha->host);
2208         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2209
2210         /* Go with write. */
2211         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2212             length >> 2);
2213
2214         /* Resume HBA -- RISC reset needed. */
2215         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2216         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2217         qla2xxx_wake_dpc(vha);
2218         qla2x00_wait_for_hba_online(vha);
2219         scsi_unblock_requests(vha->host);
2220
2221         return rval;
2222 }
2223
2224 uint8_t *
2225 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2226     uint32_t offset, uint32_t length)
2227 {
2228         int rval;
2229         dma_addr_t optrom_dma;
2230         void *optrom;
2231         uint8_t *pbuf;
2232         uint32_t faddr, left, burst;
2233         struct qla_hw_data *ha = vha->hw;
2234
2235         if (offset & 0xfff)
2236                 goto slow_read;
2237         if (length < OPTROM_BURST_SIZE)
2238                 goto slow_read;
2239
2240         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2241             &optrom_dma, GFP_KERNEL);
2242         if (!optrom) {
2243                 qla_printk(KERN_DEBUG, ha,
2244                     "Unable to allocate memory for optrom burst read "
2245                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2246
2247                 goto slow_read;
2248         }
2249
2250         pbuf = buf;
2251         faddr = offset >> 2;
2252         left = length >> 2;
2253         burst = OPTROM_BURST_DWORDS;
2254         while (left != 0) {
2255                 if (burst > left)
2256                         burst = left;
2257
2258                 rval = qla2x00_dump_ram(vha, optrom_dma,
2259                     flash_data_addr(ha, faddr), burst);
2260                 if (rval) {
2261                         qla_printk(KERN_WARNING, ha,
2262                             "Unable to burst-read optrom segment "
2263                             "(%x/%x/%llx).\n", rval,
2264                             flash_data_addr(ha, faddr),
2265                             (unsigned long long)optrom_dma);
2266                         qla_printk(KERN_WARNING, ha,
2267                             "Reverting to slow-read.\n");
2268
2269                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2270                             optrom, optrom_dma);
2271                         goto slow_read;
2272                 }
2273
2274                 memcpy(pbuf, optrom, burst * 4);
2275
2276                 left -= burst;
2277                 faddr += burst;
2278                 pbuf += burst * 4;
2279         }
2280
2281         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2282             optrom_dma);
2283
2284         return buf;
2285
2286 slow_read:
2287     return qla24xx_read_optrom_data(vha, buf, offset, length);
2288 }
2289
2290 /**
2291  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2292  * @ha: HA context
2293  * @pcids: Pointer to the FCODE PCI data structure
2294  *
2295  * The process of retrieving the FCODE version information is at best
2296  * described as interesting.
2297  *
2298  * Within the first 100h bytes of the image an ASCII string is present
2299  * which contains several pieces of information including the FCODE
2300  * version.  Unfortunately it seems the only reliable way to retrieve
2301  * the version is by scanning for another sentinel within the string,
2302  * the FCODE build date:
2303  *
2304  *      ... 2.00.02 10/17/02 ...
2305  *
2306  * Returns QLA_SUCCESS on successful retrieval of version.
2307  */
2308 static void
2309 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2310 {
2311         int ret = QLA_FUNCTION_FAILED;
2312         uint32_t istart, iend, iter, vend;
2313         uint8_t do_next, rbyte, *vbyte;
2314
2315         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2316
2317         /* Skip the PCI data structure. */
2318         istart = pcids +
2319             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2320                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2321         iend = istart + 0x100;
2322         do {
2323                 /* Scan for the sentinel date string...eeewww. */
2324                 do_next = 0;
2325                 iter = istart;
2326                 while ((iter < iend) && !do_next) {
2327                         iter++;
2328                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2329                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2330                                     '/')
2331                                         do_next++;
2332                                 else if (qla2x00_read_flash_byte(ha,
2333                                     iter + 3) == '/')
2334                                         do_next++;
2335                         }
2336                 }
2337                 if (!do_next)
2338                         break;
2339
2340                 /* Backtrack to previous ' ' (space). */
2341                 do_next = 0;
2342                 while ((iter > istart) && !do_next) {
2343                         iter--;
2344                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2345                                 do_next++;
2346                 }
2347                 if (!do_next)
2348                         break;
2349
2350                 /*
2351                  * Mark end of version tag, and find previous ' ' (space) or
2352                  * string length (recent FCODE images -- major hack ahead!!!).
2353                  */
2354                 vend = iter - 1;
2355                 do_next = 0;
2356                 while ((iter > istart) && !do_next) {
2357                         iter--;
2358                         rbyte = qla2x00_read_flash_byte(ha, iter);
2359                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2360                                 do_next++;
2361                 }
2362                 if (!do_next)
2363                         break;
2364
2365                 /* Mark beginning of version tag, and copy data. */
2366                 iter++;
2367                 if ((vend - iter) &&
2368                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2369                         vbyte = ha->fcode_revision;
2370                         while (iter <= vend) {
2371                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2372                                 iter++;
2373                         }
2374                         ret = QLA_SUCCESS;
2375                 }
2376         } while (0);
2377
2378         if (ret != QLA_SUCCESS)
2379                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2380 }
2381
2382 int
2383 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2384 {
2385         int ret = QLA_SUCCESS;
2386         uint8_t code_type, last_image;
2387         uint32_t pcihdr, pcids;
2388         uint8_t *dbyte;
2389         uint16_t *dcode;
2390         struct qla_hw_data *ha = vha->hw;
2391
2392         if (!ha->pio_address || !mbuf)
2393                 return QLA_FUNCTION_FAILED;
2394
2395         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2396         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2397         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2398         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2399
2400         qla2x00_flash_enable(ha);
2401
2402         /* Begin with first PCI expansion ROM header. */
2403         pcihdr = 0;
2404         last_image = 1;
2405         do {
2406                 /* Verify PCI expansion ROM header. */
2407                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2408                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2409                         /* No signature */
2410                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2411                             "signature.\n"));
2412                         ret = QLA_FUNCTION_FAILED;
2413                         break;
2414                 }
2415
2416                 /* Locate PCI data structure. */
2417                 pcids = pcihdr +
2418                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2419                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2420
2421                 /* Validate signature of PCI data structure. */
2422                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2423                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2424                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2425                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2426                         /* Incorrect header. */
2427                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2428                             "found pcir_adr=%x.\n", pcids));
2429                         ret = QLA_FUNCTION_FAILED;
2430                         break;
2431                 }
2432
2433                 /* Read version */
2434                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2435                 switch (code_type) {
2436                 case ROM_CODE_TYPE_BIOS:
2437                         /* Intel x86, PC-AT compatible. */
2438                         ha->bios_revision[0] =
2439                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2440                         ha->bios_revision[1] =
2441                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2442                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2443                             ha->bios_revision[1], ha->bios_revision[0]));
2444                         break;
2445                 case ROM_CODE_TYPE_FCODE:
2446                         /* Open Firmware standard for PCI (FCode). */
2447                         /* Eeeewww... */
2448                         qla2x00_get_fcode_version(ha, pcids);
2449                         break;
2450                 case ROM_CODE_TYPE_EFI:
2451                         /* Extensible Firmware Interface (EFI). */
2452                         ha->efi_revision[0] =
2453                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2454                         ha->efi_revision[1] =
2455                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2456                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2457                             ha->efi_revision[1], ha->efi_revision[0]));
2458                         break;
2459                 default:
2460                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2461                             "type %x at pcids %x.\n", code_type, pcids));
2462                         break;
2463                 }
2464
2465                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2466
2467                 /* Locate next PCI expansion ROM. */
2468                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2469                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2470         } while (!last_image);
2471
2472         if (IS_QLA2322(ha)) {
2473                 /* Read firmware image information. */
2474                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2475                 dbyte = mbuf;
2476                 memset(dbyte, 0, 8);
2477                 dcode = (uint16_t *)dbyte;
2478
2479                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2480                     8);
2481                 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2482                     "flash:\n"));
2483                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2484
2485                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2486                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2487                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2488                     dcode[3] == 0)) {
2489                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2490                             "revision at %x.\n", ha->flt_region_fw * 4));
2491                 } else {
2492                         /* values are in big endian */
2493                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2494                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2495                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2496                 }
2497         }
2498
2499         qla2x00_flash_disable(ha);
2500
2501         return ret;
2502 }
2503
2504 int
2505 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2506 {
2507         int ret = QLA_SUCCESS;
2508         uint32_t pcihdr, pcids;
2509         uint32_t *dcode;
2510         uint8_t *bcode;
2511         uint8_t code_type, last_image;
2512         int i;
2513         struct qla_hw_data *ha = vha->hw;
2514
2515         if (!mbuf)
2516                 return QLA_FUNCTION_FAILED;
2517
2518         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2519         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2520         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2521         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2522
2523         dcode = mbuf;
2524
2525         /* Begin with first PCI expansion ROM header. */
2526         pcihdr = ha->flt_region_boot;
2527         last_image = 1;
2528         do {
2529                 /* Verify PCI expansion ROM header. */
2530                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2531                 bcode = mbuf + (pcihdr % 4);
2532                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2533                         /* No signature */
2534                         DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2535                             "signature.\n"));
2536                         ret = QLA_FUNCTION_FAILED;
2537                         break;
2538                 }
2539
2540                 /* Locate PCI data structure. */
2541                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2542
2543                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2544                 bcode = mbuf + (pcihdr % 4);
2545
2546                 /* Validate signature of PCI data structure. */
2547                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2548                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2549                         /* Incorrect header. */
2550                         DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2551                             "found pcir_adr=%x.\n", pcids));
2552                         ret = QLA_FUNCTION_FAILED;
2553                         break;
2554                 }
2555
2556                 /* Read version */
2557                 code_type = bcode[0x14];
2558                 switch (code_type) {
2559                 case ROM_CODE_TYPE_BIOS:
2560                         /* Intel x86, PC-AT compatible. */
2561                         ha->bios_revision[0] = bcode[0x12];
2562                         ha->bios_revision[1] = bcode[0x13];
2563                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2564                             ha->bios_revision[1], ha->bios_revision[0]));
2565                         break;
2566                 case ROM_CODE_TYPE_FCODE:
2567                         /* Open Firmware standard for PCI (FCode). */
2568                         ha->fcode_revision[0] = bcode[0x12];
2569                         ha->fcode_revision[1] = bcode[0x13];
2570                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2571                             ha->fcode_revision[1], ha->fcode_revision[0]));
2572                         break;
2573                 case ROM_CODE_TYPE_EFI:
2574                         /* Extensible Firmware Interface (EFI). */
2575                         ha->efi_revision[0] = bcode[0x12];
2576                         ha->efi_revision[1] = bcode[0x13];
2577                         DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2578                             ha->efi_revision[1], ha->efi_revision[0]));
2579                         break;
2580                 default:
2581                         DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2582                             "type %x at pcids %x.\n", code_type, pcids));
2583                         break;
2584                 }
2585
2586                 last_image = bcode[0x15] & BIT_7;
2587
2588                 /* Locate next PCI expansion ROM. */
2589                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2590         } while (!last_image);
2591
2592         /* Read firmware image information. */
2593         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2594         dcode = mbuf;
2595
2596         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2597         for (i = 0; i < 4; i++)
2598                 dcode[i] = be32_to_cpu(dcode[i]);
2599
2600         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2601             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2602             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2603             dcode[3] == 0)) {
2604                 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2605                     "revision at %x.\n", ha->flt_region_fw * 4));
2606         } else {
2607                 ha->fw_revision[0] = dcode[0];
2608                 ha->fw_revision[1] = dcode[1];
2609                 ha->fw_revision[2] = dcode[2];
2610                 ha->fw_revision[3] = dcode[3];
2611         }
2612
2613         return ret;
2614 }
2615
2616 static int
2617 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2618 {
2619         if (pos >= end || *pos != 0x82)
2620                 return 0;
2621
2622         pos += 3 + pos[1];
2623         if (pos >= end || *pos != 0x90)
2624                 return 0;
2625
2626         pos += 3 + pos[1];
2627         if (pos >= end || *pos != 0x78)
2628                 return 0;
2629
2630         return 1;
2631 }
2632
2633 int
2634 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2635 {
2636         struct qla_hw_data *ha = vha->hw;
2637         uint8_t *pos = ha->vpd;
2638         uint8_t *end = pos + ha->vpd_size;
2639         int len = 0;
2640
2641         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2642                 return 0;
2643
2644         while (pos < end && *pos != 0x78) {
2645                 len = (*pos == 0x82) ? pos[1] : pos[2];
2646
2647                 if (!strncmp(pos, key, strlen(key)))
2648                         break;
2649
2650                 if (*pos != 0x90 && *pos != 0x91)
2651                         pos += len;
2652
2653                 pos += 3;
2654         }
2655
2656         if (pos < end - len && *pos != 0x78)
2657                 return snprintf(str, size, "%.*s", len, pos + 3);
2658
2659         return 0;
2660 }