drivers/scsi/mesh.c

   1 /*
   2  * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
   3  * bus adaptor found on Power Macintosh computers.
   4  * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
   5  * controller.
   6  *
   7  * Paul Mackerras, August 1996.
   8  * Copyright (C) 1996 Paul Mackerras.
   9  *
  10  * Apr. 21 2002  - BenH         Rework bus reset code for new error handler
  11  *                              Add delay after initial bus reset
  12  *                              Add module parameters
  13  *
  14  * Sep. 27 2003  - BenH         Move to new driver model, fix some write posting
  15  *                              issues
  16  * To do:
  17  * - handle aborts correctly
  18  * - retry arbitration if lost (unless higher levels do this for us)
  19  * - power down the chip when no device is detected
  20  */
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/delay.h>
  24 #include <linux/types.h>
  25 #include <linux/string.h>
  26 #include <linux/blkdev.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/stat.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/reboot.h>
  31 #include <linux/spinlock.h>
  32 #include <asm/dbdma.h>
  33 #include <asm/io.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/prom.h>
  36 #include <asm/system.h>
  37 #include <asm/irq.h>
  38 #include <asm/hydra.h>
  39 #include <asm/processor.h>
  40 #include <asm/machdep.h>
  41 #include <asm/pmac_feature.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/macio.h>
  44
  45 #include <scsi/scsi.h>
  46 #include <scsi/scsi_cmnd.h>
  47 #include <scsi/scsi_device.h>
  48 #include <scsi/scsi_host.h>
  49
  50 #include "mesh.h"
  51
  52 #if 1
  53 #undef KERN_DEBUG
  54 #define KERN_DEBUG KERN_WARNING
  55 #endif
  56
  57 MODULE_AUTHOR("Paul Mackerras (paulus@samba.org)");
  58 MODULE_DESCRIPTION("PowerMac MESH SCSI driver");
  59 MODULE_LICENSE("GPL");
  60
  61 static int sync_rate = CONFIG_SCSI_MESH_SYNC_RATE;
  62 static int sync_targets = 0xff;
  63 static int resel_targets = 0xff;
  64 static int debug_targets = 0;   /* print debug for these targets */
  65 static int init_reset_delay = CONFIG_SCSI_MESH_RESET_DELAY_MS;
  66
  67 module_param(sync_rate, int, 0);
  68 MODULE_PARM_DESC(sync_rate, "Synchronous rate (0..10, 0=async)");
  69 module_param(sync_targets, int, 0);
  70 MODULE_PARM_DESC(sync_targets, "Bitmask of targets allowed to set synchronous");
  71 module_param(resel_targets, int, 0);
  72 MODULE_PARM_DESC(resel_targets, "Bitmask of targets allowed to set disconnect");
  73 module_param(debug_targets, int, 0644);
  74 MODULE_PARM_DESC(debug_targets, "Bitmask of debugged targets");
  75 module_param(init_reset_delay, int, 0);
  76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
  77
  78 static int mesh_sync_period = 100;
  79 static int mesh_sync_offset = 0;
  80 static unsigned char use_active_neg = 0;  /* bit mask for SEQ_ACTIVE_NEG if used */
  81
  82 #define ALLOW_SYNC(tgt)         ((sync_targets >> (tgt)) & 1)
  83 #define ALLOW_RESEL(tgt)        ((resel_targets >> (tgt)) & 1)
  84 #define ALLOW_DEBUG(tgt)        ((debug_targets >> (tgt)) & 1)
  85 #define DEBUG_TARGET(cmd)       ((cmd) && ALLOW_DEBUG((cmd)->device->id))
  86
  87 #undef MESH_DBG
  88 #define N_DBG_LOG       50
  89 #define N_DBG_SLOG      20
  90 #define NUM_DBG_EVENTS  13
  91 #undef  DBG_USE_TB              /* bombs on 601 */
  92
  93 struct dbglog {
  94         char    *fmt;
  95         u32     tb;
  96         u8      phase;
  97         u8      bs0;
  98         u8      bs1;
  99         u8      tgt;
 100         int     d;
 101 };
 102
 103 enum mesh_phase {
 104         idle,
 105         arbitrating,
 106         selecting,
 107         commanding,
 108         dataing,
 109         statusing,
 110         busfreeing,
 111         disconnecting,
 112         reselecting,
 113         sleeping
 114 };
 115
 116 enum msg_phase {
 117         msg_none,
 118         msg_out,
 119         msg_out_xxx,
 120         msg_out_last,
 121         msg_in,
 122         msg_in_bad,
 123 };
 124
 125 enum sdtr_phase {
 126         do_sdtr,
 127         sdtr_sent,
 128         sdtr_done
 129 };
 130
 131 struct mesh_target {
 132         enum sdtr_phase sdtr_state;
 133         int     sync_params;
 134         int     data_goes_out;          /* guess as to data direction */
 135         struct scsi_cmnd *current_req;
 136         u32     saved_ptr;
 137 #ifdef MESH_DBG
 138         int     log_ix;
 139         int     n_log;
 140         struct dbglog log[N_DBG_LOG];
 141 #endif
 142 };
 143
 144 struct mesh_state {
 145         volatile struct mesh_regs __iomem *mesh;
 146         int     meshintr;
 147         volatile struct dbdma_regs __iomem *dma;
 148         int     dmaintr;
 149         struct  Scsi_Host *host;
 150         struct  mesh_state *next;
 151         struct scsi_cmnd *request_q;
 152         struct scsi_cmnd *request_qtail;
 153         enum mesh_phase phase;          /* what we're currently trying to do */
 154         enum msg_phase msgphase;
 155         int     conn_tgt;               /* target we're connected to */
 156         struct scsi_cmnd *current_req;          /* req we're currently working on */
 157         int     data_ptr;
 158         int     dma_started;
 159         int     dma_count;
 160         int     stat;
 161         int     aborting;
 162         int     expect_reply;
 163         int     n_msgin;
 164         u8      msgin[16];
 165         int     n_msgout;
 166         int     last_n_msgout;
 167         u8      msgout[16];
 168         struct dbdma_cmd *dma_cmds;     /* space for dbdma commands, aligned */
 169         dma_addr_t dma_cmd_bus;
 170         void    *dma_cmd_space;
 171         int     dma_cmd_size;
 172         int     clk_freq;
 173         struct mesh_target tgts[8];
 174         struct macio_dev *mdev;
 175         struct pci_dev* pdev;
 176 #ifdef MESH_DBG
 177         int     log_ix;
 178         int     n_log;
 179         struct dbglog log[N_DBG_SLOG];
 180 #endif
 181 };
 182
 183 /*
 184  * Driver is too messy, we need a few prototypes...
 185  */
 186 static void mesh_done(struct mesh_state *ms, int start_next);
 187 static void mesh_interrupt(struct mesh_state *ms);
 188 static void cmd_complete(struct mesh_state *ms);
 189 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
 190 static void halt_dma(struct mesh_state *ms);
 191 static void phase_mismatch(struct mesh_state *ms);
 192
 193
 194 /*
 195  * Some debugging & logging routines
 196  */
 197
 198 #ifdef MESH_DBG
 199
 200 static inline u32 readtb(void)
 201 {
 202         u32 tb;
 203
 204 #ifdef DBG_USE_TB
 205         /* Beware: if you enable this, it will crash on 601s. */
 206         asm ("mftb %0" : "=r" (tb) : );
 207 #else
 208         tb = 0;
 209 #endif
 210         return tb;
 211 }
 212
 213 static void dlog(struct mesh_state *ms, char *fmt, int a)
 214 {
 215         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 216         struct dbglog *tlp, *slp;
 217
 218         tlp = &tp->log[tp->log_ix];
 219         slp = &ms->log[ms->log_ix];
 220         tlp->fmt = fmt;
 221         tlp->tb = readtb();
 222         tlp->phase = (ms->msgphase << 4) + ms->phase;
 223         tlp->bs0 = ms->mesh->bus_status0;
 224         tlp->bs1 = ms->mesh->bus_status1;
 225         tlp->tgt = ms->conn_tgt;
 226         tlp->d = a;
 227         *slp = *tlp;
 228         if (++tp->log_ix >= N_DBG_LOG)
 229                 tp->log_ix = 0;
 230         if (tp->n_log < N_DBG_LOG)
 231                 ++tp->n_log;
 232         if (++ms->log_ix >= N_DBG_SLOG)
 233                 ms->log_ix = 0;
 234         if (ms->n_log < N_DBG_SLOG)
 235                 ++ms->n_log;
 236 }
 237
 238 static void dumplog(struct mesh_state *ms, int t)
 239 {
 240         struct mesh_target *tp = &ms->tgts[t];
 241         struct dbglog *lp;
 242         int i;
 243
 244         if (tp->n_log == 0)
 245                 return;
 246         i = tp->log_ix - tp->n_log;
 247         if (i < 0)
 248                 i += N_DBG_LOG;
 249         tp->n_log = 0;
 250         do {
 251                 lp = &tp->log[i];
 252                 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
 253                        t, lp->bs1, lp->bs0, lp->phase);
 254 #ifdef DBG_USE_TB
 255                 printk("tb=%10u ", lp->tb);
 256 #endif
 257                 printk(lp->fmt, lp->d);
 258                 printk("\n");
 259                 if (++i >= N_DBG_LOG)
 260                         i = 0;
 261         } while (i != tp->log_ix);
 262 }
 263
 264 static void dumpslog(struct mesh_state *ms)
 265 {
 266         struct dbglog *lp;
 267         int i;
 268
 269         if (ms->n_log == 0)
 270                 return;
 271         i = ms->log_ix - ms->n_log;
 272         if (i < 0)
 273                 i += N_DBG_SLOG;
 274         ms->n_log = 0;
 275         do {
 276                 lp = &ms->log[i];
 277                 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
 278                        lp->bs1, lp->bs0, lp->phase, lp->tgt);
 279 #ifdef DBG_USE_TB
 280                 printk("tb=%10u ", lp->tb);
 281 #endif
 282                 printk(lp->fmt, lp->d);
 283                 printk("\n");
 284                 if (++i >= N_DBG_SLOG)
 285                         i = 0;
 286         } while (i != ms->log_ix);
 287 }
 288
 289 #else
 290
 291 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
 292 {}
 293 static inline void dumplog(struct mesh_state *ms, int tgt)
 294 {}
 295 static inline void dumpslog(struct mesh_state *ms)
 296 {}
 297
 298 #endif /* MESH_DBG */
 299
 300 #define MKWORD(a, b, c, d)      (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
 301
 302 static void
 303 mesh_dump_regs(struct mesh_state *ms)
 304 {
 305         volatile struct mesh_regs __iomem *mr = ms->mesh;
 306         volatile struct dbdma_regs __iomem *md = ms->dma;
 307         int t;
 308         struct mesh_target *tp;
 309
 310         printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
 311                ms, mr, md);
 312         printk(KERN_DEBUG "    ct=%4x seq=%2x bs=%4x fc=%2x "
 313                "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
 314                (mr->count_hi << 8) + mr->count_lo, mr->sequence,
 315                (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
 316                mr->exception, mr->error, mr->intr_mask, mr->interrupt,
 317                mr->sync_params);
 318         while(in_8(&mr->fifo_count))
 319                 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
 320         printk(KERN_DEBUG "    dma stat=%x cmdptr=%x\n",
 321                in_le32(&md->status), in_le32(&md->cmdptr));
 322         printk(KERN_DEBUG "    phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
 323                ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
 324         printk(KERN_DEBUG "    dma_st=%d dma_ct=%d n_msgout=%d\n",
 325                ms->dma_started, ms->dma_count, ms->n_msgout);
 326         for (t = 0; t < 8; ++t) {
 327                 tp = &ms->tgts[t];
 328                 if (tp->current_req == NULL)
 329                         continue;
 330                 printk(KERN_DEBUG "    target %d: req=%p goes_out=%d saved_ptr=%d\n",
 331                        t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
 332         }
 333 }
 334
 335
 336 /*
 337  * Flush write buffers on the bus path to the mesh
 338  */
 339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
 340 {
 341         (void)in_8(&mr->mesh_id);
 342 }
 343
 344
 345 /*
 346  * Complete a SCSI command
 347  */
 348 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd)
 349 {
 350         (*cmd->scsi_done)(cmd);
 351 }
 352
 353
 354 /* Called with  meshinterrupt disabled, initialize the chipset
 355  * and eventually do the initial bus reset. The lock must not be
 356  * held since we can schedule.
 357  */
 358 static void mesh_init(struct mesh_state *ms)
 359 {
 360         volatile struct mesh_regs __iomem *mr = ms->mesh;
 361         volatile struct dbdma_regs __iomem *md = ms->dma;
 362
 363         mesh_flush_io(mr);
 364         udelay(100);
 365
 366         /* Reset controller */
 367         out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
 368         out_8(&mr->exception, 0xff);    /* clear all exception bits */
 369         out_8(&mr->error, 0xff);        /* clear all error bits */
 370         out_8(&mr->sequence, SEQ_RESETMESH);
 371         mesh_flush_io(mr);
 372         udelay(10);
 373         out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 374         out_8(&mr->source_id, ms->host->this_id);
 375         out_8(&mr->sel_timeout, 25);    /* 250ms */
 376         out_8(&mr->sync_params, ASYNC_PARAMS);
 377
 378         if (init_reset_delay) {
 379                 printk(KERN_INFO "mesh: performing initial bus reset...\n");
 380
 381                 /* Reset bus */
 382                 out_8(&mr->bus_status1, BS1_RST);       /* assert RST */
 383                 mesh_flush_io(mr);
 384                 udelay(30);                     /* leave it on for >= 25us */
 385                 out_8(&mr->bus_status1, 0);     /* negate RST */
 386                 mesh_flush_io(mr);
 387
 388                 /* Wait for bus to come back */
 389                 msleep(init_reset_delay);
 390         }
 391
 392         /* Reconfigure controller */
 393         out_8(&mr->interrupt, 0xff);    /* clear all interrupt bits */
 394         out_8(&mr->sequence, SEQ_FLUSHFIFO);
 395         mesh_flush_io(mr);
 396         udelay(1);
 397         out_8(&mr->sync_params, ASYNC_PARAMS);
 398         out_8(&mr->sequence, SEQ_ENBRESEL);
 399
 400         ms->phase = idle;
 401         ms->msgphase = msg_none;
 402 }
 403
 404
 405 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd)
 406 {
 407         volatile struct mesh_regs __iomem *mr = ms->mesh;
 408         int t, id;
 409
 410         id = cmd->device->id;
 411         ms->current_req = cmd;
 412         ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE;
 413         ms->tgts[id].current_req = cmd;
 414
 415 #if 1
 416         if (DEBUG_TARGET(cmd)) {
 417                 int i;
 418                 printk(KERN_DEBUG "mesh_start: %p ser=%lu tgt=%d cmd=",
 419                        cmd, cmd->serial_number, id);
 420                 for (i = 0; i < cmd->cmd_len; ++i)
 421                         printk(" %x", cmd->cmnd[i]);
 422                 printk(" use_sg=%d buffer=%p bufflen=%u\n",
 423                        scsi_sg_count(cmd), scsi_sglist(cmd), scsi_bufflen(cmd));
 424         }
 425 #endif
 426         if (ms->dma_started)
 427                 panic("mesh: double DMA start !\n");
 428
 429         ms->phase = arbitrating;
 430         ms->msgphase = msg_none;
 431         ms->data_ptr = 0;
 432         ms->dma_started = 0;
 433         ms->n_msgout = 0;
 434         ms->last_n_msgout = 0;
 435         ms->expect_reply = 0;
 436         ms->conn_tgt = id;
 437         ms->tgts[id].saved_ptr = 0;
 438         ms->stat = DID_OK;
 439         ms->aborting = 0;
 440 #ifdef MESH_DBG
 441         ms->tgts[id].n_log = 0;
 442         dlog(ms, "start cmd=%x", (int) cmd);
 443 #endif
 444
 445         /* Off we go */
 446         dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
 447              MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 448         out_8(&mr->interrupt, INT_CMDDONE);
 449         out_8(&mr->sequence, SEQ_ENBRESEL);
 450         mesh_flush_io(mr);
 451         udelay(1);
 452
 453         if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
 454                 /*
 455                  * Some other device has the bus or is arbitrating for it -
 456                  * probably a target which is about to reselect us.
 457                  */
 458                 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
 459                      MKWORD(mr->interrupt, mr->exception,
 460                             mr->error, mr->fifo_count));
 461                 for (t = 100; t > 0; --t) {
 462                         if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
 463                                 break;
 464                         if (in_8(&mr->interrupt) != 0) {
 465                                 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
 466                                      MKWORD(mr->interrupt, mr->exception,
 467                                             mr->error, mr->fifo_count));
 468                                 mesh_interrupt(ms);
 469                                 if (ms->phase != arbitrating)
 470                                         return;
 471                         }
 472                         udelay(1);
 473                 }
 474                 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
 475                         /* XXX should try again in a little while */
 476                         ms->stat = DID_BUS_BUSY;
 477                         ms->phase = idle;
 478                         mesh_done(ms, 0);
 479                         return;
 480                 }
 481         }
 482
 483         /*
 484          * Apparently the mesh has a bug where it will assert both its
 485          * own bit and the target's bit on the bus during arbitration.
 486          */
 487         out_8(&mr->dest_id, mr->source_id);
 488
 489         /*
 490          * There appears to be a race with reselection sometimes,
 491          * where a target reselects us just as we issue the
 492          * arbitrate command.  It seems that then the arbitrate
 493          * command just hangs waiting for the bus to be free
 494          * without giving us a reselection exception.
 495          * The only way I have found to get it to respond correctly
 496          * is this: disable reselection before issuing the arbitrate
 497          * command, then after issuing it, if it looks like a target
 498          * is trying to reselect us, reset the mesh and then enable
 499          * reselection.
 500          */
 501         out_8(&mr->sequence, SEQ_DISRESEL);
 502         if (in_8(&mr->interrupt) != 0) {
 503                 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
 504                      MKWORD(mr->interrupt, mr->exception,
 505                             mr->error, mr->fifo_count));
 506                 mesh_interrupt(ms);
 507                 if (ms->phase != arbitrating)
 508                         return;
 509                 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
 510                      MKWORD(mr->interrupt, mr->exception,
 511                             mr->error, mr->fifo_count));
 512         }
 513
 514         out_8(&mr->sequence, SEQ_ARBITRATE);
 515
 516         for (t = 230; t > 0; --t) {
 517                 if (in_8(&mr->interrupt) != 0)
 518                         break;
 519                 udelay(1);
 520         }
 521         dlog(ms, "after arb, intr/exc/err/fc=%.8x",
 522              MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 523         if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
 524             && (in_8(&mr->bus_status0) & BS0_IO)) {
 525                 /* looks like a reselection - try resetting the mesh */
 526                 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
 527                      MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 528                 out_8(&mr->sequence, SEQ_RESETMESH);
 529                 mesh_flush_io(mr);
 530                 udelay(10);
 531                 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 532                 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 533                 out_8(&mr->sequence, SEQ_ENBRESEL);
 534                 mesh_flush_io(mr);
 535                 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
 536                         udelay(1);
 537                 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
 538                      MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
 539 #ifndef MESH_MULTIPLE_HOSTS
 540                 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
 541                     && (in_8(&mr->bus_status0) & BS0_IO)) {
 542                         printk(KERN_ERR "mesh: controller not responding"
 543                                " to reselection!\n");
 544                         /*
 545                          * If this is a target reselecting us, and the
 546                          * mesh isn't responding, the higher levels of
 547                          * the scsi code will eventually time out and
 548                          * reset the bus.
 549                          */
 550                 }
 551 #endif
 552         }
 553 }
 554
 555 /*
 556  * Start the next command for a MESH.
 557  * Should be called with interrupts disabled.
 558  */
 559 static void mesh_start(struct mesh_state *ms)
 560 {
 561         struct scsi_cmnd *cmd, *prev, *next;
 562
 563         if (ms->phase != idle || ms->current_req != NULL) {
 564                 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
 565                        ms->phase, ms);
 566                 return;
 567         }
 568
 569         while (ms->phase == idle) {
 570                 prev = NULL;
 571                 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) {
 572                         if (cmd == NULL)
 573                                 return;
 574                         if (ms->tgts[cmd->device->id].current_req == NULL)
 575                                 break;
 576                         prev = cmd;
 577                 }
 578                 next = (struct scsi_cmnd *) cmd->host_scribble;
 579                 if (prev == NULL)
 580                         ms->request_q = next;
 581                 else
 582                         prev->host_scribble = (void *) next;
 583                 if (next == NULL)
 584                         ms->request_qtail = prev;
 585
 586                 mesh_start_cmd(ms, cmd);
 587         }
 588 }
 589
 590 static void mesh_done(struct mesh_state *ms, int start_next)
 591 {
 592         struct scsi_cmnd *cmd;
 593         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 594
 595         cmd = ms->current_req;
 596         ms->current_req = NULL;
 597         tp->current_req = NULL;
 598         if (cmd) {
 599                 cmd->result = (ms->stat << 16) + cmd->SCp.Status;
 600                 if (ms->stat == DID_OK)
 601                         cmd->result += (cmd->SCp.Message << 8);
 602                 if (DEBUG_TARGET(cmd)) {
 603                         printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
 604                                cmd->result, ms->data_ptr, scsi_bufflen(cmd));
 605 #if 0
 606                         /* needs to use sg? */
 607                         if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
 608                             && cmd->request_buffer != 0) {
 609                                 unsigned char *b = cmd->request_buffer;
 610                                 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
 611                                        b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
 612                         }
 613 #endif
 614                 }
 615                 cmd->SCp.this_residual -= ms->data_ptr;
 616                 mesh_completed(ms, cmd);
 617         }
 618         if (start_next) {
 619                 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
 620                 mesh_flush_io(ms->mesh);
 621                 udelay(1);
 622                 ms->phase = idle;
 623                 mesh_start(ms);
 624         }
 625 }
 626
 627 static inline void add_sdtr_msg(struct mesh_state *ms)
 628 {
 629         int i = ms->n_msgout;
 630
 631         ms->msgout[i] = EXTENDED_MESSAGE;
 632         ms->msgout[i+1] = 3;
 633         ms->msgout[i+2] = EXTENDED_SDTR;
 634         ms->msgout[i+3] = mesh_sync_period/4;
 635         ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
 636         ms->n_msgout = i + 5;
 637 }
 638
 639 static void set_sdtr(struct mesh_state *ms, int period, int offset)
 640 {
 641         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 642         volatile struct mesh_regs __iomem *mr = ms->mesh;
 643         int v, tr;
 644
 645         tp->sdtr_state = sdtr_done;
 646         if (offset == 0) {
 647                 /* asynchronous */
 648                 if (SYNC_OFF(tp->sync_params))
 649                         printk(KERN_INFO "mesh: target %d now asynchronous\n",
 650                                ms->conn_tgt);
 651                 tp->sync_params = ASYNC_PARAMS;
 652                 out_8(&mr->sync_params, ASYNC_PARAMS);
 653                 return;
 654         }
 655         /*
 656          * We need to compute ceil(clk_freq * period / 500e6) - 2
 657          * without incurring overflow.
 658          */
 659         v = (ms->clk_freq / 5000) * period;
 660         if (v <= 250000) {
 661                 /* special case: sync_period == 5 * clk_period */
 662                 v = 0;
 663                 /* units of tr are 100kB/s */
 664                 tr = (ms->clk_freq + 250000) / 500000;
 665         } else {
 666                 /* sync_period == (v + 2) * 2 * clk_period */
 667                 v = (v + 99999) / 100000 - 2;
 668                 if (v > 15)
 669                         v = 15; /* oops */
 670                 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
 671         }
 672         if (offset > 15)
 673                 offset = 15;    /* can't happen */
 674         tp->sync_params = SYNC_PARAMS(offset, v);
 675         out_8(&mr->sync_params, tp->sync_params);
 676         printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
 677                ms->conn_tgt, tr/10, tr%10);
 678 }
 679
 680 static void start_phase(struct mesh_state *ms)
 681 {
 682         int i, seq, nb;
 683         volatile struct mesh_regs __iomem *mr = ms->mesh;
 684         volatile struct dbdma_regs __iomem *md = ms->dma;
 685         struct scsi_cmnd *cmd = ms->current_req;
 686         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
 687
 688         dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
 689              MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
 690         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 691         seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
 692         switch (ms->msgphase) {
 693         case msg_none:
 694                 break;
 695
 696         case msg_in:
 697                 out_8(&mr->count_hi, 0);
 698                 out_8(&mr->count_lo, 1);
 699                 out_8(&mr->sequence, SEQ_MSGIN + seq);
 700                 ms->n_msgin = 0;
 701                 return;
 702
 703         case msg_out:
 704                 /*
 705                  * To make sure ATN drops before we assert ACK for
 706                  * the last byte of the message, we have to do the
 707                  * last byte specially.
 708                  */
 709                 if (ms->n_msgout <= 0) {
 710                         printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
 711                                ms->n_msgout);
 712                         mesh_dump_regs(ms);
 713                         ms->msgphase = msg_none;
 714                         break;
 715                 }
 716                 if (ALLOW_DEBUG(ms->conn_tgt)) {
 717                         printk(KERN_DEBUG "mesh: sending %d msg bytes:",
 718                                ms->n_msgout);
 719                         for (i = 0; i < ms->n_msgout; ++i)
 720                                 printk(" %x", ms->msgout[i]);
 721                         printk("\n");
 722                 }
 723                 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
 724                                                 ms->msgout[1], ms->msgout[2]));
 725                 out_8(&mr->count_hi, 0);
 726                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
 727                 mesh_flush_io(mr);
 728                 udelay(1);
 729                 /*
 730                  * If ATN is not already asserted, we assert it, then
 731                  * issue a SEQ_MSGOUT to get the mesh to drop ACK.
 732                  */
 733                 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
 734                         dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
 735                         out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
 736                         mesh_flush_io(mr);
 737                         udelay(1);
 738                         out_8(&mr->count_lo, 1);
 739                         out_8(&mr->sequence, SEQ_MSGOUT + seq);
 740                         out_8(&mr->bus_status0, 0); /* release explicit ATN */
 741                         dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
 742                 }
 743                 if (ms->n_msgout == 1) {
 744                         /*
 745                          * We can't issue the SEQ_MSGOUT without ATN
 746                          * until the target has asserted REQ.  The logic
 747                          * in cmd_complete handles both situations:
 748                          * REQ already asserted or not.
 749                          */
 750                         cmd_complete(ms);
 751                 } else {
 752                         out_8(&mr->count_lo, ms->n_msgout - 1);
 753                         out_8(&mr->sequence, SEQ_MSGOUT + seq);
 754                         for (i = 0; i < ms->n_msgout - 1; ++i)
 755                                 out_8(&mr->fifo, ms->msgout[i]);
 756                 }
 757                 return;
 758
 759         default:
 760                 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
 761                        ms->msgphase);
 762         }
 763
 764         switch (ms->phase) {
 765         case selecting:
 766                 out_8(&mr->dest_id, ms->conn_tgt);
 767                 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
 768                 break;
 769         case commanding:
 770                 out_8(&mr->sync_params, tp->sync_params);
 771                 out_8(&mr->count_hi, 0);
 772                 if (cmd) {
 773                         out_8(&mr->count_lo, cmd->cmd_len);
 774                         out_8(&mr->sequence, SEQ_COMMAND + seq);
 775                         for (i = 0; i < cmd->cmd_len; ++i)
 776                                 out_8(&mr->fifo, cmd->cmnd[i]);
 777                 } else {
 778                         out_8(&mr->count_lo, 6);
 779                         out_8(&mr->sequence, SEQ_COMMAND + seq);
 780                         for (i = 0; i < 6; ++i)
 781                                 out_8(&mr->fifo, 0);
 782                 }
 783                 break;
 784         case dataing:
 785                 /* transfer data, if any */
 786                 if (!ms->dma_started) {
 787                         set_dma_cmds(ms, cmd);
 788                         out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
 789                         out_le32(&md->control, (RUN << 16) | RUN);
 790                         ms->dma_started = 1;
 791                 }
 792                 nb = ms->dma_count;
 793                 if (nb > 0xfff0)
 794                         nb = 0xfff0;
 795                 ms->dma_count -= nb;
 796                 ms->data_ptr += nb;
 797                 out_8(&mr->count_lo, nb);
 798                 out_8(&mr->count_hi, nb >> 8);
 799                 out_8(&mr->sequence, (tp->data_goes_out?
 800                                 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
 801                 break;
 802         case statusing:
 803                 out_8(&mr->count_hi, 0);
 804                 out_8(&mr->count_lo, 1);
 805                 out_8(&mr->sequence, SEQ_STATUS + seq);
 806                 break;
 807         case busfreeing:
 808         case disconnecting:
 809                 out_8(&mr->sequence, SEQ_ENBRESEL);
 810                 mesh_flush_io(mr);
 811                 udelay(1);
 812                 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
 813                      MKWORD(mr->interrupt, mr->exception, mr->error,
 814                             mr->fifo_count));
 815                 out_8(&mr->sequence, SEQ_BUSFREE);
 816                 break;
 817         default:
 818                 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
 819                        ms->phase);
 820                 dumpslog(ms);
 821         }
 822
 823 }
 824
 825 static inline void get_msgin(struct mesh_state *ms)
 826 {
 827         volatile struct mesh_regs __iomem *mr = ms->mesh;
 828         int i, n;
 829
 830         n = mr->fifo_count;
 831         if (n != 0) {
 832                 i = ms->n_msgin;
 833                 ms->n_msgin = i + n;
 834                 for (; n > 0; --n)
 835                         ms->msgin[i++] = in_8(&mr->fifo);
 836         }
 837 }
 838
 839 static inline int msgin_length(struct mesh_state *ms)
 840 {
 841         int b, n;
 842
 843         n = 1;
 844         if (ms->n_msgin > 0) {
 845                 b = ms->msgin[0];
 846                 if (b == 1) {
 847                         /* extended message */
 848                         n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
 849                 } else if (0x20 <= b && b <= 0x2f) {
 850                         /* 2-byte message */
 851                         n = 2;
 852                 }
 853         }
 854         return n;
 855 }
 856
 857 static void reselected(struct mesh_state *ms)
 858 {
 859         volatile struct mesh_regs __iomem *mr = ms->mesh;
 860         struct scsi_cmnd *cmd;
 861         struct mesh_target *tp;
 862         int b, t, prev;
 863
 864         switch (ms->phase) {
 865         case idle:
 866                 break;
 867         case arbitrating:
 868                 if ((cmd = ms->current_req) != NULL) {
 869                         /* put the command back on the queue */
 870                         cmd->host_scribble = (void *) ms->request_q;
 871                         if (ms->request_q == NULL)
 872                                 ms->request_qtail = cmd;
 873                         ms->request_q = cmd;
 874                         tp = &ms->tgts[cmd->device->id];
 875                         tp->current_req = NULL;
 876                 }
 877                 break;
 878         case busfreeing:
 879                 ms->phase = reselecting;
 880                 mesh_done(ms, 0);
 881                 break;
 882         case disconnecting:
 883                 break;
 884         default:
 885                 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
 886                        ms->msgphase, ms->phase, ms->conn_tgt);
 887                 dumplog(ms, ms->conn_tgt);
 888                 dumpslog(ms);
 889         }
 890
 891         if (ms->dma_started) {
 892                 printk(KERN_ERR "mesh: reselected with DMA started !\n");
 893                 halt_dma(ms);
 894         }
 895         ms->current_req = NULL;
 896         ms->phase = dataing;
 897         ms->msgphase = msg_in;
 898         ms->n_msgout = 0;
 899         ms->last_n_msgout = 0;
 900         prev = ms->conn_tgt;
 901
 902         /*
 903          * We seem to get abortive reselections sometimes.
 904          */
 905         while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
 906                 static int mesh_aborted_resels;
 907                 mesh_aborted_resels++;
 908                 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 909                 mesh_flush_io(mr);
 910                 udelay(1);
 911                 out_8(&mr->sequence, SEQ_ENBRESEL);
 912                 mesh_flush_io(mr);
 913                 udelay(5);
 914                 dlog(ms, "extra resel err/exc/fc = %.6x",
 915                      MKWORD(0, mr->error, mr->exception, mr->fifo_count));
 916         }
 917         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
 918         mesh_flush_io(mr);
 919         udelay(1);
 920         out_8(&mr->sequence, SEQ_ENBRESEL);
 921         mesh_flush_io(mr);
 922         udelay(1);
 923         out_8(&mr->sync_params, ASYNC_PARAMS);
 924
 925         /*
 926          * Find out who reselected us.
 927          */
 928         if (in_8(&mr->fifo_count) == 0) {
 929                 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
 930                 ms->conn_tgt = ms->host->this_id;
 931                 goto bogus;
 932         }
 933         /* get the last byte in the fifo */
 934         do {
 935                 b = in_8(&mr->fifo);
 936                 dlog(ms, "reseldata %x", b);
 937         } while (in_8(&mr->fifo_count));
 938         for (t = 0; t < 8; ++t)
 939                 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
 940                         break;
 941         if (b != (1 << t) + (1 << ms->host->this_id)) {
 942                 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
 943                 ms->conn_tgt = ms->host->this_id;
 944                 goto bogus;
 945         }
 946
 947
 948         /*
 949          * Set up to continue with that target's transfer.
 950          */
 951         ms->conn_tgt = t;
 952         tp = &ms->tgts[t];
 953         out_8(&mr->sync_params, tp->sync_params);
 954         if (ALLOW_DEBUG(t)) {
 955                 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
 956                 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
 957                        tp->saved_ptr, tp->data_goes_out, tp->current_req);
 958         }
 959         ms->current_req = tp->current_req;
 960         if (tp->current_req == NULL) {
 961                 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
 962                 goto bogus;
 963         }
 964         ms->data_ptr = tp->saved_ptr;
 965         dlog(ms, "resel prev tgt=%d", prev);
 966         dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
 967         start_phase(ms);
 968         return;
 969
 970 bogus:
 971         dumplog(ms, ms->conn_tgt);
 972         dumpslog(ms);
 973         ms->data_ptr = 0;
 974         ms->aborting = 1;
 975         start_phase(ms);
 976 }
 977
 978 static void do_abort(struct mesh_state *ms)
 979 {
 980         ms->msgout[0] = ABORT;
 981         ms->n_msgout = 1;
 982         ms->aborting = 1;
 983         ms->stat = DID_ABORT;
 984         dlog(ms, "abort", 0);
 985 }
 986
 987 static void handle_reset(struct mesh_state *ms)
 988 {
 989         int tgt;
 990         struct mesh_target *tp;
 991         struct scsi_cmnd *cmd;
 992         volatile struct mesh_regs __iomem *mr = ms->mesh;
 993
 994         for (tgt = 0; tgt < 8; ++tgt) {
 995                 tp = &ms->tgts[tgt];
 996                 if ((cmd = tp->current_req) != NULL) {
 997                         cmd->result = DID_RESET << 16;
 998                         tp->current_req = NULL;
 999                         mesh_completed(ms, cmd);
1000                 }
1001                 ms->tgts[tgt].sdtr_state = do_sdtr;
1002                 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1003         }
1004         ms->current_req = NULL;
1005         while ((cmd = ms->request_q) != NULL) {
1006                 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble;
1007                 cmd->result = DID_RESET << 16;
1008                 mesh_completed(ms, cmd);
1009         }
1010         ms->phase = idle;
1011         ms->msgphase = msg_none;
1012         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1013         out_8(&mr->sequence, SEQ_FLUSHFIFO);
1014         mesh_flush_io(mr);
1015         udelay(1);
1016         out_8(&mr->sync_params, ASYNC_PARAMS);
1017         out_8(&mr->sequence, SEQ_ENBRESEL);
1018 }
1019
1020 static irqreturn_t do_mesh_interrupt(int irq, void *dev_id)
1021 {
1022         unsigned long flags;
1023         struct mesh_state *ms = dev_id;
1024         struct Scsi_Host *dev = ms->host;
1025
1026         spin_lock_irqsave(dev->host_lock, flags);
1027         mesh_interrupt(ms);
1028         spin_unlock_irqrestore(dev->host_lock, flags);
1029         return IRQ_HANDLED;
1030 }
1031
1032 static void handle_error(struct mesh_state *ms)
1033 {
1034         int err, exc, count;
1035         volatile struct mesh_regs __iomem *mr = ms->mesh;
1036
1037         err = in_8(&mr->error);
1038         exc = in_8(&mr->exception);
1039         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1040         dlog(ms, "error err/exc/fc/cl=%.8x",
1041              MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1042         if (err & ERR_SCSIRESET) {
1043                 /* SCSI bus was reset */
1044                 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1045                        "waiting for end...");
1046                 while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1047                         udelay(1);
1048                 printk("done\n");
1049                 handle_reset(ms);
1050                 /* request_q is empty, no point in mesh_start() */
1051                 return;
1052         }
1053         if (err & ERR_UNEXPDISC) {
1054                 /* Unexpected disconnect */
1055                 if (exc & EXC_RESELECTED) {
1056                         reselected(ms);
1057                         return;
1058                 }
1059                 if (!ms->aborting) {
1060                         printk(KERN_WARNING "mesh: target %d aborted\n",
1061                                ms->conn_tgt);
1062                         dumplog(ms, ms->conn_tgt);
1063                         dumpslog(ms);
1064                 }
1065                 out_8(&mr->interrupt, INT_CMDDONE);
1066                 ms->stat = DID_ABORT;
1067                 mesh_done(ms, 1);
1068                 return;
1069         }
1070         if (err & ERR_PARITY) {
1071                 if (ms->msgphase == msg_in) {
1072                         printk(KERN_ERR "mesh: msg parity error, target %d\n",
1073                                ms->conn_tgt);
1074                         ms->msgout[0] = MSG_PARITY_ERROR;
1075                         ms->n_msgout = 1;
1076                         ms->msgphase = msg_in_bad;
1077                         cmd_complete(ms);
1078                         return;
1079                 }
1080                 if (ms->stat == DID_OK) {
1081                         printk(KERN_ERR "mesh: parity error, target %d\n",
1082                                ms->conn_tgt);
1083                         ms->stat = DID_PARITY;
1084                 }
1085                 count = (mr->count_hi << 8) + mr->count_lo;
1086                 if (count == 0) {
1087                         cmd_complete(ms);
1088                 } else {
1089                         /* reissue the data transfer command */
1090                         out_8(&mr->sequence, mr->sequence);
1091                 }
1092                 return;
1093         }
1094         if (err & ERR_SEQERR) {
1095                 if (exc & EXC_RESELECTED) {
1096                         /* This can happen if we issue a command to
1097                            get the bus just after the target reselects us. */
1098                         static int mesh_resel_seqerr;
1099                         mesh_resel_seqerr++;
1100                         reselected(ms);
1101                         return;
1102                 }
1103                 if (exc == EXC_PHASEMM) {
1104                         static int mesh_phasemm_seqerr;
1105                         mesh_phasemm_seqerr++;
1106                         phase_mismatch(ms);
1107                         return;
1108                 }
1109                 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1110                        err, exc);
1111         } else {
1112                 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1113         }
1114         mesh_dump_regs(ms);
1115         dumplog(ms, ms->conn_tgt);
1116         if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1117                 /* try to do what the target wants */
1118                 do_abort(ms);
1119                 phase_mismatch(ms);
1120                 return;
1121         }
1122         ms->stat = DID_ERROR;
1123         mesh_done(ms, 1);
1124 }
1125
1126 static void handle_exception(struct mesh_state *ms)
1127 {
1128         int exc;
1129         volatile struct mesh_regs __iomem *mr = ms->mesh;
1130
1131         exc = in_8(&mr->exception);
1132         out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1133         if (exc & EXC_RESELECTED) {
1134                 static int mesh_resel_exc;
1135                 mesh_resel_exc++;
1136                 reselected(ms);
1137         } else if (exc == EXC_ARBLOST) {
1138                 printk(KERN_DEBUG "mesh: lost arbitration\n");
1139                 ms->stat = DID_BUS_BUSY;
1140                 mesh_done(ms, 1);
1141         } else if (exc == EXC_SELTO) {
1142                 /* selection timed out */
1143                 ms->stat = DID_BAD_TARGET;
1144                 mesh_done(ms, 1);
1145         } else if (exc == EXC_PHASEMM) {
1146                 /* target wants to do something different:
1147                    find out what it wants and do it. */
1148                 phase_mismatch(ms);
1149         } else {
1150                 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1151                 mesh_dump_regs(ms);
1152                 dumplog(ms, ms->conn_tgt);
1153                 do_abort(ms);
1154                 phase_mismatch(ms);
1155         }
1156 }
1157
1158 static void handle_msgin(struct mesh_state *ms)
1159 {
1160         int i, code;
1161         struct scsi_cmnd *cmd = ms->current_req;
1162         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1163
1164         if (ms->n_msgin == 0)
1165                 return;
1166         code = ms->msgin[0];
1167         if (ALLOW_DEBUG(ms->conn_tgt)) {
1168                 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1169                 for (i = 0; i < ms->n_msgin; ++i)
1170                         printk(" %x", ms->msgin[i]);
1171                 printk("\n");
1172         }
1173         dlog(ms, "msgin msg=%.8x",
1174              MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1175
1176         ms->expect_reply = 0;
1177         ms->n_msgout = 0;
1178         if (ms->n_msgin < msgin_length(ms))
1179                 goto reject;
1180         if (cmd)
1181                 cmd->SCp.Message = code;
1182         switch (code) {
1183         case COMMAND_COMPLETE:
1184                 break;
1185         case EXTENDED_MESSAGE:
1186                 switch (ms->msgin[2]) {
1187                 case EXTENDED_MODIFY_DATA_POINTER:
1188                         ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1189                                 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1190                         break;
1191                 case EXTENDED_SDTR:
1192                         if (tp->sdtr_state != sdtr_sent) {
1193                                 /* reply with an SDTR */
1194                                 add_sdtr_msg(ms);
1195                                 /* limit period to at least his value,
1196                                    offset to no more than his */
1197                                 if (ms->msgout[3] < ms->msgin[3])
1198                                         ms->msgout[3] = ms->msgin[3];
1199                                 if (ms->msgout[4] > ms->msgin[4])
1200                                         ms->msgout[4] = ms->msgin[4];
1201                                 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1202                                 ms->msgphase = msg_out;
1203                         } else {
1204                                 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1205                         }
1206                         break;
1207                 default:
1208                         goto reject;
1209                 }
1210                 break;
1211         case SAVE_POINTERS:
1212                 tp->saved_ptr = ms->data_ptr;
1213                 break;
1214         case RESTORE_POINTERS:
1215                 ms->data_ptr = tp->saved_ptr;
1216                 break;
1217         case DISCONNECT:
1218                 ms->phase = disconnecting;
1219                 break;
1220         case ABORT:
1221                 break;
1222         case MESSAGE_REJECT:
1223                 if (tp->sdtr_state == sdtr_sent)
1224                         set_sdtr(ms, 0, 0);
1225                 break;
1226         case NOP:
1227                 break;
1228         default:
1229                 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1230                         if (cmd == NULL) {
1231                                 do_abort(ms);
1232                                 ms->msgphase = msg_out;
1233                         } else if (code != cmd->device->lun + IDENTIFY_BASE) {
1234                                 printk(KERN_WARNING "mesh: lun mismatch "
1235                                        "(%d != %d) on reselection from "
1236                                        "target %d\n", code - IDENTIFY_BASE,
1237                                        cmd->device->lun, ms->conn_tgt);
1238                         }
1239                         break;
1240                 }
1241                 goto reject;
1242         }
1243         return;
1244
1245  reject:
1246         printk(KERN_WARNING "mesh: rejecting message from target %d:",
1247                ms->conn_tgt);
1248         for (i = 0; i < ms->n_msgin; ++i)
1249                 printk(" %x", ms->msgin[i]);
1250         printk("\n");
1251         ms->msgout[0] = MESSAGE_REJECT;
1252         ms->n_msgout = 1;
1253         ms->msgphase = msg_out;
1254 }
1255
1256 /*
1257  * Set up DMA commands for transferring data.
1258  */
1259 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd)
1260 {
1261         int i, dma_cmd, total, off, dtot;
1262         struct scatterlist *scl;
1263         struct dbdma_cmd *dcmds;
1264
1265         dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1266                 OUTPUT_MORE: INPUT_MORE;
1267         dcmds = ms->dma_cmds;
1268         dtot = 0;
1269         if (cmd) {
1270                 int nseg;
1271
1272                 cmd->SCp.this_residual = scsi_bufflen(cmd);
1273
1274                 nseg = scsi_dma_map(cmd);
1275                 BUG_ON(nseg < 0);
1276
1277                 if (nseg) {
1278                         total = 0;
1279                         off = ms->data_ptr;
1280
1281                         scsi_for_each_sg(cmd, scl, nseg, i) {
1282                                 u32 dma_addr = sg_dma_address(scl);
1283                                 u32 dma_len = sg_dma_len(scl);
1284
1285                                 total += scl->length;
1286                                 if (off >= dma_len) {
1287                                         off -= dma_len;
1288                                         continue;
1289                                 }
1290                                 if (dma_len > 0xffff)
1291                                         panic("mesh: scatterlist element >= 64k");
1292                                 st_le16(&dcmds->req_count, dma_len - off);
1293                                 st_le16(&dcmds->command, dma_cmd);
1294                                 st_le32(&dcmds->phy_addr, dma_addr + off);
1295                                 dcmds->xfer_status = 0;
1296                                 ++dcmds;
1297                                 dtot += dma_len - off;
1298                                 off = 0;
1299                         }
1300                 }
1301         }
1302         if (dtot == 0) {
1303                 /* Either the target has overrun our buffer,
1304                    or the caller didn't provide a buffer. */
1305                 static char mesh_extra_buf[64];
1306
1307                 dtot = sizeof(mesh_extra_buf);
1308                 st_le16(&dcmds->req_count, dtot);
1309                 st_le32(&dcmds->phy_addr, virt_to_phys(mesh_extra_buf));
1310                 dcmds->xfer_status = 0;
1311                 ++dcmds;
1312         }
1313         dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1314         st_le16(&dcmds[-1].command, dma_cmd);
1315         memset(dcmds, 0, sizeof(*dcmds));
1316         st_le16(&dcmds->command, DBDMA_STOP);
1317         ms->dma_count = dtot;
1318 }
1319
1320 static void halt_dma(struct mesh_state *ms)
1321 {
1322         volatile struct dbdma_regs __iomem *md = ms->dma;
1323         volatile struct mesh_regs __iomem *mr = ms->mesh;
1324         struct scsi_cmnd *cmd = ms->current_req;
1325         int t, nb;
1326
1327         if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1328                 /* wait a little while until the fifo drains */
1329                 t = 50;
1330                 while (t > 0 && in_8(&mr->fifo_count) != 0
1331                        && (in_le32(&md->status) & ACTIVE) != 0) {
1332                         --t;
1333                         udelay(1);
1334                 }
1335         }
1336         out_le32(&md->control, RUN << 16);      /* turn off RUN bit */
1337         nb = (mr->count_hi << 8) + mr->count_lo;
1338         dlog(ms, "halt_dma fc/count=%.6x",
1339              MKWORD(0, mr->fifo_count, 0, nb));
1340         if (ms->tgts[ms->conn_tgt].data_goes_out)
1341                 nb += mr->fifo_count;
1342         /* nb is the number of bytes not yet transferred
1343            to/from the target. */
1344         ms->data_ptr -= nb;
1345         dlog(ms, "data_ptr %x", ms->data_ptr);
1346         if (ms->data_ptr < 0) {
1347                 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1348                        ms->data_ptr, nb, ms);
1349                 ms->data_ptr = 0;
1350 #ifdef MESH_DBG
1351                 dumplog(ms, ms->conn_tgt);
1352                 dumpslog(ms);
1353 #endif /* MESH_DBG */
1354         } else if (cmd && scsi_bufflen(cmd) &&
1355                    ms->data_ptr > scsi_bufflen(cmd)) {
1356                 printk(KERN_DEBUG "mesh: target %d overrun, "
1357                        "data_ptr=%x total=%x goes_out=%d\n",
1358                        ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd),
1359                        ms->tgts[ms->conn_tgt].data_goes_out);
1360         }
1361         scsi_dma_unmap(cmd);
1362         ms->dma_started = 0;
1363 }
1364
1365 static void phase_mismatch(struct mesh_state *ms)
1366 {
1367         volatile struct mesh_regs __iomem *mr = ms->mesh;
1368         int phase;
1369
1370         dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1371              MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1372         phase = in_8(&mr->bus_status0) & BS0_PHASE;
1373         if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1374                 /* output the last byte of the message, without ATN */
1375                 out_8(&mr->count_lo, 1);
1376                 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1377                 mesh_flush_io(mr);
1378                 udelay(1);
1379                 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1380                 ms->msgphase = msg_out_last;
1381                 return;
1382         }
1383
1384         if (ms->msgphase == msg_in) {
1385                 get_msgin(ms);
1386                 if (ms->n_msgin)
1387                         handle_msgin(ms);
1388         }
1389
1390         if (ms->dma_started)
1391                 halt_dma(ms);
1392         if (mr->fifo_count) {
1393                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1394                 mesh_flush_io(mr);
1395                 udelay(1);
1396         }
1397
1398         ms->msgphase = msg_none;
1399         switch (phase) {
1400         case BP_DATAIN:
1401                 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1402                 ms->phase = dataing;
1403                 break;
1404         case BP_DATAOUT:
1405                 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1406                 ms->phase = dataing;
1407                 break;
1408         case BP_COMMAND:
1409                 ms->phase = commanding;
1410                 break;
1411         case BP_STATUS:
1412                 ms->phase = statusing;
1413                 break;
1414         case BP_MSGIN:
1415                 ms->msgphase = msg_in;
1416                 ms->n_msgin = 0;
1417                 break;
1418         case BP_MSGOUT:
1419                 ms->msgphase = msg_out;
1420                 if (ms->n_msgout == 0) {
1421                         if (ms->aborting) {
1422                                 do_abort(ms);
1423                         } else {
1424                                 if (ms->last_n_msgout == 0) {
1425                                         printk(KERN_DEBUG
1426                                                "mesh: no msg to repeat\n");
1427                                         ms->msgout[0] = NOP;
1428                                         ms->last_n_msgout = 1;
1429                                 }
1430                                 ms->n_msgout = ms->last_n_msgout;
1431                         }
1432                 }
1433                 break;
1434         default:
1435                 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1436                 ms->stat = DID_ERROR;
1437                 mesh_done(ms, 1);
1438                 return;
1439         }
1440
1441         start_phase(ms);
1442 }
1443
1444 static void cmd_complete(struct mesh_state *ms)
1445 {
1446         volatile struct mesh_regs __iomem *mr = ms->mesh;
1447         struct scsi_cmnd *cmd = ms->current_req;
1448         struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1449         int seq, n, t;
1450
1451         dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1452         seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
1453         switch (ms->msgphase) {
1454         case msg_out_xxx:
1455                 /* huh?  we expected a phase mismatch */
1456                 ms->n_msgin = 0;
1457                 ms->msgphase = msg_in;
1458                 /* fall through */
1459
1460         case msg_in:
1461                 /* should have some message bytes in fifo */
1462                 get_msgin(ms);
1463                 n = msgin_length(ms);
1464                 if (ms->n_msgin < n) {
1465                         out_8(&mr->count_lo, n - ms->n_msgin);
1466                         out_8(&mr->sequence, SEQ_MSGIN + seq);
1467                 } else {
1468                         ms->msgphase = msg_none;
1469                         handle_msgin(ms);
1470                         start_phase(ms);
1471                 }
1472                 break;
1473
1474         case msg_in_bad:
1475                 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1476                 mesh_flush_io(mr);
1477                 udelay(1);
1478                 out_8(&mr->count_lo, 1);
1479                 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1480                 break;
1481
1482         case msg_out:
1483                 /*
1484                  * To get the right timing on ATN wrt ACK, we have
1485                  * to get the MESH to drop ACK, wait until REQ gets
1486                  * asserted, then drop ATN.  To do this we first
1487                  * issue a SEQ_MSGOUT with ATN and wait for REQ,
1488                  * then change the command to a SEQ_MSGOUT w/o ATN.
1489                  * If we don't see REQ in a reasonable time, we
1490                  * change the command to SEQ_MSGIN with ATN,
1491                  * wait for the phase mismatch interrupt, then
1492                  * issue the SEQ_MSGOUT without ATN.
1493                  */
1494                 out_8(&mr->count_lo, 1);
1495                 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1496                 t = 30;         /* wait up to 30us */
1497                 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1498                         udelay(1);
1499                 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1500                      MKWORD(mr->error, mr->exception,
1501                             mr->fifo_count, mr->count_lo));
1502                 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1503                         /* whoops, target didn't do what we expected */
1504                         ms->last_n_msgout = ms->n_msgout;
1505                         ms->n_msgout = 0;
1506                         if (in_8(&mr->interrupt) & INT_ERROR) {
1507                                 printk(KERN_ERR "mesh: error %x in msg_out\n",
1508                                        in_8(&mr->error));
1509                                 handle_error(ms);
1510                                 return;
1511                         }
1512                         if (in_8(&mr->exception) != EXC_PHASEMM)
1513                                 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1514                                        in_8(&mr->exception));
1515                         else
1516                                 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1517                                        in_8(&mr->bus_status0));
1518                         handle_exception(ms);
1519                         return;
1520                 }
1521                 if (in_8(&mr->bus_status0) & BS0_REQ) {
1522                         out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1523                         mesh_flush_io(mr);
1524                         udelay(1);
1525                         out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1526                         ms->msgphase = msg_out_last;
1527                 } else {
1528                         out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1529                         ms->msgphase = msg_out_xxx;
1530                 }
1531                 break;
1532
1533         case msg_out_last:
1534                 ms->last_n_msgout = ms->n_msgout;
1535                 ms->n_msgout = 0;
1536                 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1537                 start_phase(ms);
1538                 break;
1539
1540         case msg_none:
1541                 switch (ms->phase) {
1542                 case idle:
1543                         printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1544                         dumpslog(ms);
1545                         return;
1546                 case selecting:
1547                         dlog(ms, "Selecting phase at command completion",0);
1548                         ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1549                                                  (cmd? cmd->device->lun: 0));
1550                         ms->n_msgout = 1;
1551                         ms->expect_reply = 0;
1552                         if (ms->aborting) {
1553                                 ms->msgout[0] = ABORT;
1554                                 ms->n_msgout++;
1555                         } else if (tp->sdtr_state == do_sdtr) {
1556                                 /* add SDTR message */
1557                                 add_sdtr_msg(ms);
1558                                 ms->expect_reply = 1;
1559                                 tp->sdtr_state = sdtr_sent;
1560                         }
1561                         ms->msgphase = msg_out;
1562                         /*
1563                          * We need to wait for REQ before dropping ATN.
1564                          * We wait for at most 30us, then fall back to
1565                          * a scheme where we issue a SEQ_COMMAND with ATN,
1566                          * which will give us a phase mismatch interrupt
1567                          * when REQ does come, and then we send the message.
1568                          */
1569                         t = 230;                /* wait up to 230us */
1570                         while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1571                                 if (--t < 0) {
1572                                         dlog(ms, "impatient for req", ms->n_msgout);
1573                                         ms->msgphase = msg_none;
1574                                         break;
1575                                 }
1576                                 udelay(1);
1577                         }
1578                         break;
1579                 case dataing:
1580                         if (ms->dma_count != 0) {
1581                                 start_phase(ms);
1582                                 return;
1583                         }
1584                         /*
1585                          * We can get a phase mismatch here if the target
1586                          * changes to the status phase, even though we have
1587                          * had a command complete interrupt.  Then, if we
1588                          * issue the SEQ_STATUS command, we'll get a sequence
1589                          * error interrupt.  Which isn't so bad except that
1590                          * occasionally the mesh actually executes the
1591                          * SEQ_STATUS *as well as* giving us the sequence
1592                          * error and phase mismatch exception.
1593                          */
1594                         out_8(&mr->sequence, 0);
1595                         out_8(&mr->interrupt,
1596                               INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1597                         halt_dma(ms);
1598                         break;
1599                 case statusing:
1600                         if (cmd) {
1601                                 cmd->SCp.Status = mr->fifo;
1602                                 if (DEBUG_TARGET(cmd))
1603                                         printk(KERN_DEBUG "mesh: status is %x\n",
1604                                                cmd->SCp.Status);
1605                         }
1606                         ms->msgphase = msg_in;
1607                         break;
1608                 case busfreeing:
1609                         mesh_done(ms, 1);
1610                         return;
1611                 case disconnecting:
1612                         ms->current_req = NULL;
1613                         ms->phase = idle;
1614                         mesh_start(ms);
1615                         return;
1616                 default:
1617                         break;
1618                 }
1619                 ++ms->phase;
1620                 start_phase(ms);
1621                 break;
1622         }
1623 }
1624
1625
1626 /*
1627  * Called by midlayer with host locked to queue a new
1628  * request
1629  */
1630 static int mesh_queue_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
1631 {
1632         struct mesh_state *ms;
1633
1634         cmd->scsi_done = done;
1635         cmd->host_scribble = NULL;
1636
1637         ms = (struct mesh_state *) cmd->device->host->hostdata;
1638
1639         if (ms->request_q == NULL)
1640                 ms->request_q = cmd;
1641         else
1642                 ms->request_qtail->host_scribble = (void *) cmd;
1643         ms->request_qtail = cmd;
1644
1645         if (ms->phase == idle)
1646                 mesh_start(ms);
1647
1648         return 0;
1649 }
1650
1651 static DEF_SCSI_QCMD(mesh_queue)
1652
1653 /*
1654  * Called to handle interrupts, either call by the interrupt
1655  * handler (do_mesh_interrupt) or by other functions in
1656  * exceptional circumstances
1657  */
1658 static void mesh_interrupt(struct mesh_state *ms)
1659 {
1660         volatile struct mesh_regs __iomem *mr = ms->mesh;
1661         int intr;
1662
1663 #if 0
1664         if (ALLOW_DEBUG(ms->conn_tgt))
1665                 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1666                        "phase=%d msgphase=%d\n", mr->bus_status0,
1667                        mr->interrupt, mr->exception, mr->error,
1668                        ms->phase, ms->msgphase);
1669 #endif
1670         while ((intr = in_8(&mr->interrupt)) != 0) {
1671                 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1672                      MKWORD(intr, mr->error, mr->exception, mr->sequence));
1673                 if (intr & INT_ERROR) {
1674                         handle_error(ms);
1675                 } else if (intr & INT_EXCEPTION) {
1676                         handle_exception(ms);
1677                 } else if (intr & INT_CMDDONE) {
1678                         out_8(&mr->interrupt, INT_CMDDONE);
1679                         cmd_complete(ms);
1680                 }
1681         }
1682 }
1683
1684 /* Todo: here we can at least try to remove the command from the
1685  * queue if it isn't connected yet, and for pending command, assert
1686  * ATN until the bus gets freed.
1687  */
1688 static int mesh_abort(struct scsi_cmnd *cmd)
1689 {
1690         struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1691
1692         printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
1693         mesh_dump_regs(ms);
1694         dumplog(ms, cmd->device->id);
1695         dumpslog(ms);
1696         return FAILED;
1697 }
1698
1699 /*
1700  * Called by the midlayer with the lock held to reset the
1701  * SCSI host and bus.
1702  * The midlayer will wait for devices to come back, we don't need
1703  * to do that ourselves
1704  */
1705 static int mesh_host_reset(struct scsi_cmnd *cmd)
1706 {
1707         struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata;
1708         volatile struct mesh_regs __iomem *mr = ms->mesh;
1709         volatile struct dbdma_regs __iomem *md = ms->dma;
1710         unsigned long flags;
1711
1712         printk(KERN_DEBUG "mesh_host_reset\n");
1713
1714         spin_lock_irqsave(ms->host->host_lock, flags);
1715
1716         /* Reset the controller & dbdma channel */
1717         out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16);   /* stop dma */
1718         out_8(&mr->exception, 0xff);    /* clear all exception bits */
1719         out_8(&mr->error, 0xff);        /* clear all error bits */
1720         out_8(&mr->sequence, SEQ_RESETMESH);
1721         mesh_flush_io(mr);
1722         udelay(1);
1723         out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1724         out_8(&mr->source_id, ms->host->this_id);
1725         out_8(&mr->sel_timeout, 25);    /* 250ms */
1726         out_8(&mr->sync_params, ASYNC_PARAMS);
1727
1728         /* Reset the bus */
1729         out_8(&mr->bus_status1, BS1_RST);       /* assert RST */
1730         mesh_flush_io(mr);
1731         udelay(30);                     /* leave it on for >= 25us */
1732         out_8(&mr->bus_status1, 0);     /* negate RST */
1733
1734         /* Complete pending commands */
1735         handle_reset(ms);
1736
1737         spin_unlock_irqrestore(ms->host->host_lock, flags);
1738         return SUCCESS;
1739 }
1740
1741 static void set_mesh_power(struct mesh_state *ms, int state)
1742 {
1743         if (!machine_is(powermac))
1744                 return;
1745         if (state) {
1746                 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1);
1747                 msleep(200);
1748         } else {
1749                 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0);
1750                 msleep(10);
1751         }
1752 }
1753
1754
1755 #ifdef CONFIG_PM
1756 static int mesh_suspend(struct macio_dev *mdev, pm_message_t mesg)
1757 {
1758         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1759         unsigned long flags;
1760
1761         switch (mesg.event) {
1762         case PM_EVENT_SUSPEND:
1763         case PM_EVENT_HIBERNATE:
1764         case PM_EVENT_FREEZE:
1765                 break;
1766         default:
1767                 return 0;
1768         }
1769         if (ms->phase == sleeping)
1770                 return 0;
1771
1772         scsi_block_requests(ms->host);
1773         spin_lock_irqsave(ms->host->host_lock, flags);
1774         while(ms->phase != idle) {
1775                 spin_unlock_irqrestore(ms->host->host_lock, flags);
1776                 msleep(10);
1777                 spin_lock_irqsave(ms->host->host_lock, flags);
1778         }
1779         ms->phase = sleeping;
1780         spin_unlock_irqrestore(ms->host->host_lock, flags);
1781         disable_irq(ms->meshintr);
1782         set_mesh_power(ms, 0);
1783
1784         return 0;
1785 }
1786
1787 static int mesh_resume(struct macio_dev *mdev)
1788 {
1789         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1790         unsigned long flags;
1791
1792         if (ms->phase != sleeping)
1793                 return 0;
1794
1795         set_mesh_power(ms, 1);
1796         mesh_init(ms);
1797         spin_lock_irqsave(ms->host->host_lock, flags);
1798         mesh_start(ms);
1799         spin_unlock_irqrestore(ms->host->host_lock, flags);
1800         enable_irq(ms->meshintr);
1801         scsi_unblock_requests(ms->host);
1802
1803         return 0;
1804 }
1805
1806 #endif /* CONFIG_PM */
1807
1808 /*
1809  * If we leave drives set for synchronous transfers (especially
1810  * CDROMs), and reboot to MacOS, it gets confused, poor thing.
1811  * So, on reboot we reset the SCSI bus.
1812  */
1813 static int mesh_shutdown(struct macio_dev *mdev)
1814 {
1815         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1816         volatile struct mesh_regs __iomem *mr;
1817         unsigned long flags;
1818
1819         printk(KERN_INFO "resetting MESH scsi bus(es)\n");
1820         spin_lock_irqsave(ms->host->host_lock, flags);
1821         mr = ms->mesh;
1822         out_8(&mr->intr_mask, 0);
1823         out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1824         out_8(&mr->bus_status1, BS1_RST);
1825         mesh_flush_io(mr);
1826         udelay(30);
1827         out_8(&mr->bus_status1, 0);
1828         spin_unlock_irqrestore(ms->host->host_lock, flags);
1829
1830         return 0;
1831 }
1832
1833 static struct scsi_host_template mesh_template = {
1834         .proc_name                      = "mesh",
1835         .name                           = "MESH",
1836         .queuecommand                   = mesh_queue,
1837         .eh_abort_handler               = mesh_abort,
1838         .eh_host_reset_handler          = mesh_host_reset,
1839         .can_queue                      = 20,
1840         .this_id                        = 7,
1841         .sg_tablesize                   = SG_ALL,
1842         .cmd_per_lun                    = 2,
1843         .use_clustering                 = DISABLE_CLUSTERING,
1844 };
1845
1846 static int mesh_probe(struct macio_dev *mdev, const struct of_device_id *match)
1847 {
1848         struct device_node *mesh = macio_get_of_node(mdev);
1849         struct pci_dev* pdev = macio_get_pci_dev(mdev);
1850         int tgt, minper;
1851         const int *cfp;
1852         struct mesh_state *ms;
1853         struct Scsi_Host *mesh_host;
1854         void *dma_cmd_space;
1855         dma_addr_t dma_cmd_bus;
1856
1857         switch (mdev->bus->chip->type) {
1858         case macio_heathrow:
1859         case macio_gatwick:
1860         case macio_paddington:
1861                 use_active_neg = 0;
1862                 break;
1863         default:
1864                 use_active_neg = SEQ_ACTIVE_NEG;
1865         }
1866
1867         if (macio_resource_count(mdev) != 2 || macio_irq_count(mdev) != 2) {
1868                 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
1869                        " (got %d,%d)\n", macio_resource_count(mdev),
1870                        macio_irq_count(mdev));
1871                 return -ENODEV;
1872         }
1873
1874         if (macio_request_resources(mdev, "mesh") != 0) {
1875                 printk(KERN_ERR "mesh: unable to request memory resources");
1876                 return -EBUSY;
1877         }
1878         mesh_host = scsi_host_alloc(&mesh_template, sizeof(struct mesh_state));
1879         if (mesh_host == NULL) {
1880                 printk(KERN_ERR "mesh: couldn't register host");
1881                 goto out_release;
1882         }
1883
1884         /* Old junk for root discovery, that will die ultimately */
1885 #if !defined(MODULE)
1886         note_scsi_host(mesh, mesh_host);
1887 #endif
1888
1889         mesh_host->base = macio_resource_start(mdev, 0);
1890         mesh_host->irq = macio_irq(mdev, 0);
1891         ms = (struct mesh_state *) mesh_host->hostdata;
1892         macio_set_drvdata(mdev, ms);
1893         ms->host = mesh_host;
1894         ms->mdev = mdev;
1895         ms->pdev = pdev;
1896
1897         ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000);
1898         if (ms->mesh == NULL) {
1899                 printk(KERN_ERR "mesh: can't map registers\n");
1900                 goto out_free;
1901         }
1902         ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000);
1903         if (ms->dma == NULL) {
1904                 printk(KERN_ERR "mesh: can't map registers\n");
1905                 iounmap(ms->mesh);
1906                 goto out_free;
1907         }
1908
1909         ms->meshintr = macio_irq(mdev, 0);
1910         ms->dmaintr = macio_irq(mdev, 1);
1911
1912         /* Space for dma command list: +1 for stop command,
1913          * +1 to allow for aligning.
1914          */
1915         ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd);
1916
1917         /* We use the PCI APIs for now until the generic one gets fixed
1918          * enough or until we get some macio-specific versions
1919          */
1920         dma_cmd_space = pci_alloc_consistent(macio_get_pci_dev(mdev),
1921                                              ms->dma_cmd_size,
1922                                              &dma_cmd_bus);
1923         if (dma_cmd_space == NULL) {
1924                 printk(KERN_ERR "mesh: can't allocate DMA table\n");
1925                 goto out_unmap;
1926         }
1927         memset(dma_cmd_space, 0, ms->dma_cmd_size);
1928
1929         ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
1930         ms->dma_cmd_space = dma_cmd_space;
1931         ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds)
1932                 - (unsigned long)dma_cmd_space;
1933         ms->current_req = NULL;
1934         for (tgt = 0; tgt < 8; ++tgt) {
1935                 ms->tgts[tgt].sdtr_state = do_sdtr;
1936                 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1937                 ms->tgts[tgt].current_req = NULL;
1938         }
1939
1940         if ((cfp = of_get_property(mesh, "clock-frequency", NULL)))
1941                 ms->clk_freq = *cfp;
1942         else {
1943                 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
1944                 ms->clk_freq = 50000000;
1945         }
1946
1947         /* The maximum sync rate is clock / 5; increase
1948          * mesh_sync_period if necessary.
1949          */
1950         minper = 1000000000 / (ms->clk_freq / 5); /* ns */
1951         if (mesh_sync_period < minper)
1952                 mesh_sync_period = minper;
1953
1954         /* Power up the chip */
1955         set_mesh_power(ms, 1);
1956
1957         /* Set it up */
1958         mesh_init(ms);
1959
1960         /* Request interrupt */
1961         if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
1962                 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
1963                 goto out_shutdown;
1964         }
1965
1966         /* Add scsi host & scan */
1967         if (scsi_add_host(mesh_host, &mdev->ofdev.dev))
1968                 goto out_release_irq;
1969         scsi_scan_host(mesh_host);
1970
1971         return 0;
1972
1973  out_release_irq:
1974         free_irq(ms->meshintr, ms);
1975  out_shutdown:
1976         /* shutdown & reset bus in case of error or macos can be confused
1977          * at reboot if the bus was set to synchronous mode already
1978          */
1979         mesh_shutdown(mdev);
1980         set_mesh_power(ms, 0);
1981         pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size,
1982                             ms->dma_cmd_space, ms->dma_cmd_bus);
1983  out_unmap:
1984         iounmap(ms->dma);
1985         iounmap(ms->mesh);
1986  out_free:
1987         scsi_host_put(mesh_host);
1988  out_release:
1989         macio_release_resources(mdev);
1990
1991         return -ENODEV;
1992 }
1993
1994 static int mesh_remove(struct macio_dev *mdev)
1995 {
1996         struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev);
1997         struct Scsi_Host *mesh_host = ms->host;
1998
1999         scsi_remove_host(mesh_host);
2000
2001         free_irq(ms->meshintr, ms);
2002
2003         /* Reset scsi bus */
2004         mesh_shutdown(mdev);
2005
2006         /* Shut down chip & termination */
2007         set_mesh_power(ms, 0);
2008
2009         /* Unmap registers & dma controller */
2010         iounmap(ms->mesh);
2011         iounmap(ms->dma);
2012
2013         /* Free DMA commands memory */
2014         pci_free_consistent(macio_get_pci_dev(mdev), ms->dma_cmd_size,
2015                             ms->dma_cmd_space, ms->dma_cmd_bus);
2016
2017         /* Release memory resources */
2018         macio_release_resources(mdev);
2019
2020         scsi_host_put(mesh_host);
2021
2022         return 0;
2023 }
2024
2025
2026 static struct of_device_id mesh_match[] =
2027 {
2028         {
2029         .name           = "mesh",
2030         },
2031         {
2032         .type           = "scsi",
2033         .compatible     = "chrp,mesh0"
2034         },
2035         {},
2036 };
2037 MODULE_DEVICE_TABLE (of, mesh_match);
2038
2039 static struct macio_driver mesh_driver =
2040 {
2041         .driver = {
2042                 .name           = "mesh",
2043                 .owner          = THIS_MODULE,
2044                 .of_match_table = mesh_match,
2045         },
2046         .probe          = mesh_probe,
2047         .remove         = mesh_remove,
2048         .shutdown       = mesh_shutdown,
2049 #ifdef CONFIG_PM
2050         .suspend        = mesh_suspend,
2051         .resume         = mesh_resume,
2052 #endif
2053 };
2054
2055
2056 static int __init init_mesh(void)
2057 {
2058
2059         /* Calculate sync rate from module parameters */
2060         if (sync_rate > 10)
2061                 sync_rate = 10;
2062         if (sync_rate > 0) {
2063                 printk(KERN_INFO "mesh: configured for synchronous %d MB/s\n", sync_rate);
2064                 mesh_sync_period = 1000 / sync_rate;    /* ns */
2065                 mesh_sync_offset = 15;
2066         } else
2067                 printk(KERN_INFO "mesh: configured for asynchronous\n");
2068
2069         return macio_register_driver(&mesh_driver);
2070 }
2071
2072 static void __exit exit_mesh(void)
2073 {
2074         return macio_unregister_driver(&mesh_driver);
2075 }
2076
2077 module_init(init_mesh);
2078 module_exit(exit_mesh);