4e3a11b982999ac0e4702c434d645c1c0128e182
[linux-2.6.git] / drivers / scsi / lpfc / lpfc_hw4.h
1 /*******************************************************************
2  * This file is part of the Emulex Linux Device Driver for         *
3  * Fibre Channel Host Bus Adapters.                                *
4  * Copyright (C) 2009 Emulex.  All rights reserved.                *
5  * EMULEX and SLI are trademarks of Emulex.                        *
6  * www.emulex.com                                                  *
7  *                                                                 *
8  * This program is free software; you can redistribute it and/or   *
9  * modify it under the terms of version 2 of the GNU General       *
10  * Public License as published by the Free Software Foundation.    *
11  * This program is distributed in the hope that it will be useful. *
12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
17  * more details, a copy of which can be found in the file COPYING  *
18  * included with this package.                                     *
19  *******************************************************************/
20
21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
22  * associated with it (_SHIFT, _MASK, and _WORD).
23  * EG. For a bit field that is in the 7th bit of the "field4" field of a
24  * structure and is 2 bits in size the following #defines must exist:
25  *      struct temp {
26  *              uint32_t        field1;
27  *              uint32_t        field2;
28  *              uint32_t        field3;
29  *              uint32_t        field4;
30  *      #define example_bit_field_SHIFT         7
31  *      #define example_bit_field_MASK          0x03
32  *      #define example_bit_field_WORD          field4
33  *              uint32_t        field5;
34  *      };
35  * Then the macros below may be used to get or set the value of that field.
36  * EG. To get the value of the bit field from the above example:
37  *      struct temp t1;
38  *      value = bf_get(example_bit_field, &t1);
39  * And then to set that bit field:
40  *      bf_set(example_bit_field, &t1, 2);
41  * Or clear that bit field:
42  *      bf_set(example_bit_field, &t1, 0);
43  */
44 #define bf_get_le32(name, ptr) \
45         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
46 #define bf_get(name, ptr) \
47         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
48 #define bf_set_le32(name, ptr, value) \
49         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
50         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
51         ~(name##_MASK << name##_SHIFT)))))
52 #define bf_set(name, ptr, value) \
53         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
54                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
55
56 struct dma_address {
57         uint32_t addr_lo;
58         uint32_t addr_hi;
59 };
60
61 struct lpfc_sli_intf {
62         uint32_t word0;
63 #define lpfc_sli_intf_valid_SHIFT               29
64 #define lpfc_sli_intf_valid_MASK                0x00000007
65 #define lpfc_sli_intf_valid_WORD                word0
66 #define LPFC_SLI_INTF_VALID             6
67 #define lpfc_sli_intf_sli_hint2_SHIFT           24
68 #define lpfc_sli_intf_sli_hint2_MASK            0x0000001F
69 #define lpfc_sli_intf_sli_hint2_WORD            word0
70 #define LPFC_SLI_INTF_SLI_HINT2_NONE    0
71 #define lpfc_sli_intf_sli_hint1_SHIFT           16
72 #define lpfc_sli_intf_sli_hint1_MASK            0x000000FF
73 #define lpfc_sli_intf_sli_hint1_WORD            word0
74 #define LPFC_SLI_INTF_SLI_HINT1_NONE    0
75 #define LPFC_SLI_INTF_SLI_HINT1_1       1
76 #define LPFC_SLI_INTF_SLI_HINT1_2       2
77 #define lpfc_sli_intf_if_type_SHIFT             12
78 #define lpfc_sli_intf_if_type_MASK              0x0000000F
79 #define lpfc_sli_intf_if_type_WORD              word0
80 #define LPFC_SLI_INTF_IF_TYPE_0         0
81 #define LPFC_SLI_INTF_IF_TYPE_1         1
82 #define LPFC_SLI_INTF_IF_TYPE_2         2
83 #define lpfc_sli_intf_sli_family_SHIFT          8
84 #define lpfc_sli_intf_sli_family_MASK           0x0000000F
85 #define lpfc_sli_intf_sli_family_WORD           word0
86 #define LPFC_SLI_INTF_FAMILY_BE2        0x0
87 #define LPFC_SLI_INTF_FAMILY_BE3        0x1
88 #define LPFC_SLI_INTF_FAMILY_LNCR_A0    0xa
89 #define LPFC_SLI_INTF_FAMILY_LNCR_B0    0xb
90 #define lpfc_sli_intf_slirev_SHIFT              4
91 #define lpfc_sli_intf_slirev_MASK               0x0000000F
92 #define lpfc_sli_intf_slirev_WORD               word0
93 #define LPFC_SLI_INTF_REV_SLI3          3
94 #define LPFC_SLI_INTF_REV_SLI4          4
95 #define lpfc_sli_intf_func_type_SHIFT           0
96 #define lpfc_sli_intf_func_type_MASK            0x00000001
97 #define lpfc_sli_intf_func_type_WORD            word0
98 #define LPFC_SLI_INTF_IF_TYPE_PHYS      0
99 #define LPFC_SLI_INTF_IF_TYPE_VIRT      1
100 };
101
102 #define LPFC_SLI4_MBX_EMBED     true
103 #define LPFC_SLI4_MBX_NEMBED    false
104
105 #define LPFC_SLI4_MB_WORD_COUNT         64
106 #define LPFC_MAX_MQ_PAGE                8
107 #define LPFC_MAX_WQ_PAGE                8
108 #define LPFC_MAX_CQ_PAGE                4
109 #define LPFC_MAX_EQ_PAGE                8
110
111 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
112 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
113 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
114
115 /* Define SLI4 Alignment requirements. */
116 #define LPFC_ALIGN_16_BYTE      16
117 #define LPFC_ALIGN_64_BYTE      64
118
119 /* Define SLI4 specific definitions. */
120 #define LPFC_MQ_CQE_BYTE_OFFSET 256
121 #define LPFC_MBX_CMD_HDR_LENGTH 16
122 #define LPFC_MBX_ERROR_RANGE    0x4000
123 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
124 #define LPFC_BMBX_BIT1_ADDR_LO  0
125 #define LPFC_RPI_HDR_COUNT      64
126 #define LPFC_HDR_TEMPLATE_SIZE  4096
127 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
128 #define LPFC_FCF_RECORD_WD_CNT  132
129 #define LPFC_ENTIRE_FCF_DATABASE 0
130 #define LPFC_DFLT_FCF_INDEX      0
131
132 /* Virtual function numbers */
133 #define LPFC_VF0                0
134 #define LPFC_VF1                1
135 #define LPFC_VF2                2
136 #define LPFC_VF3                3
137 #define LPFC_VF4                4
138 #define LPFC_VF5                5
139 #define LPFC_VF6                6
140 #define LPFC_VF7                7
141 #define LPFC_VF8                8
142 #define LPFC_VF9                9
143 #define LPFC_VF10               10
144 #define LPFC_VF11               11
145 #define LPFC_VF12               12
146 #define LPFC_VF13               13
147 #define LPFC_VF14               14
148 #define LPFC_VF15               15
149 #define LPFC_VF16               16
150 #define LPFC_VF17               17
151 #define LPFC_VF18               18
152 #define LPFC_VF19               19
153 #define LPFC_VF20               20
154 #define LPFC_VF21               21
155 #define LPFC_VF22               22
156 #define LPFC_VF23               23
157 #define LPFC_VF24               24
158 #define LPFC_VF25               25
159 #define LPFC_VF26               26
160 #define LPFC_VF27               27
161 #define LPFC_VF28               28
162 #define LPFC_VF29               29
163 #define LPFC_VF30               30
164 #define LPFC_VF31               31
165
166 /* PCI function numbers */
167 #define LPFC_PCI_FUNC0          0
168 #define LPFC_PCI_FUNC1          1
169 #define LPFC_PCI_FUNC2          2
170 #define LPFC_PCI_FUNC3          3
171 #define LPFC_PCI_FUNC4          4
172
173 /* Active interrupt test count */
174 #define LPFC_ACT_INTR_CNT       4
175
176 /* Delay Multiplier constant */
177 #define LPFC_DMULT_CONST       651042
178 #define LPFC_MIM_IMAX          636
179 #define LPFC_FP_DEF_IMAX       10000
180 #define LPFC_SP_DEF_IMAX       10000
181
182 /* PORT_CAPABILITIES constants. */
183 #define LPFC_MAX_SUPPORTED_PAGES        8
184
185 struct ulp_bde64 {
186         union ULP_BDE_TUS {
187                 uint32_t w;
188                 struct {
189 #ifdef __BIG_ENDIAN_BITFIELD
190                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
191                                                    VALUE !! */
192                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
193 #else   /*  __LITTLE_ENDIAN_BITFIELD */
194                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
195                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
196                                                    VALUE !! */
197 #endif
198 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
199 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
200 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
201 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
202 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
203 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
204 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
205                 } f;
206         } tus;
207         uint32_t addrLow;
208         uint32_t addrHigh;
209 };
210
211 struct lpfc_sli4_flags {
212         uint32_t word0;
213 #define lpfc_fip_flag_SHIFT 0
214 #define lpfc_fip_flag_MASK 0x00000001
215 #define lpfc_fip_flag_WORD word0
216 };
217
218 struct sli4_bls_acc {
219         uint32_t word0_rsvd;      /* Word0 must be reserved */
220         uint32_t word1;
221 #define lpfc_abts_orig_SHIFT      0
222 #define lpfc_abts_orig_MASK       0x00000001
223 #define lpfc_abts_orig_WORD       word1
224 #define LPFC_ABTS_UNSOL_RSP       1
225 #define LPFC_ABTS_UNSOL_INT       0
226         uint32_t word2;
227 #define lpfc_abts_rxid_SHIFT      0
228 #define lpfc_abts_rxid_MASK       0x0000FFFF
229 #define lpfc_abts_rxid_WORD       word2
230 #define lpfc_abts_oxid_SHIFT      16
231 #define lpfc_abts_oxid_MASK       0x0000FFFF
232 #define lpfc_abts_oxid_WORD       word2
233         uint32_t word3;
234         uint32_t word4;
235         uint32_t word5_rsvd;    /* Word5 must be reserved */
236 };
237
238 /* event queue entry structure */
239 struct lpfc_eqe {
240         uint32_t word0;
241 #define lpfc_eqe_resource_id_SHIFT      16
242 #define lpfc_eqe_resource_id_MASK       0x000000FF
243 #define lpfc_eqe_resource_id_WORD       word0
244 #define lpfc_eqe_minor_code_SHIFT       4
245 #define lpfc_eqe_minor_code_MASK        0x00000FFF
246 #define lpfc_eqe_minor_code_WORD        word0
247 #define lpfc_eqe_major_code_SHIFT       1
248 #define lpfc_eqe_major_code_MASK        0x00000007
249 #define lpfc_eqe_major_code_WORD        word0
250 #define lpfc_eqe_valid_SHIFT            0
251 #define lpfc_eqe_valid_MASK             0x00000001
252 #define lpfc_eqe_valid_WORD             word0
253 };
254
255 /* completion queue entry structure (common fields for all cqe types) */
256 struct lpfc_cqe {
257         uint32_t reserved0;
258         uint32_t reserved1;
259         uint32_t reserved2;
260         uint32_t word3;
261 #define lpfc_cqe_valid_SHIFT            31
262 #define lpfc_cqe_valid_MASK             0x00000001
263 #define lpfc_cqe_valid_WORD             word3
264 #define lpfc_cqe_code_SHIFT             16
265 #define lpfc_cqe_code_MASK              0x000000FF
266 #define lpfc_cqe_code_WORD              word3
267 };
268
269 /* Completion Queue Entry Status Codes */
270 #define CQE_STATUS_SUCCESS              0x0
271 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
272 #define CQE_STATUS_REMOTE_STOP          0x2
273 #define CQE_STATUS_LOCAL_REJECT         0x3
274 #define CQE_STATUS_NPORT_RJT            0x4
275 #define CQE_STATUS_FABRIC_RJT           0x5
276 #define CQE_STATUS_NPORT_BSY            0x6
277 #define CQE_STATUS_FABRIC_BSY           0x7
278 #define CQE_STATUS_INTERMED_RSP         0x8
279 #define CQE_STATUS_LS_RJT               0x9
280 #define CQE_STATUS_CMD_REJECT           0xb
281 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
282 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
283
284 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
285 #define CQE_HW_STATUS_NO_ERR            0x0
286 #define CQE_HW_STATUS_UNDERRUN          0x1
287 #define CQE_HW_STATUS_OVERRUN           0x2
288
289 /* Completion Queue Entry Codes */
290 #define CQE_CODE_COMPL_WQE              0x1
291 #define CQE_CODE_RELEASE_WQE            0x2
292 #define CQE_CODE_RECEIVE                0x4
293 #define CQE_CODE_XRI_ABORTED            0x5
294
295 /* completion queue entry for wqe completions */
296 struct lpfc_wcqe_complete {
297         uint32_t word0;
298 #define lpfc_wcqe_c_request_tag_SHIFT   16
299 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
300 #define lpfc_wcqe_c_request_tag_WORD    word0
301 #define lpfc_wcqe_c_status_SHIFT        8
302 #define lpfc_wcqe_c_status_MASK         0x000000FF
303 #define lpfc_wcqe_c_status_WORD         word0
304 #define lpfc_wcqe_c_hw_status_SHIFT     0
305 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
306 #define lpfc_wcqe_c_hw_status_WORD      word0
307         uint32_t total_data_placed;
308         uint32_t parameter;
309         uint32_t word3;
310 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
311 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
312 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
313 #define lpfc_wcqe_c_xb_SHIFT            28
314 #define lpfc_wcqe_c_xb_MASK             0x00000001
315 #define lpfc_wcqe_c_xb_WORD             word3
316 #define lpfc_wcqe_c_pv_SHIFT            27
317 #define lpfc_wcqe_c_pv_MASK             0x00000001
318 #define lpfc_wcqe_c_pv_WORD             word3
319 #define lpfc_wcqe_c_priority_SHIFT      24
320 #define lpfc_wcqe_c_priority_MASK               0x00000007
321 #define lpfc_wcqe_c_priority_WORD               word3
322 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
323 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
324 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
325 };
326
327 /* completion queue entry for wqe release */
328 struct lpfc_wcqe_release {
329         uint32_t reserved0;
330         uint32_t reserved1;
331         uint32_t word2;
332 #define lpfc_wcqe_r_wq_id_SHIFT         16
333 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
334 #define lpfc_wcqe_r_wq_id_WORD          word2
335 #define lpfc_wcqe_r_wqe_index_SHIFT     0
336 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
337 #define lpfc_wcqe_r_wqe_index_WORD      word2
338         uint32_t word3;
339 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
340 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
341 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
342 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
343 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
344 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
345 };
346
347 struct sli4_wcqe_xri_aborted {
348         uint32_t word0;
349 #define lpfc_wcqe_xa_status_SHIFT               8
350 #define lpfc_wcqe_xa_status_MASK                0x000000FF
351 #define lpfc_wcqe_xa_status_WORD                word0
352         uint32_t parameter;
353         uint32_t word2;
354 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
355 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
356 #define lpfc_wcqe_xa_remote_xid_WORD    word2
357 #define lpfc_wcqe_xa_xri_SHIFT          0
358 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
359 #define lpfc_wcqe_xa_xri_WORD           word2
360         uint32_t word3;
361 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
362 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
363 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
364 #define lpfc_wcqe_xa_ia_SHIFT           30
365 #define lpfc_wcqe_xa_ia_MASK            0x00000001
366 #define lpfc_wcqe_xa_ia_WORD            word3
367 #define CQE_XRI_ABORTED_IA_REMOTE       0
368 #define CQE_XRI_ABORTED_IA_LOCAL        1
369 #define lpfc_wcqe_xa_br_SHIFT           29
370 #define lpfc_wcqe_xa_br_MASK            0x00000001
371 #define lpfc_wcqe_xa_br_WORD            word3
372 #define CQE_XRI_ABORTED_BR_BA_ACC       0
373 #define CQE_XRI_ABORTED_BR_BA_RJT       1
374 #define lpfc_wcqe_xa_eo_SHIFT           28
375 #define lpfc_wcqe_xa_eo_MASK            0x00000001
376 #define lpfc_wcqe_xa_eo_WORD            word3
377 #define CQE_XRI_ABORTED_EO_REMOTE       0
378 #define CQE_XRI_ABORTED_EO_LOCAL        1
379 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
380 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
381 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
382 };
383
384 /* completion queue entry structure for rqe completion */
385 struct lpfc_rcqe {
386         uint32_t word0;
387 #define lpfc_rcqe_bindex_SHIFT          16
388 #define lpfc_rcqe_bindex_MASK           0x0000FFF
389 #define lpfc_rcqe_bindex_WORD           word0
390 #define lpfc_rcqe_status_SHIFT          8
391 #define lpfc_rcqe_status_MASK           0x000000FF
392 #define lpfc_rcqe_status_WORD           word0
393 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
394 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
395 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
396 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
397         uint32_t reserved1;
398         uint32_t word2;
399 #define lpfc_rcqe_length_SHIFT          16
400 #define lpfc_rcqe_length_MASK           0x0000FFFF
401 #define lpfc_rcqe_length_WORD           word2
402 #define lpfc_rcqe_rq_id_SHIFT           6
403 #define lpfc_rcqe_rq_id_MASK            0x000003FF
404 #define lpfc_rcqe_rq_id_WORD            word2
405 #define lpfc_rcqe_fcf_id_SHIFT          0
406 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
407 #define lpfc_rcqe_fcf_id_WORD           word2
408         uint32_t word3;
409 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
410 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
411 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
412 #define lpfc_rcqe_port_SHIFT            30
413 #define lpfc_rcqe_port_MASK             0x00000001
414 #define lpfc_rcqe_port_WORD             word3
415 #define lpfc_rcqe_hdr_length_SHIFT      24
416 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
417 #define lpfc_rcqe_hdr_length_WORD       word3
418 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
419 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
420 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
421 #define lpfc_rcqe_eof_SHIFT             8
422 #define lpfc_rcqe_eof_MASK              0x000000FF
423 #define lpfc_rcqe_eof_WORD              word3
424 #define FCOE_EOFn       0x41
425 #define FCOE_EOFt       0x42
426 #define FCOE_EOFni      0x49
427 #define FCOE_EOFa       0x50
428 #define lpfc_rcqe_sof_SHIFT             0
429 #define lpfc_rcqe_sof_MASK              0x000000FF
430 #define lpfc_rcqe_sof_WORD              word3
431 #define FCOE_SOFi2      0x2d
432 #define FCOE_SOFi3      0x2e
433 #define FCOE_SOFn2      0x35
434 #define FCOE_SOFn3      0x36
435 };
436
437 struct lpfc_rqe {
438         uint32_t address_hi;
439         uint32_t address_lo;
440 };
441
442 /* buffer descriptors */
443 struct lpfc_bde4 {
444         uint32_t addr_hi;
445         uint32_t addr_lo;
446         uint32_t word2;
447 #define lpfc_bde4_last_SHIFT            31
448 #define lpfc_bde4_last_MASK             0x00000001
449 #define lpfc_bde4_last_WORD             word2
450 #define lpfc_bde4_sge_offset_SHIFT      0
451 #define lpfc_bde4_sge_offset_MASK       0x000003FF
452 #define lpfc_bde4_sge_offset_WORD       word2
453         uint32_t word3;
454 #define lpfc_bde4_length_SHIFT          0
455 #define lpfc_bde4_length_MASK           0x000000FF
456 #define lpfc_bde4_length_WORD           word3
457 };
458
459 struct lpfc_register {
460         uint32_t word0;
461 };
462
463 /* The SLI4 INTF register offset is common to all if_type values. */
464 #define LPFC_SLI_INTF                   0x0058
465
466 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
467 #define LPFC_UERR_STATUS_HI             0x00A4
468 #define LPFC_UERR_STATUS_LO             0x00A0
469 #define LPFC_UE_MASK_HI                 0x00AC
470 #define LPFC_UE_MASK_LO                 0x00A8
471
472 #define LPFC_HST_STATE                  0x00AC
473 #define lpfc_hst_state_perr_SHIFT       31
474 #define lpfc_hst_state_perr_MASK        0x1
475 #define lpfc_hst_state_perr_WORD        word0
476 #define lpfc_hst_state_sfi_SHIFT        30
477 #define lpfc_hst_state_sfi_MASK         0x1
478 #define lpfc_hst_state_sfi_WORD         word0
479 #define lpfc_hst_state_nip_SHIFT        29
480 #define lpfc_hst_state_nip_MASK         0x1
481 #define lpfc_hst_state_nip_WORD         word0
482 #define lpfc_hst_state_ipc_SHIFT        28
483 #define lpfc_hst_state_ipc_MASK         0x1
484 #define lpfc_hst_state_ipc_WORD         word0
485 #define lpfc_hst_state_xrom_SHIFT       27
486 #define lpfc_hst_state_xrom_MASK        0x1
487 #define lpfc_hst_state_xrom_WORD        word0
488 #define lpfc_hst_state_dl_SHIFT         26
489 #define lpfc_hst_state_dl_MASK          0x1
490 #define lpfc_hst_state_dl_WORD          word0
491 #define lpfc_hst_state_port_status_SHIFT        0
492 #define lpfc_hst_state_port_status_MASK         0xFFFF
493 #define lpfc_hst_state_port_status_WORD         word0
494
495 /*
496  * The following Port Status Values apply to SLI4, if_type 0 and 2
497  * UCNAs.
498  */
499 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
500 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
501 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
502 #define LPFC_POST_STAGE_BE_RESET                        0x0003
503 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
504 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
505 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
506 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
507 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
508 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
509 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
510 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
511 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
512 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
513 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
514 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
515 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
516 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
517 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
518 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
519 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
520 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
521 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
522 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
523 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
524 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
525 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
526 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
527 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
528 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
529 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
530 #define LPFC_POST_STAGE_ARMFW_READY                     0xC000
531 #define LPFC_POST_STAGE_ARMFW_UE                        0xF000
532
533
534 /* The following BAR0 register sets are defined for if_type 2 UCNAs. */
535 #define LPFC_SLIPORT_SEMAPHORE          0x0400
536 #define lpfc_sliport_smphr_perr_SHIFT   31
537 #define lpfc_sliport_smphr_perr_MASK    0x1
538 #define lpfc_sliport_smphr_perr_WORD    word0
539 #define lpfc_sliport_smphr_sfi_SHIFT    30
540 #define lpfc_sliport_smphr_sfi_MASK     0x1
541 #define lpfc_sliport_smphr_sfi_WORD     word0
542 #define lpfc_sliport_smphr_nip_SHIFT    29
543 #define lpfc_sliport_smphr_nip_MASK     0x1
544 #define lpfc_sliport_smphr_nip_WORD     word0
545 #define lpfc_sliport_smphr_ipc_SHIFT    28
546 #define lpfc_sliport_smphr_ipc_MASK     0x1
547 #define lpfc_sliport_smphr_ipc_WORD     word0
548 #define lpfc_sliport_smphr_scr1_SHIFT   27
549 #define lpfc_sliport_smphr_scr1_MASK    0x1
550 #define lpfc_sliport_smphr_scr1_WORD    word0
551 #define lpfc_sliport_smphr_scr2_SHIFT   26
552 #define lpfc_sliport_smphr_scr2_MASK    0x1
553 #define lpfc_sliport_smphr_scr2_WORD    word0
554 #define lpfc_sliport_smphr_host_scratch_SHIFT   16
555 #define lpfc_sliport_smphr_host_scratch_MASK    0xFF
556 #define lpfc_sliport_smphr_host_scratch_WORD    word0
557 #define lpfc_sliport_smphr_port_status_SHIFT    0
558 #define lpfc_sliport_smphr_port_status_MASK     0xFFFF
559 #define lpfc_sliport_smphr_port_status_WORD     word0
560
561 #define LPFC_SLIPORT_STATUS             0x0404
562 #define lpfc_sliport_status_err_SHIFT   31
563 #define lpfc_sliport_status_err_MASK    0x1
564 #define lpfc_sliport_status_err_WORD    word0
565 #define lpfc_sliport_status_end_SHIFT   30
566 #define lpfc_sliport_status_end_MASK    0x1
567 #define lpfc_sliport_status_end_WORD    word0
568 #define lpfc_sliport_status_oti_SHIFT   29
569 #define lpfc_sliport_status_oti_MASK    0x1
570 #define lpfc_sliport_status_oti_WORD    word0
571 #define lpfc_sliport_status_rn_SHIFT    24
572 #define lpfc_sliport_status_rn_MASK     0x1
573 #define lpfc_sliport_status_rn_WORD     word0
574 #define lpfc_sliport_status_rdy_SHIFT   23
575 #define lpfc_sliport_status_rdy_MASK    0x1
576 #define lpfc_sliport_status_rdy_WORD    word0
577
578 #define LPFC_SLIPORT_CONTROL            0x0408
579 #define lpfc_sliport_ctrl_end_SHIFT     30
580 #define lpfc_sliport_ctrl_end_MASK      0x1
581 #define lpfc_sliport_ctrl_end_WORD      word0
582 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
583 #define LPFC_SLIPORT_BIG_ENDIAN    1
584 #define lpfc_sliport_ctrl_ip_SHIFT      27
585 #define lpfc_sliport_ctrl_ip_MASK       0x1
586 #define lpfc_sliport_ctrl_ip_WORD       word0
587
588 #define LPFC_SLIPORT_ERROR_1            0x040C
589 #define LPFC_SLIPORT_ERROR_2            0x0410
590
591 /* BAR1 Registers */
592 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
593 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
594
595 #define LPFC_HST_ISR0           0x0C18
596 #define LPFC_HST_ISR1           0x0C1C
597 #define LPFC_HST_ISR2           0x0C20
598 #define LPFC_HST_ISR3           0x0C24
599 #define LPFC_HST_ISR4           0x0C28
600
601 #define LPFC_HST_IMR0           0x0C48
602 #define LPFC_HST_IMR1           0x0C4C
603 #define LPFC_HST_IMR2           0x0C50
604 #define LPFC_HST_IMR3           0x0C54
605 #define LPFC_HST_IMR4           0x0C58
606
607 #define LPFC_HST_ISCR0          0x0C78
608 #define LPFC_HST_ISCR1          0x0C7C
609 #define LPFC_HST_ISCR2          0x0C80
610 #define LPFC_HST_ISCR3          0x0C84
611 #define LPFC_HST_ISCR4          0x0C88
612
613 #define LPFC_SLI4_INTR0                 BIT0
614 #define LPFC_SLI4_INTR1                 BIT1
615 #define LPFC_SLI4_INTR2                 BIT2
616 #define LPFC_SLI4_INTR3                 BIT3
617 #define LPFC_SLI4_INTR4                 BIT4
618 #define LPFC_SLI4_INTR5                 BIT5
619 #define LPFC_SLI4_INTR6                 BIT6
620 #define LPFC_SLI4_INTR7                 BIT7
621 #define LPFC_SLI4_INTR8                 BIT8
622 #define LPFC_SLI4_INTR9                 BIT9
623 #define LPFC_SLI4_INTR10                BIT10
624 #define LPFC_SLI4_INTR11                BIT11
625 #define LPFC_SLI4_INTR12                BIT12
626 #define LPFC_SLI4_INTR13                BIT13
627 #define LPFC_SLI4_INTR14                BIT14
628 #define LPFC_SLI4_INTR15                BIT15
629 #define LPFC_SLI4_INTR16                BIT16
630 #define LPFC_SLI4_INTR17                BIT17
631 #define LPFC_SLI4_INTR18                BIT18
632 #define LPFC_SLI4_INTR19                BIT19
633 #define LPFC_SLI4_INTR20                BIT20
634 #define LPFC_SLI4_INTR21                BIT21
635 #define LPFC_SLI4_INTR22                BIT22
636 #define LPFC_SLI4_INTR23                BIT23
637 #define LPFC_SLI4_INTR24                BIT24
638 #define LPFC_SLI4_INTR25                BIT25
639 #define LPFC_SLI4_INTR26                BIT26
640 #define LPFC_SLI4_INTR27                BIT27
641 #define LPFC_SLI4_INTR28                BIT28
642 #define LPFC_SLI4_INTR29                BIT29
643 #define LPFC_SLI4_INTR30                BIT30
644 #define LPFC_SLI4_INTR31                BIT31
645
646 /*
647  * The Doorbell registers defined here exist in different BAR
648  * register sets depending on the UCNA Port's reported if_type
649  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
650  * BAR2.  For UCNA ports running SLI4 and if_type 2, they reside in
651  * BAR0.  The offsets are the same so the driver must account for
652  * any base address difference.
653  */
654 #define LPFC_RQ_DOORBELL                0x00A0
655 #define lpfc_rq_doorbell_num_posted_SHIFT       16
656 #define lpfc_rq_doorbell_num_posted_MASK        0x3FFF
657 #define lpfc_rq_doorbell_num_posted_WORD        word0
658 #define LPFC_RQ_POST_BATCH              8       /* RQEs to post at one time */
659 #define lpfc_rq_doorbell_id_SHIFT               0
660 #define lpfc_rq_doorbell_id_MASK                0xFFFF
661 #define lpfc_rq_doorbell_id_WORD                word0
662
663 #define LPFC_WQ_DOORBELL                0x0040
664 #define lpfc_wq_doorbell_num_posted_SHIFT       24
665 #define lpfc_wq_doorbell_num_posted_MASK        0x00FF
666 #define lpfc_wq_doorbell_num_posted_WORD        word0
667 #define lpfc_wq_doorbell_index_SHIFT            16
668 #define lpfc_wq_doorbell_index_MASK             0x00FF
669 #define lpfc_wq_doorbell_index_WORD             word0
670 #define lpfc_wq_doorbell_id_SHIFT               0
671 #define lpfc_wq_doorbell_id_MASK                0xFFFF
672 #define lpfc_wq_doorbell_id_WORD                word0
673
674 #define LPFC_EQCQ_DOORBELL              0x0120
675 #define lpfc_eqcq_doorbell_se_SHIFT             31
676 #define lpfc_eqcq_doorbell_se_MASK              0x0001
677 #define lpfc_eqcq_doorbell_se_WORD              word0
678 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF    0
679 #define LPFC_EQCQ_SOLICIT_ENABLE_ON     1
680 #define lpfc_eqcq_doorbell_arm_SHIFT            29
681 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
682 #define lpfc_eqcq_doorbell_arm_WORD             word0
683 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
684 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
685 #define lpfc_eqcq_doorbell_num_released_WORD    word0
686 #define lpfc_eqcq_doorbell_qt_SHIFT             10
687 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
688 #define lpfc_eqcq_doorbell_qt_WORD              word0
689 #define LPFC_QUEUE_TYPE_COMPLETION      0
690 #define LPFC_QUEUE_TYPE_EVENT           1
691 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
692 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
693 #define lpfc_eqcq_doorbell_eqci_WORD            word0
694 #define lpfc_eqcq_doorbell_cqid_SHIFT           0
695 #define lpfc_eqcq_doorbell_cqid_MASK            0x03FF
696 #define lpfc_eqcq_doorbell_cqid_WORD            word0
697 #define lpfc_eqcq_doorbell_eqid_SHIFT           0
698 #define lpfc_eqcq_doorbell_eqid_MASK            0x01FF
699 #define lpfc_eqcq_doorbell_eqid_WORD            word0
700
701 #define LPFC_BMBX                       0x0160
702 #define lpfc_bmbx_addr_SHIFT            2
703 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
704 #define lpfc_bmbx_addr_WORD             word0
705 #define lpfc_bmbx_hi_SHIFT              1
706 #define lpfc_bmbx_hi_MASK               0x0001
707 #define lpfc_bmbx_hi_WORD               word0
708 #define lpfc_bmbx_rdy_SHIFT             0
709 #define lpfc_bmbx_rdy_MASK              0x0001
710 #define lpfc_bmbx_rdy_WORD              word0
711
712 #define LPFC_MQ_DOORBELL                        0x0140
713 #define lpfc_mq_doorbell_num_posted_SHIFT       16
714 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
715 #define lpfc_mq_doorbell_num_posted_WORD        word0
716 #define lpfc_mq_doorbell_id_SHIFT               0
717 #define lpfc_mq_doorbell_id_MASK                0xFFFF
718 #define lpfc_mq_doorbell_id_WORD                word0
719
720 struct lpfc_sli4_cfg_mhdr {
721         uint32_t word1;
722 #define lpfc_mbox_hdr_emb_SHIFT         0
723 #define lpfc_mbox_hdr_emb_MASK          0x00000001
724 #define lpfc_mbox_hdr_emb_WORD          word1
725 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
726 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
727 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
728         uint32_t payload_length;
729         uint32_t tag_lo;
730         uint32_t tag_hi;
731         uint32_t reserved5;
732 };
733
734 union lpfc_sli4_cfg_shdr {
735         struct {
736                 uint32_t word6;
737 #define lpfc_mbox_hdr_opcode_SHIFT              0
738 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
739 #define lpfc_mbox_hdr_opcode_WORD               word6
740 #define lpfc_mbox_hdr_subsystem_SHIFT           8
741 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
742 #define lpfc_mbox_hdr_subsystem_WORD            word6
743 #define lpfc_mbox_hdr_port_number_SHIFT         16
744 #define lpfc_mbox_hdr_port_number_MASK          0x000000FF
745 #define lpfc_mbox_hdr_port_number_WORD          word6
746 #define lpfc_mbox_hdr_domain_SHIFT              24
747 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
748 #define lpfc_mbox_hdr_domain_WORD               word6
749                 uint32_t timeout;
750                 uint32_t request_length;
751                 uint32_t reserved9;
752         } request;
753         struct {
754                 uint32_t word6;
755 #define lpfc_mbox_hdr_opcode_SHIFT              0
756 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
757 #define lpfc_mbox_hdr_opcode_WORD               word6
758 #define lpfc_mbox_hdr_subsystem_SHIFT           8
759 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
760 #define lpfc_mbox_hdr_subsystem_WORD            word6
761 #define lpfc_mbox_hdr_domain_SHIFT              24
762 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
763 #define lpfc_mbox_hdr_domain_WORD               word6
764                 uint32_t word7;
765 #define lpfc_mbox_hdr_status_SHIFT              0
766 #define lpfc_mbox_hdr_status_MASK               0x000000FF
767 #define lpfc_mbox_hdr_status_WORD               word7
768 #define lpfc_mbox_hdr_add_status_SHIFT          8
769 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
770 #define lpfc_mbox_hdr_add_status_WORD           word7
771                 uint32_t response_length;
772                 uint32_t actual_response_length;
773         } response;
774 };
775
776 /* Mailbox structures */
777 struct mbox_header {
778         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
779         union  lpfc_sli4_cfg_shdr cfg_shdr;
780 };
781
782 /* Subsystem Definitions */
783 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
784 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
785
786 /* Device Specific Definitions */
787
788 /* The HOST ENDIAN defines are in Big Endian format. */
789 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
790 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
791
792 /* Common Opcodes */
793 #define LPFC_MBOX_OPCODE_CQ_CREATE              0x0C
794 #define LPFC_MBOX_OPCODE_EQ_CREATE              0x0D
795 #define LPFC_MBOX_OPCODE_MQ_CREATE              0x15
796 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES    0x20
797 #define LPFC_MBOX_OPCODE_NOP                    0x21
798 #define LPFC_MBOX_OPCODE_MQ_DESTROY             0x35
799 #define LPFC_MBOX_OPCODE_CQ_DESTROY             0x36
800 #define LPFC_MBOX_OPCODE_EQ_DESTROY             0x37
801 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG           0x3A
802 #define LPFC_MBOX_OPCODE_FUNCTION_RESET         0x3D
803 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT          0x5A
804
805 /* FCoE Opcodes */
806 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
807 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
808 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
809 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
810 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
811 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
812 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
813 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
814 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
815 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
816 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
817
818 /* Mailbox command structures */
819 struct eq_context {
820         uint32_t word0;
821 #define lpfc_eq_context_size_SHIFT      31
822 #define lpfc_eq_context_size_MASK       0x00000001
823 #define lpfc_eq_context_size_WORD       word0
824 #define LPFC_EQE_SIZE_4                 0x0
825 #define LPFC_EQE_SIZE_16                0x1
826 #define lpfc_eq_context_valid_SHIFT     29
827 #define lpfc_eq_context_valid_MASK      0x00000001
828 #define lpfc_eq_context_valid_WORD      word0
829         uint32_t word1;
830 #define lpfc_eq_context_count_SHIFT     26
831 #define lpfc_eq_context_count_MASK      0x00000003
832 #define lpfc_eq_context_count_WORD      word1
833 #define LPFC_EQ_CNT_256         0x0
834 #define LPFC_EQ_CNT_512         0x1
835 #define LPFC_EQ_CNT_1024        0x2
836 #define LPFC_EQ_CNT_2048        0x3
837 #define LPFC_EQ_CNT_4096        0x4
838         uint32_t word2;
839 #define lpfc_eq_context_delay_multi_SHIFT       13
840 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
841 #define lpfc_eq_context_delay_multi_WORD        word2
842         uint32_t reserved3;
843 };
844
845 struct sgl_page_pairs {
846         uint32_t sgl_pg0_addr_lo;
847         uint32_t sgl_pg0_addr_hi;
848         uint32_t sgl_pg1_addr_lo;
849         uint32_t sgl_pg1_addr_hi;
850 };
851
852 struct lpfc_mbx_post_sgl_pages {
853         struct mbox_header header;
854         uint32_t word0;
855 #define lpfc_post_sgl_pages_xri_SHIFT   0
856 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
857 #define lpfc_post_sgl_pages_xri_WORD    word0
858 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
859 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
860 #define lpfc_post_sgl_pages_xricnt_WORD word0
861         struct sgl_page_pairs  sgl_pg_pairs[1];
862 };
863
864 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
865 struct lpfc_mbx_post_uembed_sgl_page1 {
866         union  lpfc_sli4_cfg_shdr cfg_shdr;
867         uint32_t word0;
868         struct sgl_page_pairs sgl_pg_pairs;
869 };
870
871 struct lpfc_mbx_sge {
872         uint32_t pa_lo;
873         uint32_t pa_hi;
874         uint32_t length;
875 };
876
877 struct lpfc_mbx_nembed_cmd {
878         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
879 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
880         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
881 };
882
883 struct lpfc_mbx_nembed_sge_virt {
884         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
885 };
886
887 struct lpfc_mbx_eq_create {
888         struct mbox_header header;
889         union {
890                 struct {
891                         uint32_t word0;
892 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
893 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
894 #define lpfc_mbx_eq_create_num_pages_WORD       word0
895                         struct eq_context context;
896                         struct dma_address page[LPFC_MAX_EQ_PAGE];
897                 } request;
898                 struct {
899                         uint32_t word0;
900 #define lpfc_mbx_eq_create_q_id_SHIFT   0
901 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
902 #define lpfc_mbx_eq_create_q_id_WORD    word0
903                 } response;
904         } u;
905 };
906
907 struct lpfc_mbx_eq_destroy {
908         struct mbox_header header;
909         union {
910                 struct {
911                         uint32_t word0;
912 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
913 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
914 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
915                 } request;
916                 struct {
917                         uint32_t word0;
918                 } response;
919         } u;
920 };
921
922 struct lpfc_mbx_nop {
923         struct mbox_header header;
924         uint32_t context[2];
925 };
926
927 struct cq_context {
928         uint32_t word0;
929 #define lpfc_cq_context_event_SHIFT     31
930 #define lpfc_cq_context_event_MASK      0x00000001
931 #define lpfc_cq_context_event_WORD      word0
932 #define lpfc_cq_context_valid_SHIFT     29
933 #define lpfc_cq_context_valid_MASK      0x00000001
934 #define lpfc_cq_context_valid_WORD      word0
935 #define lpfc_cq_context_count_SHIFT     27
936 #define lpfc_cq_context_count_MASK      0x00000003
937 #define lpfc_cq_context_count_WORD      word0
938 #define LPFC_CQ_CNT_256         0x0
939 #define LPFC_CQ_CNT_512         0x1
940 #define LPFC_CQ_CNT_1024        0x2
941         uint32_t word1;
942 #define lpfc_cq_eq_id_SHIFT             22
943 #define lpfc_cq_eq_id_MASK              0x000000FF
944 #define lpfc_cq_eq_id_WORD              word1
945         uint32_t reserved0;
946         uint32_t reserved1;
947 };
948
949 struct lpfc_mbx_cq_create {
950         struct mbox_header header;
951         union {
952                 struct {
953                         uint32_t word0;
954 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
955 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
956 #define lpfc_mbx_cq_create_num_pages_WORD       word0
957                         struct cq_context context;
958                         struct dma_address page[LPFC_MAX_CQ_PAGE];
959                 } request;
960                 struct {
961                         uint32_t word0;
962 #define lpfc_mbx_cq_create_q_id_SHIFT   0
963 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
964 #define lpfc_mbx_cq_create_q_id_WORD    word0
965                 } response;
966         } u;
967 };
968
969 struct lpfc_mbx_cq_destroy {
970         struct mbox_header header;
971         union {
972                 struct {
973                         uint32_t word0;
974 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
975 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
976 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
977                 } request;
978                 struct {
979                         uint32_t word0;
980                 } response;
981         } u;
982 };
983
984 struct wq_context {
985         uint32_t reserved0;
986         uint32_t reserved1;
987         uint32_t reserved2;
988         uint32_t reserved3;
989 };
990
991 struct lpfc_mbx_wq_create {
992         struct mbox_header header;
993         union {
994                 struct {
995                         uint32_t word0;
996 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
997 #define lpfc_mbx_wq_create_num_pages_MASK       0x0000FFFF
998 #define lpfc_mbx_wq_create_num_pages_WORD       word0
999 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
1000 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
1001 #define lpfc_mbx_wq_create_cq_id_WORD           word0
1002                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1003                 } request;
1004                 struct {
1005                         uint32_t word0;
1006 #define lpfc_mbx_wq_create_q_id_SHIFT   0
1007 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
1008 #define lpfc_mbx_wq_create_q_id_WORD    word0
1009                 } response;
1010         } u;
1011 };
1012
1013 struct lpfc_mbx_wq_destroy {
1014         struct mbox_header header;
1015         union {
1016                 struct {
1017                         uint32_t word0;
1018 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
1019 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1020 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1021                 } request;
1022                 struct {
1023                         uint32_t word0;
1024                 } response;
1025         } u;
1026 };
1027
1028 #define LPFC_HDR_BUF_SIZE 128
1029 #define LPFC_DATA_BUF_SIZE 2048
1030 struct rq_context {
1031         uint32_t word0;
1032 #define lpfc_rq_context_rq_size_SHIFT   16
1033 #define lpfc_rq_context_rq_size_MASK    0x0000000F
1034 #define lpfc_rq_context_rq_size_WORD    word0
1035 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1036 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1037 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1038 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1039         uint32_t reserved1;
1040         uint32_t word2;
1041 #define lpfc_rq_context_cq_id_SHIFT     16
1042 #define lpfc_rq_context_cq_id_MASK      0x000003FF
1043 #define lpfc_rq_context_cq_id_WORD      word2
1044 #define lpfc_rq_context_buf_size_SHIFT  0
1045 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1046 #define lpfc_rq_context_buf_size_WORD   word2
1047         uint32_t reserved3;
1048 };
1049
1050 struct lpfc_mbx_rq_create {
1051         struct mbox_header header;
1052         union {
1053                 struct {
1054                         uint32_t word0;
1055 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1056 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1057 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1058                         struct rq_context context;
1059                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1060                 } request;
1061                 struct {
1062                         uint32_t word0;
1063 #define lpfc_mbx_rq_create_q_id_SHIFT   0
1064 #define lpfc_mbx_rq_create_q_id_MASK    0x0000FFFF
1065 #define lpfc_mbx_rq_create_q_id_WORD    word0
1066                 } response;
1067         } u;
1068 };
1069
1070 struct lpfc_mbx_rq_destroy {
1071         struct mbox_header header;
1072         union {
1073                 struct {
1074                         uint32_t word0;
1075 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1076 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1077 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1078                 } request;
1079                 struct {
1080                         uint32_t word0;
1081                 } response;
1082         } u;
1083 };
1084
1085 struct mq_context {
1086         uint32_t word0;
1087 #define lpfc_mq_context_cq_id_SHIFT     22
1088 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1089 #define lpfc_mq_context_cq_id_WORD      word0
1090 #define lpfc_mq_context_count_SHIFT     16
1091 #define lpfc_mq_context_count_MASK      0x0000000F
1092 #define lpfc_mq_context_count_WORD      word0
1093 #define LPFC_MQ_CNT_16          0x5
1094 #define LPFC_MQ_CNT_32          0x6
1095 #define LPFC_MQ_CNT_64          0x7
1096 #define LPFC_MQ_CNT_128         0x8
1097         uint32_t word1;
1098 #define lpfc_mq_context_valid_SHIFT     31
1099 #define lpfc_mq_context_valid_MASK      0x00000001
1100 #define lpfc_mq_context_valid_WORD      word1
1101         uint32_t reserved2;
1102         uint32_t reserved3;
1103 };
1104
1105 struct lpfc_mbx_mq_create {
1106         struct mbox_header header;
1107         union {
1108                 struct {
1109                         uint32_t word0;
1110 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1111 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1112 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1113                         struct mq_context context;
1114                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1115                 } request;
1116                 struct {
1117                         uint32_t word0;
1118 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1119 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1120 #define lpfc_mbx_mq_create_q_id_WORD    word0
1121                 } response;
1122         } u;
1123 };
1124
1125 struct lpfc_mbx_mq_create_ext {
1126         struct mbox_header header;
1127         union {
1128                 struct {
1129                         uint32_t word0;
1130 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT          0
1131 #define lpfc_mbx_mq_create_ext_num_pages_MASK           0x0000FFFF
1132 #define lpfc_mbx_mq_create_ext_num_pages_WORD           word0
1133                         uint32_t async_evt_bmap;
1134 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1135 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1136 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1137 #define lpfc_mbx_mq_create_ext_async_evt_fcfste_SHIFT   LPFC_TRAILER_CODE_FCOE
1138 #define lpfc_mbx_mq_create_ext_async_evt_fcfste_MASK    0x00000001
1139 #define lpfc_mbx_mq_create_ext_async_evt_fcfste_WORD    async_evt_bmap
1140 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1141 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1142 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1143                         struct mq_context context;
1144                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1145                 } request;
1146                 struct {
1147                         uint32_t word0;
1148 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1149 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1150 #define lpfc_mbx_mq_create_q_id_WORD    word0
1151                 } response;
1152         } u;
1153 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1154 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1155 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1156 };
1157
1158 struct lpfc_mbx_mq_destroy {
1159         struct mbox_header header;
1160         union {
1161                 struct {
1162                         uint32_t word0;
1163 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1164 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1165 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1166                 } request;
1167                 struct {
1168                         uint32_t word0;
1169                 } response;
1170         } u;
1171 };
1172
1173 struct lpfc_mbx_post_hdr_tmpl {
1174         struct mbox_header header;
1175         uint32_t word10;
1176 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
1177 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
1178 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
1179 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
1180 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
1181 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
1182         uint32_t rpi_paddr_lo;
1183         uint32_t rpi_paddr_hi;
1184 };
1185
1186 struct sli4_sge {       /* SLI-4 */
1187         uint32_t addr_hi;
1188         uint32_t addr_lo;
1189
1190         uint32_t word2;
1191 #define lpfc_sli4_sge_offset_SHIFT      0 /* Offset of buffer - Not used*/
1192 #define lpfc_sli4_sge_offset_MASK       0x00FFFFFF
1193 #define lpfc_sli4_sge_offset_WORD       word2
1194 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets
1195                                                 this  flag !! */
1196 #define lpfc_sli4_sge_last_MASK         0x00000001
1197 #define lpfc_sli4_sge_last_WORD         word2
1198         uint32_t sge_len;
1199 };
1200
1201 struct fcf_record {
1202         uint32_t max_rcv_size;
1203         uint32_t fka_adv_period;
1204         uint32_t fip_priority;
1205         uint32_t word3;
1206 #define lpfc_fcf_record_mac_0_SHIFT             0
1207 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
1208 #define lpfc_fcf_record_mac_0_WORD              word3
1209 #define lpfc_fcf_record_mac_1_SHIFT             8
1210 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
1211 #define lpfc_fcf_record_mac_1_WORD              word3
1212 #define lpfc_fcf_record_mac_2_SHIFT             16
1213 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
1214 #define lpfc_fcf_record_mac_2_WORD              word3
1215 #define lpfc_fcf_record_mac_3_SHIFT             24
1216 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
1217 #define lpfc_fcf_record_mac_3_WORD              word3
1218         uint32_t word4;
1219 #define lpfc_fcf_record_mac_4_SHIFT             0
1220 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
1221 #define lpfc_fcf_record_mac_4_WORD              word4
1222 #define lpfc_fcf_record_mac_5_SHIFT             8
1223 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
1224 #define lpfc_fcf_record_mac_5_WORD              word4
1225 #define lpfc_fcf_record_fcf_avail_SHIFT         16
1226 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
1227 #define lpfc_fcf_record_fcf_avail_WORD          word4
1228 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
1229 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
1230 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
1231 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
1232 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
1233         uint32_t word5;
1234 #define lpfc_fcf_record_fab_name_0_SHIFT        0
1235 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
1236 #define lpfc_fcf_record_fab_name_0_WORD         word5
1237 #define lpfc_fcf_record_fab_name_1_SHIFT        8
1238 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
1239 #define lpfc_fcf_record_fab_name_1_WORD         word5
1240 #define lpfc_fcf_record_fab_name_2_SHIFT        16
1241 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
1242 #define lpfc_fcf_record_fab_name_2_WORD         word5
1243 #define lpfc_fcf_record_fab_name_3_SHIFT        24
1244 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
1245 #define lpfc_fcf_record_fab_name_3_WORD         word5
1246         uint32_t word6;
1247 #define lpfc_fcf_record_fab_name_4_SHIFT        0
1248 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
1249 #define lpfc_fcf_record_fab_name_4_WORD         word6
1250 #define lpfc_fcf_record_fab_name_5_SHIFT        8
1251 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
1252 #define lpfc_fcf_record_fab_name_5_WORD         word6
1253 #define lpfc_fcf_record_fab_name_6_SHIFT        16
1254 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
1255 #define lpfc_fcf_record_fab_name_6_WORD         word6
1256 #define lpfc_fcf_record_fab_name_7_SHIFT        24
1257 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
1258 #define lpfc_fcf_record_fab_name_7_WORD         word6
1259         uint32_t word7;
1260 #define lpfc_fcf_record_fc_map_0_SHIFT          0
1261 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
1262 #define lpfc_fcf_record_fc_map_0_WORD           word7
1263 #define lpfc_fcf_record_fc_map_1_SHIFT          8
1264 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
1265 #define lpfc_fcf_record_fc_map_1_WORD           word7
1266 #define lpfc_fcf_record_fc_map_2_SHIFT          16
1267 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
1268 #define lpfc_fcf_record_fc_map_2_WORD           word7
1269 #define lpfc_fcf_record_fcf_valid_SHIFT         24
1270 #define lpfc_fcf_record_fcf_valid_MASK          0x000000FF
1271 #define lpfc_fcf_record_fcf_valid_WORD          word7
1272         uint32_t word8;
1273 #define lpfc_fcf_record_fcf_index_SHIFT         0
1274 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
1275 #define lpfc_fcf_record_fcf_index_WORD          word8
1276 #define lpfc_fcf_record_fcf_state_SHIFT         16
1277 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
1278 #define lpfc_fcf_record_fcf_state_WORD          word8
1279         uint8_t vlan_bitmap[512];
1280         uint32_t word137;
1281 #define lpfc_fcf_record_switch_name_0_SHIFT     0
1282 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
1283 #define lpfc_fcf_record_switch_name_0_WORD      word137
1284 #define lpfc_fcf_record_switch_name_1_SHIFT     8
1285 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
1286 #define lpfc_fcf_record_switch_name_1_WORD      word137
1287 #define lpfc_fcf_record_switch_name_2_SHIFT     16
1288 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
1289 #define lpfc_fcf_record_switch_name_2_WORD      word137
1290 #define lpfc_fcf_record_switch_name_3_SHIFT     24
1291 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
1292 #define lpfc_fcf_record_switch_name_3_WORD      word137
1293         uint32_t word138;
1294 #define lpfc_fcf_record_switch_name_4_SHIFT     0
1295 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
1296 #define lpfc_fcf_record_switch_name_4_WORD      word138
1297 #define lpfc_fcf_record_switch_name_5_SHIFT     8
1298 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
1299 #define lpfc_fcf_record_switch_name_5_WORD      word138
1300 #define lpfc_fcf_record_switch_name_6_SHIFT     16
1301 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
1302 #define lpfc_fcf_record_switch_name_6_WORD      word138
1303 #define lpfc_fcf_record_switch_name_7_SHIFT     24
1304 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
1305 #define lpfc_fcf_record_switch_name_7_WORD      word138
1306 };
1307
1308 struct lpfc_mbx_read_fcf_tbl {
1309         union lpfc_sli4_cfg_shdr cfg_shdr;
1310         union {
1311                 struct {
1312                         uint32_t word10;
1313 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
1314 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
1315 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
1316                 } request;
1317                 struct {
1318                         uint32_t eventag;
1319                 } response;
1320         } u;
1321         uint32_t word11;
1322 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
1323 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
1324 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
1325 };
1326
1327 struct lpfc_mbx_add_fcf_tbl_entry {
1328         union lpfc_sli4_cfg_shdr cfg_shdr;
1329         uint32_t word10;
1330 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
1331 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
1332 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
1333         struct lpfc_mbx_sge fcf_sge;
1334 };
1335
1336 struct lpfc_mbx_del_fcf_tbl_entry {
1337         struct mbox_header header;
1338         uint32_t word10;
1339 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
1340 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
1341 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
1342 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
1343 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
1344 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
1345 };
1346
1347 struct lpfc_mbx_redisc_fcf_tbl {
1348         struct mbox_header header;
1349         uint32_t word10;
1350 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
1351 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
1352 #define lpfc_mbx_redisc_fcf_count_WORD          word10
1353         uint32_t resvd;
1354         uint32_t word12;
1355 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
1356 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
1357 #define lpfc_mbx_redisc_fcf_index_WORD          word12
1358 };
1359
1360 struct lpfc_mbx_query_fw_cfg {
1361         struct mbox_header header;
1362         uint32_t config_number;
1363         uint32_t asic_rev;
1364         uint32_t phys_port;
1365         uint32_t function_mode;
1366 /* firmware Function Mode */
1367 #define lpfc_function_mode_toe_SHIFT            0
1368 #define lpfc_function_mode_toe_MASK             0x00000001
1369 #define lpfc_function_mode_toe_WORD             function_mode
1370 #define lpfc_function_mode_nic_SHIFT            1
1371 #define lpfc_function_mode_nic_MASK             0x00000001
1372 #define lpfc_function_mode_nic_WORD             function_mode
1373 #define lpfc_function_mode_rdma_SHIFT           2
1374 #define lpfc_function_mode_rdma_MASK            0x00000001
1375 #define lpfc_function_mode_rdma_WORD            function_mode
1376 #define lpfc_function_mode_vm_SHIFT             3
1377 #define lpfc_function_mode_vm_MASK              0x00000001
1378 #define lpfc_function_mode_vm_WORD              function_mode
1379 #define lpfc_function_mode_iscsi_i_SHIFT        4
1380 #define lpfc_function_mode_iscsi_i_MASK         0x00000001
1381 #define lpfc_function_mode_iscsi_i_WORD         function_mode
1382 #define lpfc_function_mode_iscsi_t_SHIFT        5
1383 #define lpfc_function_mode_iscsi_t_MASK         0x00000001
1384 #define lpfc_function_mode_iscsi_t_WORD         function_mode
1385 #define lpfc_function_mode_fcoe_i_SHIFT         6
1386 #define lpfc_function_mode_fcoe_i_MASK          0x00000001
1387 #define lpfc_function_mode_fcoe_i_WORD          function_mode
1388 #define lpfc_function_mode_fcoe_t_SHIFT         7
1389 #define lpfc_function_mode_fcoe_t_MASK          0x00000001
1390 #define lpfc_function_mode_fcoe_t_WORD          function_mode
1391 #define lpfc_function_mode_dal_SHIFT            8
1392 #define lpfc_function_mode_dal_MASK             0x00000001
1393 #define lpfc_function_mode_dal_WORD             function_mode
1394 #define lpfc_function_mode_lro_SHIFT            9
1395 #define lpfc_function_mode_lro_MASK             0x00000001
1396 #define lpfc_function_mode_lro_WORD             function_mode9
1397 #define lpfc_function_mode_flex10_SHIFT         10
1398 #define lpfc_function_mode_flex10_MASK          0x00000001
1399 #define lpfc_function_mode_flex10_WORD          function_mode
1400 #define lpfc_function_mode_ncsi_SHIFT           11
1401 #define lpfc_function_mode_ncsi_MASK            0x00000001
1402 #define lpfc_function_mode_ncsi_WORD            function_mode
1403 };
1404
1405 /* Status field for embedded SLI_CONFIG mailbox command */
1406 #define STATUS_SUCCESS                                  0x0
1407 #define STATUS_FAILED                                   0x1
1408 #define STATUS_ILLEGAL_REQUEST                          0x2
1409 #define STATUS_ILLEGAL_FIELD                            0x3
1410 #define STATUS_INSUFFICIENT_BUFFER                      0x4
1411 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
1412 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
1413 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
1414 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
1415 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
1416 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
1417 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
1418 #define STATUS_ASSERT_FAILED                            0x1e
1419 #define STATUS_INVALID_SESSION                          0x1f
1420 #define STATUS_INVALID_CONNECTION                       0x20
1421 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
1422 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
1423 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
1424 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
1425 #define STATUS_FLASHROM_READ_FAILED                     0x27
1426 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
1427 #define STATUS_ERROR_ACITMAIN                           0x2a
1428 #define STATUS_REBOOT_REQUIRED                          0x2c
1429 #define STATUS_FCF_IN_USE                               0x3a
1430 #define STATUS_FCF_TABLE_EMPTY                          0x43
1431
1432 struct lpfc_mbx_sli4_config {
1433         struct mbox_header header;
1434 };
1435
1436 struct lpfc_mbx_init_vfi {
1437         uint32_t word1;
1438 #define lpfc_init_vfi_vr_SHIFT          31
1439 #define lpfc_init_vfi_vr_MASK           0x00000001
1440 #define lpfc_init_vfi_vr_WORD           word1
1441 #define lpfc_init_vfi_vt_SHIFT          30
1442 #define lpfc_init_vfi_vt_MASK           0x00000001
1443 #define lpfc_init_vfi_vt_WORD           word1
1444 #define lpfc_init_vfi_vf_SHIFT          29
1445 #define lpfc_init_vfi_vf_MASK           0x00000001
1446 #define lpfc_init_vfi_vf_WORD           word1
1447 #define lpfc_init_vfi_vp_SHIFT          28
1448 #define lpfc_init_vfi_vp_MASK           0x00000001
1449 #define lpfc_init_vfi_vp_WORD           word1
1450 #define lpfc_init_vfi_vfi_SHIFT         0
1451 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
1452 #define lpfc_init_vfi_vfi_WORD          word1
1453         uint32_t word2;
1454 #define lpfc_init_vfi_vpi_SHIFT         16
1455 #define lpfc_init_vfi_vpi_MASK          0x0000FFFF
1456 #define lpfc_init_vfi_vpi_WORD          word2
1457 #define lpfc_init_vfi_fcfi_SHIFT        0
1458 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
1459 #define lpfc_init_vfi_fcfi_WORD         word2
1460         uint32_t word3;
1461 #define lpfc_init_vfi_pri_SHIFT         13
1462 #define lpfc_init_vfi_pri_MASK          0x00000007
1463 #define lpfc_init_vfi_pri_WORD          word3
1464 #define lpfc_init_vfi_vf_id_SHIFT       1
1465 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
1466 #define lpfc_init_vfi_vf_id_WORD        word3
1467         uint32_t word4;
1468 #define lpfc_init_vfi_hop_count_SHIFT   24
1469 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
1470 #define lpfc_init_vfi_hop_count_WORD    word4
1471 };
1472
1473 struct lpfc_mbx_reg_vfi {
1474         uint32_t word1;
1475 #define lpfc_reg_vfi_vp_SHIFT           28
1476 #define lpfc_reg_vfi_vp_MASK            0x00000001
1477 #define lpfc_reg_vfi_vp_WORD            word1
1478 #define lpfc_reg_vfi_vfi_SHIFT          0
1479 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
1480 #define lpfc_reg_vfi_vfi_WORD           word1
1481         uint32_t word2;
1482 #define lpfc_reg_vfi_vpi_SHIFT          16
1483 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
1484 #define lpfc_reg_vfi_vpi_WORD           word2
1485 #define lpfc_reg_vfi_fcfi_SHIFT         0
1486 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
1487 #define lpfc_reg_vfi_fcfi_WORD          word2
1488         uint32_t wwn[2];
1489         struct ulp_bde64 bde;
1490         uint32_t e_d_tov;
1491         uint32_t r_a_tov;
1492         uint32_t word10;
1493 #define lpfc_reg_vfi_nport_id_SHIFT             0
1494 #define lpfc_reg_vfi_nport_id_MASK              0x00FFFFFF
1495 #define lpfc_reg_vfi_nport_id_WORD              word10
1496 };
1497
1498 struct lpfc_mbx_init_vpi {
1499         uint32_t word1;
1500 #define lpfc_init_vpi_vfi_SHIFT         16
1501 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
1502 #define lpfc_init_vpi_vfi_WORD          word1
1503 #define lpfc_init_vpi_vpi_SHIFT         0
1504 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
1505 #define lpfc_init_vpi_vpi_WORD          word1
1506 };
1507
1508 struct lpfc_mbx_read_vpi {
1509         uint32_t word1_rsvd;
1510         uint32_t word2;
1511 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
1512 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
1513 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
1514         uint32_t word3_rsvd;
1515         uint32_t word4;
1516 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
1517 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
1518 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
1519 #define lpfc_mbx_read_vpi_pb_SHIFT              15
1520 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
1521 #define lpfc_mbx_read_vpi_pb_WORD               word4
1522 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
1523 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
1524 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
1525 #define lpfc_mbx_read_vpi_ns_SHIFT              30
1526 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
1527 #define lpfc_mbx_read_vpi_ns_WORD               word4
1528 #define lpfc_mbx_read_vpi_hl_SHIFT              31
1529 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
1530 #define lpfc_mbx_read_vpi_hl_WORD               word4
1531         uint32_t word5_rsvd;
1532         uint32_t word6;
1533 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
1534 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
1535 #define lpfc_mbx_read_vpi_vpi_WORD              word6
1536         uint32_t word7;
1537 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
1538 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
1539 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
1540 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
1541 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
1542 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
1543 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
1544 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
1545 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
1546 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
1547 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
1548 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
1549         uint32_t word8;
1550 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
1551 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
1552 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
1553 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
1554 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
1555 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
1556 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
1557 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
1558 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
1559 #define lpfc_mbx_read_vpi_vv_SHIFT              28
1560 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
1561 #define lpfc_mbx_read_vpi_vv_WORD               word8
1562 };
1563
1564 struct lpfc_mbx_unreg_vfi {
1565         uint32_t word1_rsvd;
1566         uint32_t word2;
1567 #define lpfc_unreg_vfi_vfi_SHIFT        0
1568 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
1569 #define lpfc_unreg_vfi_vfi_WORD         word2
1570 };
1571
1572 struct lpfc_mbx_resume_rpi {
1573         uint32_t word1;
1574 #define lpfc_resume_rpi_index_SHIFT     0
1575 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
1576 #define lpfc_resume_rpi_index_WORD      word1
1577 #define lpfc_resume_rpi_ii_SHIFT        30
1578 #define lpfc_resume_rpi_ii_MASK         0x00000003
1579 #define lpfc_resume_rpi_ii_WORD         word1
1580 #define RESUME_INDEX_RPI                0
1581 #define RESUME_INDEX_VPI                1
1582 #define RESUME_INDEX_VFI                2
1583 #define RESUME_INDEX_FCFI               3
1584         uint32_t event_tag;
1585 };
1586
1587 #define REG_FCF_INVALID_QID     0xFFFF
1588 struct lpfc_mbx_reg_fcfi {
1589         uint32_t word1;
1590 #define lpfc_reg_fcfi_info_index_SHIFT  0
1591 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
1592 #define lpfc_reg_fcfi_info_index_WORD   word1
1593 #define lpfc_reg_fcfi_fcfi_SHIFT        16
1594 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
1595 #define lpfc_reg_fcfi_fcfi_WORD         word1
1596         uint32_t word2;
1597 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
1598 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
1599 #define lpfc_reg_fcfi_rq_id1_WORD       word2
1600 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
1601 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
1602 #define lpfc_reg_fcfi_rq_id0_WORD       word2
1603         uint32_t word3;
1604 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
1605 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
1606 #define lpfc_reg_fcfi_rq_id3_WORD       word3
1607 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
1608 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
1609 #define lpfc_reg_fcfi_rq_id2_WORD       word3
1610         uint32_t word4;
1611 #define lpfc_reg_fcfi_type_match0_SHIFT 24
1612 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
1613 #define lpfc_reg_fcfi_type_match0_WORD  word4
1614 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
1615 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
1616 #define lpfc_reg_fcfi_type_mask0_WORD   word4
1617 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1618 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
1619 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
1620 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
1621 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
1622 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
1623         uint32_t word5;
1624 #define lpfc_reg_fcfi_type_match1_SHIFT 24
1625 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
1626 #define lpfc_reg_fcfi_type_match1_WORD  word5
1627 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
1628 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
1629 #define lpfc_reg_fcfi_type_mask1_WORD   word5
1630 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
1631 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
1632 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
1633 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
1634 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
1635 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
1636         uint32_t word6;
1637 #define lpfc_reg_fcfi_type_match2_SHIFT 24
1638 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
1639 #define lpfc_reg_fcfi_type_match2_WORD  word6
1640 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
1641 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
1642 #define lpfc_reg_fcfi_type_mask2_WORD   word6
1643 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
1644 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
1645 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
1646 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
1647 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
1648 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
1649         uint32_t word7;
1650 #define lpfc_reg_fcfi_type_match3_SHIFT 24
1651 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
1652 #define lpfc_reg_fcfi_type_match3_WORD  word7
1653 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
1654 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
1655 #define lpfc_reg_fcfi_type_mask3_WORD   word7
1656 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
1657 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
1658 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
1659 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
1660 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
1661 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
1662         uint32_t word8;
1663 #define lpfc_reg_fcfi_mam_SHIFT         13
1664 #define lpfc_reg_fcfi_mam_MASK          0x00000003
1665 #define lpfc_reg_fcfi_mam_WORD          word8
1666 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
1667 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
1668 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
1669 #define lpfc_reg_fcfi_vv_SHIFT          12
1670 #define lpfc_reg_fcfi_vv_MASK           0x00000001
1671 #define lpfc_reg_fcfi_vv_WORD           word8
1672 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
1673 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
1674 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
1675 };
1676
1677 struct lpfc_mbx_unreg_fcfi {
1678         uint32_t word1_rsv;
1679         uint32_t word2;
1680 #define lpfc_unreg_fcfi_SHIFT           0
1681 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
1682 #define lpfc_unreg_fcfi_WORD            word2
1683 };
1684
1685 struct lpfc_mbx_read_rev {
1686         uint32_t word1;
1687 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
1688 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
1689 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
1690 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
1691 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
1692 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
1693 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
1694 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
1695 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
1696 #define LPFC_PREDCBX_CEE_MODE   0
1697 #define LPFC_DCBX_CEE_MODE      1
1698 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
1699 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
1700 #define lpfc_mbx_rd_rev_vpd_WORD                word1
1701         uint32_t first_hw_rev;
1702         uint32_t second_hw_rev;
1703         uint32_t word4_rsvd;
1704         uint32_t third_hw_rev;
1705         uint32_t word6;
1706 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
1707 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
1708 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
1709 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
1710 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
1711 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
1712 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
1713 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
1714 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
1715 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
1716 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
1717 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
1718         uint32_t word7_rsvd;
1719         uint32_t fw_id_rev;
1720         uint8_t  fw_name[16];
1721         uint32_t ulp_fw_id_rev;
1722         uint8_t  ulp_fw_name[16];
1723         uint32_t word18_47_rsvd[30];
1724         uint32_t word48;
1725 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
1726 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
1727 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
1728         uint32_t vpd_paddr_low;
1729         uint32_t vpd_paddr_high;
1730         uint32_t avail_vpd_len;
1731         uint32_t rsvd_52_63[12];
1732 };
1733
1734 struct lpfc_mbx_read_config {
1735         uint32_t word1;
1736 #define lpfc_mbx_rd_conf_max_bbc_SHIFT          0
1737 #define lpfc_mbx_rd_conf_max_bbc_MASK           0x000000FF
1738 #define lpfc_mbx_rd_conf_max_bbc_WORD           word1
1739 #define lpfc_mbx_rd_conf_init_bbc_SHIFT         8
1740 #define lpfc_mbx_rd_conf_init_bbc_MASK          0x000000FF
1741 #define lpfc_mbx_rd_conf_init_bbc_WORD          word1
1742         uint32_t word2;
1743 #define lpfc_mbx_rd_conf_nport_did_SHIFT        0
1744 #define lpfc_mbx_rd_conf_nport_did_MASK         0x00FFFFFF
1745 #define lpfc_mbx_rd_conf_nport_did_WORD         word2
1746 #define lpfc_mbx_rd_conf_topology_SHIFT         24
1747 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
1748 #define lpfc_mbx_rd_conf_topology_WORD          word2
1749         uint32_t word3;
1750 #define lpfc_mbx_rd_conf_ao_SHIFT               0
1751 #define lpfc_mbx_rd_conf_ao_MASK                0x00000001
1752 #define lpfc_mbx_rd_conf_ao_WORD                word3
1753 #define lpfc_mbx_rd_conf_bb_scn_SHIFT           8
1754 #define lpfc_mbx_rd_conf_bb_scn_MASK            0x0000000F
1755 #define lpfc_mbx_rd_conf_bb_scn_WORD            word3
1756 #define lpfc_mbx_rd_conf_cbb_scn_SHIFT          12
1757 #define lpfc_mbx_rd_conf_cbb_scn_MASK           0x0000000F
1758 #define lpfc_mbx_rd_conf_cbb_scn_WORD           word3
1759 #define lpfc_mbx_rd_conf_mc_SHIFT               29
1760 #define lpfc_mbx_rd_conf_mc_MASK                0x00000001
1761 #define lpfc_mbx_rd_conf_mc_WORD                word3
1762         uint32_t word4;
1763 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
1764 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
1765 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
1766         uint32_t word5;
1767 #define lpfc_mbx_rd_conf_lp_tov_SHIFT           0
1768 #define lpfc_mbx_rd_conf_lp_tov_MASK            0x0000FFFF
1769 #define lpfc_mbx_rd_conf_lp_tov_WORD            word5
1770         uint32_t word6;
1771 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
1772 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
1773 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
1774         uint32_t word7;
1775 #define lpfc_mbx_rd_conf_r_t_tov_SHIFT          0
1776 #define lpfc_mbx_rd_conf_r_t_tov_MASK           0x000000FF
1777 #define lpfc_mbx_rd_conf_r_t_tov_WORD           word7
1778         uint32_t word8;
1779 #define lpfc_mbx_rd_conf_al_tov_SHIFT           0
1780 #define lpfc_mbx_rd_conf_al_tov_MASK            0x0000000F
1781 #define lpfc_mbx_rd_conf_al_tov_WORD            word8
1782         uint32_t word9;
1783 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
1784 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
1785 #define lpfc_mbx_rd_conf_lmt_WORD               word9
1786         uint32_t word10;
1787 #define lpfc_mbx_rd_conf_max_alpa_SHIFT         0
1788 #define lpfc_mbx_rd_conf_max_alpa_MASK          0x000000FF
1789 #define lpfc_mbx_rd_conf_max_alpa_WORD          word10
1790         uint32_t word11_rsvd;
1791         uint32_t word12;
1792 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
1793 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
1794 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
1795 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
1796 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
1797 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
1798         uint32_t word13;
1799 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
1800 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
1801 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
1802 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
1803 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
1804 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
1805         uint32_t word14;
1806 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
1807 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
1808 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
1809 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
1810 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
1811 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
1812         uint32_t word15;
1813 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
1814 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
1815 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
1816 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
1817 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
1818 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
1819         uint32_t word16;
1820 #define lpfc_mbx_rd_conf_fcfi_base_SHIFT        0
1821 #define lpfc_mbx_rd_conf_fcfi_base_MASK         0x0000FFFF
1822 #define lpfc_mbx_rd_conf_fcfi_base_WORD         word16
1823 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
1824 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
1825 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
1826         uint32_t word17;
1827 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
1828 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
1829 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
1830 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
1831 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
1832 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
1833         uint32_t word18;
1834 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
1835 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
1836 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
1837 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
1838 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
1839 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
1840 };
1841
1842 struct lpfc_mbx_request_features {
1843         uint32_t word1;
1844 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
1845 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
1846 #define lpfc_mbx_rq_ftr_qry_WORD                word1
1847         uint32_t word2;
1848 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
1849 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
1850 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
1851 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
1852 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
1853 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
1854 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
1855 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
1856 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
1857 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
1858 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
1859 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
1860 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
1861 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
1862 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
1863 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
1864 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
1865 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
1866 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
1867 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
1868 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
1869 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
1870 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
1871 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
1872         uint32_t word3;
1873 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
1874 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
1875 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
1876 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
1877 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
1878 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
1879 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
1880 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
1881 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
1882 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
1883 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
1884 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
1885 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
1886 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
1887 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
1888 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
1889 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
1890 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
1891 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
1892 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
1893 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
1894 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
1895 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
1896 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
1897 };
1898
1899 struct lpfc_mbx_supp_pages {
1900         uint32_t word1;
1901 #define qs_SHIFT                                0
1902 #define qs_MASK                                 0x00000001
1903 #define qs_WORD                                 word1
1904 #define wr_SHIFT                                1
1905 #define wr_MASK                                 0x00000001
1906 #define wr_WORD                                 word1
1907 #define pf_SHIFT                                8
1908 #define pf_MASK                                 0x000000ff
1909 #define pf_WORD                                 word1
1910 #define cpn_SHIFT                               16
1911 #define cpn_MASK                                0x000000ff
1912 #define cpn_WORD                                word1
1913         uint32_t word2;
1914 #define list_offset_SHIFT                       0
1915 #define list_offset_MASK                        0x000000ff
1916 #define list_offset_WORD                        word2
1917 #define next_offset_SHIFT                       8
1918 #define next_offset_MASK                        0x000000ff
1919 #define next_offset_WORD                        word2
1920 #define elem_cnt_SHIFT                          16
1921 #define elem_cnt_MASK                           0x000000ff
1922 #define elem_cnt_WORD                           word2
1923         uint32_t word3;
1924 #define pn_0_SHIFT                              24
1925 #define pn_0_MASK                               0x000000ff
1926 #define pn_0_WORD                               word3
1927 #define pn_1_SHIFT                              16
1928 #define pn_1_MASK                               0x000000ff
1929 #define pn_1_WORD                               word3
1930 #define pn_2_SHIFT                              8
1931 #define pn_2_MASK                               0x000000ff
1932 #define pn_2_WORD                               word3
1933 #define pn_3_SHIFT                              0
1934 #define pn_3_MASK                               0x000000ff
1935 #define pn_3_WORD                               word3
1936         uint32_t word4;
1937 #define pn_4_SHIFT                              24
1938 #define pn_4_MASK                               0x000000ff
1939 #define pn_4_WORD                               word4
1940 #define pn_5_SHIFT                              16
1941 #define pn_5_MASK                               0x000000ff
1942 #define pn_5_WORD                               word4
1943 #define pn_6_SHIFT                              8
1944 #define pn_6_MASK                               0x000000ff
1945 #define pn_6_WORD                               word4
1946 #define pn_7_SHIFT                              0
1947 #define pn_7_MASK                               0x000000ff
1948 #define pn_7_WORD                               word4
1949         uint32_t rsvd[27];
1950 #define LPFC_SUPP_PAGES                 0
1951 #define LPFC_BLOCK_GUARD_PROFILES       1
1952 #define LPFC_SLI4_PARAMETERS            2
1953 };
1954
1955 struct lpfc_mbx_sli4_params {
1956         uint32_t word1;
1957 #define qs_SHIFT                                0
1958 #define qs_MASK                                 0x00000001
1959 #define qs_WORD                                 word1
1960 #define wr_SHIFT                                1
1961 #define wr_MASK                                 0x00000001
1962 #define wr_WORD                                 word1
1963 #define pf_SHIFT                                8
1964 #define pf_MASK                                 0x000000ff
1965 #define pf_WORD                                 word1
1966 #define cpn_SHIFT                               16
1967 #define cpn_MASK                                0x000000ff
1968 #define cpn_WORD                                word1
1969         uint32_t word2;
1970 #define if_type_SHIFT                           0
1971 #define if_type_MASK                            0x00000007
1972 #define if_type_WORD                            word2
1973 #define sli_rev_SHIFT                           4
1974 #define sli_rev_MASK                            0x0000000f
1975 #define sli_rev_WORD                            word2
1976 #define sli_family_SHIFT                        8
1977 #define sli_family_MASK                         0x000000ff
1978 #define sli_family_WORD                         word2
1979 #define featurelevel_1_SHIFT                    16
1980 #define featurelevel_1_MASK                     0x000000ff
1981 #define featurelevel_1_WORD                     word2
1982 #define featurelevel_2_SHIFT                    24
1983 #define featurelevel_2_MASK                     0x0000001f
1984 #define featurelevel_2_WORD                     word2
1985         uint32_t word3;
1986 #define fcoe_SHIFT                              0
1987 #define fcoe_MASK                               0x00000001
1988 #define fcoe_WORD                               word3
1989 #define fc_SHIFT                                1
1990 #define fc_MASK                                 0x00000001
1991 #define fc_WORD                                 word3
1992 #define nic_SHIFT                               2
1993 #define nic_MASK                                0x00000001
1994 #define nic_WORD                                word3
1995 #define iscsi_SHIFT                             3
1996 #define iscsi_MASK                              0x00000001
1997 #define iscsi_WORD                              word3
1998 #define rdma_SHIFT                              4
1999 #define rdma_MASK                               0x00000001
2000 #define rdma_WORD                               word3
2001         uint32_t sge_supp_len;
2002 #define SLI4_PAGE_SIZE 4096
2003         uint32_t word5;
2004 #define if_page_sz_SHIFT                        0
2005 #define if_page_sz_MASK                         0x0000ffff
2006 #define if_page_sz_WORD                         word5
2007 #define loopbk_scope_SHIFT                      24
2008 #define loopbk_scope_MASK                       0x0000000f
2009 #define loopbk_scope_WORD                       word5
2010 #define rq_db_window_SHIFT                      28
2011 #define rq_db_window_MASK                       0x0000000f
2012 #define rq_db_window_WORD                       word5
2013         uint32_t word6;
2014 #define eq_pages_SHIFT                          0
2015 #define eq_pages_MASK                           0x0000000f
2016 #define eq_pages_WORD                           word6
2017 #define eqe_size_SHIFT                          8
2018 #define eqe_size_MASK                           0x000000ff
2019 #define eqe_size_WORD                           word6
2020         uint32_t word7;
2021 #define cq_pages_SHIFT                          0
2022 #define cq_pages_MASK                           0x0000000f
2023 #define cq_pages_WORD                           word7
2024 #define cqe_size_SHIFT                          8
2025 #define cqe_size_MASK                           0x000000ff
2026 #define cqe_size_WORD                           word7
2027         uint32_t word8;
2028 #define mq_pages_SHIFT                          0
2029 #define mq_pages_MASK                           0x0000000f
2030 #define mq_pages_WORD                           word8
2031 #define mqe_size_SHIFT                          8
2032 #define mqe_size_MASK                           0x000000ff
2033 #define mqe_size_WORD                           word8
2034 #define mq_elem_cnt_SHIFT                       16
2035 #define mq_elem_cnt_MASK                        0x000000ff
2036 #define mq_elem_cnt_WORD                        word8
2037         uint32_t word9;
2038 #define wq_pages_SHIFT                          0
2039 #define wq_pages_MASK                           0x0000ffff
2040 #define wq_pages_WORD                           word9
2041 #define wqe_size_SHIFT                          8
2042 #define wqe_size_MASK                           0x000000ff
2043 #define wqe_size_WORD                           word9
2044         uint32_t word10;
2045 #define rq_pages_SHIFT                          0
2046 #define rq_pages_MASK                           0x0000ffff
2047 #define rq_pages_WORD                           word10
2048 #define rqe_size_SHIFT                          8
2049 #define rqe_size_MASK                           0x000000ff
2050 #define rqe_size_WORD                           word10
2051         uint32_t word11;
2052 #define hdr_pages_SHIFT                         0
2053 #define hdr_pages_MASK                          0x0000000f
2054 #define hdr_pages_WORD                          word11
2055 #define hdr_size_SHIFT                          8
2056 #define hdr_size_MASK                           0x0000000f
2057 #define hdr_size_WORD                           word11
2058 #define hdr_pp_align_SHIFT                      16
2059 #define hdr_pp_align_MASK                       0x0000ffff
2060 #define hdr_pp_align_WORD                       word11
2061         uint32_t word12;
2062 #define sgl_pages_SHIFT                         0
2063 #define sgl_pages_MASK                          0x0000000f
2064 #define sgl_pages_WORD                          word12
2065 #define sgl_pp_align_SHIFT                      16
2066 #define sgl_pp_align_MASK                       0x0000ffff
2067 #define sgl_pp_align_WORD                       word12
2068         uint32_t rsvd_13_63[51];
2069 };
2070
2071 /* Mailbox Completion Queue Error Messages */
2072 #define MB_CQE_STATUS_SUCCESS                   0x0
2073 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
2074 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
2075 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
2076 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
2077 #define MB_CQE_STATUS_DMA_FAILED                0x5
2078
2079 /* mailbox queue entry structure */
2080 struct lpfc_mqe {
2081         uint32_t word0;
2082 #define lpfc_mqe_status_SHIFT           16
2083 #define lpfc_mqe_status_MASK            0x0000FFFF
2084 #define lpfc_mqe_status_WORD            word0
2085 #define lpfc_mqe_command_SHIFT          8
2086 #define lpfc_mqe_command_MASK           0x000000FF
2087 #define lpfc_mqe_command_WORD           word0
2088         union {
2089                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
2090                 /* sli4 mailbox commands */
2091                 struct lpfc_mbx_sli4_config sli4_config;
2092                 struct lpfc_mbx_init_vfi init_vfi;
2093                 struct lpfc_mbx_reg_vfi reg_vfi;
2094                 struct lpfc_mbx_reg_vfi unreg_vfi;
2095                 struct lpfc_mbx_init_vpi init_vpi;
2096                 struct lpfc_mbx_resume_rpi resume_rpi;
2097                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
2098                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
2099                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
2100                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
2101                 struct lpfc_mbx_reg_fcfi reg_fcfi;
2102                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
2103                 struct lpfc_mbx_mq_create mq_create;
2104                 struct lpfc_mbx_mq_create_ext mq_create_ext;
2105                 struct lpfc_mbx_eq_create eq_create;
2106                 struct lpfc_mbx_cq_create cq_create;
2107                 struct lpfc_mbx_wq_create wq_create;
2108                 struct lpfc_mbx_rq_create rq_create;
2109                 struct lpfc_mbx_mq_destroy mq_destroy;
2110                 struct lpfc_mbx_eq_destroy eq_destroy;
2111                 struct lpfc_mbx_cq_destroy cq_destroy;
2112                 struct lpfc_mbx_wq_destroy wq_destroy;
2113                 struct lpfc_mbx_rq_destroy rq_destroy;
2114                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
2115                 struct lpfc_mbx_nembed_cmd nembed_cmd;
2116                 struct lpfc_mbx_read_rev read_rev;
2117                 struct lpfc_mbx_read_vpi read_vpi;
2118                 struct lpfc_mbx_read_config rd_config;
2119                 struct lpfc_mbx_request_features req_ftrs;
2120                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
2121                 struct lpfc_mbx_query_fw_cfg query_fw_cfg;
2122                 struct lpfc_mbx_supp_pages supp_pages;
2123                 struct lpfc_mbx_sli4_params sli4_params;
2124                 struct lpfc_mbx_nop nop;
2125         } un;
2126 };
2127
2128 struct lpfc_mcqe {
2129         uint32_t word0;
2130 #define lpfc_mcqe_status_SHIFT          0
2131 #define lpfc_mcqe_status_MASK           0x0000FFFF
2132 #define lpfc_mcqe_status_WORD           word0
2133 #define lpfc_mcqe_ext_status_SHIFT      16
2134 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
2135 #define lpfc_mcqe_ext_status_WORD       word0
2136         uint32_t mcqe_tag0;
2137         uint32_t mcqe_tag1;
2138         uint32_t trailer;
2139 #define lpfc_trailer_valid_SHIFT        31
2140 #define lpfc_trailer_valid_MASK         0x00000001
2141 #define lpfc_trailer_valid_WORD         trailer
2142 #define lpfc_trailer_async_SHIFT        30
2143 #define lpfc_trailer_async_MASK         0x00000001
2144 #define lpfc_trailer_async_WORD         trailer
2145 #define lpfc_trailer_hpi_SHIFT          29
2146 #define lpfc_trailer_hpi_MASK           0x00000001
2147 #define lpfc_trailer_hpi_WORD           trailer
2148 #define lpfc_trailer_completed_SHIFT    28
2149 #define lpfc_trailer_completed_MASK     0x00000001
2150 #define lpfc_trailer_completed_WORD     trailer
2151 #define lpfc_trailer_consumed_SHIFT     27
2152 #define lpfc_trailer_consumed_MASK      0x00000001
2153 #define lpfc_trailer_consumed_WORD      trailer
2154 #define lpfc_trailer_type_SHIFT         16
2155 #define lpfc_trailer_type_MASK          0x000000FF
2156 #define lpfc_trailer_type_WORD          trailer
2157 #define lpfc_trailer_code_SHIFT         8
2158 #define lpfc_trailer_code_MASK          0x000000FF
2159 #define lpfc_trailer_code_WORD          trailer
2160 #define LPFC_TRAILER_CODE_LINK  0x1
2161 #define LPFC_TRAILER_CODE_FCOE  0x2
2162 #define LPFC_TRAILER_CODE_DCBX  0x3
2163 #define LPFC_TRAILER_CODE_GRP5  0x5
2164 #define LPFC_TRAILER_CODE_FC    0x10
2165 };
2166
2167 struct lpfc_acqe_link {
2168         uint32_t word0;
2169 #define lpfc_acqe_link_speed_SHIFT              24
2170 #define lpfc_acqe_link_speed_MASK               0x000000FF
2171 #define lpfc_acqe_link_speed_WORD               word0
2172 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
2173 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
2174 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
2175 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
2176 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
2177 #define lpfc_acqe_link_duplex_SHIFT             16
2178 #define lpfc_acqe_link_duplex_MASK              0x000000FF
2179 #define lpfc_acqe_link_duplex_WORD              word0
2180 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
2181 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
2182 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
2183 #define lpfc_acqe_link_status_SHIFT             8
2184 #define lpfc_acqe_link_status_MASK              0x000000FF
2185 #define lpfc_acqe_link_status_WORD              word0
2186 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
2187 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
2188 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
2189 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
2190 #define lpfc_acqe_link_physical_SHIFT           0
2191 #define lpfc_acqe_link_physical_MASK            0x000000FF
2192 #define lpfc_acqe_link_physical_WORD            word0
2193 #define LPFC_ASYNC_LINK_PORT_A                  0x0
2194 #define LPFC_ASYNC_LINK_PORT_B                  0x1
2195         uint32_t word1;
2196 #define lpfc_acqe_link_fault_SHIFT      0
2197 #define lpfc_acqe_link_fault_MASK       0x000000FF
2198 #define lpfc_acqe_link_fault_WORD       word1
2199 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
2200 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
2201 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
2202 #define lpfc_acqe_qos_link_speed_SHIFT  16
2203 #define lpfc_acqe_qos_link_speed_MASK   0x0000FFFF
2204 #define lpfc_acqe_qos_link_speed_WORD   word1
2205         uint32_t event_tag;
2206         uint32_t trailer;
2207 };
2208
2209 struct lpfc_acqe_fcoe {
2210         uint32_t index;
2211         uint32_t word1;
2212 #define lpfc_acqe_fcoe_fcf_count_SHIFT          0
2213 #define lpfc_acqe_fcoe_fcf_count_MASK           0x0000FFFF
2214 #define lpfc_acqe_fcoe_fcf_count_WORD           word1
2215 #define lpfc_acqe_fcoe_event_type_SHIFT         16
2216 #define lpfc_acqe_fcoe_event_type_MASK          0x0000FFFF
2217 #define lpfc_acqe_fcoe_event_type_WORD          word1
2218 #define LPFC_FCOE_EVENT_TYPE_NEW_FCF            0x1
2219 #define LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL     0x2
2220 #define LPFC_FCOE_EVENT_TYPE_FCF_DEAD           0x3
2221 #define LPFC_FCOE_EVENT_TYPE_CVL                0x4
2222 #define LPFC_FCOE_EVENT_TYPE_FCF_PARAM_MOD      0x5
2223         uint32_t event_tag;
2224         uint32_t trailer;
2225 };
2226
2227 struct lpfc_acqe_dcbx {
2228         uint32_t tlv_ttl;
2229         uint32_t reserved;
2230         uint32_t event_tag;
2231         uint32_t trailer;
2232 };
2233
2234 struct lpfc_acqe_grp5 {
2235         uint32_t word0;
2236 #define lpfc_acqe_grp5_pport_SHIFT      0
2237 #define lpfc_acqe_grp5_pport_MASK       0x000000FF
2238 #define lpfc_acqe_grp5_pport_WORD       word0
2239         uint32_t word1;
2240 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
2241 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
2242 #define lpfc_acqe_grp5_llink_spd_WORD   word1
2243         uint32_t event_tag;
2244         uint32_t trailer;
2245 };
2246
2247 /*
2248  * Define the bootstrap mailbox (bmbx) region used to communicate
2249  * mailbox command between the host and port. The mailbox consists
2250  * of a payload area of 256 bytes and a completion queue of length
2251  * 16 bytes.
2252  */
2253 struct lpfc_bmbx_create {
2254         struct lpfc_mqe mqe;
2255         struct lpfc_mcqe mcqe;
2256 };
2257
2258 #define SGL_ALIGN_SZ 64
2259 #define SGL_PAGE_SIZE 4096
2260 /* align SGL addr on a size boundary - adjust address up */
2261 #define NO_XRI  ((uint16_t)-1)
2262
2263 struct wqe_common {
2264         uint32_t word6;
2265 #define wqe_xri_tag_SHIFT     0
2266 #define wqe_xri_tag_MASK      0x0000FFFF
2267 #define wqe_xri_tag_WORD      word6
2268 #define wqe_ctxt_tag_SHIFT    16
2269 #define wqe_ctxt_tag_MASK     0x0000FFFF
2270 #define wqe_ctxt_tag_WORD     word6
2271         uint32_t word7;
2272 #define wqe_ct_SHIFT          2
2273 #define wqe_ct_MASK           0x00000003
2274 #define wqe_ct_WORD           word7
2275 #define wqe_status_SHIFT      4
2276 #define wqe_status_MASK       0x0000000f
2277 #define wqe_status_WORD       word7
2278 #define wqe_cmnd_SHIFT        8
2279 #define wqe_cmnd_MASK         0x000000ff
2280 #define wqe_cmnd_WORD         word7
2281 #define wqe_class_SHIFT       16
2282 #define wqe_class_MASK        0x00000007
2283 #define wqe_class_WORD        word7
2284 #define wqe_pu_SHIFT          20
2285 #define wqe_pu_MASK           0x00000003
2286 #define wqe_pu_WORD           word7
2287 #define wqe_erp_SHIFT         22
2288 #define wqe_erp_MASK          0x00000001
2289 #define wqe_erp_WORD          word7
2290 #define wqe_lnk_SHIFT         23
2291 #define wqe_lnk_MASK          0x00000001
2292 #define wqe_lnk_WORD          word7
2293 #define wqe_tmo_SHIFT         24
2294 #define wqe_tmo_MASK          0x000000ff
2295 #define wqe_tmo_WORD          word7
2296         uint32_t abort_tag; /* word 8 in WQE */
2297         uint32_t word9;
2298 #define wqe_reqtag_SHIFT      0
2299 #define wqe_reqtag_MASK       0x0000FFFF
2300 #define wqe_reqtag_WORD       word9
2301 #define wqe_rcvoxid_SHIFT     16
2302 #define wqe_rcvoxid_MASK      0x0000FFFF
2303 #define wqe_rcvoxid_WORD      word9
2304         uint32_t word10;
2305 #define wqe_ebde_cnt_SHIFT    0
2306 #define wqe_ebde_cnt_MASK     0x00000007
2307 #define wqe_ebde_cnt_WORD     word10
2308 #define wqe_lenloc_SHIFT      7
2309 #define wqe_lenloc_MASK       0x00000003
2310 #define wqe_lenloc_WORD       word10
2311 #define LPFC_WQE_LENLOC_NONE            0
2312 #define LPFC_WQE_LENLOC_WORD3   1
2313 #define LPFC_WQE_LENLOC_WORD12  2
2314 #define LPFC_WQE_LENLOC_WORD4   3
2315 #define wqe_qosd_SHIFT        9
2316 #define wqe_qosd_MASK         0x00000001
2317 #define wqe_qosd_WORD         word10
2318 #define wqe_xbl_SHIFT         11
2319 #define wqe_xbl_MASK          0x00000001
2320 #define wqe_xbl_WORD          word10
2321 #define wqe_iod_SHIFT         13
2322 #define wqe_iod_MASK          0x00000001
2323 #define wqe_iod_WORD          word10
2324 #define LPFC_WQE_IOD_WRITE      0
2325 #define LPFC_WQE_IOD_READ       1
2326 #define wqe_dbde_SHIFT        14
2327 #define wqe_dbde_MASK         0x00000001
2328 #define wqe_dbde_WORD         word10
2329 #define wqe_wqes_SHIFT        15
2330 #define wqe_wqes_MASK         0x00000001
2331 #define wqe_wqes_WORD         word10
2332 #define wqe_pri_SHIFT         16
2333 #define wqe_pri_MASK          0x00000007
2334 #define wqe_pri_WORD          word10
2335 #define wqe_pv_SHIFT          19
2336 #define wqe_pv_MASK           0x00000001
2337 #define wqe_pv_WORD           word10
2338 #define wqe_xc_SHIFT          21
2339 #define wqe_xc_MASK           0x00000001
2340 #define wqe_xc_WORD           word10
2341 #define wqe_ccpe_SHIFT        23
2342 #define wqe_ccpe_MASK         0x00000001
2343 #define wqe_ccpe_WORD         word10
2344 #define wqe_ccp_SHIFT         24
2345 #define wqe_ccp_MASK          0x000000ff
2346 #define wqe_ccp_WORD          word10
2347         uint32_t word11;
2348 #define wqe_cmd_type_SHIFT    0
2349 #define wqe_cmd_type_MASK     0x0000000f
2350 #define wqe_cmd_type_WORD     word11
2351 #define wqe_els_id_SHIFT      4
2352 #define wqe_els_id_MASK       0x00000003
2353 #define wqe_els_id_WORD       word11
2354 #define LPFC_ELS_ID_FLOGI       3
2355 #define LPFC_ELS_ID_FDISC       2
2356 #define LPFC_ELS_ID_LOGO        1
2357 #define LPFC_ELS_ID_DEFAULT     0
2358 #define wqe_wqec_SHIFT        7
2359 #define wqe_wqec_MASK         0x00000001
2360 #define wqe_wqec_WORD         word11
2361 #define wqe_cqid_SHIFT        16
2362 #define wqe_cqid_MASK         0x0000ffff
2363 #define wqe_cqid_WORD         word11
2364 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
2365 };
2366
2367 struct wqe_did {
2368         uint32_t word5;
2369 #define wqe_els_did_SHIFT         0
2370 #define wqe_els_did_MASK          0x00FFFFFF
2371 #define wqe_els_did_WORD          word5
2372 #define wqe_xmit_bls_pt_SHIFT         28
2373 #define wqe_xmit_bls_pt_MASK          0x00000003
2374 #define wqe_xmit_bls_pt_WORD          word5
2375 #define wqe_xmit_bls_ar_SHIFT         30
2376 #define wqe_xmit_bls_ar_MASK          0x00000001
2377 #define wqe_xmit_bls_ar_WORD          word5
2378 #define wqe_xmit_bls_xo_SHIFT         31
2379 #define wqe_xmit_bls_xo_MASK          0x00000001
2380 #define wqe_xmit_bls_xo_WORD          word5
2381 };
2382
2383 struct lpfc_wqe_generic{
2384         struct ulp_bde64 bde;
2385         uint32_t word3;
2386         uint32_t word4;
2387         uint32_t word5;
2388         struct wqe_common wqe_com;
2389         uint32_t payload[4];
2390 };
2391
2392 struct els_request64_wqe {
2393         struct ulp_bde64 bde;
2394         uint32_t payload_len;
2395         uint32_t word4;
2396 #define els_req64_sid_SHIFT         0
2397 #define els_req64_sid_MASK          0x00FFFFFF
2398 #define els_req64_sid_WORD          word4
2399 #define els_req64_sp_SHIFT          24
2400 #define els_req64_sp_MASK           0x00000001
2401 #define els_req64_sp_WORD           word4
2402 #define els_req64_vf_SHIFT          25
2403 #define els_req64_vf_MASK           0x00000001
2404 #define els_req64_vf_WORD           word4
2405         struct wqe_did  wqe_dest;
2406         struct wqe_common wqe_com; /* words 6-11 */
2407         uint32_t word12;
2408 #define els_req64_vfid_SHIFT        1
2409 #define els_req64_vfid_MASK         0x00000FFF
2410 #define els_req64_vfid_WORD         word12
2411 #define els_req64_pri_SHIFT         13
2412 #define els_req64_pri_MASK          0x00000007
2413 #define els_req64_pri_WORD          word12
2414         uint32_t word13;
2415 #define els_req64_hopcnt_SHIFT      24
2416 #define els_req64_hopcnt_MASK       0x000000ff
2417 #define els_req64_hopcnt_WORD       word13
2418         uint32_t reserved[2];
2419 };
2420
2421 struct xmit_els_rsp64_wqe {
2422         struct ulp_bde64 bde;
2423         uint32_t response_payload_len;
2424         uint32_t rsvd4;
2425         struct wqe_did wqe_dest;
2426         struct wqe_common wqe_com; /* words 6-11 */
2427         uint32_t rsvd_12_15[4];
2428 };
2429
2430 struct xmit_bls_rsp64_wqe {
2431         uint32_t payload0;
2432 /* Payload0 for BA_ACC */
2433 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
2434 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
2435 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
2436 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
2437 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
2438 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
2439 /* Payload0 for BA_RJT */
2440 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
2441 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
2442 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
2443 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
2444 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
2445 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
2446 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
2447 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
2448 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
2449         uint32_t word1;
2450 #define xmit_bls_rsp64_rxid_SHIFT  0
2451 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
2452 #define xmit_bls_rsp64_rxid_WORD   word1
2453 #define xmit_bls_rsp64_oxid_SHIFT  16
2454 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
2455 #define xmit_bls_rsp64_oxid_WORD   word1
2456         uint32_t word2;
2457 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
2458 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
2459 #define xmit_bls_rsp64_seqcnthi_WORD   word2
2460 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
2461 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
2462 #define xmit_bls_rsp64_seqcntlo_WORD   word2
2463         uint32_t rsrvd3;
2464         uint32_t rsrvd4;
2465         struct wqe_did  wqe_dest;
2466         struct wqe_common wqe_com; /* words 6-11 */
2467         uint32_t rsvd_12_15[4];
2468 };
2469
2470 struct wqe_rctl_dfctl {
2471         uint32_t word5;
2472 #define wqe_si_SHIFT 2
2473 #define wqe_si_MASK  0x000000001
2474 #define wqe_si_WORD  word5
2475 #define wqe_la_SHIFT 3
2476 #define wqe_la_MASK  0x000000001
2477 #define wqe_la_WORD  word5
2478 #define wqe_ls_SHIFT 7
2479 #define wqe_ls_MASK  0x000000001
2480 #define wqe_ls_WORD  word5
2481 #define wqe_dfctl_SHIFT 8
2482 #define wqe_dfctl_MASK  0x0000000ff
2483 #define wqe_dfctl_WORD  word5
2484 #define wqe_type_SHIFT 16
2485 #define wqe_type_MASK  0x0000000ff
2486 #define wqe_type_WORD  word5
2487 #define wqe_rctl_SHIFT 24
2488 #define wqe_rctl_MASK  0x0000000ff
2489 #define wqe_rctl_WORD  word5
2490 };
2491
2492 struct xmit_seq64_wqe {
2493         struct ulp_bde64 bde;
2494         uint32_t rsvd3;
2495         uint32_t relative_offset;
2496         struct wqe_rctl_dfctl wge_ctl;
2497         struct wqe_common wqe_com; /* words 6-11 */
2498         /* Note: word10 different REVISIT */
2499         uint32_t xmit_len;
2500         uint32_t rsvd_12_15[3];
2501 };
2502 struct xmit_bcast64_wqe {
2503         struct ulp_bde64 bde;
2504         uint32_t seq_payload_len;
2505         uint32_t rsvd4;
2506         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2507         struct wqe_common wqe_com;     /* words 6-11 */
2508         uint32_t rsvd_12_15[4];
2509 };
2510
2511 struct gen_req64_wqe {
2512         struct ulp_bde64 bde;
2513         uint32_t request_payload_len;
2514         uint32_t relative_offset;
2515         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2516         struct wqe_common wqe_com;     /* words 6-11 */
2517         uint32_t rsvd_12_15[4];
2518 };
2519
2520 struct create_xri_wqe {
2521         uint32_t rsrvd[5];           /* words 0-4 */
2522         struct wqe_did  wqe_dest;  /* word 5 */
2523         struct wqe_common wqe_com; /* words 6-11 */
2524         uint32_t rsvd_12_15[4];         /* word 12-15 */
2525 };
2526
2527 #define T_REQUEST_TAG 3
2528 #define T_XRI_TAG 1
2529
2530 struct abort_cmd_wqe {
2531         uint32_t rsrvd[3];
2532         uint32_t word3;
2533 #define abort_cmd_ia_SHIFT  0
2534 #define abort_cmd_ia_MASK  0x000000001
2535 #define abort_cmd_ia_WORD  word3
2536 #define abort_cmd_criteria_SHIFT  8
2537 #define abort_cmd_criteria_MASK  0x0000000ff
2538 #define abort_cmd_criteria_WORD  word3
2539         uint32_t rsrvd4;
2540         uint32_t rsrvd5;
2541         struct wqe_common wqe_com;     /* words 6-11 */
2542         uint32_t rsvd_12_15[4];         /* word 12-15 */
2543 };
2544
2545 struct fcp_iwrite64_wqe {
2546         struct ulp_bde64 bde;
2547         uint32_t payload_offset_len;
2548         uint32_t total_xfer_len;
2549         uint32_t initial_xfer_len;
2550         struct wqe_common wqe_com;     /* words 6-11 */
2551         uint32_t rsvd_12_15[4];         /* word 12-15 */
2552 };
2553
2554 struct fcp_iread64_wqe {
2555         struct ulp_bde64 bde;
2556         uint32_t payload_offset_len;   /* word 3 */
2557         uint32_t total_xfer_len;       /* word 4 */
2558         uint32_t rsrvd5;               /* word 5 */
2559         struct wqe_common wqe_com;     /* words 6-11 */
2560         uint32_t rsvd_12_15[4];         /* word 12-15 */
2561 };
2562
2563 struct fcp_icmnd64_wqe {
2564         struct ulp_bde64 bde;          /* words 0-2 */
2565         uint32_t rsrvd3;               /* word 3 */
2566         uint32_t rsrvd4;               /* word 4 */
2567         uint32_t rsrvd5;               /* word 5 */
2568         struct wqe_common wqe_com;     /* words 6-11 */
2569         uint32_t rsvd_12_15[4];        /* word 12-15 */
2570 };
2571
2572
2573 union lpfc_wqe {
2574         uint32_t words[16];
2575         struct lpfc_wqe_generic generic;
2576         struct fcp_icmnd64_wqe fcp_icmd;
2577         struct fcp_iread64_wqe fcp_iread;
2578         struct fcp_iwrite64_wqe fcp_iwrite;
2579         struct abort_cmd_wqe abort_cmd;
2580         struct create_xri_wqe create_xri;
2581         struct xmit_bcast64_wqe xmit_bcast64;
2582         struct xmit_seq64_wqe xmit_sequence;
2583         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
2584         struct xmit_els_rsp64_wqe xmit_els_rsp;
2585         struct els_request64_wqe els_req;
2586         struct gen_req64_wqe gen_req;
2587 };
2588
2589 #define FCP_COMMAND 0x0
2590 #define FCP_COMMAND_DATA_OUT 0x1
2591 #define ELS_COMMAND_NON_FIP 0xC
2592 #define ELS_COMMAND_FIP 0xD
2593 #define OTHER_COMMAND 0x8
2594