isci: fix frame received locking
[linux-2.6.git] / drivers / scsi / isci / phy.c
1 /*
2  * This file is provided under a dual BSD/GPLv2 license.  When using or
3  * redistributing this file, you may do so under either license.
4  *
5  * GPL LICENSE SUMMARY
6  *
7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * BSD LICENSE
25  *
26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27  * All rights reserved.
28  *
29  * Redistribution and use in source and binary forms, with or without
30  * modification, are permitted provided that the following conditions
31  * are met:
32  *
33  *   * Redistributions of source code must retain the above copyright
34  *     notice, this list of conditions and the following disclaimer.
35  *   * Redistributions in binary form must reproduce the above copyright
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37  *     the documentation and/or other materials provided with the
38  *     distribution.
39  *   * Neither the name of Intel Corporation nor the names of its
40  *     contributors may be used to endorse or promote products derived
41  *     from this software without specific prior written permission.
42  *
43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54  */
55
56 #include "isci.h"
57 #include "host.h"
58 #include "phy.h"
59 #include "scu_event_codes.h"
60 #include "probe_roms.h"
61
62 /* Maximum arbitration wait time in micro-seconds */
63 #define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME  (700)
64
65 enum sas_linkrate sci_phy_linkrate(struct scic_sds_phy *sci_phy)
66 {
67         return sci_phy->max_negotiated_speed;
68 }
69
70 /*
71  * *****************************************************************************
72  * * SCIC SDS PHY Internal Methods
73  * ***************************************************************************** */
74
75 /**
76  * This method will initialize the phy transport layer registers
77  * @sci_phy:
78  * @transport_layer_registers
79  *
80  * enum sci_status
81  */
82 static enum sci_status scic_sds_phy_transport_layer_initialization(
83         struct scic_sds_phy *sci_phy,
84         struct scu_transport_layer_registers __iomem *transport_layer_registers)
85 {
86         u32 tl_control;
87
88         sci_phy->transport_layer_registers = transport_layer_registers;
89
90         writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
91                 &sci_phy->transport_layer_registers->stp_rni);
92
93         /*
94          * Hardware team recommends that we enable the STP prefetch for all
95          * transports
96          */
97         tl_control = readl(&sci_phy->transport_layer_registers->control);
98         tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH);
99         writel(tl_control, &sci_phy->transport_layer_registers->control);
100
101         return SCI_SUCCESS;
102 }
103
104 /**
105  * This method will initialize the phy link layer registers
106  * @sci_phy:
107  * @link_layer_registers:
108  *
109  * enum sci_status
110  */
111 static enum sci_status
112 scic_sds_phy_link_layer_initialization(struct scic_sds_phy *sci_phy,
113                                        struct scu_link_layer_registers __iomem *link_layer_registers)
114 {
115         struct scic_sds_controller *scic =
116                 sci_phy->owning_port->owning_controller;
117         int phy_idx = sci_phy->phy_index;
118         struct sci_phy_user_params *phy_user =
119                 &scic->user_parameters.sds1.phys[phy_idx];
120         struct sci_phy_oem_params *phy_oem =
121                 &scic->oem_parameters.sds1.phys[phy_idx];
122         u32 phy_configuration;
123         struct scic_phy_cap phy_cap;
124         u32 parity_check = 0;
125         u32 parity_count = 0;
126         u32 llctl, link_rate;
127         u32 clksm_value = 0;
128
129         sci_phy->link_layer_registers = link_layer_registers;
130
131         /* Set our IDENTIFY frame data */
132         #define SCI_END_DEVICE 0x01
133
134         writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
135                SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) |
136                SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) |
137                SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) |
138                SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE),
139                &sci_phy->link_layer_registers->transmit_identification);
140
141         /* Write the device SAS Address */
142         writel(0xFEDCBA98,
143                &sci_phy->link_layer_registers->sas_device_name_high);
144         writel(phy_idx, &sci_phy->link_layer_registers->sas_device_name_low);
145
146         /* Write the source SAS Address */
147         writel(phy_oem->sas_address.high,
148                 &sci_phy->link_layer_registers->source_sas_address_high);
149         writel(phy_oem->sas_address.low,
150                 &sci_phy->link_layer_registers->source_sas_address_low);
151
152         /* Clear and Set the PHY Identifier */
153         writel(0, &sci_phy->link_layer_registers->identify_frame_phy_id);
154         writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx),
155                 &sci_phy->link_layer_registers->identify_frame_phy_id);
156
157         /* Change the initial state of the phy configuration register */
158         phy_configuration =
159                 readl(&sci_phy->link_layer_registers->phy_configuration);
160
161         /* Hold OOB state machine in reset */
162         phy_configuration |=  SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
163         writel(phy_configuration,
164                 &sci_phy->link_layer_registers->phy_configuration);
165
166         /* Configure the SNW capabilities */
167         phy_cap.all = 0;
168         phy_cap.start = 1;
169         phy_cap.gen3_no_ssc = 1;
170         phy_cap.gen2_no_ssc = 1;
171         phy_cap.gen1_no_ssc = 1;
172         if (scic->oem_parameters.sds1.controller.do_enable_ssc == true) {
173                 phy_cap.gen3_ssc = 1;
174                 phy_cap.gen2_ssc = 1;
175                 phy_cap.gen1_ssc = 1;
176         }
177
178         /*
179          * The SAS specification indicates that the phy_capabilities that
180          * are transmitted shall have an even parity.  Calculate the parity. */
181         parity_check = phy_cap.all;
182         while (parity_check != 0) {
183                 if (parity_check & 0x1)
184                         parity_count++;
185                 parity_check >>= 1;
186         }
187
188         /*
189          * If parity indicates there are an odd number of bits set, then
190          * set the parity bit to 1 in the phy capabilities. */
191         if ((parity_count % 2) != 0)
192                 phy_cap.parity = 1;
193
194         writel(phy_cap.all, &sci_phy->link_layer_registers->phy_capabilities);
195
196         /* Set the enable spinup period but disable the ability to send
197          * notify enable spinup
198          */
199         writel(SCU_ENSPINUP_GEN_VAL(COUNT,
200                         phy_user->notify_enable_spin_up_insertion_frequency),
201                 &sci_phy->link_layer_registers->notify_enable_spinup_control);
202
203         /* Write the ALIGN Insertion Ferequency for connected phy and
204          * inpendent of connected state
205          */
206         clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
207                         phy_user->in_connection_align_insertion_frequency);
208
209         clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
210                         phy_user->align_insertion_frequency);
211
212         writel(clksm_value, &sci_phy->link_layer_registers->clock_skew_management);
213
214         /* @todo Provide a way to write this register correctly */
215         writel(0x02108421,
216                 &sci_phy->link_layer_registers->afe_lookup_table_control);
217
218         llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT,
219                 (u8)scic->user_parameters.sds1.no_outbound_task_timeout);
220
221         switch(phy_user->max_speed_generation) {
222         case SCIC_SDS_PARM_GEN3_SPEED:
223                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3;
224                 break;
225         case SCIC_SDS_PARM_GEN2_SPEED:
226                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2;
227                 break;
228         default:
229                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1;
230                 break;
231         }
232         llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);
233         writel(llctl, &sci_phy->link_layer_registers->link_layer_control);
234
235         if (is_a0() || is_a2()) {
236                 /* Program the max ARB time for the PHY to 700us so we inter-operate with
237                  * the PMC expander which shuts down PHYs if the expander PHY generates too
238                  * many breaks.  This time value will guarantee that the initiator PHY will
239                  * generate the break.
240                  */
241                 writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
242                         &sci_phy->link_layer_registers->maximum_arbitration_wait_timer_timeout);
243         }
244
245         /* Disable link layer hang detection, rely on the OS timeout for I/O timeouts. */
246         writel(0, &sci_phy->link_layer_registers->link_layer_hang_detection_timeout);
247
248         /* We can exit the initial state to the stopped state */
249         sci_change_state(&sci_phy->sm, SCI_PHY_STOPPED);
250
251         return SCI_SUCCESS;
252 }
253
254 static void phy_sata_timeout(unsigned long data)
255 {
256         struct sci_timer *tmr = (struct sci_timer *)data;
257         struct scic_sds_phy *sci_phy = container_of(tmr, typeof(*sci_phy), sata_timer);
258         struct isci_host *ihost = scic_to_ihost(sci_phy->owning_port->owning_controller);
259         unsigned long flags;
260
261         spin_lock_irqsave(&ihost->scic_lock, flags);
262
263         if (tmr->cancel)
264                 goto done;
265
266         dev_dbg(sciphy_to_dev(sci_phy),
267                  "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
268                  "timeout.\n",
269                  __func__,
270                  sci_phy);
271
272         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
273 done:
274         spin_unlock_irqrestore(&ihost->scic_lock, flags);
275 }
276
277 /**
278  * This method returns the port currently containing this phy. If the phy is
279  *    currently contained by the dummy port, then the phy is considered to not
280  *    be part of a port.
281  * @sci_phy: This parameter specifies the phy for which to retrieve the
282  *    containing port.
283  *
284  * This method returns a handle to a port that contains the supplied phy.
285  * NULL This value is returned if the phy is not part of a real
286  * port (i.e. it's contained in the dummy port). !NULL All other
287  * values indicate a handle/pointer to the port containing the phy.
288  */
289 struct scic_sds_port *phy_get_non_dummy_port(
290         struct scic_sds_phy *sci_phy)
291 {
292         if (scic_sds_port_get_index(sci_phy->owning_port) == SCIC_SDS_DUMMY_PORT)
293                 return NULL;
294
295         return sci_phy->owning_port;
296 }
297
298 /**
299  * This method will assign a port to the phy object.
300  * @out]: sci_phy This parameter specifies the phy for which to assign a port
301  *    object.
302  *
303  *
304  */
305 void scic_sds_phy_set_port(
306         struct scic_sds_phy *sci_phy,
307         struct scic_sds_port *sci_port)
308 {
309         sci_phy->owning_port = sci_port;
310
311         if (sci_phy->bcn_received_while_port_unassigned) {
312                 sci_phy->bcn_received_while_port_unassigned = false;
313                 scic_sds_port_broadcast_change_received(sci_phy->owning_port, sci_phy);
314         }
315 }
316
317 /**
318  * This method will initialize the constructed phy
319  * @sci_phy:
320  * @link_layer_registers:
321  *
322  * enum sci_status
323  */
324 enum sci_status scic_sds_phy_initialize(
325         struct scic_sds_phy *sci_phy,
326         struct scu_transport_layer_registers __iomem *transport_layer_registers,
327         struct scu_link_layer_registers __iomem *link_layer_registers)
328 {
329         /* Perfrom the initialization of the TL hardware */
330         scic_sds_phy_transport_layer_initialization(
331                         sci_phy,
332                         transport_layer_registers);
333
334         /* Perofrm the initialization of the PE hardware */
335         scic_sds_phy_link_layer_initialization(sci_phy, link_layer_registers);
336
337         /*
338          * There is nothing that needs to be done in this state just
339          * transition to the stopped state. */
340         sci_change_state(&sci_phy->sm, SCI_PHY_STOPPED);
341
342         return SCI_SUCCESS;
343 }
344
345 /**
346  * This method assigns the direct attached device ID for this phy.
347  *
348  * @sci_phy The phy for which the direct attached device id is to
349  *       be assigned.
350  * @device_id The direct attached device ID to assign to the phy.
351  *       This will either be the RNi for the device or an invalid RNi if there
352  *       is no current device assigned to the phy.
353  */
354 void scic_sds_phy_setup_transport(
355         struct scic_sds_phy *sci_phy,
356         u32 device_id)
357 {
358         u32 tl_control;
359
360         writel(device_id, &sci_phy->transport_layer_registers->stp_rni);
361
362         /*
363          * The read should guarantee that the first write gets posted
364          * before the next write
365          */
366         tl_control = readl(&sci_phy->transport_layer_registers->control);
367         tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE);
368         writel(tl_control, &sci_phy->transport_layer_registers->control);
369 }
370
371 /**
372  *
373  * @sci_phy: The phy object to be suspended.
374  *
375  * This function will perform the register reads/writes to suspend the SCU
376  * hardware protocol engine. none
377  */
378 static void scic_sds_phy_suspend(
379         struct scic_sds_phy *sci_phy)
380 {
381         u32 scu_sas_pcfg_value;
382
383         scu_sas_pcfg_value =
384                 readl(&sci_phy->link_layer_registers->phy_configuration);
385         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
386         writel(scu_sas_pcfg_value,
387                 &sci_phy->link_layer_registers->phy_configuration);
388
389         scic_sds_phy_setup_transport(
390                         sci_phy,
391                         SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX);
392 }
393
394 void scic_sds_phy_resume(struct scic_sds_phy *sci_phy)
395 {
396         u32 scu_sas_pcfg_value;
397
398         scu_sas_pcfg_value =
399                 readl(&sci_phy->link_layer_registers->phy_configuration);
400         scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
401         writel(scu_sas_pcfg_value,
402                 &sci_phy->link_layer_registers->phy_configuration);
403 }
404
405 void scic_sds_phy_get_sas_address(struct scic_sds_phy *sci_phy,
406                                   struct sci_sas_address *sas_address)
407 {
408         sas_address->high = readl(&sci_phy->link_layer_registers->source_sas_address_high);
409         sas_address->low = readl(&sci_phy->link_layer_registers->source_sas_address_low);
410 }
411
412 void scic_sds_phy_get_attached_sas_address(struct scic_sds_phy *sci_phy,
413                                            struct sci_sas_address *sas_address)
414 {
415         struct sas_identify_frame *iaf;
416         struct isci_phy *iphy = sci_phy_to_iphy(sci_phy);
417
418         iaf = &iphy->frame_rcvd.iaf;
419         memcpy(sas_address, iaf->sas_addr, SAS_ADDR_SIZE);
420 }
421
422 void scic_sds_phy_get_protocols(struct scic_sds_phy *sci_phy,
423                                 struct scic_phy_proto *protocols)
424 {
425         protocols->all =
426                 (u16)(readl(&sci_phy->
427                         link_layer_registers->transmit_identification) &
428                                 0x0000FFFF);
429 }
430
431 enum sci_status scic_sds_phy_start(struct scic_sds_phy *sci_phy)
432 {
433         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
434
435         if (state != SCI_PHY_STOPPED) {
436                 dev_dbg(sciphy_to_dev(sci_phy),
437                          "%s: in wrong state: %d\n", __func__, state);
438                 return SCI_FAILURE_INVALID_STATE;
439         }
440
441         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
442         return SCI_SUCCESS;
443 }
444
445 enum sci_status scic_sds_phy_stop(struct scic_sds_phy *sci_phy)
446 {
447         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
448
449         switch (state) {
450         case SCI_PHY_SUB_INITIAL:
451         case SCI_PHY_SUB_AWAIT_OSSP_EN:
452         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
453         case SCI_PHY_SUB_AWAIT_SAS_POWER:
454         case SCI_PHY_SUB_AWAIT_SATA_POWER:
455         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
456         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
457         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
458         case SCI_PHY_SUB_FINAL:
459         case SCI_PHY_READY:
460                 break;
461         default:
462                 dev_dbg(sciphy_to_dev(sci_phy),
463                         "%s: in wrong state: %d\n", __func__, state);
464                 return SCI_FAILURE_INVALID_STATE;
465         }
466
467         sci_change_state(&sci_phy->sm, SCI_PHY_STOPPED);
468         return SCI_SUCCESS;
469 }
470
471 enum sci_status scic_sds_phy_reset(struct scic_sds_phy *sci_phy)
472 {
473         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
474
475         if (state != SCI_PHY_READY) {
476                 dev_dbg(sciphy_to_dev(sci_phy),
477                         "%s: in wrong state: %d\n", __func__, state);
478                 return SCI_FAILURE_INVALID_STATE;
479         }
480
481         sci_change_state(&sci_phy->sm, SCI_PHY_RESETTING);
482         return SCI_SUCCESS;
483 }
484
485 enum sci_status scic_sds_phy_consume_power_handler(struct scic_sds_phy *sci_phy)
486 {
487         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
488
489         switch (state) {
490         case SCI_PHY_SUB_AWAIT_SAS_POWER: {
491                 u32 enable_spinup;
492
493                 enable_spinup = readl(&sci_phy->link_layer_registers->notify_enable_spinup_control);
494                 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
495                 writel(enable_spinup, &sci_phy->link_layer_registers->notify_enable_spinup_control);
496
497                 /* Change state to the final state this substate machine has run to completion */
498                 sci_change_state(&sci_phy->sm, SCI_PHY_SUB_FINAL);
499
500                 return SCI_SUCCESS;
501         }
502         case SCI_PHY_SUB_AWAIT_SATA_POWER: {
503                 u32 scu_sas_pcfg_value;
504
505                 /* Release the spinup hold state and reset the OOB state machine */
506                 scu_sas_pcfg_value =
507                         readl(&sci_phy->link_layer_registers->phy_configuration);
508                 scu_sas_pcfg_value &=
509                         ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
510                 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
511                 writel(scu_sas_pcfg_value,
512                         &sci_phy->link_layer_registers->phy_configuration);
513
514                 /* Now restart the OOB operation */
515                 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
516                 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
517                 writel(scu_sas_pcfg_value,
518                         &sci_phy->link_layer_registers->phy_configuration);
519
520                 /* Change state to the final state this substate machine has run to completion */
521                 sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN);
522
523                 return SCI_SUCCESS;
524         }
525         default:
526                 dev_dbg(sciphy_to_dev(sci_phy),
527                         "%s: in wrong state: %d\n", __func__, state);
528                 return SCI_FAILURE_INVALID_STATE;
529         }
530 }
531
532 /*
533  * *****************************************************************************
534  * * SCIC SDS PHY HELPER FUNCTIONS
535  * ***************************************************************************** */
536
537
538 /**
539  *
540  * @sci_phy: The phy object that received SAS PHY DETECTED.
541  *
542  * This method continues the link training for the phy as if it were a SAS PHY
543  * instead of a SATA PHY. This is done because the completion queue had a SAS
544  * PHY DETECTED event when the state machine was expecting a SATA PHY event.
545  * none
546  */
547 static void scic_sds_phy_start_sas_link_training(
548         struct scic_sds_phy *sci_phy)
549 {
550         u32 phy_control;
551
552         phy_control =
553                 readl(&sci_phy->link_layer_registers->phy_configuration);
554         phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
555         writel(phy_control,
556                 &sci_phy->link_layer_registers->phy_configuration);
557
558         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN);
559
560         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SAS;
561 }
562
563 /**
564  *
565  * @sci_phy: The phy object that received a SATA SPINUP HOLD event
566  *
567  * This method continues the link training for the phy as if it were a SATA PHY
568  * instead of a SAS PHY.  This is done because the completion queue had a SATA
569  * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
570  */
571 static void scic_sds_phy_start_sata_link_training(
572         struct scic_sds_phy *sci_phy)
573 {
574         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER);
575
576         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
577 }
578
579 /**
580  * scic_sds_phy_complete_link_training - perform processing common to
581  *    all protocols upon completion of link training.
582  * @sci_phy: This parameter specifies the phy object for which link training
583  *    has completed.
584  * @max_link_rate: This parameter specifies the maximum link rate to be
585  *    associated with this phy.
586  * @next_state: This parameter specifies the next state for the phy's starting
587  *    sub-state machine.
588  *
589  */
590 static void scic_sds_phy_complete_link_training(
591         struct scic_sds_phy *sci_phy,
592         enum sas_linkrate max_link_rate,
593         u32 next_state)
594 {
595         sci_phy->max_negotiated_speed = max_link_rate;
596
597         sci_change_state(&sci_phy->sm, next_state);
598 }
599
600 enum sci_status scic_sds_phy_event_handler(struct scic_sds_phy *sci_phy,
601                                            u32 event_code)
602 {
603         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
604
605         switch (state) {
606         case SCI_PHY_SUB_AWAIT_OSSP_EN:
607                 switch (scu_get_event_code(event_code)) {
608                 case SCU_EVENT_SAS_PHY_DETECTED:
609                         scic_sds_phy_start_sas_link_training(sci_phy);
610                         sci_phy->is_in_link_training = true;
611                         break;
612                 case SCU_EVENT_SATA_SPINUP_HOLD:
613                         scic_sds_phy_start_sata_link_training(sci_phy);
614                         sci_phy->is_in_link_training = true;
615                         break;
616                 default:
617                         dev_dbg(sciphy_to_dev(sci_phy),
618                                 "%s: PHY starting substate machine received "
619                                 "unexpected event_code %x\n",
620                                 __func__,
621                                 event_code);
622                         return SCI_FAILURE;
623                 }
624                 return SCI_SUCCESS;
625         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
626                 switch (scu_get_event_code(event_code)) {
627                 case SCU_EVENT_SAS_PHY_DETECTED:
628                         /*
629                          * Why is this being reported again by the controller?
630                          * We would re-enter this state so just stay here */
631                         break;
632                 case SCU_EVENT_SAS_15:
633                 case SCU_EVENT_SAS_15_SSC:
634                         scic_sds_phy_complete_link_training(
635                                 sci_phy,
636                                 SAS_LINK_RATE_1_5_GBPS,
637                                 SCI_PHY_SUB_AWAIT_IAF_UF);
638                         break;
639                 case SCU_EVENT_SAS_30:
640                 case SCU_EVENT_SAS_30_SSC:
641                         scic_sds_phy_complete_link_training(
642                                 sci_phy,
643                                 SAS_LINK_RATE_3_0_GBPS,
644                                 SCI_PHY_SUB_AWAIT_IAF_UF);
645                         break;
646                 case SCU_EVENT_SAS_60:
647                 case SCU_EVENT_SAS_60_SSC:
648                         scic_sds_phy_complete_link_training(
649                                 sci_phy,
650                                 SAS_LINK_RATE_6_0_GBPS,
651                                 SCI_PHY_SUB_AWAIT_IAF_UF);
652                         break;
653                 case SCU_EVENT_SATA_SPINUP_HOLD:
654                         /*
655                          * We were doing SAS PHY link training and received a SATA PHY event
656                          * continue OOB/SN as if this were a SATA PHY */
657                         scic_sds_phy_start_sata_link_training(sci_phy);
658                         break;
659                 case SCU_EVENT_LINK_FAILURE:
660                         /* Link failure change state back to the starting state */
661                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
662                         break;
663                 default:
664                         dev_warn(sciphy_to_dev(sci_phy),
665                                  "%s: PHY starting substate machine received "
666                                  "unexpected event_code %x\n",
667                                  __func__, event_code);
668
669                         return SCI_FAILURE;
670                         break;
671                 }
672                 return SCI_SUCCESS;
673         case SCI_PHY_SUB_AWAIT_IAF_UF:
674                 switch (scu_get_event_code(event_code)) {
675                 case SCU_EVENT_SAS_PHY_DETECTED:
676                         /* Backup the state machine */
677                         scic_sds_phy_start_sas_link_training(sci_phy);
678                         break;
679                 case SCU_EVENT_SATA_SPINUP_HOLD:
680                         /* We were doing SAS PHY link training and received a
681                          * SATA PHY event continue OOB/SN as if this were a
682                          * SATA PHY
683                          */
684                         scic_sds_phy_start_sata_link_training(sci_phy);
685                         break;
686                 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
687                 case SCU_EVENT_LINK_FAILURE:
688                 case SCU_EVENT_HARD_RESET_RECEIVED:
689                         /* Start the oob/sn state machine over again */
690                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
691                         break;
692                 default:
693                         dev_warn(sciphy_to_dev(sci_phy),
694                                  "%s: PHY starting substate machine received "
695                                  "unexpected event_code %x\n",
696                                  __func__, event_code);
697                         return SCI_FAILURE;
698                 }
699                 return SCI_SUCCESS;
700         case SCI_PHY_SUB_AWAIT_SAS_POWER:
701                 switch (scu_get_event_code(event_code)) {
702                 case SCU_EVENT_LINK_FAILURE:
703                         /* Link failure change state back to the starting state */
704                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
705                         break;
706                 default:
707                         dev_warn(sciphy_to_dev(sci_phy),
708                                 "%s: PHY starting substate machine received unexpected "
709                                 "event_code %x\n",
710                                 __func__,
711                                 event_code);
712                         return SCI_FAILURE;
713                 }
714                 return SCI_SUCCESS;
715         case SCI_PHY_SUB_AWAIT_SATA_POWER:
716                 switch (scu_get_event_code(event_code)) {
717                 case SCU_EVENT_LINK_FAILURE:
718                         /* Link failure change state back to the starting state */
719                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
720                         break;
721                 case SCU_EVENT_SATA_SPINUP_HOLD:
722                         /* These events are received every 10ms and are
723                          * expected while in this state
724                          */
725                         break;
726
727                 case SCU_EVENT_SAS_PHY_DETECTED:
728                         /* There has been a change in the phy type before OOB/SN for the
729                          * SATA finished start down the SAS link traning path.
730                          */
731                         scic_sds_phy_start_sas_link_training(sci_phy);
732                         break;
733
734                 default:
735                         dev_warn(sciphy_to_dev(sci_phy),
736                                  "%s: PHY starting substate machine received "
737                                  "unexpected event_code %x\n",
738                                  __func__, event_code);
739
740                         return SCI_FAILURE;
741                 }
742                 return SCI_SUCCESS;
743         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
744                 switch (scu_get_event_code(event_code)) {
745                 case SCU_EVENT_LINK_FAILURE:
746                         /* Link failure change state back to the starting state */
747                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
748                         break;
749                 case SCU_EVENT_SATA_SPINUP_HOLD:
750                         /* These events might be received since we dont know how many may be in
751                          * the completion queue while waiting for power
752                          */
753                         break;
754                 case SCU_EVENT_SATA_PHY_DETECTED:
755                         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
756
757                         /* We have received the SATA PHY notification change state */
758                         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
759                         break;
760                 case SCU_EVENT_SAS_PHY_DETECTED:
761                         /* There has been a change in the phy type before OOB/SN for the
762                          * SATA finished start down the SAS link traning path.
763                          */
764                         scic_sds_phy_start_sas_link_training(sci_phy);
765                         break;
766                 default:
767                         dev_warn(sciphy_to_dev(sci_phy),
768                                  "%s: PHY starting substate machine received "
769                                  "unexpected event_code %x\n",
770                                  __func__,
771                                  event_code);
772
773                         return SCI_FAILURE;;
774                 }
775                 return SCI_SUCCESS;
776         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
777                 switch (scu_get_event_code(event_code)) {
778                 case SCU_EVENT_SATA_PHY_DETECTED:
779                         /*
780                          * The hardware reports multiple SATA PHY detected events
781                          * ignore the extras */
782                         break;
783                 case SCU_EVENT_SATA_15:
784                 case SCU_EVENT_SATA_15_SSC:
785                         scic_sds_phy_complete_link_training(
786                                 sci_phy,
787                                 SAS_LINK_RATE_1_5_GBPS,
788                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
789                         break;
790                 case SCU_EVENT_SATA_30:
791                 case SCU_EVENT_SATA_30_SSC:
792                         scic_sds_phy_complete_link_training(
793                                 sci_phy,
794                                 SAS_LINK_RATE_3_0_GBPS,
795                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
796                         break;
797                 case SCU_EVENT_SATA_60:
798                 case SCU_EVENT_SATA_60_SSC:
799                         scic_sds_phy_complete_link_training(
800                                 sci_phy,
801                                 SAS_LINK_RATE_6_0_GBPS,
802                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
803                         break;
804                 case SCU_EVENT_LINK_FAILURE:
805                         /* Link failure change state back to the starting state */
806                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
807                         break;
808                 case SCU_EVENT_SAS_PHY_DETECTED:
809                         /*
810                          * There has been a change in the phy type before OOB/SN for the
811                          * SATA finished start down the SAS link traning path. */
812                         scic_sds_phy_start_sas_link_training(sci_phy);
813                         break;
814                 default:
815                         dev_warn(sciphy_to_dev(sci_phy),
816                                  "%s: PHY starting substate machine received "
817                                  "unexpected event_code %x\n",
818                                  __func__, event_code);
819
820                         return SCI_FAILURE;
821                 }
822
823                 return SCI_SUCCESS;
824         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
825                 switch (scu_get_event_code(event_code)) {
826                 case SCU_EVENT_SATA_PHY_DETECTED:
827                         /* Backup the state machine */
828                         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
829                         break;
830
831                 case SCU_EVENT_LINK_FAILURE:
832                         /* Link failure change state back to the starting state */
833                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
834                         break;
835
836                 default:
837                         dev_warn(sciphy_to_dev(sci_phy),
838                                  "%s: PHY starting substate machine received "
839                                  "unexpected event_code %x\n",
840                                  __func__,
841                                  event_code);
842
843                         return SCI_FAILURE;
844                 }
845                 return SCI_SUCCESS;
846         case SCI_PHY_READY:
847                 switch (scu_get_event_code(event_code)) {
848                 case SCU_EVENT_LINK_FAILURE:
849                         /* Link failure change state back to the starting state */
850                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
851                         break;
852                 case SCU_EVENT_BROADCAST_CHANGE:
853                         /* Broadcast change received. Notify the port. */
854                         if (phy_get_non_dummy_port(sci_phy) != NULL)
855                                 scic_sds_port_broadcast_change_received(sci_phy->owning_port, sci_phy);
856                         else
857                                 sci_phy->bcn_received_while_port_unassigned = true;
858                         break;
859                 default:
860                         dev_warn(sciphy_to_dev(sci_phy),
861                                  "%sP SCIC PHY 0x%p ready state machine received "
862                                  "unexpected event_code %x\n",
863                                  __func__, sci_phy, event_code);
864                         return SCI_FAILURE_INVALID_STATE;
865                 }
866                 return SCI_SUCCESS;
867         case SCI_PHY_RESETTING:
868                 switch (scu_get_event_code(event_code)) {
869                 case SCU_EVENT_HARD_RESET_TRANSMITTED:
870                         /* Link failure change state back to the starting state */
871                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
872                         break;
873                 default:
874                         dev_warn(sciphy_to_dev(sci_phy),
875                                  "%s: SCIC PHY 0x%p resetting state machine received "
876                                  "unexpected event_code %x\n",
877                                  __func__, sci_phy, event_code);
878
879                         return SCI_FAILURE_INVALID_STATE;
880                         break;
881                 }
882                 return SCI_SUCCESS;
883         default:
884                 dev_dbg(sciphy_to_dev(sci_phy),
885                         "%s: in wrong state: %d\n", __func__, state);
886                 return SCI_FAILURE_INVALID_STATE;
887         }
888 }
889
890 enum sci_status scic_sds_phy_frame_handler(struct scic_sds_phy *sci_phy,
891                                            u32 frame_index)
892 {
893         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
894         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
895         enum sci_status result;
896         unsigned long flags;
897
898         switch (state) {
899         case SCI_PHY_SUB_AWAIT_IAF_UF: {
900                 u32 *frame_words;
901                 struct sas_identify_frame iaf;
902                 struct isci_phy *iphy = sci_phy_to_iphy(sci_phy);
903
904                 result = scic_sds_unsolicited_frame_control_get_header(&scic->uf_control,
905                                                                        frame_index,
906                                                                        (void **)&frame_words);
907
908                 if (result != SCI_SUCCESS)
909                         return result;
910
911                 sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32));
912                 if (iaf.frame_type == 0) {
913                         u32 state;
914
915                         spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
916                         memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf));
917                         spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
918                         if (iaf.smp_tport) {
919                                 /* We got the IAF for an expander PHY go to the final
920                                  * state since there are no power requirements for
921                                  * expander phys.
922                                  */
923                                 state = SCI_PHY_SUB_FINAL;
924                         } else {
925                                 /* We got the IAF we can now go to the await spinup
926                                  * semaphore state
927                                  */
928                                 state = SCI_PHY_SUB_AWAIT_SAS_POWER;
929                         }
930                         sci_change_state(&sci_phy->sm, state);
931                         result = SCI_SUCCESS;
932                 } else
933                         dev_warn(sciphy_to_dev(sci_phy),
934                                 "%s: PHY starting substate machine received "
935                                 "unexpected frame id %x\n",
936                                 __func__, frame_index);
937
938                 scic_sds_controller_release_frame(scic, frame_index);
939                 return result;
940         }
941         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: {
942                 struct dev_to_host_fis *frame_header;
943                 u32 *fis_frame_data;
944                 struct isci_phy *iphy = sci_phy_to_iphy(sci_phy);
945
946                 result = scic_sds_unsolicited_frame_control_get_header(
947                         &(scic_sds_phy_get_controller(sci_phy)->uf_control),
948                         frame_index,
949                         (void **)&frame_header);
950
951                 if (result != SCI_SUCCESS)
952                         return result;
953
954                 if ((frame_header->fis_type == FIS_REGD2H) &&
955                     !(frame_header->status & ATA_BUSY)) {
956                         scic_sds_unsolicited_frame_control_get_buffer(&scic->uf_control,
957                                                                       frame_index,
958                                                                       (void **)&fis_frame_data);
959
960                         spin_lock_irqsave(&iphy->sas_phy.frame_rcvd_lock, flags);
961                         scic_sds_controller_copy_sata_response(&iphy->frame_rcvd.fis,
962                                                                frame_header,
963                                                                fis_frame_data);
964                         spin_unlock_irqrestore(&iphy->sas_phy.frame_rcvd_lock, flags);
965
966                         /* got IAF we can now go to the await spinup semaphore state */
967                         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_FINAL);
968
969                         result = SCI_SUCCESS;
970                 } else
971                         dev_warn(sciphy_to_dev(sci_phy),
972                                  "%s: PHY starting substate machine received "
973                                  "unexpected frame id %x\n",
974                                  __func__, frame_index);
975
976                 /* Regardless of the result we are done with this frame with it */
977                 scic_sds_controller_release_frame(scic, frame_index);
978
979                 return result;
980         }
981         default:
982                 dev_dbg(sciphy_to_dev(sci_phy),
983                         "%s: in wrong state: %d\n", __func__, state);
984                 return SCI_FAILURE_INVALID_STATE;
985         }
986         
987 }
988
989 static void scic_sds_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm)
990 {
991         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
992
993         /* This is just an temporary state go off to the starting state */
994         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN);
995 }
996
997 static void scic_sds_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm)
998 {
999         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1000         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
1001
1002         scic_sds_controller_power_control_queue_insert(scic, sci_phy);
1003 }
1004
1005 static void scic_sds_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm)
1006 {
1007         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1008         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
1009
1010         scic_sds_controller_power_control_queue_remove(scic, sci_phy);
1011 }
1012
1013 static void scic_sds_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm)
1014 {
1015         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1016         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
1017
1018         scic_sds_controller_power_control_queue_insert(scic, sci_phy);
1019 }
1020
1021 static void scic_sds_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm)
1022 {
1023         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1024         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
1025
1026         scic_sds_controller_power_control_queue_remove(scic, sci_phy);
1027 }
1028
1029 static void scic_sds_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm)
1030 {
1031         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1032
1033         sci_mod_timer(&sci_phy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1034 }
1035
1036 static void scic_sds_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm)
1037 {
1038         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1039
1040         sci_del_timer(&sci_phy->sata_timer);
1041 }
1042
1043 static void scic_sds_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm)
1044 {
1045         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1046
1047         sci_mod_timer(&sci_phy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1048 }
1049
1050 static void scic_sds_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm)
1051 {
1052         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1053
1054         sci_del_timer(&sci_phy->sata_timer);
1055 }
1056
1057 static void scic_sds_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm)
1058 {
1059         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1060
1061         if (scic_sds_port_link_detected(sci_phy->owning_port, sci_phy)) {
1062
1063                 /*
1064                  * Clear the PE suspend condition so we can actually
1065                  * receive SIG FIS
1066                  * The hardware will not respond to the XRDY until the PE
1067                  * suspend condition is cleared.
1068                  */
1069                 scic_sds_phy_resume(sci_phy);
1070
1071                 sci_mod_timer(&sci_phy->sata_timer,
1072                               SCIC_SDS_SIGNATURE_FIS_TIMEOUT);
1073         } else
1074                 sci_phy->is_in_link_training = false;
1075 }
1076
1077 static void scic_sds_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm)
1078 {
1079         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1080
1081         sci_del_timer(&sci_phy->sata_timer);
1082 }
1083
1084 static void scic_sds_phy_starting_final_substate_enter(struct sci_base_state_machine *sm)
1085 {
1086         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1087
1088         /* State machine has run to completion so exit out and change
1089          * the base state machine to the ready state
1090          */
1091         sci_change_state(&sci_phy->sm, SCI_PHY_READY);
1092 }
1093
1094 /**
1095  *
1096  * @sci_phy: This is the struct scic_sds_phy object to stop.
1097  *
1098  * This method will stop the struct scic_sds_phy object. This does not reset the
1099  * protocol engine it just suspends it and places it in a state where it will
1100  * not cause the end device to power up. none
1101  */
1102 static void scu_link_layer_stop_protocol_engine(
1103         struct scic_sds_phy *sci_phy)
1104 {
1105         u32 scu_sas_pcfg_value;
1106         u32 enable_spinup_value;
1107
1108         /* Suspend the protocol engine and place it in a sata spinup hold state */
1109         scu_sas_pcfg_value =
1110                 readl(&sci_phy->link_layer_registers->phy_configuration);
1111         scu_sas_pcfg_value |=
1112                 (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1113                  SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) |
1114                  SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD));
1115         writel(scu_sas_pcfg_value,
1116                &sci_phy->link_layer_registers->phy_configuration);
1117
1118         /* Disable the notify enable spinup primitives */
1119         enable_spinup_value = readl(&sci_phy->link_layer_registers->notify_enable_spinup_control);
1120         enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
1121         writel(enable_spinup_value, &sci_phy->link_layer_registers->notify_enable_spinup_control);
1122 }
1123
1124 /**
1125  *
1126  *
1127  * This method will start the OOB/SN state machine for this struct scic_sds_phy object.
1128  */
1129 static void scu_link_layer_start_oob(
1130         struct scic_sds_phy *sci_phy)
1131 {
1132         u32 scu_sas_pcfg_value;
1133
1134         scu_sas_pcfg_value =
1135                 readl(&sci_phy->link_layer_registers->phy_configuration);
1136         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1137         scu_sas_pcfg_value &=
1138                 ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1139                 SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
1140         writel(scu_sas_pcfg_value,
1141                &sci_phy->link_layer_registers->phy_configuration);
1142 }
1143
1144 /**
1145  *
1146  *
1147  * This method will transmit a hard reset request on the specified phy. The SCU
1148  * hardware requires that we reset the OOB state machine and set the hard reset
1149  * bit in the phy configuration register. We then must start OOB over with the
1150  * hard reset bit set.
1151  */
1152 static void scu_link_layer_tx_hard_reset(
1153         struct scic_sds_phy *sci_phy)
1154 {
1155         u32 phy_configuration_value;
1156
1157         /*
1158          * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1159          * to the starting state. */
1160         phy_configuration_value =
1161                 readl(&sci_phy->link_layer_registers->phy_configuration);
1162         phy_configuration_value |=
1163                 (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) |
1164                  SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
1165         writel(phy_configuration_value,
1166                &sci_phy->link_layer_registers->phy_configuration);
1167
1168         /* Now take the OOB state machine out of reset */
1169         phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1170         phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
1171         writel(phy_configuration_value,
1172                &sci_phy->link_layer_registers->phy_configuration);
1173 }
1174
1175 static void scic_sds_phy_stopped_state_enter(struct sci_base_state_machine *sm)
1176 {
1177         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1178
1179         /*
1180          * @todo We need to get to the controller to place this PE in a
1181          * reset state
1182          */
1183         sci_del_timer(&sci_phy->sata_timer);
1184
1185         scu_link_layer_stop_protocol_engine(sci_phy);
1186
1187         if (sci_phy->sm.previous_state_id != SCI_PHY_INITIAL)
1188                 scic_sds_controller_link_down(scic_sds_phy_get_controller(sci_phy),
1189                                               phy_get_non_dummy_port(sci_phy),
1190                                               sci_phy);
1191 }
1192
1193 static void scic_sds_phy_starting_state_enter(struct sci_base_state_machine *sm)
1194 {
1195         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1196
1197         scu_link_layer_stop_protocol_engine(sci_phy);
1198         scu_link_layer_start_oob(sci_phy);
1199
1200         /* We don't know what kind of phy we are going to be just yet */
1201         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1202         sci_phy->bcn_received_while_port_unassigned = false;
1203
1204         if (sci_phy->sm.previous_state_id == SCI_PHY_READY)
1205                 scic_sds_controller_link_down(scic_sds_phy_get_controller(sci_phy),
1206                                               phy_get_non_dummy_port(sci_phy),
1207                                               sci_phy);
1208
1209         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_INITIAL);
1210 }
1211
1212 static void scic_sds_phy_ready_state_enter(struct sci_base_state_machine *sm)
1213 {
1214         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1215
1216         scic_sds_controller_link_up(scic_sds_phy_get_controller(sci_phy),
1217                                     phy_get_non_dummy_port(sci_phy),
1218                                     sci_phy);
1219
1220 }
1221
1222 static void scic_sds_phy_ready_state_exit(struct sci_base_state_machine *sm)
1223 {
1224         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1225
1226         scic_sds_phy_suspend(sci_phy);
1227 }
1228
1229 static void scic_sds_phy_resetting_state_enter(struct sci_base_state_machine *sm)
1230 {
1231         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1232
1233         /* The phy is being reset, therefore deactivate it from the port.  In
1234          * the resetting state we don't notify the user regarding link up and
1235          * link down notifications
1236          */
1237         scic_sds_port_deactivate_phy(sci_phy->owning_port, sci_phy, false);
1238
1239         if (sci_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1240                 scu_link_layer_tx_hard_reset(sci_phy);
1241         } else {
1242                 /* The SCU does not need to have a discrete reset state so
1243                  * just go back to the starting state.
1244                  */
1245                 sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
1246         }
1247 }
1248
1249 static const struct sci_base_state scic_sds_phy_state_table[] = {
1250         [SCI_PHY_INITIAL] = { },
1251         [SCI_PHY_STOPPED] = {
1252                 .enter_state = scic_sds_phy_stopped_state_enter,
1253         },
1254         [SCI_PHY_STARTING] = {
1255                 .enter_state = scic_sds_phy_starting_state_enter,
1256         },
1257         [SCI_PHY_SUB_INITIAL] = {
1258                 .enter_state = scic_sds_phy_starting_initial_substate_enter,
1259         },
1260         [SCI_PHY_SUB_AWAIT_OSSP_EN] = { },
1261         [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { },
1262         [SCI_PHY_SUB_AWAIT_IAF_UF] = { },
1263         [SCI_PHY_SUB_AWAIT_SAS_POWER] = {
1264                 .enter_state = scic_sds_phy_starting_await_sas_power_substate_enter,
1265                 .exit_state  = scic_sds_phy_starting_await_sas_power_substate_exit,
1266         },
1267         [SCI_PHY_SUB_AWAIT_SATA_POWER] = {
1268                 .enter_state = scic_sds_phy_starting_await_sata_power_substate_enter,
1269                 .exit_state  = scic_sds_phy_starting_await_sata_power_substate_exit
1270         },
1271         [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = {
1272                 .enter_state = scic_sds_phy_starting_await_sata_phy_substate_enter,
1273                 .exit_state  = scic_sds_phy_starting_await_sata_phy_substate_exit
1274         },
1275         [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = {
1276                 .enter_state = scic_sds_phy_starting_await_sata_speed_substate_enter,
1277                 .exit_state  = scic_sds_phy_starting_await_sata_speed_substate_exit
1278         },
1279         [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = {
1280                 .enter_state = scic_sds_phy_starting_await_sig_fis_uf_substate_enter,
1281                 .exit_state  = scic_sds_phy_starting_await_sig_fis_uf_substate_exit
1282         },
1283         [SCI_PHY_SUB_FINAL] = {
1284                 .enter_state = scic_sds_phy_starting_final_substate_enter,
1285         },
1286         [SCI_PHY_READY] = {
1287                 .enter_state = scic_sds_phy_ready_state_enter,
1288                 .exit_state = scic_sds_phy_ready_state_exit,
1289         },
1290         [SCI_PHY_RESETTING] = {
1291                 .enter_state = scic_sds_phy_resetting_state_enter,
1292         },
1293         [SCI_PHY_FINAL] = { },
1294 };
1295
1296 void scic_sds_phy_construct(struct scic_sds_phy *sci_phy,
1297                             struct scic_sds_port *owning_port, u8 phy_index)
1298 {
1299         sci_init_sm(&sci_phy->sm, scic_sds_phy_state_table, SCI_PHY_INITIAL);
1300
1301         /* Copy the rest of the input data to our locals */
1302         sci_phy->owning_port = owning_port;
1303         sci_phy->phy_index = phy_index;
1304         sci_phy->bcn_received_while_port_unassigned = false;
1305         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1306         sci_phy->link_layer_registers = NULL;
1307         sci_phy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN;
1308
1309         /* Create the SIGNATURE FIS Timeout timer for this phy */
1310         sci_init_timer(&sci_phy->sata_timer, phy_sata_timeout);
1311 }
1312
1313 void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
1314 {
1315         union scic_oem_parameters oem;
1316         u64 sci_sas_addr;
1317         __be64 sas_addr;
1318
1319         scic_oem_parameters_get(&ihost->sci, &oem);
1320         sci_sas_addr = oem.sds1.phys[index].sas_address.high;
1321         sci_sas_addr <<= 32;
1322         sci_sas_addr |= oem.sds1.phys[index].sas_address.low;
1323         sas_addr = cpu_to_be64(sci_sas_addr);
1324         memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
1325
1326         iphy->isci_port = NULL;
1327         iphy->sas_phy.enabled = 0;
1328         iphy->sas_phy.id = index;
1329         iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
1330         iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
1331         iphy->sas_phy.ha = &ihost->sas_ha;
1332         iphy->sas_phy.lldd_phy = iphy;
1333         iphy->sas_phy.enabled = 1;
1334         iphy->sas_phy.class = SAS;
1335         iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
1336         iphy->sas_phy.tproto = 0;
1337         iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
1338         iphy->sas_phy.role = PHY_ROLE_INITIATOR;
1339         iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
1340         iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
1341         memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
1342 }
1343
1344
1345 /**
1346  * isci_phy_control() - This function is one of the SAS Domain Template
1347  *    functions. This is a phy management function.
1348  * @phy: This parameter specifies the sphy being controlled.
1349  * @func: This parameter specifies the phy control function being invoked.
1350  * @buf: This parameter is specific to the phy function being invoked.
1351  *
1352  * status, zero indicates success.
1353  */
1354 int isci_phy_control(struct asd_sas_phy *sas_phy,
1355                      enum phy_func func,
1356                      void *buf)
1357 {
1358         int ret = 0;
1359         struct isci_phy *iphy = sas_phy->lldd_phy;
1360         struct isci_port *iport = iphy->isci_port;
1361         struct isci_host *ihost = sas_phy->ha->lldd_ha;
1362         unsigned long flags;
1363
1364         dev_dbg(&ihost->pdev->dev,
1365                 "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1366                 __func__, sas_phy, func, buf, iphy, iport);
1367
1368         switch (func) {
1369         case PHY_FUNC_DISABLE:
1370                 spin_lock_irqsave(&ihost->scic_lock, flags);
1371                 scic_sds_phy_stop(&iphy->sci);
1372                 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1373                 break;
1374
1375         case PHY_FUNC_LINK_RESET:
1376                 spin_lock_irqsave(&ihost->scic_lock, flags);
1377                 scic_sds_phy_stop(&iphy->sci);
1378                 scic_sds_phy_start(&iphy->sci);
1379                 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1380                 break;
1381
1382         case PHY_FUNC_HARD_RESET:
1383                 if (!iport)
1384                         return -ENODEV;
1385
1386                 /* Perform the port reset. */
1387                 ret = isci_port_perform_hard_reset(ihost, iport, iphy);
1388
1389                 break;
1390
1391         default:
1392                 dev_dbg(&ihost->pdev->dev,
1393                            "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1394                            __func__, sas_phy, func);
1395                 ret = -ENOSYS;
1396                 break;
1397         }
1398         return ret;
1399 }