9de21c7193518ab04db74018df9c20e9e9b129ef
[linux-2.6.git] / drivers / scsi / isci / phy.c
1 /*
2  * This file is provided under a dual BSD/GPLv2 license.  When using or
3  * redistributing this file, you may do so under either license.
4  *
5  * GPL LICENSE SUMMARY
6  *
7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * BSD LICENSE
25  *
26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27  * All rights reserved.
28  *
29  * Redistribution and use in source and binary forms, with or without
30  * modification, are permitted provided that the following conditions
31  * are met:
32  *
33  *   * Redistributions of source code must retain the above copyright
34  *     notice, this list of conditions and the following disclaimer.
35  *   * Redistributions in binary form must reproduce the above copyright
36  *     notice, this list of conditions and the following disclaimer in
37  *     the documentation and/or other materials provided with the
38  *     distribution.
39  *   * Neither the name of Intel Corporation nor the names of its
40  *     contributors may be used to endorse or promote products derived
41  *     from this software without specific prior written permission.
42  *
43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54  */
55
56 #include "isci.h"
57 #include "host.h"
58 #include "phy.h"
59 #include "scu_event_codes.h"
60 #include "probe_roms.h"
61
62 /* Maximum arbitration wait time in micro-seconds */
63 #define SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME  (700)
64
65 enum sas_linkrate sci_phy_linkrate(struct scic_sds_phy *sci_phy)
66 {
67         return sci_phy->max_negotiated_speed;
68 }
69
70 /*
71  * *****************************************************************************
72  * * SCIC SDS PHY Internal Methods
73  * ***************************************************************************** */
74
75 /**
76  * This method will initialize the phy transport layer registers
77  * @sci_phy:
78  * @transport_layer_registers
79  *
80  * enum sci_status
81  */
82 static enum sci_status scic_sds_phy_transport_layer_initialization(
83         struct scic_sds_phy *sci_phy,
84         struct scu_transport_layer_registers __iomem *transport_layer_registers)
85 {
86         u32 tl_control;
87
88         sci_phy->transport_layer_registers = transport_layer_registers;
89
90         writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX,
91                 &sci_phy->transport_layer_registers->stp_rni);
92
93         /*
94          * Hardware team recommends that we enable the STP prefetch for all
95          * transports
96          */
97         tl_control = readl(&sci_phy->transport_layer_registers->control);
98         tl_control |= SCU_TLCR_GEN_BIT(STP_WRITE_DATA_PREFETCH);
99         writel(tl_control, &sci_phy->transport_layer_registers->control);
100
101         return SCI_SUCCESS;
102 }
103
104 /**
105  * This method will initialize the phy link layer registers
106  * @sci_phy:
107  * @link_layer_registers:
108  *
109  * enum sci_status
110  */
111 static enum sci_status
112 scic_sds_phy_link_layer_initialization(struct scic_sds_phy *sci_phy,
113                                        struct scu_link_layer_registers __iomem *link_layer_registers)
114 {
115         struct scic_sds_controller *scic =
116                 sci_phy->owning_port->owning_controller;
117         int phy_idx = sci_phy->phy_index;
118         struct sci_phy_user_params *phy_user =
119                 &scic->user_parameters.sds1.phys[phy_idx];
120         struct sci_phy_oem_params *phy_oem =
121                 &scic->oem_parameters.sds1.phys[phy_idx];
122         u32 phy_configuration;
123         struct scic_phy_cap phy_cap;
124         u32 parity_check = 0;
125         u32 parity_count = 0;
126         u32 llctl, link_rate;
127         u32 clksm_value = 0;
128
129         sci_phy->link_layer_registers = link_layer_registers;
130
131         /* Set our IDENTIFY frame data */
132         #define SCI_END_DEVICE 0x01
133
134         writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) |
135                SCU_SAS_TIID_GEN_BIT(SSP_INITIATOR) |
136                SCU_SAS_TIID_GEN_BIT(STP_INITIATOR) |
137                SCU_SAS_TIID_GEN_BIT(DA_SATA_HOST) |
138                SCU_SAS_TIID_GEN_VAL(DEVICE_TYPE, SCI_END_DEVICE),
139                &sci_phy->link_layer_registers->transmit_identification);
140
141         /* Write the device SAS Address */
142         writel(0xFEDCBA98,
143                &sci_phy->link_layer_registers->sas_device_name_high);
144         writel(phy_idx, &sci_phy->link_layer_registers->sas_device_name_low);
145
146         /* Write the source SAS Address */
147         writel(phy_oem->sas_address.high,
148                 &sci_phy->link_layer_registers->source_sas_address_high);
149         writel(phy_oem->sas_address.low,
150                 &sci_phy->link_layer_registers->source_sas_address_low);
151
152         /* Clear and Set the PHY Identifier */
153         writel(0, &sci_phy->link_layer_registers->identify_frame_phy_id);
154         writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx),
155                 &sci_phy->link_layer_registers->identify_frame_phy_id);
156
157         /* Change the initial state of the phy configuration register */
158         phy_configuration =
159                 readl(&sci_phy->link_layer_registers->phy_configuration);
160
161         /* Hold OOB state machine in reset */
162         phy_configuration |=  SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
163         writel(phy_configuration,
164                 &sci_phy->link_layer_registers->phy_configuration);
165
166         /* Configure the SNW capabilities */
167         phy_cap.all = 0;
168         phy_cap.start = 1;
169         phy_cap.gen3_no_ssc = 1;
170         phy_cap.gen2_no_ssc = 1;
171         phy_cap.gen1_no_ssc = 1;
172         if (scic->oem_parameters.sds1.controller.do_enable_ssc == true) {
173                 phy_cap.gen3_ssc = 1;
174                 phy_cap.gen2_ssc = 1;
175                 phy_cap.gen1_ssc = 1;
176         }
177
178         /*
179          * The SAS specification indicates that the phy_capabilities that
180          * are transmitted shall have an even parity.  Calculate the parity. */
181         parity_check = phy_cap.all;
182         while (parity_check != 0) {
183                 if (parity_check & 0x1)
184                         parity_count++;
185                 parity_check >>= 1;
186         }
187
188         /*
189          * If parity indicates there are an odd number of bits set, then
190          * set the parity bit to 1 in the phy capabilities. */
191         if ((parity_count % 2) != 0)
192                 phy_cap.parity = 1;
193
194         writel(phy_cap.all, &sci_phy->link_layer_registers->phy_capabilities);
195
196         /* Set the enable spinup period but disable the ability to send
197          * notify enable spinup
198          */
199         writel(SCU_ENSPINUP_GEN_VAL(COUNT,
200                         phy_user->notify_enable_spin_up_insertion_frequency),
201                 &sci_phy->link_layer_registers->notify_enable_spinup_control);
202
203         /* Write the ALIGN Insertion Ferequency for connected phy and
204          * inpendent of connected state
205          */
206         clksm_value = SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(CONNECTED,
207                         phy_user->in_connection_align_insertion_frequency);
208
209         clksm_value |= SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(GENERAL,
210                         phy_user->align_insertion_frequency);
211
212         writel(clksm_value, &sci_phy->link_layer_registers->clock_skew_management);
213
214         /* @todo Provide a way to write this register correctly */
215         writel(0x02108421,
216                 &sci_phy->link_layer_registers->afe_lookup_table_control);
217
218         llctl = SCU_SAS_LLCTL_GEN_VAL(NO_OUTBOUND_TASK_TIMEOUT,
219                 (u8)scic->user_parameters.sds1.no_outbound_task_timeout);
220
221         switch(phy_user->max_speed_generation) {
222         case SCIC_SDS_PARM_GEN3_SPEED:
223                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3;
224                 break;
225         case SCIC_SDS_PARM_GEN2_SPEED:
226                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2;
227                 break;
228         default:
229                 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1;
230                 break;
231         }
232         llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate);
233         writel(llctl, &sci_phy->link_layer_registers->link_layer_control);
234
235         if (is_a0() || is_a2()) {
236                 /* Program the max ARB time for the PHY to 700us so we inter-operate with
237                  * the PMC expander which shuts down PHYs if the expander PHY generates too
238                  * many breaks.  This time value will guarantee that the initiator PHY will
239                  * generate the break.
240                  */
241                 writel(SCIC_SDS_PHY_MAX_ARBITRATION_WAIT_TIME,
242                         &sci_phy->link_layer_registers->maximum_arbitration_wait_timer_timeout);
243         }
244
245         /*
246          * Set the link layer hang detection to 500ms (0x1F4) from its default
247          * value of 128ms.  Max value is 511 ms.
248          */
249         writel(0x1F4, &sci_phy->link_layer_registers->link_layer_hang_detection_timeout);
250
251         /* We can exit the initial state to the stopped state */
252         sci_change_state(&sci_phy->sm, SCI_PHY_STOPPED);
253
254         return SCI_SUCCESS;
255 }
256
257 static void phy_sata_timeout(unsigned long data)
258 {
259         struct sci_timer *tmr = (struct sci_timer *)data;
260         struct scic_sds_phy *sci_phy = container_of(tmr, typeof(*sci_phy), sata_timer);
261         struct isci_host *ihost = scic_to_ihost(sci_phy->owning_port->owning_controller);
262         unsigned long flags;
263
264         spin_lock_irqsave(&ihost->scic_lock, flags);
265
266         if (tmr->cancel)
267                 goto done;
268
269         dev_dbg(sciphy_to_dev(sci_phy),
270                  "%s: SCIC SDS Phy 0x%p did not receive signature fis before "
271                  "timeout.\n",
272                  __func__,
273                  sci_phy);
274
275         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
276 done:
277         spin_unlock_irqrestore(&ihost->scic_lock, flags);
278 }
279
280 /**
281  * This method returns the port currently containing this phy. If the phy is
282  *    currently contained by the dummy port, then the phy is considered to not
283  *    be part of a port.
284  * @sci_phy: This parameter specifies the phy for which to retrieve the
285  *    containing port.
286  *
287  * This method returns a handle to a port that contains the supplied phy.
288  * NULL This value is returned if the phy is not part of a real
289  * port (i.e. it's contained in the dummy port). !NULL All other
290  * values indicate a handle/pointer to the port containing the phy.
291  */
292 struct scic_sds_port *phy_get_non_dummy_port(
293         struct scic_sds_phy *sci_phy)
294 {
295         if (scic_sds_port_get_index(sci_phy->owning_port) == SCIC_SDS_DUMMY_PORT)
296                 return NULL;
297
298         return sci_phy->owning_port;
299 }
300
301 /**
302  * This method will assign a port to the phy object.
303  * @out]: sci_phy This parameter specifies the phy for which to assign a port
304  *    object.
305  *
306  *
307  */
308 void scic_sds_phy_set_port(
309         struct scic_sds_phy *sci_phy,
310         struct scic_sds_port *sci_port)
311 {
312         sci_phy->owning_port = sci_port;
313
314         if (sci_phy->bcn_received_while_port_unassigned) {
315                 sci_phy->bcn_received_while_port_unassigned = false;
316                 scic_sds_port_broadcast_change_received(sci_phy->owning_port, sci_phy);
317         }
318 }
319
320 /**
321  * This method will initialize the constructed phy
322  * @sci_phy:
323  * @link_layer_registers:
324  *
325  * enum sci_status
326  */
327 enum sci_status scic_sds_phy_initialize(
328         struct scic_sds_phy *sci_phy,
329         struct scu_transport_layer_registers __iomem *transport_layer_registers,
330         struct scu_link_layer_registers __iomem *link_layer_registers)
331 {
332         /* Perfrom the initialization of the TL hardware */
333         scic_sds_phy_transport_layer_initialization(
334                         sci_phy,
335                         transport_layer_registers);
336
337         /* Perofrm the initialization of the PE hardware */
338         scic_sds_phy_link_layer_initialization(sci_phy, link_layer_registers);
339
340         /*
341          * There is nothing that needs to be done in this state just
342          * transition to the stopped state. */
343         sci_change_state(&sci_phy->sm, SCI_PHY_STOPPED);
344
345         return SCI_SUCCESS;
346 }
347
348 /**
349  * This method assigns the direct attached device ID for this phy.
350  *
351  * @sci_phy The phy for which the direct attached device id is to
352  *       be assigned.
353  * @device_id The direct attached device ID to assign to the phy.
354  *       This will either be the RNi for the device or an invalid RNi if there
355  *       is no current device assigned to the phy.
356  */
357 void scic_sds_phy_setup_transport(
358         struct scic_sds_phy *sci_phy,
359         u32 device_id)
360 {
361         u32 tl_control;
362
363         writel(device_id, &sci_phy->transport_layer_registers->stp_rni);
364
365         /*
366          * The read should guarantee that the first write gets posted
367          * before the next write
368          */
369         tl_control = readl(&sci_phy->transport_layer_registers->control);
370         tl_control |= SCU_TLCR_GEN_BIT(CLEAR_TCI_NCQ_MAPPING_TABLE);
371         writel(tl_control, &sci_phy->transport_layer_registers->control);
372 }
373
374 /**
375  *
376  * @sci_phy: The phy object to be suspended.
377  *
378  * This function will perform the register reads/writes to suspend the SCU
379  * hardware protocol engine. none
380  */
381 static void scic_sds_phy_suspend(
382         struct scic_sds_phy *sci_phy)
383 {
384         u32 scu_sas_pcfg_value;
385
386         scu_sas_pcfg_value =
387                 readl(&sci_phy->link_layer_registers->phy_configuration);
388         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
389         writel(scu_sas_pcfg_value,
390                 &sci_phy->link_layer_registers->phy_configuration);
391
392         scic_sds_phy_setup_transport(
393                         sci_phy,
394                         SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX);
395 }
396
397 void scic_sds_phy_resume(struct scic_sds_phy *sci_phy)
398 {
399         u32 scu_sas_pcfg_value;
400
401         scu_sas_pcfg_value =
402                 readl(&sci_phy->link_layer_registers->phy_configuration);
403         scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE);
404         writel(scu_sas_pcfg_value,
405                 &sci_phy->link_layer_registers->phy_configuration);
406 }
407
408 void scic_sds_phy_get_sas_address(struct scic_sds_phy *sci_phy,
409                                   struct sci_sas_address *sas_address)
410 {
411         sas_address->high = readl(&sci_phy->link_layer_registers->source_sas_address_high);
412         sas_address->low = readl(&sci_phy->link_layer_registers->source_sas_address_low);
413 }
414
415 void scic_sds_phy_get_attached_sas_address(struct scic_sds_phy *sci_phy,
416                                            struct sci_sas_address *sas_address)
417 {
418         struct sas_identify_frame *iaf;
419         struct isci_phy *iphy = sci_phy_to_iphy(sci_phy);
420
421         iaf = &iphy->frame_rcvd.iaf;
422         memcpy(sas_address, iaf->sas_addr, SAS_ADDR_SIZE);
423 }
424
425 void scic_sds_phy_get_protocols(struct scic_sds_phy *sci_phy,
426                                 struct scic_phy_proto *protocols)
427 {
428         protocols->all =
429                 (u16)(readl(&sci_phy->
430                         link_layer_registers->transmit_identification) &
431                                 0x0000FFFF);
432 }
433
434 enum sci_status scic_sds_phy_start(struct scic_sds_phy *sci_phy)
435 {
436         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
437
438         if (state != SCI_PHY_STOPPED) {
439                 dev_dbg(sciphy_to_dev(sci_phy),
440                          "%s: in wrong state: %d\n", __func__, state);
441                 return SCI_FAILURE_INVALID_STATE;
442         }
443
444         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
445         return SCI_SUCCESS;
446 }
447
448 enum sci_status scic_sds_phy_stop(struct scic_sds_phy *sci_phy)
449 {
450         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
451
452         switch (state) {
453         case SCI_PHY_SUB_INITIAL:
454         case SCI_PHY_SUB_AWAIT_OSSP_EN:
455         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
456         case SCI_PHY_SUB_AWAIT_SAS_POWER:
457         case SCI_PHY_SUB_AWAIT_SATA_POWER:
458         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
459         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
460         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
461         case SCI_PHY_SUB_FINAL:
462         case SCI_PHY_READY:
463                 break;
464         default:
465                 dev_dbg(sciphy_to_dev(sci_phy),
466                         "%s: in wrong state: %d\n", __func__, state);
467                 return SCI_FAILURE_INVALID_STATE;
468         }
469
470         sci_change_state(&sci_phy->sm, SCI_PHY_STOPPED);
471         return SCI_SUCCESS;
472 }
473
474 enum sci_status scic_sds_phy_reset(struct scic_sds_phy *sci_phy)
475 {
476         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
477
478         if (state != SCI_PHY_READY) {
479                 dev_dbg(sciphy_to_dev(sci_phy),
480                         "%s: in wrong state: %d\n", __func__, state);
481                 return SCI_FAILURE_INVALID_STATE;
482         }
483
484         sci_change_state(&sci_phy->sm, SCI_PHY_RESETTING);
485         return SCI_SUCCESS;
486 }
487
488 enum sci_status scic_sds_phy_consume_power_handler(struct scic_sds_phy *sci_phy)
489 {
490         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
491
492         switch (state) {
493         case SCI_PHY_SUB_AWAIT_SAS_POWER: {
494                 u32 enable_spinup;
495
496                 enable_spinup = readl(&sci_phy->link_layer_registers->notify_enable_spinup_control);
497                 enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);
498                 writel(enable_spinup, &sci_phy->link_layer_registers->notify_enable_spinup_control);
499
500                 /* Change state to the final state this substate machine has run to completion */
501                 sci_change_state(&sci_phy->sm, SCI_PHY_SUB_FINAL);
502
503                 return SCI_SUCCESS;
504         }
505         case SCI_PHY_SUB_AWAIT_SATA_POWER: {
506                 u32 scu_sas_pcfg_value;
507
508                 /* Release the spinup hold state and reset the OOB state machine */
509                 scu_sas_pcfg_value =
510                         readl(&sci_phy->link_layer_registers->phy_configuration);
511                 scu_sas_pcfg_value &=
512                         ~(SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD) | SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE));
513                 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
514                 writel(scu_sas_pcfg_value,
515                         &sci_phy->link_layer_registers->phy_configuration);
516
517                 /* Now restart the OOB operation */
518                 scu_sas_pcfg_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
519                 scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
520                 writel(scu_sas_pcfg_value,
521                         &sci_phy->link_layer_registers->phy_configuration);
522
523                 /* Change state to the final state this substate machine has run to completion */
524                 sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SATA_PHY_EN);
525
526                 return SCI_SUCCESS;
527         }
528         default:
529                 dev_dbg(sciphy_to_dev(sci_phy),
530                         "%s: in wrong state: %d\n", __func__, state);
531                 return SCI_FAILURE_INVALID_STATE;
532         }
533 }
534
535 /*
536  * *****************************************************************************
537  * * SCIC SDS PHY HELPER FUNCTIONS
538  * ***************************************************************************** */
539
540
541 /**
542  *
543  * @sci_phy: The phy object that received SAS PHY DETECTED.
544  *
545  * This method continues the link training for the phy as if it were a SAS PHY
546  * instead of a SATA PHY. This is done because the completion queue had a SAS
547  * PHY DETECTED event when the state machine was expecting a SATA PHY event.
548  * none
549  */
550 static void scic_sds_phy_start_sas_link_training(
551         struct scic_sds_phy *sci_phy)
552 {
553         u32 phy_control;
554
555         phy_control =
556                 readl(&sci_phy->link_layer_registers->phy_configuration);
557         phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD);
558         writel(phy_control,
559                 &sci_phy->link_layer_registers->phy_configuration);
560
561         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SAS_SPEED_EN);
562
563         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SAS;
564 }
565
566 /**
567  *
568  * @sci_phy: The phy object that received a SATA SPINUP HOLD event
569  *
570  * This method continues the link training for the phy as if it were a SATA PHY
571  * instead of a SAS PHY.  This is done because the completion queue had a SATA
572  * SPINUP HOLD event when the state machine was expecting a SAS PHY event. none
573  */
574 static void scic_sds_phy_start_sata_link_training(
575         struct scic_sds_phy *sci_phy)
576 {
577         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SATA_POWER);
578
579         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
580 }
581
582 /**
583  * scic_sds_phy_complete_link_training - perform processing common to
584  *    all protocols upon completion of link training.
585  * @sci_phy: This parameter specifies the phy object for which link training
586  *    has completed.
587  * @max_link_rate: This parameter specifies the maximum link rate to be
588  *    associated with this phy.
589  * @next_state: This parameter specifies the next state for the phy's starting
590  *    sub-state machine.
591  *
592  */
593 static void scic_sds_phy_complete_link_training(
594         struct scic_sds_phy *sci_phy,
595         enum sas_linkrate max_link_rate,
596         u32 next_state)
597 {
598         sci_phy->max_negotiated_speed = max_link_rate;
599
600         sci_change_state(&sci_phy->sm, next_state);
601 }
602
603 enum sci_status scic_sds_phy_event_handler(struct scic_sds_phy *sci_phy,
604                                            u32 event_code)
605 {
606         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
607
608         switch (state) {
609         case SCI_PHY_SUB_AWAIT_OSSP_EN:
610                 switch (scu_get_event_code(event_code)) {
611                 case SCU_EVENT_SAS_PHY_DETECTED:
612                         scic_sds_phy_start_sas_link_training(sci_phy);
613                         sci_phy->is_in_link_training = true;
614                         break;
615                 case SCU_EVENT_SATA_SPINUP_HOLD:
616                         scic_sds_phy_start_sata_link_training(sci_phy);
617                         sci_phy->is_in_link_training = true;
618                         break;
619                 default:
620                         dev_dbg(sciphy_to_dev(sci_phy),
621                                 "%s: PHY starting substate machine received "
622                                 "unexpected event_code %x\n",
623                                 __func__,
624                                 event_code);
625                         return SCI_FAILURE;
626                 }
627                 return SCI_SUCCESS;
628         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
629                 switch (scu_get_event_code(event_code)) {
630                 case SCU_EVENT_SAS_PHY_DETECTED:
631                         /*
632                          * Why is this being reported again by the controller?
633                          * We would re-enter this state so just stay here */
634                         break;
635                 case SCU_EVENT_SAS_15:
636                 case SCU_EVENT_SAS_15_SSC:
637                         scic_sds_phy_complete_link_training(
638                                 sci_phy,
639                                 SAS_LINK_RATE_1_5_GBPS,
640                                 SCI_PHY_SUB_AWAIT_IAF_UF);
641                         break;
642                 case SCU_EVENT_SAS_30:
643                 case SCU_EVENT_SAS_30_SSC:
644                         scic_sds_phy_complete_link_training(
645                                 sci_phy,
646                                 SAS_LINK_RATE_3_0_GBPS,
647                                 SCI_PHY_SUB_AWAIT_IAF_UF);
648                         break;
649                 case SCU_EVENT_SAS_60:
650                 case SCU_EVENT_SAS_60_SSC:
651                         scic_sds_phy_complete_link_training(
652                                 sci_phy,
653                                 SAS_LINK_RATE_6_0_GBPS,
654                                 SCI_PHY_SUB_AWAIT_IAF_UF);
655                         break;
656                 case SCU_EVENT_SATA_SPINUP_HOLD:
657                         /*
658                          * We were doing SAS PHY link training and received a SATA PHY event
659                          * continue OOB/SN as if this were a SATA PHY */
660                         scic_sds_phy_start_sata_link_training(sci_phy);
661                         break;
662                 case SCU_EVENT_LINK_FAILURE:
663                         /* Link failure change state back to the starting state */
664                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
665                         break;
666                 default:
667                         dev_warn(sciphy_to_dev(sci_phy),
668                                  "%s: PHY starting substate machine received "
669                                  "unexpected event_code %x\n",
670                                  __func__, event_code);
671
672                         return SCI_FAILURE;
673                         break;
674                 }
675                 return SCI_SUCCESS;
676         case SCI_PHY_SUB_AWAIT_IAF_UF:
677                 switch (scu_get_event_code(event_code)) {
678                 case SCU_EVENT_SAS_PHY_DETECTED:
679                         /* Backup the state machine */
680                         scic_sds_phy_start_sas_link_training(sci_phy);
681                         break;
682                 case SCU_EVENT_SATA_SPINUP_HOLD:
683                         /* We were doing SAS PHY link training and received a
684                          * SATA PHY event continue OOB/SN as if this were a
685                          * SATA PHY
686                          */
687                         scic_sds_phy_start_sata_link_training(sci_phy);
688                         break;
689                 case SCU_EVENT_RECEIVED_IDENTIFY_TIMEOUT:
690                 case SCU_EVENT_LINK_FAILURE:
691                 case SCU_EVENT_HARD_RESET_RECEIVED:
692                         /* Start the oob/sn state machine over again */
693                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
694                         break;
695                 default:
696                         dev_warn(sciphy_to_dev(sci_phy),
697                                  "%s: PHY starting substate machine received "
698                                  "unexpected event_code %x\n",
699                                  __func__, event_code);
700                         return SCI_FAILURE;
701                 }
702                 return SCI_SUCCESS;
703         case SCI_PHY_SUB_AWAIT_SAS_POWER:
704                 switch (scu_get_event_code(event_code)) {
705                 case SCU_EVENT_LINK_FAILURE:
706                         /* Link failure change state back to the starting state */
707                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
708                         break;
709                 default:
710                         dev_warn(sciphy_to_dev(sci_phy),
711                                 "%s: PHY starting substate machine received unexpected "
712                                 "event_code %x\n",
713                                 __func__,
714                                 event_code);
715                         return SCI_FAILURE;
716                 }
717                 return SCI_SUCCESS;
718         case SCI_PHY_SUB_AWAIT_SATA_POWER:
719                 switch (scu_get_event_code(event_code)) {
720                 case SCU_EVENT_LINK_FAILURE:
721                         /* Link failure change state back to the starting state */
722                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
723                         break;
724                 case SCU_EVENT_SATA_SPINUP_HOLD:
725                         /* These events are received every 10ms and are
726                          * expected while in this state
727                          */
728                         break;
729
730                 case SCU_EVENT_SAS_PHY_DETECTED:
731                         /* There has been a change in the phy type before OOB/SN for the
732                          * SATA finished start down the SAS link traning path.
733                          */
734                         scic_sds_phy_start_sas_link_training(sci_phy);
735                         break;
736
737                 default:
738                         dev_warn(sciphy_to_dev(sci_phy),
739                                  "%s: PHY starting substate machine received "
740                                  "unexpected event_code %x\n",
741                                  __func__, event_code);
742
743                         return SCI_FAILURE;
744                 }
745                 return SCI_SUCCESS;
746         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
747                 switch (scu_get_event_code(event_code)) {
748                 case SCU_EVENT_LINK_FAILURE:
749                         /* Link failure change state back to the starting state */
750                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
751                         break;
752                 case SCU_EVENT_SATA_SPINUP_HOLD:
753                         /* These events might be received since we dont know how many may be in
754                          * the completion queue while waiting for power
755                          */
756                         break;
757                 case SCU_EVENT_SATA_PHY_DETECTED:
758                         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_SATA;
759
760                         /* We have received the SATA PHY notification change state */
761                         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
762                         break;
763                 case SCU_EVENT_SAS_PHY_DETECTED:
764                         /* There has been a change in the phy type before OOB/SN for the
765                          * SATA finished start down the SAS link traning path.
766                          */
767                         scic_sds_phy_start_sas_link_training(sci_phy);
768                         break;
769                 default:
770                         dev_warn(sciphy_to_dev(sci_phy),
771                                  "%s: PHY starting substate machine received "
772                                  "unexpected event_code %x\n",
773                                  __func__,
774                                  event_code);
775
776                         return SCI_FAILURE;;
777                 }
778                 return SCI_SUCCESS;
779         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
780                 switch (scu_get_event_code(event_code)) {
781                 case SCU_EVENT_SATA_PHY_DETECTED:
782                         /*
783                          * The hardware reports multiple SATA PHY detected events
784                          * ignore the extras */
785                         break;
786                 case SCU_EVENT_SATA_15:
787                 case SCU_EVENT_SATA_15_SSC:
788                         scic_sds_phy_complete_link_training(
789                                 sci_phy,
790                                 SAS_LINK_RATE_1_5_GBPS,
791                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
792                         break;
793                 case SCU_EVENT_SATA_30:
794                 case SCU_EVENT_SATA_30_SSC:
795                         scic_sds_phy_complete_link_training(
796                                 sci_phy,
797                                 SAS_LINK_RATE_3_0_GBPS,
798                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
799                         break;
800                 case SCU_EVENT_SATA_60:
801                 case SCU_EVENT_SATA_60_SSC:
802                         scic_sds_phy_complete_link_training(
803                                 sci_phy,
804                                 SAS_LINK_RATE_6_0_GBPS,
805                                 SCI_PHY_SUB_AWAIT_SIG_FIS_UF);
806                         break;
807                 case SCU_EVENT_LINK_FAILURE:
808                         /* Link failure change state back to the starting state */
809                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
810                         break;
811                 case SCU_EVENT_SAS_PHY_DETECTED:
812                         /*
813                          * There has been a change in the phy type before OOB/SN for the
814                          * SATA finished start down the SAS link traning path. */
815                         scic_sds_phy_start_sas_link_training(sci_phy);
816                         break;
817                 default:
818                         dev_warn(sciphy_to_dev(sci_phy),
819                                  "%s: PHY starting substate machine received "
820                                  "unexpected event_code %x\n",
821                                  __func__, event_code);
822
823                         return SCI_FAILURE;
824                 }
825
826                 return SCI_SUCCESS;
827         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
828                 switch (scu_get_event_code(event_code)) {
829                 case SCU_EVENT_SATA_PHY_DETECTED:
830                         /* Backup the state machine */
831                         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_SATA_SPEED_EN);
832                         break;
833
834                 case SCU_EVENT_LINK_FAILURE:
835                         /* Link failure change state back to the starting state */
836                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
837                         break;
838
839                 default:
840                         dev_warn(sciphy_to_dev(sci_phy),
841                                  "%s: PHY starting substate machine received "
842                                  "unexpected event_code %x\n",
843                                  __func__,
844                                  event_code);
845
846                         return SCI_FAILURE;
847                 }
848                 return SCI_SUCCESS;
849         case SCI_PHY_READY:
850                 switch (scu_get_event_code(event_code)) {
851                 case SCU_EVENT_LINK_FAILURE:
852                         /* Link failure change state back to the starting state */
853                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
854                         break;
855                 case SCU_EVENT_BROADCAST_CHANGE:
856                         /* Broadcast change received. Notify the port. */
857                         if (phy_get_non_dummy_port(sci_phy) != NULL)
858                                 scic_sds_port_broadcast_change_received(sci_phy->owning_port, sci_phy);
859                         else
860                                 sci_phy->bcn_received_while_port_unassigned = true;
861                         break;
862                 default:
863                         dev_warn(sciphy_to_dev(sci_phy),
864                                  "%sP SCIC PHY 0x%p ready state machine received "
865                                  "unexpected event_code %x\n",
866                                  __func__, sci_phy, event_code);
867                         return SCI_FAILURE_INVALID_STATE;
868                 }
869                 return SCI_SUCCESS;
870         case SCI_PHY_RESETTING:
871                 switch (scu_get_event_code(event_code)) {
872                 case SCU_EVENT_HARD_RESET_TRANSMITTED:
873                         /* Link failure change state back to the starting state */
874                         sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
875                         break;
876                 default:
877                         dev_warn(sciphy_to_dev(sci_phy),
878                                  "%s: SCIC PHY 0x%p resetting state machine received "
879                                  "unexpected event_code %x\n",
880                                  __func__, sci_phy, event_code);
881
882                         return SCI_FAILURE_INVALID_STATE;
883                         break;
884                 }
885                 return SCI_SUCCESS;
886         default:
887                 dev_dbg(sciphy_to_dev(sci_phy),
888                         "%s: in wrong state: %d\n", __func__, state);
889                 return SCI_FAILURE_INVALID_STATE;
890         }
891 }
892
893 enum sci_status scic_sds_phy_frame_handler(struct scic_sds_phy *sci_phy,
894                                            u32 frame_index)
895 {
896         enum scic_sds_phy_states state = sci_phy->sm.current_state_id;
897         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
898         enum sci_status result;
899
900         switch (state) {
901         case SCI_PHY_SUB_AWAIT_IAF_UF: {
902                 u32 *frame_words;
903                 struct sas_identify_frame iaf;
904                 struct isci_phy *iphy = sci_phy_to_iphy(sci_phy);
905
906                 result = scic_sds_unsolicited_frame_control_get_header(&scic->uf_control,
907                                                                        frame_index,
908                                                                        (void **)&frame_words);
909
910                 if (result != SCI_SUCCESS)
911                         return result;
912
913                 sci_swab32_cpy(&iaf, frame_words, sizeof(iaf) / sizeof(u32));
914                 if (iaf.frame_type == 0) {
915                         u32 state;
916
917                         memcpy(&iphy->frame_rcvd.iaf, &iaf, sizeof(iaf));
918                         if (iaf.smp_tport) {
919                                 /* We got the IAF for an expander PHY go to the final
920                                  * state since there are no power requirements for
921                                  * expander phys.
922                                  */
923                                 state = SCI_PHY_SUB_FINAL;
924                         } else {
925                                 /* We got the IAF we can now go to the await spinup
926                                  * semaphore state
927                                  */
928                                 state = SCI_PHY_SUB_AWAIT_SAS_POWER;
929                         }
930                         sci_change_state(&sci_phy->sm, state);
931                         result = SCI_SUCCESS;
932                 } else
933                         dev_warn(sciphy_to_dev(sci_phy),
934                                 "%s: PHY starting substate machine received "
935                                 "unexpected frame id %x\n",
936                                 __func__, frame_index);
937
938                 scic_sds_controller_release_frame(scic, frame_index);
939                 return result;
940         }
941         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: {
942                 struct dev_to_host_fis *frame_header;
943                 u32 *fis_frame_data;
944                 struct isci_phy *iphy = sci_phy_to_iphy(sci_phy);
945
946                 result = scic_sds_unsolicited_frame_control_get_header(
947                         &(scic_sds_phy_get_controller(sci_phy)->uf_control),
948                         frame_index,
949                         (void **)&frame_header);
950
951                 if (result != SCI_SUCCESS)
952                         return result;
953
954                 if ((frame_header->fis_type == FIS_REGD2H) &&
955                     !(frame_header->status & ATA_BUSY)) {
956                         scic_sds_unsolicited_frame_control_get_buffer(&scic->uf_control,
957                                                                       frame_index,
958                                                                       (void **)&fis_frame_data);
959
960                         scic_sds_controller_copy_sata_response(&iphy->frame_rcvd.fis,
961                                                                frame_header,
962                                                                fis_frame_data);
963
964                         /* got IAF we can now go to the await spinup semaphore state */
965                         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_FINAL);
966
967                         result = SCI_SUCCESS;
968                 } else
969                         dev_warn(sciphy_to_dev(sci_phy),
970                                  "%s: PHY starting substate machine received "
971                                  "unexpected frame id %x\n",
972                                  __func__, frame_index);
973
974                 /* Regardless of the result we are done with this frame with it */
975                 scic_sds_controller_release_frame(scic, frame_index);
976
977                 return result;
978         }
979         default:
980                 dev_dbg(sciphy_to_dev(sci_phy),
981                         "%s: in wrong state: %d\n", __func__, state);
982                 return SCI_FAILURE_INVALID_STATE;
983         }
984         
985 }
986
987 static void scic_sds_phy_starting_initial_substate_enter(struct sci_base_state_machine *sm)
988 {
989         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
990
991         /* This is just an temporary state go off to the starting state */
992         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_AWAIT_OSSP_EN);
993 }
994
995 static void scic_sds_phy_starting_await_sas_power_substate_enter(struct sci_base_state_machine *sm)
996 {
997         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
998         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
999
1000         scic_sds_controller_power_control_queue_insert(scic, sci_phy);
1001 }
1002
1003 static void scic_sds_phy_starting_await_sas_power_substate_exit(struct sci_base_state_machine *sm)
1004 {
1005         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1006         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
1007
1008         scic_sds_controller_power_control_queue_remove(scic, sci_phy);
1009 }
1010
1011 static void scic_sds_phy_starting_await_sata_power_substate_enter(struct sci_base_state_machine *sm)
1012 {
1013         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1014         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
1015
1016         scic_sds_controller_power_control_queue_insert(scic, sci_phy);
1017 }
1018
1019 static void scic_sds_phy_starting_await_sata_power_substate_exit(struct sci_base_state_machine *sm)
1020 {
1021         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1022         struct scic_sds_controller *scic = sci_phy->owning_port->owning_controller;
1023
1024         scic_sds_controller_power_control_queue_remove(scic, sci_phy);
1025 }
1026
1027 static void scic_sds_phy_starting_await_sata_phy_substate_enter(struct sci_base_state_machine *sm)
1028 {
1029         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1030
1031         sci_mod_timer(&sci_phy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1032 }
1033
1034 static void scic_sds_phy_starting_await_sata_phy_substate_exit(struct sci_base_state_machine *sm)
1035 {
1036         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1037
1038         sci_del_timer(&sci_phy->sata_timer);
1039 }
1040
1041 static void scic_sds_phy_starting_await_sata_speed_substate_enter(struct sci_base_state_machine *sm)
1042 {
1043         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1044
1045         sci_mod_timer(&sci_phy->sata_timer, SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT);
1046 }
1047
1048 static void scic_sds_phy_starting_await_sata_speed_substate_exit(struct sci_base_state_machine *sm)
1049 {
1050         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1051
1052         sci_del_timer(&sci_phy->sata_timer);
1053 }
1054
1055 static void scic_sds_phy_starting_await_sig_fis_uf_substate_enter(struct sci_base_state_machine *sm)
1056 {
1057         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1058
1059         if (scic_sds_port_link_detected(sci_phy->owning_port, sci_phy)) {
1060
1061                 /*
1062                  * Clear the PE suspend condition so we can actually
1063                  * receive SIG FIS
1064                  * The hardware will not respond to the XRDY until the PE
1065                  * suspend condition is cleared.
1066                  */
1067                 scic_sds_phy_resume(sci_phy);
1068
1069                 sci_mod_timer(&sci_phy->sata_timer,
1070                               SCIC_SDS_SIGNATURE_FIS_TIMEOUT);
1071         } else
1072                 sci_phy->is_in_link_training = false;
1073 }
1074
1075 static void scic_sds_phy_starting_await_sig_fis_uf_substate_exit(struct sci_base_state_machine *sm)
1076 {
1077         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1078
1079         sci_del_timer(&sci_phy->sata_timer);
1080 }
1081
1082 static void scic_sds_phy_starting_final_substate_enter(struct sci_base_state_machine *sm)
1083 {
1084         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1085
1086         /* State machine has run to completion so exit out and change
1087          * the base state machine to the ready state
1088          */
1089         sci_change_state(&sci_phy->sm, SCI_PHY_READY);
1090 }
1091
1092 /**
1093  *
1094  * @sci_phy: This is the struct scic_sds_phy object to stop.
1095  *
1096  * This method will stop the struct scic_sds_phy object. This does not reset the
1097  * protocol engine it just suspends it and places it in a state where it will
1098  * not cause the end device to power up. none
1099  */
1100 static void scu_link_layer_stop_protocol_engine(
1101         struct scic_sds_phy *sci_phy)
1102 {
1103         u32 scu_sas_pcfg_value;
1104         u32 enable_spinup_value;
1105
1106         /* Suspend the protocol engine and place it in a sata spinup hold state */
1107         scu_sas_pcfg_value =
1108                 readl(&sci_phy->link_layer_registers->phy_configuration);
1109         scu_sas_pcfg_value |=
1110                 (SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1111                  SCU_SAS_PCFG_GEN_BIT(SUSPEND_PROTOCOL_ENGINE) |
1112                  SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD));
1113         writel(scu_sas_pcfg_value,
1114                &sci_phy->link_layer_registers->phy_configuration);
1115
1116         /* Disable the notify enable spinup primitives */
1117         enable_spinup_value = readl(&sci_phy->link_layer_registers->notify_enable_spinup_control);
1118         enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);
1119         writel(enable_spinup_value, &sci_phy->link_layer_registers->notify_enable_spinup_control);
1120 }
1121
1122 /**
1123  *
1124  *
1125  * This method will start the OOB/SN state machine for this struct scic_sds_phy object.
1126  */
1127 static void scu_link_layer_start_oob(
1128         struct scic_sds_phy *sci_phy)
1129 {
1130         u32 scu_sas_pcfg_value;
1131
1132         scu_sas_pcfg_value =
1133                 readl(&sci_phy->link_layer_registers->phy_configuration);
1134         scu_sas_pcfg_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1135         scu_sas_pcfg_value &=
1136                 ~(SCU_SAS_PCFG_GEN_BIT(OOB_RESET) |
1137                 SCU_SAS_PCFG_GEN_BIT(HARD_RESET));
1138         writel(scu_sas_pcfg_value,
1139                &sci_phy->link_layer_registers->phy_configuration);
1140 }
1141
1142 /**
1143  *
1144  *
1145  * This method will transmit a hard reset request on the specified phy. The SCU
1146  * hardware requires that we reset the OOB state machine and set the hard reset
1147  * bit in the phy configuration register. We then must start OOB over with the
1148  * hard reset bit set.
1149  */
1150 static void scu_link_layer_tx_hard_reset(
1151         struct scic_sds_phy *sci_phy)
1152 {
1153         u32 phy_configuration_value;
1154
1155         /*
1156          * SAS Phys must wait for the HARD_RESET_TX event notification to transition
1157          * to the starting state. */
1158         phy_configuration_value =
1159                 readl(&sci_phy->link_layer_registers->phy_configuration);
1160         phy_configuration_value |=
1161                 (SCU_SAS_PCFG_GEN_BIT(HARD_RESET) |
1162                  SCU_SAS_PCFG_GEN_BIT(OOB_RESET));
1163         writel(phy_configuration_value,
1164                &sci_phy->link_layer_registers->phy_configuration);
1165
1166         /* Now take the OOB state machine out of reset */
1167         phy_configuration_value |= SCU_SAS_PCFG_GEN_BIT(OOB_ENABLE);
1168         phy_configuration_value &= ~SCU_SAS_PCFG_GEN_BIT(OOB_RESET);
1169         writel(phy_configuration_value,
1170                &sci_phy->link_layer_registers->phy_configuration);
1171 }
1172
1173 static void scic_sds_phy_stopped_state_enter(struct sci_base_state_machine *sm)
1174 {
1175         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1176
1177         /*
1178          * @todo We need to get to the controller to place this PE in a
1179          * reset state
1180          */
1181         sci_del_timer(&sci_phy->sata_timer);
1182
1183         scu_link_layer_stop_protocol_engine(sci_phy);
1184
1185         if (sci_phy->sm.previous_state_id != SCI_PHY_INITIAL)
1186                 scic_sds_controller_link_down(scic_sds_phy_get_controller(sci_phy),
1187                                               phy_get_non_dummy_port(sci_phy),
1188                                               sci_phy);
1189 }
1190
1191 static void scic_sds_phy_starting_state_enter(struct sci_base_state_machine *sm)
1192 {
1193         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1194
1195         scu_link_layer_stop_protocol_engine(sci_phy);
1196         scu_link_layer_start_oob(sci_phy);
1197
1198         /* We don't know what kind of phy we are going to be just yet */
1199         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1200         sci_phy->bcn_received_while_port_unassigned = false;
1201
1202         if (sci_phy->sm.previous_state_id == SCI_PHY_READY)
1203                 scic_sds_controller_link_down(scic_sds_phy_get_controller(sci_phy),
1204                                               phy_get_non_dummy_port(sci_phy),
1205                                               sci_phy);
1206
1207         sci_change_state(&sci_phy->sm, SCI_PHY_SUB_INITIAL);
1208 }
1209
1210 static void scic_sds_phy_ready_state_enter(struct sci_base_state_machine *sm)
1211 {
1212         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1213
1214         scic_sds_controller_link_up(scic_sds_phy_get_controller(sci_phy),
1215                                     phy_get_non_dummy_port(sci_phy),
1216                                     sci_phy);
1217
1218 }
1219
1220 static void scic_sds_phy_ready_state_exit(struct sci_base_state_machine *sm)
1221 {
1222         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1223
1224         scic_sds_phy_suspend(sci_phy);
1225 }
1226
1227 static void scic_sds_phy_resetting_state_enter(struct sci_base_state_machine *sm)
1228 {
1229         struct scic_sds_phy *sci_phy = container_of(sm, typeof(*sci_phy), sm);
1230
1231         /* The phy is being reset, therefore deactivate it from the port.  In
1232          * the resetting state we don't notify the user regarding link up and
1233          * link down notifications
1234          */
1235         scic_sds_port_deactivate_phy(sci_phy->owning_port, sci_phy, false);
1236
1237         if (sci_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1238                 scu_link_layer_tx_hard_reset(sci_phy);
1239         } else {
1240                 /* The SCU does not need to have a discrete reset state so
1241                  * just go back to the starting state.
1242                  */
1243                 sci_change_state(&sci_phy->sm, SCI_PHY_STARTING);
1244         }
1245 }
1246
1247 static const struct sci_base_state scic_sds_phy_state_table[] = {
1248         [SCI_PHY_INITIAL] = { },
1249         [SCI_PHY_STOPPED] = {
1250                 .enter_state = scic_sds_phy_stopped_state_enter,
1251         },
1252         [SCI_PHY_STARTING] = {
1253                 .enter_state = scic_sds_phy_starting_state_enter,
1254         },
1255         [SCI_PHY_SUB_INITIAL] = {
1256                 .enter_state = scic_sds_phy_starting_initial_substate_enter,
1257         },
1258         [SCI_PHY_SUB_AWAIT_OSSP_EN] = { },
1259         [SCI_PHY_SUB_AWAIT_SAS_SPEED_EN] = { },
1260         [SCI_PHY_SUB_AWAIT_IAF_UF] = { },
1261         [SCI_PHY_SUB_AWAIT_SAS_POWER] = {
1262                 .enter_state = scic_sds_phy_starting_await_sas_power_substate_enter,
1263                 .exit_state  = scic_sds_phy_starting_await_sas_power_substate_exit,
1264         },
1265         [SCI_PHY_SUB_AWAIT_SATA_POWER] = {
1266                 .enter_state = scic_sds_phy_starting_await_sata_power_substate_enter,
1267                 .exit_state  = scic_sds_phy_starting_await_sata_power_substate_exit
1268         },
1269         [SCI_PHY_SUB_AWAIT_SATA_PHY_EN] = {
1270                 .enter_state = scic_sds_phy_starting_await_sata_phy_substate_enter,
1271                 .exit_state  = scic_sds_phy_starting_await_sata_phy_substate_exit
1272         },
1273         [SCI_PHY_SUB_AWAIT_SATA_SPEED_EN] = {
1274                 .enter_state = scic_sds_phy_starting_await_sata_speed_substate_enter,
1275                 .exit_state  = scic_sds_phy_starting_await_sata_speed_substate_exit
1276         },
1277         [SCI_PHY_SUB_AWAIT_SIG_FIS_UF] = {
1278                 .enter_state = scic_sds_phy_starting_await_sig_fis_uf_substate_enter,
1279                 .exit_state  = scic_sds_phy_starting_await_sig_fis_uf_substate_exit
1280         },
1281         [SCI_PHY_SUB_FINAL] = {
1282                 .enter_state = scic_sds_phy_starting_final_substate_enter,
1283         },
1284         [SCI_PHY_READY] = {
1285                 .enter_state = scic_sds_phy_ready_state_enter,
1286                 .exit_state = scic_sds_phy_ready_state_exit,
1287         },
1288         [SCI_PHY_RESETTING] = {
1289                 .enter_state = scic_sds_phy_resetting_state_enter,
1290         },
1291         [SCI_PHY_FINAL] = { },
1292 };
1293
1294 void scic_sds_phy_construct(struct scic_sds_phy *sci_phy,
1295                             struct scic_sds_port *owning_port, u8 phy_index)
1296 {
1297         sci_base_state_machine_construct(&sci_phy->sm,
1298                                          scic_sds_phy_state_table,
1299                                          SCI_PHY_INITIAL);
1300
1301         sci_base_state_machine_start(&sci_phy->sm);
1302
1303         /* Copy the rest of the input data to our locals */
1304         sci_phy->owning_port = owning_port;
1305         sci_phy->phy_index = phy_index;
1306         sci_phy->bcn_received_while_port_unassigned = false;
1307         sci_phy->protocol = SCIC_SDS_PHY_PROTOCOL_UNKNOWN;
1308         sci_phy->link_layer_registers = NULL;
1309         sci_phy->max_negotiated_speed = SAS_LINK_RATE_UNKNOWN;
1310
1311         /* Create the SIGNATURE FIS Timeout timer for this phy */
1312         sci_init_timer(&sci_phy->sata_timer, phy_sata_timeout);
1313 }
1314
1315 void isci_phy_init(struct isci_phy *iphy, struct isci_host *ihost, int index)
1316 {
1317         union scic_oem_parameters oem;
1318         u64 sci_sas_addr;
1319         __be64 sas_addr;
1320
1321         scic_oem_parameters_get(&ihost->sci, &oem);
1322         sci_sas_addr = oem.sds1.phys[index].sas_address.high;
1323         sci_sas_addr <<= 32;
1324         sci_sas_addr |= oem.sds1.phys[index].sas_address.low;
1325         sas_addr = cpu_to_be64(sci_sas_addr);
1326         memcpy(iphy->sas_addr, &sas_addr, sizeof(sas_addr));
1327
1328         iphy->isci_port = NULL;
1329         iphy->sas_phy.enabled = 0;
1330         iphy->sas_phy.id = index;
1331         iphy->sas_phy.sas_addr = &iphy->sas_addr[0];
1332         iphy->sas_phy.frame_rcvd = (u8 *)&iphy->frame_rcvd;
1333         iphy->sas_phy.ha = &ihost->sas_ha;
1334         iphy->sas_phy.lldd_phy = iphy;
1335         iphy->sas_phy.enabled = 1;
1336         iphy->sas_phy.class = SAS;
1337         iphy->sas_phy.iproto = SAS_PROTOCOL_ALL;
1338         iphy->sas_phy.tproto = 0;
1339         iphy->sas_phy.type = PHY_TYPE_PHYSICAL;
1340         iphy->sas_phy.role = PHY_ROLE_INITIATOR;
1341         iphy->sas_phy.oob_mode = OOB_NOT_CONNECTED;
1342         iphy->sas_phy.linkrate = SAS_LINK_RATE_UNKNOWN;
1343         memset(&iphy->frame_rcvd, 0, sizeof(iphy->frame_rcvd));
1344 }
1345
1346
1347 /**
1348  * isci_phy_control() - This function is one of the SAS Domain Template
1349  *    functions. This is a phy management function.
1350  * @phy: This parameter specifies the sphy being controlled.
1351  * @func: This parameter specifies the phy control function being invoked.
1352  * @buf: This parameter is specific to the phy function being invoked.
1353  *
1354  * status, zero indicates success.
1355  */
1356 int isci_phy_control(struct asd_sas_phy *sas_phy,
1357                      enum phy_func func,
1358                      void *buf)
1359 {
1360         int ret = 0;
1361         struct isci_phy *iphy = sas_phy->lldd_phy;
1362         struct isci_port *iport = iphy->isci_port;
1363         struct isci_host *ihost = sas_phy->ha->lldd_ha;
1364         unsigned long flags;
1365
1366         dev_dbg(&ihost->pdev->dev,
1367                 "%s: phy %p; func %d; buf %p; isci phy %p, port %p\n",
1368                 __func__, sas_phy, func, buf, iphy, iport);
1369
1370         switch (func) {
1371         case PHY_FUNC_DISABLE:
1372                 spin_lock_irqsave(&ihost->scic_lock, flags);
1373                 scic_sds_phy_stop(&iphy->sci);
1374                 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1375                 break;
1376
1377         case PHY_FUNC_LINK_RESET:
1378                 spin_lock_irqsave(&ihost->scic_lock, flags);
1379                 scic_sds_phy_stop(&iphy->sci);
1380                 scic_sds_phy_start(&iphy->sci);
1381                 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1382                 break;
1383
1384         case PHY_FUNC_HARD_RESET:
1385                 if (!iport)
1386                         return -ENODEV;
1387
1388                 /* Perform the port reset. */
1389                 ret = isci_port_perform_hard_reset(ihost, iport, iphy);
1390
1391                 break;
1392
1393         default:
1394                 dev_dbg(&ihost->pdev->dev,
1395                            "%s: phy %p; func %d NOT IMPLEMENTED!\n",
1396                            __func__, sas_phy, func);
1397                 ret = -ENOSYS;
1398                 break;
1399         }
1400         return ret;
1401 }