c99fab53dd0c78748658308e696dfc85c85307f2
[linux-2.6.git] / drivers / scsi / isci / host.c
1 /*
2  * This file is provided under a dual BSD/GPLv2 license.  When using or
3  * redistributing this file, you may do so under either license.
4  *
5  * GPL LICENSE SUMMARY
6  *
7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * BSD LICENSE
25  *
26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27  * All rights reserved.
28  *
29  * Redistribution and use in source and binary forms, with or without
30  * modification, are permitted provided that the following conditions
31  * are met:
32  *
33  *   * Redistributions of source code must retain the above copyright
34  *     notice, this list of conditions and the following disclaimer.
35  *   * Redistributions in binary form must reproduce the above copyright
36  *     notice, this list of conditions and the following disclaimer in
37  *     the documentation and/or other materials provided with the
38  *     distribution.
39  *   * Neither the name of Intel Corporation nor the names of its
40  *     contributors may be used to endorse or promote products derived
41  *     from this software without specific prior written permission.
42  *
43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54  */
55 #include <linux/circ_buf.h>
56 #include <linux/device.h>
57 #include <scsi/sas.h>
58 #include "host.h"
59 #include "isci.h"
60 #include "port.h"
61 #include "host.h"
62 #include "probe_roms.h"
63 #include "remote_device.h"
64 #include "request.h"
65 #include "scu_completion_codes.h"
66 #include "scu_event_codes.h"
67 #include "registers.h"
68 #include "scu_remote_node_context.h"
69 #include "scu_task_context.h"
70 #include "scu_unsolicited_frame.h"
71
72 #define SCU_CONTEXT_RAM_INIT_STALL_TIME      200
73
74 #define smu_max_ports(dcc_value) \
75         (\
76                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
77                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
78         )
79
80 #define smu_max_task_contexts(dcc_value)        \
81         (\
82                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
83                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
84         )
85
86 #define smu_max_rncs(dcc_value) \
87         (\
88                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
89                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
90         )
91
92 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT      100
93
94 /**
95  *
96  *
97  * The number of milliseconds to wait while a given phy is consuming power
98  * before allowing another set of phys to consume power. Ultimately, this will
99  * be specified by OEM parameter.
100  */
101 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
102
103 /**
104  * NORMALIZE_PUT_POINTER() -
105  *
106  * This macro will normalize the completion queue put pointer so its value can
107  * be used as an array inde
108  */
109 #define NORMALIZE_PUT_POINTER(x) \
110         ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
111
112
113 /**
114  * NORMALIZE_EVENT_POINTER() -
115  *
116  * This macro will normalize the completion queue event entry so its value can
117  * be used as an index.
118  */
119 #define NORMALIZE_EVENT_POINTER(x) \
120         (\
121                 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
122                 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
123         )
124
125 /**
126  * NORMALIZE_GET_POINTER() -
127  *
128  * This macro will normalize the completion queue get pointer so its value can
129  * be used as an index into an array
130  */
131 #define NORMALIZE_GET_POINTER(x) \
132         ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
133
134 /**
135  * NORMALIZE_GET_POINTER_CYCLE_BIT() -
136  *
137  * This macro will normalize the completion queue cycle pointer so it matches
138  * the completion queue cycle bit
139  */
140 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
141         ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
142
143 /**
144  * COMPLETION_QUEUE_CYCLE_BIT() -
145  *
146  * This macro will return the cycle bit of the completion queue entry
147  */
148 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
149
150 /* Init the state machine and call the state entry function (if any) */
151 void sci_init_sm(struct sci_base_state_machine *sm,
152                  const struct sci_base_state *state_table, u32 initial_state)
153 {
154         sci_state_transition_t handler;
155
156         sm->initial_state_id    = initial_state;
157         sm->previous_state_id   = initial_state;
158         sm->current_state_id    = initial_state;
159         sm->state_table         = state_table;
160
161         handler = sm->state_table[initial_state].enter_state;
162         if (handler)
163                 handler(sm);
164 }
165
166 /* Call the state exit fn, update the current state, call the state entry fn */
167 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
168 {
169         sci_state_transition_t handler;
170
171         handler = sm->state_table[sm->current_state_id].exit_state;
172         if (handler)
173                 handler(sm);
174
175         sm->previous_state_id = sm->current_state_id;
176         sm->current_state_id = next_state;
177
178         handler = sm->state_table[sm->current_state_id].enter_state;
179         if (handler)
180                 handler(sm);
181 }
182
183 static bool scic_sds_controller_completion_queue_has_entries(
184         struct scic_sds_controller *scic)
185 {
186         u32 get_value = scic->completion_queue_get;
187         u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
188
189         if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
190             COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index]))
191                 return true;
192
193         return false;
194 }
195
196 static bool scic_sds_controller_isr(struct scic_sds_controller *scic)
197 {
198         if (scic_sds_controller_completion_queue_has_entries(scic)) {
199                 return true;
200         } else {
201                 /*
202                  * we have a spurious interrupt it could be that we have already
203                  * emptied the completion queue from a previous interrupt */
204                 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
205
206                 /*
207                  * There is a race in the hardware that could cause us not to be notified
208                  * of an interrupt completion if we do not take this step.  We will mask
209                  * then unmask the interrupts so if there is another interrupt pending
210                  * the clearing of the interrupt source we get the next interrupt message. */
211                 writel(0xFF000000, &scic->smu_registers->interrupt_mask);
212                 writel(0, &scic->smu_registers->interrupt_mask);
213         }
214
215         return false;
216 }
217
218 irqreturn_t isci_msix_isr(int vec, void *data)
219 {
220         struct isci_host *ihost = data;
221
222         if (scic_sds_controller_isr(&ihost->sci))
223                 tasklet_schedule(&ihost->completion_tasklet);
224
225         return IRQ_HANDLED;
226 }
227
228 static bool scic_sds_controller_error_isr(struct scic_sds_controller *scic)
229 {
230         u32 interrupt_status;
231
232         interrupt_status =
233                 readl(&scic->smu_registers->interrupt_status);
234         interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
235
236         if (interrupt_status != 0) {
237                 /*
238                  * There is an error interrupt pending so let it through and handle
239                  * in the callback */
240                 return true;
241         }
242
243         /*
244          * There is a race in the hardware that could cause us not to be notified
245          * of an interrupt completion if we do not take this step.  We will mask
246          * then unmask the error interrupts so if there was another interrupt
247          * pending we will be notified.
248          * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
249         writel(0xff, &scic->smu_registers->interrupt_mask);
250         writel(0, &scic->smu_registers->interrupt_mask);
251
252         return false;
253 }
254
255 static void scic_sds_controller_task_completion(struct scic_sds_controller *scic,
256                                                 u32 completion_entry)
257 {
258         u32 index;
259         struct scic_sds_request *sci_req;
260
261         index = SCU_GET_COMPLETION_INDEX(completion_entry);
262         sci_req = scic->io_request_table[index];
263
264         /* Make sure that we really want to process this IO request */
265         if (sci_req && sci_req->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
266             ISCI_TAG_SEQ(sci_req->io_tag) == scic->io_request_sequence[index])
267                 /* Yep this is a valid io request pass it along to the io request handler */
268                 scic_sds_io_request_tc_completion(sci_req, completion_entry);
269 }
270
271 static void scic_sds_controller_sdma_completion(struct scic_sds_controller *scic,
272                                                 u32 completion_entry)
273 {
274         u32 index;
275         struct scic_sds_request *io_request;
276         struct scic_sds_remote_device *device;
277
278         index = SCU_GET_COMPLETION_INDEX(completion_entry);
279
280         switch (scu_get_command_request_type(completion_entry)) {
281         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
282         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
283                 io_request = scic->io_request_table[index];
284                 dev_warn(scic_to_dev(scic),
285                          "%s: SCIC SDS Completion type SDMA %x for io request "
286                          "%p\n",
287                          __func__,
288                          completion_entry,
289                          io_request);
290                 /* @todo For a post TC operation we need to fail the IO
291                  * request
292                  */
293                 break;
294
295         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
296         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
297         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
298                 device = scic->device_table[index];
299                 dev_warn(scic_to_dev(scic),
300                          "%s: SCIC SDS Completion type SDMA %x for remote "
301                          "device %p\n",
302                          __func__,
303                          completion_entry,
304                          device);
305                 /* @todo For a port RNC operation we need to fail the
306                  * device
307                  */
308                 break;
309
310         default:
311                 dev_warn(scic_to_dev(scic),
312                          "%s: SCIC SDS Completion unknown SDMA completion "
313                          "type %x\n",
314                          __func__,
315                          completion_entry);
316                 break;
317
318         }
319 }
320
321 static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *scic,
322                                                   u32 completion_entry)
323 {
324         u32 index;
325         u32 frame_index;
326
327         struct isci_host *ihost = scic_to_ihost(scic);
328         struct scu_unsolicited_frame_header *frame_header;
329         struct scic_sds_phy *phy;
330         struct scic_sds_remote_device *device;
331
332         enum sci_status result = SCI_FAILURE;
333
334         frame_index = SCU_GET_FRAME_INDEX(completion_entry);
335
336         frame_header = scic->uf_control.buffers.array[frame_index].header;
337         scic->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
338
339         if (SCU_GET_FRAME_ERROR(completion_entry)) {
340                 /*
341                  * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
342                  * /       this cause a problem? We expect the phy initialization will
343                  * /       fail if there is an error in the frame. */
344                 scic_sds_controller_release_frame(scic, frame_index);
345                 return;
346         }
347
348         if (frame_header->is_address_frame) {
349                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
350                 phy = &ihost->phys[index].sci;
351                 result = scic_sds_phy_frame_handler(phy, frame_index);
352         } else {
353
354                 index = SCU_GET_COMPLETION_INDEX(completion_entry);
355
356                 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
357                         /*
358                          * This is a signature fis or a frame from a direct attached SATA
359                          * device that has not yet been created.  In either case forwared
360                          * the frame to the PE and let it take care of the frame data. */
361                         index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
362                         phy = &ihost->phys[index].sci;
363                         result = scic_sds_phy_frame_handler(phy, frame_index);
364                 } else {
365                         if (index < scic->remote_node_entries)
366                                 device = scic->device_table[index];
367                         else
368                                 device = NULL;
369
370                         if (device != NULL)
371                                 result = scic_sds_remote_device_frame_handler(device, frame_index);
372                         else
373                                 scic_sds_controller_release_frame(scic, frame_index);
374                 }
375         }
376
377         if (result != SCI_SUCCESS) {
378                 /*
379                  * / @todo Is there any reason to report some additional error message
380                  * /       when we get this failure notifiction? */
381         }
382 }
383
384 static void scic_sds_controller_event_completion(struct scic_sds_controller *scic,
385                                                  u32 completion_entry)
386 {
387         struct isci_host *ihost = scic_to_ihost(scic);
388         struct scic_sds_request *io_request;
389         struct scic_sds_remote_device *device;
390         struct scic_sds_phy *phy;
391         u32 index;
392
393         index = SCU_GET_COMPLETION_INDEX(completion_entry);
394
395         switch (scu_get_event_type(completion_entry)) {
396         case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
397                 /* / @todo The driver did something wrong and we need to fix the condtion. */
398                 dev_err(scic_to_dev(scic),
399                         "%s: SCIC Controller 0x%p received SMU command error "
400                         "0x%x\n",
401                         __func__,
402                         scic,
403                         completion_entry);
404                 break;
405
406         case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
407         case SCU_EVENT_TYPE_SMU_ERROR:
408         case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
409                 /*
410                  * / @todo This is a hardware failure and its likely that we want to
411                  * /       reset the controller. */
412                 dev_err(scic_to_dev(scic),
413                         "%s: SCIC Controller 0x%p received fatal controller "
414                         "event  0x%x\n",
415                         __func__,
416                         scic,
417                         completion_entry);
418                 break;
419
420         case SCU_EVENT_TYPE_TRANSPORT_ERROR:
421                 io_request = scic->io_request_table[index];
422                 scic_sds_io_request_event_handler(io_request, completion_entry);
423                 break;
424
425         case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
426                 switch (scu_get_event_specifier(completion_entry)) {
427                 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
428                 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
429                         io_request = scic->io_request_table[index];
430                         if (io_request != NULL)
431                                 scic_sds_io_request_event_handler(io_request, completion_entry);
432                         else
433                                 dev_warn(scic_to_dev(scic),
434                                          "%s: SCIC Controller 0x%p received "
435                                          "event 0x%x for io request object "
436                                          "that doesnt exist.\n",
437                                          __func__,
438                                          scic,
439                                          completion_entry);
440
441                         break;
442
443                 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
444                         device = scic->device_table[index];
445                         if (device != NULL)
446                                 scic_sds_remote_device_event_handler(device, completion_entry);
447                         else
448                                 dev_warn(scic_to_dev(scic),
449                                          "%s: SCIC Controller 0x%p received "
450                                          "event 0x%x for remote device object "
451                                          "that doesnt exist.\n",
452                                          __func__,
453                                          scic,
454                                          completion_entry);
455
456                         break;
457                 }
458                 break;
459
460         case SCU_EVENT_TYPE_BROADCAST_CHANGE:
461         /*
462          * direct the broadcast change event to the phy first and then let
463          * the phy redirect the broadcast change to the port object */
464         case SCU_EVENT_TYPE_ERR_CNT_EVENT:
465         /*
466          * direct error counter event to the phy object since that is where
467          * we get the event notification.  This is a type 4 event. */
468         case SCU_EVENT_TYPE_OSSP_EVENT:
469                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry);
470                 phy = &ihost->phys[index].sci;
471                 scic_sds_phy_event_handler(phy, completion_entry);
472                 break;
473
474         case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
475         case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
476         case SCU_EVENT_TYPE_RNC_OPS_MISC:
477                 if (index < scic->remote_node_entries) {
478                         device = scic->device_table[index];
479
480                         if (device != NULL)
481                                 scic_sds_remote_device_event_handler(device, completion_entry);
482                 } else
483                         dev_err(scic_to_dev(scic),
484                                 "%s: SCIC Controller 0x%p received event 0x%x "
485                                 "for remote device object 0x%0x that doesnt "
486                                 "exist.\n",
487                                 __func__,
488                                 scic,
489                                 completion_entry,
490                                 index);
491
492                 break;
493
494         default:
495                 dev_warn(scic_to_dev(scic),
496                          "%s: SCIC Controller received unknown event code %x\n",
497                          __func__,
498                          completion_entry);
499                 break;
500         }
501 }
502
503 static void scic_sds_controller_process_completions(struct scic_sds_controller *scic)
504 {
505         u32 completion_count = 0;
506         u32 completion_entry;
507         u32 get_index;
508         u32 get_cycle;
509         u32 event_get;
510         u32 event_cycle;
511
512         dev_dbg(scic_to_dev(scic),
513                 "%s: completion queue begining get:0x%08x\n",
514                 __func__,
515                 scic->completion_queue_get);
516
517         /* Get the component parts of the completion queue */
518         get_index = NORMALIZE_GET_POINTER(scic->completion_queue_get);
519         get_cycle = SMU_CQGR_CYCLE_BIT & scic->completion_queue_get;
520
521         event_get = NORMALIZE_EVENT_POINTER(scic->completion_queue_get);
522         event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & scic->completion_queue_get;
523
524         while (
525                 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
526                 == COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index])
527                 ) {
528                 completion_count++;
529
530                 completion_entry = scic->completion_queue[get_index];
531
532                 /* increment the get pointer and check for rollover to toggle the cycle bit */
533                 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
534                              (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
535                 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
536
537                 dev_dbg(scic_to_dev(scic),
538                         "%s: completion queue entry:0x%08x\n",
539                         __func__,
540                         completion_entry);
541
542                 switch (SCU_GET_COMPLETION_TYPE(completion_entry)) {
543                 case SCU_COMPLETION_TYPE_TASK:
544                         scic_sds_controller_task_completion(scic, completion_entry);
545                         break;
546
547                 case SCU_COMPLETION_TYPE_SDMA:
548                         scic_sds_controller_sdma_completion(scic, completion_entry);
549                         break;
550
551                 case SCU_COMPLETION_TYPE_UFI:
552                         scic_sds_controller_unsolicited_frame(scic, completion_entry);
553                         break;
554
555                 case SCU_COMPLETION_TYPE_EVENT:
556                 case SCU_COMPLETION_TYPE_NOTIFY: {
557                         event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
558                                        (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
559                         event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
560
561                         scic_sds_controller_event_completion(scic, completion_entry);
562                         break;
563                 }
564                 default:
565                         dev_warn(scic_to_dev(scic),
566                                  "%s: SCIC Controller received unknown "
567                                  "completion type %x\n",
568                                  __func__,
569                                  completion_entry);
570                         break;
571                 }
572         }
573
574         /* Update the get register if we completed one or more entries */
575         if (completion_count > 0) {
576                 scic->completion_queue_get =
577                         SMU_CQGR_GEN_BIT(ENABLE) |
578                         SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
579                         event_cycle |
580                         SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
581                         get_cycle |
582                         SMU_CQGR_GEN_VAL(POINTER, get_index);
583
584                 writel(scic->completion_queue_get,
585                        &scic->smu_registers->completion_queue_get);
586
587         }
588
589         dev_dbg(scic_to_dev(scic),
590                 "%s: completion queue ending get:0x%08x\n",
591                 __func__,
592                 scic->completion_queue_get);
593
594 }
595
596 static void scic_sds_controller_error_handler(struct scic_sds_controller *scic)
597 {
598         u32 interrupt_status;
599
600         interrupt_status =
601                 readl(&scic->smu_registers->interrupt_status);
602
603         if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
604             scic_sds_controller_completion_queue_has_entries(scic)) {
605
606                 scic_sds_controller_process_completions(scic);
607                 writel(SMU_ISR_QUEUE_SUSPEND, &scic->smu_registers->interrupt_status);
608         } else {
609                 dev_err(scic_to_dev(scic), "%s: status: %#x\n", __func__,
610                         interrupt_status);
611
612                 sci_change_state(&scic->sm, SCIC_FAILED);
613
614                 return;
615         }
616
617         /* If we dont process any completions I am not sure that we want to do this.
618          * We are in the middle of a hardware fault and should probably be reset.
619          */
620         writel(0, &scic->smu_registers->interrupt_mask);
621 }
622
623 irqreturn_t isci_intx_isr(int vec, void *data)
624 {
625         irqreturn_t ret = IRQ_NONE;
626         struct isci_host *ihost = data;
627         struct scic_sds_controller *scic = &ihost->sci;
628
629         if (scic_sds_controller_isr(scic)) {
630                 writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
631                 tasklet_schedule(&ihost->completion_tasklet);
632                 ret = IRQ_HANDLED;
633         } else if (scic_sds_controller_error_isr(scic)) {
634                 spin_lock(&ihost->scic_lock);
635                 scic_sds_controller_error_handler(scic);
636                 spin_unlock(&ihost->scic_lock);
637                 ret = IRQ_HANDLED;
638         }
639
640         return ret;
641 }
642
643 irqreturn_t isci_error_isr(int vec, void *data)
644 {
645         struct isci_host *ihost = data;
646
647         if (scic_sds_controller_error_isr(&ihost->sci))
648                 scic_sds_controller_error_handler(&ihost->sci);
649
650         return IRQ_HANDLED;
651 }
652
653 /**
654  * isci_host_start_complete() - This function is called by the core library,
655  *    through the ISCI Module, to indicate controller start status.
656  * @isci_host: This parameter specifies the ISCI host object
657  * @completion_status: This parameter specifies the completion status from the
658  *    core library.
659  *
660  */
661 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
662 {
663         if (completion_status != SCI_SUCCESS)
664                 dev_info(&ihost->pdev->dev,
665                         "controller start timed out, continuing...\n");
666         isci_host_change_state(ihost, isci_ready);
667         clear_bit(IHOST_START_PENDING, &ihost->flags);
668         wake_up(&ihost->eventq);
669 }
670
671 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
672 {
673         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
674
675         if (test_bit(IHOST_START_PENDING, &ihost->flags))
676                 return 0;
677
678         /* todo: use sas_flush_discovery once it is upstream */
679         scsi_flush_work(shost);
680
681         scsi_flush_work(shost);
682
683         dev_dbg(&ihost->pdev->dev,
684                 "%s: ihost->status = %d, time = %ld\n",
685                  __func__, isci_host_get_state(ihost), time);
686
687         return 1;
688
689 }
690
691 /**
692  * scic_controller_get_suggested_start_timeout() - This method returns the
693  *    suggested scic_controller_start() timeout amount.  The user is free to
694  *    use any timeout value, but this method provides the suggested minimum
695  *    start timeout value.  The returned value is based upon empirical
696  *    information determined as a result of interoperability testing.
697  * @controller: the handle to the controller object for which to return the
698  *    suggested start timeout.
699  *
700  * This method returns the number of milliseconds for the suggested start
701  * operation timeout.
702  */
703 static u32 scic_controller_get_suggested_start_timeout(
704         struct scic_sds_controller *sc)
705 {
706         /* Validate the user supplied parameters. */
707         if (sc == NULL)
708                 return 0;
709
710         /*
711          * The suggested minimum timeout value for a controller start operation:
712          *
713          *     Signature FIS Timeout
714          *   + Phy Start Timeout
715          *   + Number of Phy Spin Up Intervals
716          *   ---------------------------------
717          *   Number of milliseconds for the controller start operation.
718          *
719          * NOTE: The number of phy spin up intervals will be equivalent
720          *       to the number of phys divided by the number phys allowed
721          *       per interval - 1 (once OEM parameters are supported).
722          *       Currently we assume only 1 phy per interval. */
723
724         return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
725                 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
726                 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
727 }
728
729 static void scic_controller_enable_interrupts(
730         struct scic_sds_controller *scic)
731 {
732         BUG_ON(scic->smu_registers == NULL);
733         writel(0, &scic->smu_registers->interrupt_mask);
734 }
735
736 void scic_controller_disable_interrupts(
737         struct scic_sds_controller *scic)
738 {
739         BUG_ON(scic->smu_registers == NULL);
740         writel(0xffffffff, &scic->smu_registers->interrupt_mask);
741 }
742
743 static void scic_sds_controller_enable_port_task_scheduler(
744         struct scic_sds_controller *scic)
745 {
746         u32 port_task_scheduler_value;
747
748         port_task_scheduler_value =
749                 readl(&scic->scu_registers->peg0.ptsg.control);
750         port_task_scheduler_value |=
751                 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
752                  SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
753         writel(port_task_scheduler_value,
754                &scic->scu_registers->peg0.ptsg.control);
755 }
756
757 static void scic_sds_controller_assign_task_entries(struct scic_sds_controller *scic)
758 {
759         u32 task_assignment;
760
761         /*
762          * Assign all the TCs to function 0
763          * TODO: Do we actually need to read this register to write it back?
764          */
765
766         task_assignment =
767                 readl(&scic->smu_registers->task_context_assignment[0]);
768
769         task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
770                 (SMU_TCA_GEN_VAL(ENDING,  scic->task_context_entries - 1)) |
771                 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
772
773         writel(task_assignment,
774                 &scic->smu_registers->task_context_assignment[0]);
775
776 }
777
778 static void scic_sds_controller_initialize_completion_queue(struct scic_sds_controller *scic)
779 {
780         u32 index;
781         u32 completion_queue_control_value;
782         u32 completion_queue_get_value;
783         u32 completion_queue_put_value;
784
785         scic->completion_queue_get = 0;
786
787         completion_queue_control_value =
788                 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
789                  SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
790
791         writel(completion_queue_control_value,
792                &scic->smu_registers->completion_queue_control);
793
794
795         /* Set the completion queue get pointer and enable the queue */
796         completion_queue_get_value = (
797                 (SMU_CQGR_GEN_VAL(POINTER, 0))
798                 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
799                 | (SMU_CQGR_GEN_BIT(ENABLE))
800                 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
801                 );
802
803         writel(completion_queue_get_value,
804                &scic->smu_registers->completion_queue_get);
805
806         /* Set the completion queue put pointer */
807         completion_queue_put_value = (
808                 (SMU_CQPR_GEN_VAL(POINTER, 0))
809                 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
810                 );
811
812         writel(completion_queue_put_value,
813                &scic->smu_registers->completion_queue_put);
814
815         /* Initialize the cycle bit of the completion queue entries */
816         for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
817                 /*
818                  * If get.cycle_bit != completion_queue.cycle_bit
819                  * its not a valid completion queue entry
820                  * so at system start all entries are invalid */
821                 scic->completion_queue[index] = 0x80000000;
822         }
823 }
824
825 static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_sds_controller *scic)
826 {
827         u32 frame_queue_control_value;
828         u32 frame_queue_get_value;
829         u32 frame_queue_put_value;
830
831         /* Write the queue size */
832         frame_queue_control_value =
833                 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
834
835         writel(frame_queue_control_value,
836                &scic->scu_registers->sdma.unsolicited_frame_queue_control);
837
838         /* Setup the get pointer for the unsolicited frame queue */
839         frame_queue_get_value = (
840                 SCU_UFQGP_GEN_VAL(POINTER, 0)
841                 |  SCU_UFQGP_GEN_BIT(ENABLE_BIT)
842                 );
843
844         writel(frame_queue_get_value,
845                &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
846         /* Setup the put pointer for the unsolicited frame queue */
847         frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
848         writel(frame_queue_put_value,
849                &scic->scu_registers->sdma.unsolicited_frame_put_pointer);
850 }
851
852 /**
853  * This method will attempt to transition into the ready state for the
854  *    controller and indicate that the controller start operation has completed
855  *    if all criteria are met.
856  * @scic: This parameter indicates the controller object for which
857  *    to transition to ready.
858  * @status: This parameter indicates the status value to be pass into the call
859  *    to scic_cb_controller_start_complete().
860  *
861  * none.
862  */
863 static void scic_sds_controller_transition_to_ready(
864         struct scic_sds_controller *scic,
865         enum sci_status status)
866 {
867         struct isci_host *ihost = scic_to_ihost(scic);
868
869         if (scic->sm.current_state_id == SCIC_STARTING) {
870                 /*
871                  * We move into the ready state, because some of the phys/ports
872                  * may be up and operational.
873                  */
874                 sci_change_state(&scic->sm, SCIC_READY);
875
876                 isci_host_start_complete(ihost, status);
877         }
878 }
879
880 static bool is_phy_starting(struct scic_sds_phy *sci_phy)
881 {
882         enum scic_sds_phy_states state;
883
884         state = sci_phy->sm.current_state_id;
885         switch (state) {
886         case SCI_PHY_STARTING:
887         case SCI_PHY_SUB_INITIAL:
888         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
889         case SCI_PHY_SUB_AWAIT_IAF_UF:
890         case SCI_PHY_SUB_AWAIT_SAS_POWER:
891         case SCI_PHY_SUB_AWAIT_SATA_POWER:
892         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
893         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
894         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
895         case SCI_PHY_SUB_FINAL:
896                 return true;
897         default:
898                 return false;
899         }
900 }
901
902 /**
903  * scic_sds_controller_start_next_phy - start phy
904  * @scic: controller
905  *
906  * If all the phys have been started, then attempt to transition the
907  * controller to the READY state and inform the user
908  * (scic_cb_controller_start_complete()).
909  */
910 static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_controller *scic)
911 {
912         struct isci_host *ihost = scic_to_ihost(scic);
913         struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
914         struct scic_sds_phy *sci_phy;
915         enum sci_status status;
916
917         status = SCI_SUCCESS;
918
919         if (scic->phy_startup_timer_pending)
920                 return status;
921
922         if (scic->next_phy_to_start >= SCI_MAX_PHYS) {
923                 bool is_controller_start_complete = true;
924                 u32 state;
925                 u8 index;
926
927                 for (index = 0; index < SCI_MAX_PHYS; index++) {
928                         sci_phy = &ihost->phys[index].sci;
929                         state = sci_phy->sm.current_state_id;
930
931                         if (!phy_get_non_dummy_port(sci_phy))
932                                 continue;
933
934                         /* The controller start operation is complete iff:
935                          * - all links have been given an opportunity to start
936                          * - have no indication of a connected device
937                          * - have an indication of a connected device and it has
938                          *   finished the link training process.
939                          */
940                         if ((sci_phy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
941                             (sci_phy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
942                             (sci_phy->is_in_link_training == true && is_phy_starting(sci_phy))) {
943                                 is_controller_start_complete = false;
944                                 break;
945                         }
946                 }
947
948                 /*
949                  * The controller has successfully finished the start process.
950                  * Inform the SCI Core user and transition to the READY state. */
951                 if (is_controller_start_complete == true) {
952                         scic_sds_controller_transition_to_ready(scic, SCI_SUCCESS);
953                         sci_del_timer(&scic->phy_timer);
954                         scic->phy_startup_timer_pending = false;
955                 }
956         } else {
957                 sci_phy = &ihost->phys[scic->next_phy_to_start].sci;
958
959                 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
960                         if (phy_get_non_dummy_port(sci_phy) == NULL) {
961                                 scic->next_phy_to_start++;
962
963                                 /* Caution recursion ahead be forwarned
964                                  *
965                                  * The PHY was never added to a PORT in MPC mode
966                                  * so start the next phy in sequence This phy
967                                  * will never go link up and will not draw power
968                                  * the OEM parameters either configured the phy
969                                  * incorrectly for the PORT or it was never
970                                  * assigned to a PORT
971                                  */
972                                 return scic_sds_controller_start_next_phy(scic);
973                         }
974                 }
975
976                 status = scic_sds_phy_start(sci_phy);
977
978                 if (status == SCI_SUCCESS) {
979                         sci_mod_timer(&scic->phy_timer,
980                                       SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
981                         scic->phy_startup_timer_pending = true;
982                 } else {
983                         dev_warn(scic_to_dev(scic),
984                                  "%s: Controller stop operation failed "
985                                  "to stop phy %d because of status "
986                                  "%d.\n",
987                                  __func__,
988                                  ihost->phys[scic->next_phy_to_start].sci.phy_index,
989                                  status);
990                 }
991
992                 scic->next_phy_to_start++;
993         }
994
995         return status;
996 }
997
998 static void phy_startup_timeout(unsigned long data)
999 {
1000         struct sci_timer *tmr = (struct sci_timer *)data;
1001         struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), phy_timer);
1002         struct isci_host *ihost = scic_to_ihost(scic);
1003         unsigned long flags;
1004         enum sci_status status;
1005
1006         spin_lock_irqsave(&ihost->scic_lock, flags);
1007
1008         if (tmr->cancel)
1009                 goto done;
1010
1011         scic->phy_startup_timer_pending = false;
1012
1013         do {
1014                 status = scic_sds_controller_start_next_phy(scic);
1015         } while (status != SCI_SUCCESS);
1016
1017 done:
1018         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1019 }
1020
1021 static u16 isci_tci_active(struct isci_host *ihost)
1022 {
1023         return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
1024 }
1025
1026 static enum sci_status scic_controller_start(struct scic_sds_controller *scic,
1027                                              u32 timeout)
1028 {
1029         struct isci_host *ihost = scic_to_ihost(scic);
1030         enum sci_status result;
1031         u16 index;
1032
1033         if (scic->sm.current_state_id != SCIC_INITIALIZED) {
1034                 dev_warn(scic_to_dev(scic),
1035                          "SCIC Controller start operation requested in "
1036                          "invalid state\n");
1037                 return SCI_FAILURE_INVALID_STATE;
1038         }
1039
1040         /* Build the TCi free pool */
1041         BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
1042         ihost->tci_head = 0;
1043         ihost->tci_tail = 0;
1044         for (index = 0; index < scic->task_context_entries; index++)
1045                 isci_tci_free(ihost, index);
1046
1047         /* Build the RNi free pool */
1048         scic_sds_remote_node_table_initialize(
1049                         &scic->available_remote_nodes,
1050                         scic->remote_node_entries);
1051
1052         /*
1053          * Before anything else lets make sure we will not be
1054          * interrupted by the hardware.
1055          */
1056         scic_controller_disable_interrupts(scic);
1057
1058         /* Enable the port task scheduler */
1059         scic_sds_controller_enable_port_task_scheduler(scic);
1060
1061         /* Assign all the task entries to scic physical function */
1062         scic_sds_controller_assign_task_entries(scic);
1063
1064         /* Now initialize the completion queue */
1065         scic_sds_controller_initialize_completion_queue(scic);
1066
1067         /* Initialize the unsolicited frame queue for use */
1068         scic_sds_controller_initialize_unsolicited_frame_queue(scic);
1069
1070         /* Start all of the ports on this controller */
1071         for (index = 0; index < scic->logical_port_entries; index++) {
1072                 struct scic_sds_port *sci_port = &ihost->ports[index].sci;
1073
1074                 result = scic_sds_port_start(sci_port);
1075                 if (result)
1076                         return result;
1077         }
1078
1079         scic_sds_controller_start_next_phy(scic);
1080
1081         sci_mod_timer(&scic->timer, timeout);
1082
1083         sci_change_state(&scic->sm, SCIC_STARTING);
1084
1085         return SCI_SUCCESS;
1086 }
1087
1088 void isci_host_scan_start(struct Scsi_Host *shost)
1089 {
1090         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1091         unsigned long tmo = scic_controller_get_suggested_start_timeout(&ihost->sci);
1092
1093         set_bit(IHOST_START_PENDING, &ihost->flags);
1094
1095         spin_lock_irq(&ihost->scic_lock);
1096         scic_controller_start(&ihost->sci, tmo);
1097         scic_controller_enable_interrupts(&ihost->sci);
1098         spin_unlock_irq(&ihost->scic_lock);
1099 }
1100
1101 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1102 {
1103         isci_host_change_state(ihost, isci_stopped);
1104         scic_controller_disable_interrupts(&ihost->sci);
1105         clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1106         wake_up(&ihost->eventq);
1107 }
1108
1109 static void scic_sds_controller_completion_handler(struct scic_sds_controller *scic)
1110 {
1111         /* Empty out the completion queue */
1112         if (scic_sds_controller_completion_queue_has_entries(scic))
1113                 scic_sds_controller_process_completions(scic);
1114
1115         /* Clear the interrupt and enable all interrupts again */
1116         writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status);
1117         /* Could we write the value of SMU_ISR_COMPLETION? */
1118         writel(0xFF000000, &scic->smu_registers->interrupt_mask);
1119         writel(0, &scic->smu_registers->interrupt_mask);
1120 }
1121
1122 /**
1123  * isci_host_completion_routine() - This function is the delayed service
1124  *    routine that calls the sci core library's completion handler. It's
1125  *    scheduled as a tasklet from the interrupt service routine when interrupts
1126  *    in use, or set as the timeout function in polled mode.
1127  * @data: This parameter specifies the ISCI host object
1128  *
1129  */
1130 static void isci_host_completion_routine(unsigned long data)
1131 {
1132         struct isci_host *isci_host = (struct isci_host *)data;
1133         struct list_head    completed_request_list;
1134         struct list_head    errored_request_list;
1135         struct list_head    *current_position;
1136         struct list_head    *next_position;
1137         struct isci_request *request;
1138         struct isci_request *next_request;
1139         struct sas_task     *task;
1140
1141         INIT_LIST_HEAD(&completed_request_list);
1142         INIT_LIST_HEAD(&errored_request_list);
1143
1144         spin_lock_irq(&isci_host->scic_lock);
1145
1146         scic_sds_controller_completion_handler(&isci_host->sci);
1147
1148         /* Take the lists of completed I/Os from the host. */
1149
1150         list_splice_init(&isci_host->requests_to_complete,
1151                          &completed_request_list);
1152
1153         /* Take the list of errored I/Os from the host. */
1154         list_splice_init(&isci_host->requests_to_errorback,
1155                          &errored_request_list);
1156
1157         spin_unlock_irq(&isci_host->scic_lock);
1158
1159         /* Process any completions in the lists. */
1160         list_for_each_safe(current_position, next_position,
1161                            &completed_request_list) {
1162
1163                 request = list_entry(current_position, struct isci_request,
1164                                      completed_node);
1165                 task = isci_request_access_task(request);
1166
1167                 /* Normal notification (task_done) */
1168                 dev_dbg(&isci_host->pdev->dev,
1169                         "%s: Normal - request/task = %p/%p\n",
1170                         __func__,
1171                         request,
1172                         task);
1173
1174                 /* Return the task to libsas */
1175                 if (task != NULL) {
1176
1177                         task->lldd_task = NULL;
1178                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1179
1180                                 /* If the task is already in the abort path,
1181                                 * the task_done callback cannot be called.
1182                                 */
1183                                 task->task_done(task);
1184                         }
1185                 }
1186
1187                 spin_lock_irq(&isci_host->scic_lock);
1188                 isci_free_tag(isci_host, request->sci.io_tag);
1189                 spin_unlock_irq(&isci_host->scic_lock);
1190
1191                 /* Free the request object. */
1192                 isci_request_free(isci_host, request);
1193         }
1194         list_for_each_entry_safe(request, next_request, &errored_request_list,
1195                                  completed_node) {
1196
1197                 task = isci_request_access_task(request);
1198
1199                 /* Use sas_task_abort */
1200                 dev_warn(&isci_host->pdev->dev,
1201                          "%s: Error - request/task = %p/%p\n",
1202                          __func__,
1203                          request,
1204                          task);
1205
1206                 if (task != NULL) {
1207
1208                         /* Put the task into the abort path if it's not there
1209                          * already.
1210                          */
1211                         if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1212                                 sas_task_abort(task);
1213
1214                 } else {
1215                         /* This is a case where the request has completed with a
1216                          * status such that it needed further target servicing,
1217                          * but the sas_task reference has already been removed
1218                          * from the request.  Since it was errored, it was not
1219                          * being aborted, so there is nothing to do except free
1220                          * it.
1221                          */
1222
1223                         spin_lock_irq(&isci_host->scic_lock);
1224                         /* Remove the request from the remote device's list
1225                         * of pending requests.
1226                         */
1227                         list_del_init(&request->dev_node);
1228                         isci_free_tag(isci_host, request->sci.io_tag);
1229                         spin_unlock_irq(&isci_host->scic_lock);
1230
1231                         /* Free the request object. */
1232                         isci_request_free(isci_host, request);
1233                 }
1234         }
1235
1236 }
1237
1238 /**
1239  * scic_controller_stop() - This method will stop an individual controller
1240  *    object.This method will invoke the associated user callback upon
1241  *    completion.  The completion callback is called when the following
1242  *    conditions are met: -# the method return status is SCI_SUCCESS. -# the
1243  *    controller has been quiesced. This method will ensure that all IO
1244  *    requests are quiesced, phys are stopped, and all additional operation by
1245  *    the hardware is halted.
1246  * @controller: the handle to the controller object to stop.
1247  * @timeout: This parameter specifies the number of milliseconds in which the
1248  *    stop operation should complete.
1249  *
1250  * The controller must be in the STARTED or STOPPED state. Indicate if the
1251  * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1252  * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1253  * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1254  * controller is not either in the STARTED or STOPPED states.
1255  */
1256 static enum sci_status scic_controller_stop(struct scic_sds_controller *scic,
1257                                             u32 timeout)
1258 {
1259         if (scic->sm.current_state_id != SCIC_READY) {
1260                 dev_warn(scic_to_dev(scic),
1261                          "SCIC Controller stop operation requested in "
1262                          "invalid state\n");
1263                 return SCI_FAILURE_INVALID_STATE;
1264         }
1265
1266         sci_mod_timer(&scic->timer, timeout);
1267         sci_change_state(&scic->sm, SCIC_STOPPING);
1268         return SCI_SUCCESS;
1269 }
1270
1271 /**
1272  * scic_controller_reset() - This method will reset the supplied core
1273  *    controller regardless of the state of said controller.  This operation is
1274  *    considered destructive.  In other words, all current operations are wiped
1275  *    out.  No IO completions for outstanding devices occur.  Outstanding IO
1276  *    requests are not aborted or completed at the actual remote device.
1277  * @controller: the handle to the controller object to reset.
1278  *
1279  * Indicate if the controller reset method succeeded or failed in some way.
1280  * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1281  * the controller reset operation is unable to complete.
1282  */
1283 static enum sci_status scic_controller_reset(struct scic_sds_controller *scic)
1284 {
1285         switch (scic->sm.current_state_id) {
1286         case SCIC_RESET:
1287         case SCIC_READY:
1288         case SCIC_STOPPED:
1289         case SCIC_FAILED:
1290                 /*
1291                  * The reset operation is not a graceful cleanup, just
1292                  * perform the state transition.
1293                  */
1294                 sci_change_state(&scic->sm, SCIC_RESETTING);
1295                 return SCI_SUCCESS;
1296         default:
1297                 dev_warn(scic_to_dev(scic),
1298                          "SCIC Controller reset operation requested in "
1299                          "invalid state\n");
1300                 return SCI_FAILURE_INVALID_STATE;
1301         }
1302 }
1303
1304 void isci_host_deinit(struct isci_host *ihost)
1305 {
1306         int i;
1307
1308         isci_host_change_state(ihost, isci_stopping);
1309         for (i = 0; i < SCI_MAX_PORTS; i++) {
1310                 struct isci_port *iport = &ihost->ports[i];
1311                 struct isci_remote_device *idev, *d;
1312
1313                 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
1314                         if (test_bit(IDEV_ALLOCATED, &idev->flags))
1315                                 isci_remote_device_stop(ihost, idev);
1316                 }
1317         }
1318
1319         set_bit(IHOST_STOP_PENDING, &ihost->flags);
1320
1321         spin_lock_irq(&ihost->scic_lock);
1322         scic_controller_stop(&ihost->sci, SCIC_CONTROLLER_STOP_TIMEOUT);
1323         spin_unlock_irq(&ihost->scic_lock);
1324
1325         wait_for_stop(ihost);
1326         scic_controller_reset(&ihost->sci);
1327
1328         /* Cancel any/all outstanding port timers */
1329         for (i = 0; i < ihost->sci.logical_port_entries; i++) {
1330                 struct scic_sds_port *sci_port = &ihost->ports[i].sci;
1331                 del_timer_sync(&sci_port->timer.timer);
1332         }
1333
1334         /* Cancel any/all outstanding phy timers */
1335         for (i = 0; i < SCI_MAX_PHYS; i++) {
1336                 struct scic_sds_phy *sci_phy = &ihost->phys[i].sci;
1337                 del_timer_sync(&sci_phy->sata_timer.timer);
1338         }
1339
1340         del_timer_sync(&ihost->sci.port_agent.timer.timer);
1341
1342         del_timer_sync(&ihost->sci.power_control.timer.timer);
1343
1344         del_timer_sync(&ihost->sci.timer.timer);
1345
1346         del_timer_sync(&ihost->sci.phy_timer.timer);
1347 }
1348
1349 static void __iomem *scu_base(struct isci_host *isci_host)
1350 {
1351         struct pci_dev *pdev = isci_host->pdev;
1352         int id = isci_host->id;
1353
1354         return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1355 }
1356
1357 static void __iomem *smu_base(struct isci_host *isci_host)
1358 {
1359         struct pci_dev *pdev = isci_host->pdev;
1360         int id = isci_host->id;
1361
1362         return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1363 }
1364
1365 static void isci_user_parameters_get(
1366                 struct isci_host *isci_host,
1367                 union scic_user_parameters *scic_user_params)
1368 {
1369         struct scic_sds_user_parameters *u = &scic_user_params->sds1;
1370         int i;
1371
1372         for (i = 0; i < SCI_MAX_PHYS; i++) {
1373                 struct sci_phy_user_params *u_phy = &u->phys[i];
1374
1375                 u_phy->max_speed_generation = phy_gen;
1376
1377                 /* we are not exporting these for now */
1378                 u_phy->align_insertion_frequency = 0x7f;
1379                 u_phy->in_connection_align_insertion_frequency = 0xff;
1380                 u_phy->notify_enable_spin_up_insertion_frequency = 0x33;
1381         }
1382
1383         u->stp_inactivity_timeout = stp_inactive_to;
1384         u->ssp_inactivity_timeout = ssp_inactive_to;
1385         u->stp_max_occupancy_timeout = stp_max_occ_to;
1386         u->ssp_max_occupancy_timeout = ssp_max_occ_to;
1387         u->no_outbound_task_timeout = no_outbound_task_to;
1388         u->max_number_concurrent_device_spin_up = max_concurr_spinup;
1389 }
1390
1391 static void scic_sds_controller_initial_state_enter(struct sci_base_state_machine *sm)
1392 {
1393         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1394
1395         sci_change_state(&scic->sm, SCIC_RESET);
1396 }
1397
1398 static inline void scic_sds_controller_starting_state_exit(struct sci_base_state_machine *sm)
1399 {
1400         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1401
1402         sci_del_timer(&scic->timer);
1403 }
1404
1405 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1406 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1407 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US                    2700000
1408 #define INTERRUPT_COALESCE_NUMBER_MAX                        256
1409 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN                7
1410 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX                28
1411
1412 /**
1413  * scic_controller_set_interrupt_coalescence() - This method allows the user to
1414  *    configure the interrupt coalescence.
1415  * @controller: This parameter represents the handle to the controller object
1416  *    for which its interrupt coalesce register is overridden.
1417  * @coalesce_number: Used to control the number of entries in the Completion
1418  *    Queue before an interrupt is generated. If the number of entries exceed
1419  *    this number, an interrupt will be generated. The valid range of the input
1420  *    is [0, 256]. A setting of 0 results in coalescing being disabled.
1421  * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1422  *    input is [0, 2700000] . A setting of 0 is allowed and results in no
1423  *    interrupt coalescing timeout.
1424  *
1425  * Indicate if the user successfully set the interrupt coalesce parameters.
1426  * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1427  * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1428  */
1429 static enum sci_status scic_controller_set_interrupt_coalescence(
1430         struct scic_sds_controller *scic_controller,
1431         u32 coalesce_number,
1432         u32 coalesce_timeout)
1433 {
1434         u8 timeout_encode = 0;
1435         u32 min = 0;
1436         u32 max = 0;
1437
1438         /* Check if the input parameters fall in the range. */
1439         if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1440                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1441
1442         /*
1443          *  Defined encoding for interrupt coalescing timeout:
1444          *              Value   Min      Max     Units
1445          *              -----   ---      ---     -----
1446          *              0       -        -       Disabled
1447          *              1       13.3     20.0    ns
1448          *              2       26.7     40.0
1449          *              3       53.3     80.0
1450          *              4       106.7    160.0
1451          *              5       213.3    320.0
1452          *              6       426.7    640.0
1453          *              7       853.3    1280.0
1454          *              8       1.7      2.6     us
1455          *              9       3.4      5.1
1456          *              10      6.8      10.2
1457          *              11      13.7     20.5
1458          *              12      27.3     41.0
1459          *              13      54.6     81.9
1460          *              14      109.2    163.8
1461          *              15      218.5    327.7
1462          *              16      436.9    655.4
1463          *              17      873.8    1310.7
1464          *              18      1.7      2.6     ms
1465          *              19      3.5      5.2
1466          *              20      7.0      10.5
1467          *              21      14.0     21.0
1468          *              22      28.0     41.9
1469          *              23      55.9     83.9
1470          *              24      111.8    167.8
1471          *              25      223.7    335.5
1472          *              26      447.4    671.1
1473          *              27      894.8    1342.2
1474          *              28      1.8      2.7     s
1475          *              Others Undefined */
1476
1477         /*
1478          * Use the table above to decide the encode of interrupt coalescing timeout
1479          * value for register writing. */
1480         if (coalesce_timeout == 0)
1481                 timeout_encode = 0;
1482         else{
1483                 /* make the timeout value in unit of (10 ns). */
1484                 coalesce_timeout = coalesce_timeout * 100;
1485                 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1486                 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1487
1488                 /* get the encode of timeout for register writing. */
1489                 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1490                       timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1491                       timeout_encode++) {
1492                         if (min <= coalesce_timeout &&  max > coalesce_timeout)
1493                                 break;
1494                         else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1495                                  && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1496                                 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1497                                         break;
1498                                 else{
1499                                         timeout_encode++;
1500                                         break;
1501                                 }
1502                         } else {
1503                                 max = max * 2;
1504                                 min = min * 2;
1505                         }
1506                 }
1507
1508                 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1509                         /* the value is out of range. */
1510                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1511         }
1512
1513         writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1514                SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1515                &scic_controller->smu_registers->interrupt_coalesce_control);
1516
1517
1518         scic_controller->interrupt_coalesce_number = (u16)coalesce_number;
1519         scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100;
1520
1521         return SCI_SUCCESS;
1522 }
1523
1524
1525 static void scic_sds_controller_ready_state_enter(struct sci_base_state_machine *sm)
1526 {
1527         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1528
1529         /* set the default interrupt coalescence number and timeout value. */
1530         scic_controller_set_interrupt_coalescence(scic, 0x10, 250);
1531 }
1532
1533 static void scic_sds_controller_ready_state_exit(struct sci_base_state_machine *sm)
1534 {
1535         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1536
1537         /* disable interrupt coalescence. */
1538         scic_controller_set_interrupt_coalescence(scic, 0, 0);
1539 }
1540
1541 static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller *scic)
1542 {
1543         u32 index;
1544         enum sci_status status;
1545         enum sci_status phy_status;
1546         struct isci_host *ihost = scic_to_ihost(scic);
1547
1548         status = SCI_SUCCESS;
1549
1550         for (index = 0; index < SCI_MAX_PHYS; index++) {
1551                 phy_status = scic_sds_phy_stop(&ihost->phys[index].sci);
1552
1553                 if (phy_status != SCI_SUCCESS &&
1554                     phy_status != SCI_FAILURE_INVALID_STATE) {
1555                         status = SCI_FAILURE;
1556
1557                         dev_warn(scic_to_dev(scic),
1558                                  "%s: Controller stop operation failed to stop "
1559                                  "phy %d because of status %d.\n",
1560                                  __func__,
1561                                  ihost->phys[index].sci.phy_index, phy_status);
1562                 }
1563         }
1564
1565         return status;
1566 }
1567
1568 static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic)
1569 {
1570         u32 index;
1571         enum sci_status port_status;
1572         enum sci_status status = SCI_SUCCESS;
1573         struct isci_host *ihost = scic_to_ihost(scic);
1574
1575         for (index = 0; index < scic->logical_port_entries; index++) {
1576                 struct scic_sds_port *sci_port = &ihost->ports[index].sci;
1577
1578                 port_status = scic_sds_port_stop(sci_port);
1579
1580                 if ((port_status != SCI_SUCCESS) &&
1581                     (port_status != SCI_FAILURE_INVALID_STATE)) {
1582                         status = SCI_FAILURE;
1583
1584                         dev_warn(scic_to_dev(scic),
1585                                  "%s: Controller stop operation failed to "
1586                                  "stop port %d because of status %d.\n",
1587                                  __func__,
1588                                  sci_port->logical_port_index,
1589                                  port_status);
1590                 }
1591         }
1592
1593         return status;
1594 }
1595
1596 static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controller *scic)
1597 {
1598         u32 index;
1599         enum sci_status status;
1600         enum sci_status device_status;
1601
1602         status = SCI_SUCCESS;
1603
1604         for (index = 0; index < scic->remote_node_entries; index++) {
1605                 if (scic->device_table[index] != NULL) {
1606                         /* / @todo What timeout value do we want to provide to this request? */
1607                         device_status = scic_remote_device_stop(scic->device_table[index], 0);
1608
1609                         if ((device_status != SCI_SUCCESS) &&
1610                             (device_status != SCI_FAILURE_INVALID_STATE)) {
1611                                 dev_warn(scic_to_dev(scic),
1612                                          "%s: Controller stop operation failed "
1613                                          "to stop device 0x%p because of "
1614                                          "status %d.\n",
1615                                          __func__,
1616                                          scic->device_table[index], device_status);
1617                         }
1618                 }
1619         }
1620
1621         return status;
1622 }
1623
1624 static void scic_sds_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1625 {
1626         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1627
1628         /* Stop all of the components for this controller */
1629         scic_sds_controller_stop_phys(scic);
1630         scic_sds_controller_stop_ports(scic);
1631         scic_sds_controller_stop_devices(scic);
1632 }
1633
1634 static void scic_sds_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1635 {
1636         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1637
1638         sci_del_timer(&scic->timer);
1639 }
1640
1641
1642 /**
1643  * scic_sds_controller_reset_hardware() -
1644  *
1645  * This method will reset the controller hardware.
1646  */
1647 static void scic_sds_controller_reset_hardware(struct scic_sds_controller *scic)
1648 {
1649         /* Disable interrupts so we dont take any spurious interrupts */
1650         scic_controller_disable_interrupts(scic);
1651
1652         /* Reset the SCU */
1653         writel(0xFFFFFFFF, &scic->smu_registers->soft_reset_control);
1654
1655         /* Delay for 1ms to before clearing the CQP and UFQPR. */
1656         udelay(1000);
1657
1658         /* The write to the CQGR clears the CQP */
1659         writel(0x00000000, &scic->smu_registers->completion_queue_get);
1660
1661         /* The write to the UFQGP clears the UFQPR */
1662         writel(0, &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
1663 }
1664
1665 static void scic_sds_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1666 {
1667         struct scic_sds_controller *scic = container_of(sm, typeof(*scic), sm);
1668
1669         scic_sds_controller_reset_hardware(scic);
1670         sci_change_state(&scic->sm, SCIC_RESET);
1671 }
1672
1673 static const struct sci_base_state scic_sds_controller_state_table[] = {
1674         [SCIC_INITIAL] = {
1675                 .enter_state = scic_sds_controller_initial_state_enter,
1676         },
1677         [SCIC_RESET] = {},
1678         [SCIC_INITIALIZING] = {},
1679         [SCIC_INITIALIZED] = {},
1680         [SCIC_STARTING] = {
1681                 .exit_state  = scic_sds_controller_starting_state_exit,
1682         },
1683         [SCIC_READY] = {
1684                 .enter_state = scic_sds_controller_ready_state_enter,
1685                 .exit_state  = scic_sds_controller_ready_state_exit,
1686         },
1687         [SCIC_RESETTING] = {
1688                 .enter_state = scic_sds_controller_resetting_state_enter,
1689         },
1690         [SCIC_STOPPING] = {
1691                 .enter_state = scic_sds_controller_stopping_state_enter,
1692                 .exit_state = scic_sds_controller_stopping_state_exit,
1693         },
1694         [SCIC_STOPPED] = {},
1695         [SCIC_FAILED] = {}
1696 };
1697
1698 static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic)
1699 {
1700         /* these defaults are overridden by the platform / firmware */
1701         struct isci_host *ihost = scic_to_ihost(scic);
1702         u16 index;
1703
1704         /* Default to APC mode. */
1705         scic->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
1706
1707         /* Default to APC mode. */
1708         scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1;
1709
1710         /* Default to no SSC operation. */
1711         scic->oem_parameters.sds1.controller.do_enable_ssc = false;
1712
1713         /* Initialize all of the port parameter information to narrow ports. */
1714         for (index = 0; index < SCI_MAX_PORTS; index++) {
1715                 scic->oem_parameters.sds1.ports[index].phy_mask = 0;
1716         }
1717
1718         /* Initialize all of the phy parameter information. */
1719         for (index = 0; index < SCI_MAX_PHYS; index++) {
1720                 /* Default to 6G (i.e. Gen 3) for now. */
1721                 scic->user_parameters.sds1.phys[index].max_speed_generation = 3;
1722
1723                 /* the frequencies cannot be 0 */
1724                 scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f;
1725                 scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff;
1726                 scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
1727
1728                 /*
1729                  * Previous Vitesse based expanders had a arbitration issue that
1730                  * is worked around by having the upper 32-bits of SAS address
1731                  * with a value greater then the Vitesse company identifier.
1732                  * Hence, usage of 0x5FCFFFFF. */
1733                 scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id;
1734                 scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF;
1735         }
1736
1737         scic->user_parameters.sds1.stp_inactivity_timeout = 5;
1738         scic->user_parameters.sds1.ssp_inactivity_timeout = 5;
1739         scic->user_parameters.sds1.stp_max_occupancy_timeout = 5;
1740         scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20;
1741         scic->user_parameters.sds1.no_outbound_task_timeout = 20;
1742 }
1743
1744 static void controller_timeout(unsigned long data)
1745 {
1746         struct sci_timer *tmr = (struct sci_timer *)data;
1747         struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), timer);
1748         struct isci_host *ihost = scic_to_ihost(scic);
1749         struct sci_base_state_machine *sm = &scic->sm;
1750         unsigned long flags;
1751
1752         spin_lock_irqsave(&ihost->scic_lock, flags);
1753
1754         if (tmr->cancel)
1755                 goto done;
1756
1757         if (sm->current_state_id == SCIC_STARTING)
1758                 scic_sds_controller_transition_to_ready(scic, SCI_FAILURE_TIMEOUT);
1759         else if (sm->current_state_id == SCIC_STOPPING) {
1760                 sci_change_state(sm, SCIC_FAILED);
1761                 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1762         } else  /* / @todo Now what do we want to do in this case? */
1763                 dev_err(scic_to_dev(scic),
1764                         "%s: Controller timer fired when controller was not "
1765                         "in a state being timed.\n",
1766                         __func__);
1767
1768 done:
1769         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1770 }
1771
1772 /**
1773  * scic_controller_construct() - This method will attempt to construct a
1774  *    controller object utilizing the supplied parameter information.
1775  * @c: This parameter specifies the controller to be constructed.
1776  * @scu_base: mapped base address of the scu registers
1777  * @smu_base: mapped base address of the smu registers
1778  *
1779  * Indicate if the controller was successfully constructed or if it failed in
1780  * some way. SCI_SUCCESS This value is returned if the controller was
1781  * successfully constructed. SCI_WARNING_TIMER_CONFLICT This value is returned
1782  * if the interrupt coalescence timer may cause SAS compliance issues for SMP
1783  * Target mode response processing. SCI_FAILURE_UNSUPPORTED_CONTROLLER_TYPE
1784  * This value is returned if the controller does not support the supplied type.
1785  * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the
1786  * controller does not support the supplied initialization data version.
1787  */
1788 static enum sci_status scic_controller_construct(struct scic_sds_controller *scic,
1789                                           void __iomem *scu_base,
1790                                           void __iomem *smu_base)
1791 {
1792         struct isci_host *ihost = scic_to_ihost(scic);
1793         u8 i;
1794
1795         sci_init_sm(&scic->sm, scic_sds_controller_state_table, SCIC_INITIAL);
1796
1797         scic->scu_registers = scu_base;
1798         scic->smu_registers = smu_base;
1799
1800         scic_sds_port_configuration_agent_construct(&scic->port_agent);
1801
1802         /* Construct the ports for this controller */
1803         for (i = 0; i < SCI_MAX_PORTS; i++)
1804                 scic_sds_port_construct(&ihost->ports[i].sci, i, scic);
1805         scic_sds_port_construct(&ihost->ports[i].sci, SCIC_SDS_DUMMY_PORT, scic);
1806
1807         /* Construct the phys for this controller */
1808         for (i = 0; i < SCI_MAX_PHYS; i++) {
1809                 /* Add all the PHYs to the dummy port */
1810                 scic_sds_phy_construct(&ihost->phys[i].sci,
1811                                        &ihost->ports[SCI_MAX_PORTS].sci, i);
1812         }
1813
1814         scic->invalid_phy_mask = 0;
1815
1816         sci_init_timer(&scic->timer, controller_timeout);
1817
1818         /* Initialize the User and OEM parameters to default values. */
1819         scic_sds_controller_set_default_config_parameters(scic);
1820
1821         return scic_controller_reset(scic);
1822 }
1823
1824 int scic_oem_parameters_validate(struct scic_sds_oem_params *oem)
1825 {
1826         int i;
1827
1828         for (i = 0; i < SCI_MAX_PORTS; i++)
1829                 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1830                         return -EINVAL;
1831
1832         for (i = 0; i < SCI_MAX_PHYS; i++)
1833                 if (oem->phys[i].sas_address.high == 0 &&
1834                     oem->phys[i].sas_address.low == 0)
1835                         return -EINVAL;
1836
1837         if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1838                 for (i = 0; i < SCI_MAX_PHYS; i++)
1839                         if (oem->ports[i].phy_mask != 0)
1840                                 return -EINVAL;
1841         } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1842                 u8 phy_mask = 0;
1843
1844                 for (i = 0; i < SCI_MAX_PHYS; i++)
1845                         phy_mask |= oem->ports[i].phy_mask;
1846
1847                 if (phy_mask == 0)
1848                         return -EINVAL;
1849         } else
1850                 return -EINVAL;
1851
1852         if (oem->controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT)
1853                 return -EINVAL;
1854
1855         return 0;
1856 }
1857
1858 static enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic,
1859                                         union scic_oem_parameters *scic_parms)
1860 {
1861         u32 state = scic->sm.current_state_id;
1862
1863         if (state == SCIC_RESET ||
1864             state == SCIC_INITIALIZING ||
1865             state == SCIC_INITIALIZED) {
1866
1867                 if (scic_oem_parameters_validate(&scic_parms->sds1))
1868                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1869                 scic->oem_parameters.sds1 = scic_parms->sds1;
1870
1871                 return SCI_SUCCESS;
1872         }
1873
1874         return SCI_FAILURE_INVALID_STATE;
1875 }
1876
1877 void scic_oem_parameters_get(
1878         struct scic_sds_controller *scic,
1879         union scic_oem_parameters *scic_parms)
1880 {
1881         memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms));
1882 }
1883
1884 static void power_control_timeout(unsigned long data)
1885 {
1886         struct sci_timer *tmr = (struct sci_timer *)data;
1887         struct scic_sds_controller *scic = container_of(tmr, typeof(*scic), power_control.timer);
1888         struct isci_host *ihost = scic_to_ihost(scic);
1889         struct scic_sds_phy *sci_phy;
1890         unsigned long flags;
1891         u8 i;
1892
1893         spin_lock_irqsave(&ihost->scic_lock, flags);
1894
1895         if (tmr->cancel)
1896                 goto done;
1897
1898         scic->power_control.phys_granted_power = 0;
1899
1900         if (scic->power_control.phys_waiting == 0) {
1901                 scic->power_control.timer_started = false;
1902                 goto done;
1903         }
1904
1905         for (i = 0; i < SCI_MAX_PHYS; i++) {
1906
1907                 if (scic->power_control.phys_waiting == 0)
1908                         break;
1909
1910                 sci_phy = scic->power_control.requesters[i];
1911                 if (sci_phy == NULL)
1912                         continue;
1913
1914                 if (scic->power_control.phys_granted_power >=
1915                     scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up)
1916                         break;
1917
1918                 scic->power_control.requesters[i] = NULL;
1919                 scic->power_control.phys_waiting--;
1920                 scic->power_control.phys_granted_power++;
1921                 scic_sds_phy_consume_power_handler(sci_phy);
1922         }
1923
1924         /*
1925          * It doesn't matter if the power list is empty, we need to start the
1926          * timer in case another phy becomes ready.
1927          */
1928         sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1929         scic->power_control.timer_started = true;
1930
1931 done:
1932         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1933 }
1934
1935 /**
1936  * This method inserts the phy in the stagger spinup control queue.
1937  * @scic:
1938  *
1939  *
1940  */
1941 void scic_sds_controller_power_control_queue_insert(
1942         struct scic_sds_controller *scic,
1943         struct scic_sds_phy *sci_phy)
1944 {
1945         BUG_ON(sci_phy == NULL);
1946
1947         if (scic->power_control.phys_granted_power <
1948             scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) {
1949                 scic->power_control.phys_granted_power++;
1950                 scic_sds_phy_consume_power_handler(sci_phy);
1951
1952                 /*
1953                  * stop and start the power_control timer. When the timer fires, the
1954                  * no_of_phys_granted_power will be set to 0
1955                  */
1956                 if (scic->power_control.timer_started)
1957                         sci_del_timer(&scic->power_control.timer);
1958
1959                 sci_mod_timer(&scic->power_control.timer,
1960                                  SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1961                 scic->power_control.timer_started = true;
1962
1963         } else {
1964                 /* Add the phy in the waiting list */
1965                 scic->power_control.requesters[sci_phy->phy_index] = sci_phy;
1966                 scic->power_control.phys_waiting++;
1967         }
1968 }
1969
1970 /**
1971  * This method removes the phy from the stagger spinup control queue.
1972  * @scic:
1973  *
1974  *
1975  */
1976 void scic_sds_controller_power_control_queue_remove(
1977         struct scic_sds_controller *scic,
1978         struct scic_sds_phy *sci_phy)
1979 {
1980         BUG_ON(sci_phy == NULL);
1981
1982         if (scic->power_control.requesters[sci_phy->phy_index] != NULL) {
1983                 scic->power_control.phys_waiting--;
1984         }
1985
1986         scic->power_control.requesters[sci_phy->phy_index] = NULL;
1987 }
1988
1989 #define AFE_REGISTER_WRITE_DELAY 10
1990
1991 /* Initialize the AFE for this phy index. We need to read the AFE setup from
1992  * the OEM parameters
1993  */
1994 static void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic)
1995 {
1996         const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1;
1997         u32 afe_status;
1998         u32 phy_id;
1999
2000         /* Clear DFX Status registers */
2001         writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0);
2002         udelay(AFE_REGISTER_WRITE_DELAY);
2003
2004         if (is_b0()) {
2005                 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
2006                  * Timer, PM Stagger Timer */
2007                 writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2);
2008                 udelay(AFE_REGISTER_WRITE_DELAY);
2009         }
2010
2011         /* Configure bias currents to normal */
2012         if (is_a0())
2013                 writel(0x00005500, &scic->scu_registers->afe.afe_bias_control);
2014         else if (is_a2())
2015                 writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control);
2016         else if (is_b0() || is_c0())
2017                 writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control);
2018
2019         udelay(AFE_REGISTER_WRITE_DELAY);
2020
2021         /* Enable PLL */
2022         if (is_b0() || is_c0())
2023                 writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0);
2024         else
2025                 writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0);
2026
2027         udelay(AFE_REGISTER_WRITE_DELAY);
2028
2029         /* Wait for the PLL to lock */
2030         do {
2031                 afe_status = readl(&scic->scu_registers->afe.afe_common_block_status);
2032                 udelay(AFE_REGISTER_WRITE_DELAY);
2033         } while ((afe_status & 0x00001000) == 0);
2034
2035         if (is_a0() || is_a2()) {
2036                 /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
2037                 writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0);
2038                 udelay(AFE_REGISTER_WRITE_DELAY);
2039         }
2040
2041         for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
2042                 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
2043
2044                 if (is_b0()) {
2045                          /* Configure transmitter SSC parameters */
2046                         writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2047                         udelay(AFE_REGISTER_WRITE_DELAY);
2048                 } else if (is_c0()) {
2049                          /* Configure transmitter SSC parameters */
2050                         writel(0x0003000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control);
2051                         udelay(AFE_REGISTER_WRITE_DELAY);
2052
2053                         /*
2054                          * All defaults, except the Receive Word Alignament/Comma Detect
2055                          * Enable....(0xe800) */
2056                         writel(0x00004500, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2057                         udelay(AFE_REGISTER_WRITE_DELAY);
2058                 } else {
2059                         /*
2060                          * All defaults, except the Receive Word Alignament/Comma Detect
2061                          * Enable....(0xe800) */
2062                         writel(0x00004512, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2063                         udelay(AFE_REGISTER_WRITE_DELAY);
2064
2065                         writel(0x0050100F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1);
2066                         udelay(AFE_REGISTER_WRITE_DELAY);
2067                 }
2068
2069                 /*
2070                  * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2071                  * & increase TX int & ext bias 20%....(0xe85c) */
2072                 if (is_a0())
2073                         writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2074                 else if (is_a2())
2075                         writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2076                 else if (is_b0()) {
2077                          /* Power down TX and RX (PWRDNTX and PWRDNRX) */
2078                         writel(0x000003D7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2079                         udelay(AFE_REGISTER_WRITE_DELAY);
2080
2081                         /*
2082                          * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2083                          * & increase TX int & ext bias 20%....(0xe85c) */
2084                         writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2085                 } else {
2086                         writel(0x000001E7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2087                         udelay(AFE_REGISTER_WRITE_DELAY);
2088
2089                         /*
2090                          * Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
2091                          * & increase TX int & ext bias 20%....(0xe85c) */
2092                         writel(0x000001E4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control);
2093                 }
2094                 udelay(AFE_REGISTER_WRITE_DELAY);
2095
2096                 if (is_a0() || is_a2()) {
2097                         /* Enable TX equalization (0xe824) */
2098                         writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2099                         udelay(AFE_REGISTER_WRITE_DELAY);
2100                 }
2101
2102                 /*
2103                  * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On),
2104                  * RDD=0x0(RX Detect Enabled) ....(0xe800) */
2105                 writel(0x00004100, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0);
2106                 udelay(AFE_REGISTER_WRITE_DELAY);
2107
2108                 /* Leave DFE/FFE on */
2109                 if (is_a0())
2110                         writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2111                 else if (is_a2())
2112                         writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2113                 else if (is_b0()) {
2114                         writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2115                         udelay(AFE_REGISTER_WRITE_DELAY);
2116                         /* Enable TX equalization (0xe824) */
2117                         writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2118                 } else {
2119                         writel(0x0140DF0F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1);
2120                         udelay(AFE_REGISTER_WRITE_DELAY);
2121
2122                         writel(0x3F6F103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0);
2123                         udelay(AFE_REGISTER_WRITE_DELAY);
2124
2125                         /* Enable TX equalization (0xe824) */
2126                         writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control);
2127                 }
2128
2129                 udelay(AFE_REGISTER_WRITE_DELAY);
2130
2131                 writel(oem_phy->afe_tx_amp_control0,
2132                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0);
2133                 udelay(AFE_REGISTER_WRITE_DELAY);
2134
2135                 writel(oem_phy->afe_tx_amp_control1,
2136                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1);
2137                 udelay(AFE_REGISTER_WRITE_DELAY);
2138
2139                 writel(oem_phy->afe_tx_amp_control2,
2140                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2);
2141                 udelay(AFE_REGISTER_WRITE_DELAY);
2142
2143                 writel(oem_phy->afe_tx_amp_control3,
2144                         &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3);
2145                 udelay(AFE_REGISTER_WRITE_DELAY);
2146         }
2147
2148         /* Transfer control to the PEs */
2149         writel(0x00010f00, &scic->scu_registers->afe.afe_dfx_master_control0);
2150         udelay(AFE_REGISTER_WRITE_DELAY);
2151 }
2152
2153 static void scic_sds_controller_initialize_power_control(struct scic_sds_controller *scic)
2154 {
2155         sci_init_timer(&scic->power_control.timer, power_control_timeout);
2156
2157         memset(scic->power_control.requesters, 0,
2158                sizeof(scic->power_control.requesters));
2159
2160         scic->power_control.phys_waiting = 0;
2161         scic->power_control.phys_granted_power = 0;
2162 }
2163
2164 static enum sci_status scic_controller_initialize(struct scic_sds_controller *scic)
2165 {
2166         struct sci_base_state_machine *sm = &scic->sm;
2167         struct isci_host *ihost = scic_to_ihost(scic);
2168         enum sci_status result = SCI_FAILURE;
2169         unsigned long i, state, val;
2170
2171         if (scic->sm.current_state_id != SCIC_RESET) {
2172                 dev_warn(scic_to_dev(scic),
2173                          "SCIC Controller initialize operation requested "
2174                          "in invalid state\n");
2175                 return SCI_FAILURE_INVALID_STATE;
2176         }
2177
2178         sci_change_state(sm, SCIC_INITIALIZING);
2179
2180         sci_init_timer(&scic->phy_timer, phy_startup_timeout);
2181
2182         scic->next_phy_to_start = 0;
2183         scic->phy_startup_timer_pending = false;
2184
2185         scic_sds_controller_initialize_power_control(scic);
2186
2187         /*
2188          * There is nothing to do here for B0 since we do not have to
2189          * program the AFE registers.
2190          * / @todo The AFE settings are supposed to be correct for the B0 but
2191          * /       presently they seem to be wrong. */
2192         scic_sds_controller_afe_initialization(scic);
2193
2194
2195         /* Take the hardware out of reset */
2196         writel(0, &scic->smu_registers->soft_reset_control);
2197
2198         /*
2199          * / @todo Provide meaningfull error code for hardware failure
2200          * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2201         for (i = 100; i >= 1; i--) {
2202                 u32 status;
2203
2204                 /* Loop until the hardware reports success */
2205                 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2206                 status = readl(&scic->smu_registers->control_status);
2207
2208                 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2209                         break;
2210         }
2211         if (i == 0)
2212                 goto out;
2213
2214         /*
2215          * Determine what are the actaul device capacities that the
2216          * hardware will support */
2217         val = readl(&scic->smu_registers->device_context_capacity);
2218
2219         /* Record the smaller of the two capacity values */
2220         scic->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2221         scic->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2222         scic->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2223
2224         /*
2225          * Make all PEs that are unassigned match up with the
2226          * logical ports
2227          */
2228         for (i = 0; i < scic->logical_port_entries; i++) {
2229                 struct scu_port_task_scheduler_group_registers __iomem
2230                         *ptsg = &scic->scu_registers->peg0.ptsg;
2231
2232                 writel(i, &ptsg->protocol_engine[i]);
2233         }
2234
2235         /* Initialize hardware PCI Relaxed ordering in DMA engines */
2236         val = readl(&scic->scu_registers->sdma.pdma_configuration);
2237         val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2238         writel(val, &scic->scu_registers->sdma.pdma_configuration);
2239
2240         val = readl(&scic->scu_registers->sdma.cdma_configuration);
2241         val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2242         writel(val, &scic->scu_registers->sdma.cdma_configuration);
2243
2244         /*
2245          * Initialize the PHYs before the PORTs because the PHY registers
2246          * are accessed during the port initialization.
2247          */
2248         for (i = 0; i < SCI_MAX_PHYS; i++) {
2249                 result = scic_sds_phy_initialize(&ihost->phys[i].sci,
2250                                                  &scic->scu_registers->peg0.pe[i].tl,
2251                                                  &scic->scu_registers->peg0.pe[i].ll);
2252                 if (result != SCI_SUCCESS)
2253                         goto out;
2254         }
2255
2256         for (i = 0; i < scic->logical_port_entries; i++) {
2257                 result = scic_sds_port_initialize(&ihost->ports[i].sci,
2258                                                   &scic->scu_registers->peg0.ptsg.port[i],
2259                                                   &scic->scu_registers->peg0.ptsg.protocol_engine,
2260                                                   &scic->scu_registers->peg0.viit[i]);
2261
2262                 if (result != SCI_SUCCESS)
2263                         goto out;
2264         }
2265
2266         result = scic_sds_port_configuration_agent_initialize(scic, &scic->port_agent);
2267
2268  out:
2269         /* Advance the controller state machine */
2270         if (result == SCI_SUCCESS)
2271                 state = SCIC_INITIALIZED;
2272         else
2273                 state = SCIC_FAILED;
2274         sci_change_state(sm, state);
2275
2276         return result;
2277 }
2278
2279 static enum sci_status scic_user_parameters_set(
2280         struct scic_sds_controller *scic,
2281         union scic_user_parameters *scic_parms)
2282 {
2283         u32 state = scic->sm.current_state_id;
2284
2285         if (state == SCIC_RESET ||
2286             state == SCIC_INITIALIZING ||
2287             state == SCIC_INITIALIZED) {
2288                 u16 index;
2289
2290                 /*
2291                  * Validate the user parameters.  If they are not legal, then
2292                  * return a failure.
2293                  */
2294                 for (index = 0; index < SCI_MAX_PHYS; index++) {
2295                         struct sci_phy_user_params *user_phy;
2296
2297                         user_phy = &scic_parms->sds1.phys[index];
2298
2299                         if (!((user_phy->max_speed_generation <=
2300                                                 SCIC_SDS_PARM_MAX_SPEED) &&
2301                               (user_phy->max_speed_generation >
2302                                                 SCIC_SDS_PARM_NO_SPEED)))
2303                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2304
2305                         if (user_phy->in_connection_align_insertion_frequency <
2306                                         3)
2307                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2308
2309                         if ((user_phy->in_connection_align_insertion_frequency <
2310                                                 3) ||
2311                             (user_phy->align_insertion_frequency == 0) ||
2312                             (user_phy->
2313                                 notify_enable_spin_up_insertion_frequency ==
2314                                                 0))
2315                                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2316                 }
2317
2318                 if ((scic_parms->sds1.stp_inactivity_timeout == 0) ||
2319                     (scic_parms->sds1.ssp_inactivity_timeout == 0) ||
2320                     (scic_parms->sds1.stp_max_occupancy_timeout == 0) ||
2321                     (scic_parms->sds1.ssp_max_occupancy_timeout == 0) ||
2322                     (scic_parms->sds1.no_outbound_task_timeout == 0))
2323                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2324
2325                 memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms));
2326
2327                 return SCI_SUCCESS;
2328         }
2329
2330         return SCI_FAILURE_INVALID_STATE;
2331 }
2332
2333 static int scic_controller_mem_init(struct scic_sds_controller *scic)
2334 {
2335         struct device *dev = scic_to_dev(scic);
2336         dma_addr_t dma;
2337         size_t size;
2338         int err;
2339
2340         size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2341         scic->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2342         if (!scic->completion_queue)
2343                 return -ENOMEM;
2344
2345         writel(lower_32_bits(dma), &scic->smu_registers->completion_queue_lower);
2346         writel(upper_32_bits(dma), &scic->smu_registers->completion_queue_upper);
2347
2348         size = scic->remote_node_entries * sizeof(union scu_remote_node_context);
2349         scic->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma,
2350                                                               GFP_KERNEL);
2351         if (!scic->remote_node_context_table)
2352                 return -ENOMEM;
2353
2354         writel(lower_32_bits(dma), &scic->smu_registers->remote_node_context_lower);
2355         writel(upper_32_bits(dma), &scic->smu_registers->remote_node_context_upper);
2356
2357         size = scic->task_context_entries * sizeof(struct scu_task_context),
2358         scic->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2359         if (!scic->task_context_table)
2360                 return -ENOMEM;
2361
2362         scic->task_context_dma = dma;
2363         writel(lower_32_bits(dma), &scic->smu_registers->host_task_table_lower);
2364         writel(upper_32_bits(dma), &scic->smu_registers->host_task_table_upper);
2365
2366         err = scic_sds_unsolicited_frame_control_construct(scic);
2367         if (err)
2368                 return err;
2369
2370         /*
2371          * Inform the silicon as to the location of the UF headers and
2372          * address table.
2373          */
2374         writel(lower_32_bits(scic->uf_control.headers.physical_address),
2375                 &scic->scu_registers->sdma.uf_header_base_address_lower);
2376         writel(upper_32_bits(scic->uf_control.headers.physical_address),
2377                 &scic->scu_registers->sdma.uf_header_base_address_upper);
2378
2379         writel(lower_32_bits(scic->uf_control.address_table.physical_address),
2380                 &scic->scu_registers->sdma.uf_address_table_lower);
2381         writel(upper_32_bits(scic->uf_control.address_table.physical_address),
2382                 &scic->scu_registers->sdma.uf_address_table_upper);
2383
2384         return 0;
2385 }
2386
2387 int isci_host_init(struct isci_host *isci_host)
2388 {
2389         int err = 0, i;
2390         enum sci_status status;
2391         union scic_oem_parameters oem;
2392         union scic_user_parameters scic_user_params;
2393         struct isci_pci_info *pci_info = to_pci_info(isci_host->pdev);
2394
2395         spin_lock_init(&isci_host->state_lock);
2396         spin_lock_init(&isci_host->scic_lock);
2397         init_waitqueue_head(&isci_host->eventq);
2398
2399         isci_host_change_state(isci_host, isci_starting);
2400
2401         status = scic_controller_construct(&isci_host->sci, scu_base(isci_host),
2402                                            smu_base(isci_host));
2403
2404         if (status != SCI_SUCCESS) {
2405                 dev_err(&isci_host->pdev->dev,
2406                         "%s: scic_controller_construct failed - status = %x\n",
2407                         __func__,
2408                         status);
2409                 return -ENODEV;
2410         }
2411
2412         isci_host->sas_ha.dev = &isci_host->pdev->dev;
2413         isci_host->sas_ha.lldd_ha = isci_host;
2414
2415         /*
2416          * grab initial values stored in the controller object for OEM and USER
2417          * parameters
2418          */
2419         isci_user_parameters_get(isci_host, &scic_user_params);
2420         status = scic_user_parameters_set(&isci_host->sci,
2421                                           &scic_user_params);
2422         if (status != SCI_SUCCESS) {
2423                 dev_warn(&isci_host->pdev->dev,
2424                          "%s: scic_user_parameters_set failed\n",
2425                          __func__);
2426                 return -ENODEV;
2427         }
2428
2429         scic_oem_parameters_get(&isci_host->sci, &oem);
2430
2431         /* grab any OEM parameters specified in orom */
2432         if (pci_info->orom) {
2433                 status = isci_parse_oem_parameters(&oem,
2434                                                    pci_info->orom,
2435                                                    isci_host->id);
2436                 if (status != SCI_SUCCESS) {
2437                         dev_warn(&isci_host->pdev->dev,
2438                                  "parsing firmware oem parameters failed\n");
2439                         return -EINVAL;
2440                 }
2441         }
2442
2443         status = scic_oem_parameters_set(&isci_host->sci, &oem);
2444         if (status != SCI_SUCCESS) {
2445                 dev_warn(&isci_host->pdev->dev,
2446                                 "%s: scic_oem_parameters_set failed\n",
2447                                 __func__);
2448                 return -ENODEV;
2449         }
2450
2451         tasklet_init(&isci_host->completion_tasklet,
2452                      isci_host_completion_routine, (unsigned long)isci_host);
2453
2454         INIT_LIST_HEAD(&isci_host->requests_to_complete);
2455         INIT_LIST_HEAD(&isci_host->requests_to_errorback);
2456
2457         spin_lock_irq(&isci_host->scic_lock);
2458         status = scic_controller_initialize(&isci_host->sci);
2459         spin_unlock_irq(&isci_host->scic_lock);
2460         if (status != SCI_SUCCESS) {
2461                 dev_warn(&isci_host->pdev->dev,
2462                          "%s: scic_controller_initialize failed -"
2463                          " status = 0x%x\n",
2464                          __func__, status);
2465                 return -ENODEV;
2466         }
2467
2468         err = scic_controller_mem_init(&isci_host->sci);
2469         if (err)
2470                 return err;
2471
2472         isci_host->dma_pool = dmam_pool_create(DRV_NAME, &isci_host->pdev->dev,
2473                                                sizeof(struct isci_request),
2474                                                SLAB_HWCACHE_ALIGN, 0);
2475
2476         if (!isci_host->dma_pool)
2477                 return -ENOMEM;
2478
2479         for (i = 0; i < SCI_MAX_PORTS; i++)
2480                 isci_port_init(&isci_host->ports[i], isci_host, i);
2481
2482         for (i = 0; i < SCI_MAX_PHYS; i++)
2483                 isci_phy_init(&isci_host->phys[i], isci_host, i);
2484
2485         for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
2486                 struct isci_remote_device *idev = &isci_host->devices[i];
2487
2488                 INIT_LIST_HEAD(&idev->reqs_in_process);
2489                 INIT_LIST_HEAD(&idev->node);
2490         }
2491
2492         return 0;
2493 }
2494
2495 void scic_sds_controller_link_up(struct scic_sds_controller *scic,
2496                 struct scic_sds_port *port, struct scic_sds_phy *phy)
2497 {
2498         switch (scic->sm.current_state_id) {
2499         case SCIC_STARTING:
2500                 sci_del_timer(&scic->phy_timer);
2501                 scic->phy_startup_timer_pending = false;
2502                 scic->port_agent.link_up_handler(scic, &scic->port_agent,
2503                                                  port, phy);
2504                 scic_sds_controller_start_next_phy(scic);
2505                 break;
2506         case SCIC_READY:
2507                 scic->port_agent.link_up_handler(scic, &scic->port_agent,
2508                                                  port, phy);
2509                 break;
2510         default:
2511                 dev_dbg(scic_to_dev(scic),
2512                         "%s: SCIC Controller linkup event from phy %d in "
2513                         "unexpected state %d\n", __func__, phy->phy_index,
2514                         scic->sm.current_state_id);
2515         }
2516 }
2517
2518 void scic_sds_controller_link_down(struct scic_sds_controller *scic,
2519                 struct scic_sds_port *port, struct scic_sds_phy *phy)
2520 {
2521         switch (scic->sm.current_state_id) {
2522         case SCIC_STARTING:
2523         case SCIC_READY:
2524                 scic->port_agent.link_down_handler(scic, &scic->port_agent,
2525                                                    port, phy);
2526                 break;
2527         default:
2528                 dev_dbg(scic_to_dev(scic),
2529                         "%s: SCIC Controller linkdown event from phy %d in "
2530                         "unexpected state %d\n",
2531                         __func__,
2532                         phy->phy_index,
2533                         scic->sm.current_state_id);
2534         }
2535 }
2536
2537 /**
2538  * This is a helper method to determine if any remote devices on this
2539  * controller are still in the stopping state.
2540  *
2541  */
2542 static bool scic_sds_controller_has_remote_devices_stopping(
2543         struct scic_sds_controller *controller)
2544 {
2545         u32 index;
2546
2547         for (index = 0; index < controller->remote_node_entries; index++) {
2548                 if ((controller->device_table[index] != NULL) &&
2549                    (controller->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2550                         return true;
2551         }
2552
2553         return false;
2554 }
2555
2556 /**
2557  * This method is called by the remote device to inform the controller
2558  * object that the remote device has stopped.
2559  */
2560 void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic,
2561                                                struct scic_sds_remote_device *sci_dev)
2562 {
2563         if (scic->sm.current_state_id != SCIC_STOPPING) {
2564                 dev_dbg(scic_to_dev(scic),
2565                         "SCIC Controller 0x%p remote device stopped event "
2566                         "from device 0x%p in unexpected state %d\n",
2567                         scic, sci_dev,
2568                         scic->sm.current_state_id);
2569                 return;
2570         }
2571
2572         if (!scic_sds_controller_has_remote_devices_stopping(scic)) {
2573                 sci_change_state(&scic->sm, SCIC_STOPPED);
2574         }
2575 }
2576
2577 /**
2578  * This method will write to the SCU PCP register the request value. The method
2579  *    is used to suspend/resume ports, devices, and phys.
2580  * @scic:
2581  *
2582  *
2583  */
2584 void scic_sds_controller_post_request(
2585         struct scic_sds_controller *scic,
2586         u32 request)
2587 {
2588         dev_dbg(scic_to_dev(scic),
2589                 "%s: SCIC Controller 0x%p post request 0x%08x\n",
2590                 __func__,
2591                 scic,
2592                 request);
2593
2594         writel(request, &scic->smu_registers->post_context_port);
2595 }
2596
2597 struct scic_sds_request *scic_request_by_tag(struct scic_sds_controller *scic, u16 io_tag)
2598 {
2599         u16 task_index;
2600         u16 task_sequence;
2601
2602         task_index = ISCI_TAG_TCI(io_tag);
2603
2604         if (task_index < scic->task_context_entries) {
2605                 if (scic->io_request_table[task_index] != NULL) {
2606                         task_sequence = ISCI_TAG_SEQ(io_tag);
2607
2608                         if (task_sequence == scic->io_request_sequence[task_index]) {
2609                                 return scic->io_request_table[task_index];
2610                         }
2611                 }
2612         }
2613
2614         return NULL;
2615 }
2616
2617 /**
2618  * This method allocates remote node index and the reserves the remote node
2619  *    context space for use. This method can fail if there are no more remote
2620  *    node index available.
2621  * @scic: This is the controller object which contains the set of
2622  *    free remote node ids
2623  * @sci_dev: This is the device object which is requesting the a remote node
2624  *    id
2625  * @node_id: This is the remote node id that is assinged to the device if one
2626  *    is available
2627  *
2628  * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2629  * node index available.
2630  */
2631 enum sci_status scic_sds_controller_allocate_remote_node_context(
2632         struct scic_sds_controller *scic,
2633         struct scic_sds_remote_device *sci_dev,
2634         u16 *node_id)
2635 {
2636         u16 node_index;
2637         u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev);
2638
2639         node_index = scic_sds_remote_node_table_allocate_remote_node(
2640                 &scic->available_remote_nodes, remote_node_count
2641                 );
2642
2643         if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2644                 scic->device_table[node_index] = sci_dev;
2645
2646                 *node_id = node_index;
2647
2648                 return SCI_SUCCESS;
2649         }
2650
2651         return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2652 }
2653
2654 /**
2655  * This method frees the remote node index back to the available pool.  Once
2656  *    this is done the remote node context buffer is no longer valid and can
2657  *    not be used.
2658  * @scic:
2659  * @sci_dev:
2660  * @node_id:
2661  *
2662  */
2663 void scic_sds_controller_free_remote_node_context(
2664         struct scic_sds_controller *scic,
2665         struct scic_sds_remote_device *sci_dev,
2666         u16 node_id)
2667 {
2668         u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev);
2669
2670         if (scic->device_table[node_id] == sci_dev) {
2671                 scic->device_table[node_id] = NULL;
2672
2673                 scic_sds_remote_node_table_release_remote_node_index(
2674                         &scic->available_remote_nodes, remote_node_count, node_id
2675                         );
2676         }
2677 }
2678
2679 /**
2680  * This method returns the union scu_remote_node_context for the specified remote
2681  *    node id.
2682  * @scic:
2683  * @node_id:
2684  *
2685  * union scu_remote_node_context*
2686  */
2687 union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer(
2688         struct scic_sds_controller *scic,
2689         u16 node_id
2690         ) {
2691         if (
2692                 (node_id < scic->remote_node_entries)
2693                 && (scic->device_table[node_id] != NULL)
2694                 ) {
2695                 return &scic->remote_node_context_table[node_id];
2696         }
2697
2698         return NULL;
2699 }
2700
2701 /**
2702  *
2703  * @resposne_buffer: This is the buffer into which the D2H register FIS will be
2704  *    constructed.
2705  * @frame_header: This is the frame header returned by the hardware.
2706  * @frame_buffer: This is the frame buffer returned by the hardware.
2707  *
2708  * This method will combind the frame header and frame buffer to create a SATA
2709  * D2H register FIS none
2710  */
2711 void scic_sds_controller_copy_sata_response(
2712         void *response_buffer,
2713         void *frame_header,
2714         void *frame_buffer)
2715 {
2716         memcpy(response_buffer, frame_header, sizeof(u32));
2717
2718         memcpy(response_buffer + sizeof(u32),
2719                frame_buffer,
2720                sizeof(struct dev_to_host_fis) - sizeof(u32));
2721 }
2722
2723 /**
2724  * This method releases the frame once this is done the frame is available for
2725  *    re-use by the hardware.  The data contained in the frame header and frame
2726  *    buffer is no longer valid. The UF queue get pointer is only updated if UF
2727  *    control indicates this is appropriate.
2728  * @scic:
2729  * @frame_index:
2730  *
2731  */
2732 void scic_sds_controller_release_frame(
2733         struct scic_sds_controller *scic,
2734         u32 frame_index)
2735 {
2736         if (scic_sds_unsolicited_frame_control_release_frame(
2737                     &scic->uf_control, frame_index) == true)
2738                 writel(scic->uf_control.get,
2739                         &scic->scu_registers->sdma.unsolicited_frame_get_pointer);
2740 }
2741
2742 void isci_tci_free(struct isci_host *ihost, u16 tci)
2743 {
2744         u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2745
2746         ihost->tci_pool[tail] = tci;
2747         ihost->tci_tail = tail + 1;
2748 }
2749
2750 static u16 isci_tci_alloc(struct isci_host *ihost)
2751 {
2752         u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2753         u16 tci = ihost->tci_pool[head];
2754
2755         ihost->tci_head = head + 1;
2756         return tci;
2757 }
2758
2759 static u16 isci_tci_space(struct isci_host *ihost)
2760 {
2761         return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2762 }
2763
2764 u16 isci_alloc_tag(struct isci_host *ihost)
2765 {
2766         if (isci_tci_space(ihost)) {
2767                 u16 tci = isci_tci_alloc(ihost);
2768                 u8 seq = ihost->sci.io_request_sequence[tci];
2769
2770                 return ISCI_TAG(seq, tci);
2771         }
2772
2773         return SCI_CONTROLLER_INVALID_IO_TAG;
2774 }
2775
2776 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2777 {
2778         struct scic_sds_controller *scic = &ihost->sci;
2779         u16 tci = ISCI_TAG_TCI(io_tag);
2780         u16 seq = ISCI_TAG_SEQ(io_tag);
2781
2782         /* prevent tail from passing head */
2783         if (isci_tci_active(ihost) == 0)
2784                 return SCI_FAILURE_INVALID_IO_TAG;
2785
2786         if (seq == scic->io_request_sequence[tci]) {
2787                 scic->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2788
2789                 isci_tci_free(ihost, tci);
2790
2791                 return SCI_SUCCESS;
2792         }
2793         return SCI_FAILURE_INVALID_IO_TAG;
2794 }
2795
2796 /**
2797  * scic_controller_start_io() - This method is called by the SCI user to
2798  *    send/start an IO request. If the method invocation is successful, then
2799  *    the IO request has been queued to the hardware for processing.
2800  * @controller: the handle to the controller object for which to start an IO
2801  *    request.
2802  * @remote_device: the handle to the remote device object for which to start an
2803  *    IO request.
2804  * @io_request: the handle to the io request object to start.
2805  * @io_tag: This parameter specifies a previously allocated IO tag that the
2806  *    user desires to be utilized for this request.
2807  */
2808 enum sci_status scic_controller_start_io(struct scic_sds_controller *scic,
2809                                          struct scic_sds_remote_device *rdev,
2810                                          struct scic_sds_request *req)
2811 {
2812         enum sci_status status;
2813
2814         if (scic->sm.current_state_id != SCIC_READY) {
2815                 dev_warn(scic_to_dev(scic), "invalid state to start I/O");
2816                 return SCI_FAILURE_INVALID_STATE;
2817         }
2818
2819         status = scic_sds_remote_device_start_io(scic, rdev, req);
2820         if (status != SCI_SUCCESS)
2821                 return status;
2822
2823         scic->io_request_table[ISCI_TAG_TCI(req->io_tag)] = req;
2824         scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(req));
2825         return SCI_SUCCESS;
2826 }
2827
2828 /**
2829  * scic_controller_terminate_request() - This method is called by the SCI Core
2830  *    user to terminate an ongoing (i.e. started) core IO request.  This does
2831  *    not abort the IO request at the target, but rather removes the IO request
2832  *    from the host controller.
2833  * @controller: the handle to the controller object for which to terminate a
2834  *    request.
2835  * @remote_device: the handle to the remote device object for which to
2836  *    terminate a request.
2837  * @request: the handle to the io or task management request object to
2838  *    terminate.
2839  *
2840  * Indicate if the controller successfully began the terminate process for the
2841  * IO request. SCI_SUCCESS if the terminate process was successfully started
2842  * for the request. Determine the failure situations and return values.
2843  */
2844 enum sci_status scic_controller_terminate_request(
2845         struct scic_sds_controller *scic,
2846         struct scic_sds_remote_device *rdev,
2847         struct scic_sds_request *req)
2848 {
2849         enum sci_status status;
2850
2851         if (scic->sm.current_state_id != SCIC_READY) {
2852                 dev_warn(scic_to_dev(scic),
2853                          "invalid state to terminate request\n");
2854                 return SCI_FAILURE_INVALID_STATE;
2855         }
2856
2857         status = scic_sds_io_request_terminate(req);
2858         if (status != SCI_SUCCESS)
2859                 return status;
2860
2861         /*
2862          * Utilize the original post context command and or in the POST_TC_ABORT
2863          * request sub-type.
2864          */
2865         scic_sds_controller_post_request(scic,
2866                 scic_sds_request_get_post_context(req) |
2867                 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2868         return SCI_SUCCESS;
2869 }
2870
2871 /**
2872  * scic_controller_complete_io() - This method will perform core specific
2873  *    completion operations for an IO request.  After this method is invoked,
2874  *    the user should consider the IO request as invalid until it is properly
2875  *    reused (i.e. re-constructed).
2876  * @controller: The handle to the controller object for which to complete the
2877  *    IO request.
2878  * @remote_device: The handle to the remote device object for which to complete
2879  *    the IO request.
2880  * @io_request: the handle to the io request object to complete.
2881  */
2882 enum sci_status scic_controller_complete_io(
2883         struct scic_sds_controller *scic,
2884         struct scic_sds_remote_device *rdev,
2885         struct scic_sds_request *request)
2886 {
2887         enum sci_status status;
2888         u16 index;
2889
2890         switch (scic->sm.current_state_id) {
2891         case SCIC_STOPPING:
2892                 /* XXX: Implement this function */
2893                 return SCI_FAILURE;
2894         case SCIC_READY:
2895                 status = scic_sds_remote_device_complete_io(scic, rdev, request);
2896                 if (status != SCI_SUCCESS)
2897                         return status;
2898
2899                 index = ISCI_TAG_TCI(request->io_tag);
2900                 scic->io_request_table[index] = NULL;
2901                 return SCI_SUCCESS;
2902         default:
2903                 dev_warn(scic_to_dev(scic), "invalid state to complete I/O");
2904                 return SCI_FAILURE_INVALID_STATE;
2905         }
2906
2907 }
2908
2909 enum sci_status scic_controller_continue_io(struct scic_sds_request *sci_req)
2910 {
2911         struct scic_sds_controller *scic = sci_req->owning_controller;
2912
2913         if (scic->sm.current_state_id != SCIC_READY) {
2914                 dev_warn(scic_to_dev(scic), "invalid state to continue I/O");
2915                 return SCI_FAILURE_INVALID_STATE;
2916         }
2917
2918         scic->io_request_table[ISCI_TAG_TCI(sci_req->io_tag)] = sci_req;
2919         scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(sci_req));
2920         return SCI_SUCCESS;
2921 }
2922
2923 /**
2924  * scic_controller_start_task() - This method is called by the SCIC user to
2925  *    send/start a framework task management request.
2926  * @controller: the handle to the controller object for which to start the task
2927  *    management request.
2928  * @remote_device: the handle to the remote device object for which to start
2929  *    the task management request.
2930  * @task_request: the handle to the task request object to start.
2931  */
2932 enum sci_task_status scic_controller_start_task(
2933         struct scic_sds_controller *scic,
2934         struct scic_sds_remote_device *rdev,
2935         struct scic_sds_request *req)
2936 {
2937         enum sci_status status;
2938
2939         if (scic->sm.current_state_id != SCIC_READY) {
2940                 dev_warn(scic_to_dev(scic),
2941                          "%s: SCIC Controller starting task from invalid "
2942                          "state\n",
2943                          __func__);
2944                 return SCI_TASK_FAILURE_INVALID_STATE;
2945         }
2946
2947         status = scic_sds_remote_device_start_task(scic, rdev, req);
2948         switch (status) {
2949         case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2950                 scic->io_request_table[ISCI_TAG_TCI(req->io_tag)] = req;
2951
2952                 /*
2953                  * We will let framework know this task request started successfully,
2954                  * although core is still woring on starting the request (to post tc when
2955                  * RNC is resumed.)
2956                  */
2957                 return SCI_SUCCESS;
2958         case SCI_SUCCESS:
2959                 scic->io_request_table[ISCI_TAG_TCI(req->io_tag)] = req;
2960
2961                 scic_sds_controller_post_request(scic,
2962                         scic_sds_request_get_post_context(req));
2963                 break;
2964         default:
2965                 break;
2966         }
2967
2968         return status;
2969 }