[SCSI] bfa: remove all OS wrappers
[linux-2.6.git] / drivers / scsi / bfa / bfa_ioc_ct.c
1 /*
2  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
3  * All rights reserved
4  * www.brocade.com
5  *
6  * Linux driver for Brocade Fibre Channel Host Bus Adapter.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License (GPL) Version 2 as
10  * published by the Free Software Foundation
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  */
17
18 #include "bfad_drv.h"
19 #include "bfa_ioc.h"
20 #include "bfi_ctreg.h"
21 #include "bfa_defs.h"
22
23 BFA_TRC_FILE(CNA, IOC_CT);
24
25 /*
26  * forward declarations
27  */
28 static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc);
29 static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc);
30 static void bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc);
31 static void bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc);
32 static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
33 static void bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc);
34 static void bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc);
35
36 static struct bfa_ioc_hwif_s hwif_ct;
37
38 /*
39  * Called from bfa_ioc_attach() to map asic specific calls.
40  */
41 void
42 bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc)
43 {
44         hwif_ct.ioc_pll_init = bfa_ioc_ct_pll_init;
45         hwif_ct.ioc_firmware_lock = bfa_ioc_ct_firmware_lock;
46         hwif_ct.ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock;
47         hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
48         hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
49         hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
50         hwif_ct.ioc_notify_hbfail = bfa_ioc_ct_notify_hbfail;
51         hwif_ct.ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
52
53         ioc->ioc_hwif = &hwif_ct;
54 }
55
56 /*
57  * Return true if firmware of current driver matches the running firmware.
58  */
59 static bfa_boolean_t
60 bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc)
61 {
62         enum bfi_ioc_state ioc_fwstate;
63         u32 usecnt;
64         struct bfi_ioc_image_hdr_s fwhdr;
65
66         /*
67          * Firmware match check is relevant only for CNA.
68          */
69         if (!ioc->cna)
70                 return BFA_TRUE;
71
72         /*
73          * If bios boot (flash based) -- do not increment usage count
74          */
75         if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
76                                                 BFA_IOC_FWIMG_MINSZ)
77                 return BFA_TRUE;
78
79         bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
80         usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
81
82         /*
83          * If usage count is 0, always return TRUE.
84          */
85         if (usecnt == 0) {
86                 writel(1, ioc->ioc_regs.ioc_usage_reg);
87                 writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
88                 bfa_trc(ioc, usecnt);
89                 return BFA_TRUE;
90         }
91
92         ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
93         bfa_trc(ioc, ioc_fwstate);
94
95         /*
96          * Use count cannot be non-zero and chip in uninitialized state.
97          */
98         bfa_assert(ioc_fwstate != BFI_IOC_UNINIT);
99
100         /*
101          * Check if another driver with a different firmware is active
102          */
103         bfa_ioc_fwver_get(ioc, &fwhdr);
104         if (!bfa_ioc_fwver_cmp(ioc, &fwhdr)) {
105                 writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
106                 bfa_trc(ioc, usecnt);
107                 return BFA_FALSE;
108         }
109
110         /*
111          * Same firmware version. Increment the reference count.
112          */
113         usecnt++;
114         writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
115         writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
116         bfa_trc(ioc, usecnt);
117         return BFA_TRUE;
118 }
119
120 static void
121 bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc)
122 {
123         u32 usecnt;
124
125         /*
126          * Firmware lock is relevant only for CNA.
127          */
128         if (!ioc->cna)
129                 return;
130
131         /*
132          * If bios boot (flash based) -- do not decrement usage count
133          */
134         if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
135                                                 BFA_IOC_FWIMG_MINSZ)
136                 return;
137
138         /*
139          * decrement usage count
140          */
141         bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
142         usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
143         bfa_assert(usecnt > 0);
144
145         usecnt--;
146         writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
147         bfa_trc(ioc, usecnt);
148
149         writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
150 }
151
152 /*
153  * Notify other functions on HB failure.
154  */
155 static void
156 bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc)
157 {
158         if (ioc->cna) {
159                 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
160                 /* Wait for halt to take effect */
161                 readl(ioc->ioc_regs.ll_halt);
162         } else {
163                 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
164                 readl(ioc->ioc_regs.err_set);
165         }
166 }
167
168 /*
169  * Host to LPU mailbox message addresses
170  */
171 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
172         { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
173         { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
174         { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
175         { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
176 };
177
178 /*
179  * Host <-> LPU mailbox command/status registers - port 0
180  */
181 static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = {
182         { HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT },
183         { HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT },
184         { HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT },
185         { HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT }
186 };
187
188 /*
189  * Host <-> LPU mailbox command/status registers - port 1
190  */
191 static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
192         { HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT },
193         { HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT },
194         { HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT },
195         { HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT }
196 };
197
198 static void
199 bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
200 {
201         void __iomem *rb;
202         int             pcifn = bfa_ioc_pcifn(ioc);
203
204         rb = bfa_ioc_bar0(ioc);
205
206         ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
207         ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
208         ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
209
210         if (ioc->port_id == 0) {
211                 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
212                 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
213                 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn;
214                 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu;
215                 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
216         } else {
217                 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
218                 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
219                 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn;
220                 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu;
221                 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
222         }
223
224         /*
225          * PSS control registers
226          */
227         ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
228         ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
229         ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG);
230         ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG);
231
232         /*
233          * IOC semaphore registers and serialization
234          */
235         ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
236         ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
237         ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
238         ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
239
240         /*
241          * sram memory access
242          */
243         ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
244         ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
245
246         /*
247          * err set reg : for notification of hb failure in fcmode
248          */
249         ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
250 }
251
252 /*
253  * Initialize IOC to port mapping.
254  */
255
256 #define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8)
257 static void
258 bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc)
259 {
260         void __iomem *rb = ioc->pcidev.pci_bar_kva;
261         u32     r32;
262
263         /*
264          * For catapult, base port id on personality register and IOC type
265          */
266         r32 = readl(rb + FNC_PERS_REG);
267         r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
268         ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
269
270         bfa_trc(ioc, bfa_ioc_pcifn(ioc));
271         bfa_trc(ioc, ioc->port_id);
272 }
273
274 /*
275  * Set interrupt mode for a function: INTX or MSIX
276  */
277 static void
278 bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
279 {
280         void __iomem *rb = ioc->pcidev.pci_bar_kva;
281         u32     r32, mode;
282
283         r32 = readl(rb + FNC_PERS_REG);
284         bfa_trc(ioc, r32);
285
286         mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
287                 __F0_INTX_STATUS;
288
289         /*
290          * If already in desired mode, do not change anything
291          */
292         if (!msix && mode)
293                 return;
294
295         if (msix)
296                 mode = __F0_INTX_STATUS_MSIX;
297         else
298                 mode = __F0_INTX_STATUS_INTA;
299
300         r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
301         r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
302         bfa_trc(ioc, r32);
303
304         writel(r32, rb + FNC_PERS_REG);
305 }
306
307 /*
308  * Cleanup hw semaphore and usecnt registers
309  */
310 static void
311 bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
312 {
313
314         if (ioc->cna) {
315                 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
316                 writel(0, ioc->ioc_regs.ioc_usage_reg);
317                 writel(1, ioc->ioc_regs.ioc_usage_sem_reg);
318         }
319
320         /*
321          * Read the hw sem reg to make sure that it is locked
322          * before we clear it. If it is not locked, writing 1
323          * will lock it instead of clearing it.
324          */
325         readl(ioc->ioc_regs.ioc_sem_reg);
326         writel(1, ioc->ioc_regs.ioc_sem_reg);
327 }
328
329
330
331 /*
332  * Check the firmware state to know if pll_init has been completed already
333  */
334 bfa_boolean_t
335 bfa_ioc_ct_pll_init_complete(void __iomem *rb)
336 {
337         if ((readl(rb + BFA_IOC0_STATE_REG) == BFI_IOC_OP) ||
338           (readl(rb + BFA_IOC1_STATE_REG) == BFI_IOC_OP))
339                 return BFA_TRUE;
340
341         return BFA_FALSE;
342 }
343
344 bfa_status_t
345 bfa_ioc_ct_pll_init(void __iomem *rb, bfa_boolean_t fcmode)
346 {
347         u32     pll_sclk, pll_fclk, r32;
348
349         pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST |
350                 __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) |
351                 __APP_PLL_312_JITLMT0_1(3U) |
352                 __APP_PLL_312_CNTLMT0_1(1U);
353         pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST |
354                 __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) |
355                 __APP_PLL_425_JITLMT0_1(3U) |
356                 __APP_PLL_425_CNTLMT0_1(1U);
357         if (fcmode) {
358                 writel(0, (rb + OP_MODE));
359                 writel(__APP_EMS_CMLCKSEL | __APP_EMS_REFCKBUFEN2 |
360                          __APP_EMS_CHANNEL_SEL, (rb + ETH_MAC_SER_REG));
361         } else {
362                 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
363                 writel(__APP_EMS_REFCKBUFEN1, (rb + ETH_MAC_SER_REG));
364         }
365         writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
366         writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
367         writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
368         writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
369         writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
370         writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
371         writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
372         writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
373         writel(pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET,
374                         rb + APP_PLL_312_CTL_REG);
375         writel(pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET,
376                         rb + APP_PLL_425_CTL_REG);
377         writel(pll_sclk | __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE,
378                         rb + APP_PLL_312_CTL_REG);
379         writel(pll_fclk | __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE,
380                         rb + APP_PLL_425_CTL_REG);
381         readl(rb + HOSTFN0_INT_MSK);
382         udelay(2000);
383         writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
384         writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
385         writel(pll_sclk | __APP_PLL_312_ENABLE, rb + APP_PLL_312_CTL_REG);
386         writel(pll_fclk | __APP_PLL_425_ENABLE, rb + APP_PLL_425_CTL_REG);
387         if (!fcmode) {
388                 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
389                 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
390         }
391         r32 = readl((rb + PSS_CTL_REG));
392         r32 &= ~__PSS_LMEM_RESET;
393         writel(r32, (rb + PSS_CTL_REG));
394         udelay(1000);
395         if (!fcmode) {
396                 writel(0, (rb + PMM_1T_RESET_REG_P0));
397                 writel(0, (rb + PMM_1T_RESET_REG_P1));
398         }
399
400         writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
401         udelay(1000);
402         r32 = readl((rb + MBIST_STAT_REG));
403         writel(0, (rb + MBIST_CTL_REG));
404         return BFA_STATUS_OK;
405 }