regulator: max77663: Active-discharge mode for SDx
[linux-2.6.git] / drivers / regulator / max77663-regulator.c
1 /*
2  * drivers/regulator/max77663-regulator.c
3  * Maxim LDO and Buck regulators driver
4  *
5  * Copyright 2011 Maxim Integrated Products, Inc.
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of the
11  * License, or (at your option) any later version.
12  *
13  */
14
15 #include <linux/err.h>
16 #include <linux/string.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/debugfs.h>
22 #include <linux/uaccess.h>
23 #include <linux/i2c.h>
24 #include <linux/mfd/max77663-core.h>
25 #include <linux/regulator/driver.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/regulator/max77663-regulator.h>
28
29 /* Regulator types */
30 #define REGULATOR_TYPE_SD               0
31 #define REGULATOR_TYPE_LDO              1
32
33 /* SD and LDO Registers */
34 #define MAX77663_REG_SD0                0x16
35 #define MAX77663_REG_SD1                0x17
36 #define MAX77663_REG_SD2                0x18
37 #define MAX77663_REG_SD3                0x19
38 #define MAX77663_REG_SD4                0x1A
39 #define MAX77663_REG_DVSSD0             0x1B
40 #define MAX77663_REG_DVSSD1             0x1C
41 #define MAX77663_REG_SD0_CFG            0x1D
42 #define MAX77663_REG_DVSSD0_CFG         MAX77663_REG_SD0_CFG
43 #define MAX77663_REG_SD1_CFG            0x1E
44 #define MAX77663_REG_DVSSD1_CFG         MAX77663_REG_SD1_CFG
45 #define MAX77663_REG_SD2_CFG            0x1F
46 #define MAX77663_REG_SD3_CFG            0x20
47 #define MAX77663_REG_SD4_CFG            0x21
48 #define MAX77663_REG_LDO0_CFG           0x23
49 #define MAX77663_REG_LDO0_CFG2          0x24
50 #define MAX77663_REG_LDO1_CFG           0x25
51 #define MAX77663_REG_LDO1_CFG2          0x26
52 #define MAX77663_REG_LDO2_CFG           0x27
53 #define MAX77663_REG_LDO2_CFG2          0x28
54 #define MAX77663_REG_LDO3_CFG           0x29
55 #define MAX77663_REG_LDO3_CFG2          0x2A
56 #define MAX77663_REG_LDO4_CFG           0x2B
57 #define MAX77663_REG_LDO4_CFG2          0x2C
58 #define MAX77663_REG_LDO5_CFG           0x2D
59 #define MAX77663_REG_LDO5_CFG2          0x2E
60 #define MAX77663_REG_LDO6_CFG           0x2F
61 #define MAX77663_REG_LDO6_CFG2          0x30
62 #define MAX77663_REG_LDO7_CFG           0x31
63 #define MAX77663_REG_LDO7_CFG2          0x32
64 #define MAX77663_REG_LDO8_CFG           0x33
65 #define MAX77663_REG_LDO8_CFG2          0x34
66
67 /* Power Mode */
68 #define POWER_MODE_NORMAL               3
69 #define POWER_MODE_LPM                  2
70 #define POWER_MODE_GLPM                 1
71 #define POWER_MODE_DISABLE              0
72 #define SD_POWER_MODE_MASK              0x30
73 #define SD_POWER_MODE_SHIFT             4
74 #define LDO_POWER_MODE_MASK             0xC0
75 #define LDO_POWER_MODE_SHIFT            6
76
77 /* SD Slew Rate */
78 #define SD_SR_13_75                     0
79 #define SD_SR_27_5                      1
80 #define SD_SR_55                        2
81 #define SD_SR_100                       3
82 #define SD_SR_MASK                      0xC0
83 #define SD_SR_SHIFT                     6
84
85 /* SD Forced PWM Mode */
86 #define SD_FPWM_MASK                    0x04
87 #define SD_FPWM_SHIFT                   2
88
89 /* SD Failling slew rate Active-Discharge Mode */
90 #define SD_FSRADE_MASK                  0x01
91 #define SD_FSRADE_SHIFT         0
92
93 /* Voltage */
94 #define SDX_VOLT_MASK                   0xFF
95 #define SD1_VOLT_MASK                   0x3F
96 #define LDO_VOLT_MASK                   0x3F
97
98 /* FPS Registers */
99 #define MAX77663_REG_FPS_CFG0           0x43
100 #define MAX77663_REG_FPS_CFG1           0x44
101 #define MAX77663_REG_FPS_CFG2           0x45
102 #define MAX77663_REG_FPS_LDO0           0x46
103 #define MAX77663_REG_FPS_LDO1           0x47
104 #define MAX77663_REG_FPS_LDO2           0x48
105 #define MAX77663_REG_FPS_LDO3           0x49
106 #define MAX77663_REG_FPS_LDO4           0x4A
107 #define MAX77663_REG_FPS_LDO5           0x4B
108 #define MAX77663_REG_FPS_LDO6           0x4C
109 #define MAX77663_REG_FPS_LDO7           0x4D
110 #define MAX77663_REG_FPS_LDO8           0x4E
111 #define MAX77663_REG_FPS_SD0            0x4F
112 #define MAX77663_REG_FPS_SD1            0x50
113 #define MAX77663_REG_FPS_SD2            0x51
114 #define MAX77663_REG_FPS_SD3            0x52
115 #define MAX77663_REG_FPS_SD4            0x53
116 #define MAX77663_REG_FPS_NONE           0
117
118 #define FPS_TIME_PERIOD_MASK            0x38
119 #define FPS_TIME_PERIOD_SHIFT           3
120 #define FPS_EN_SRC_MASK                 0x06
121 #define FPS_EN_SRC_SHIFT                1
122 #define FPS_SW_EN_MASK                  0x01
123 #define FPS_SW_EN_SHIFT                 0
124 #define FPS_SRC_MASK                    0xC0
125 #define FPS_SRC_SHIFT                   6
126 #define FPS_PU_PERIOD_MASK              0x38
127 #define FPS_PU_PERIOD_SHIFT             3
128 #define FPS_PD_PERIOD_MASK              0x07
129 #define FPS_PD_PERIOD_SHIFT             0
130
131 struct max77663_regulator {
132         struct regulator_dev *rdev;
133         struct device *dev;
134
135         u8 id;
136         u8 type;
137         u32 min_uV;
138         u32 max_uV;
139         u32 step_uV;
140         u32 regulator_mode;
141
142         u8 volt_reg;
143         u8 cfg_reg;
144         u8 fps_reg;
145
146         enum max77663_regulator_fps_src fps_src;
147
148         u8 volt_mask;
149
150         u8 power_mode;
151         u8 power_mode_mask;
152         u8 power_mode_shift;
153 };
154
155 #define fps_src_name(fps_src)   \
156         (fps_src == FPS_SRC_0 ? "FPS_SRC_0" :   \
157         fps_src == FPS_SRC_1 ? "FPS_SRC_1" :    \
158         fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
159
160 static int fps_cfg_init;
161 static u8 fps_cfg_reg[] = {
162         MAX77663_REG_FPS_CFG0,
163         MAX77663_REG_FPS_CFG1,
164         MAX77663_REG_FPS_CFG2
165 };
166
167 static inline struct max77663_regulator_platform_data
168 *_to_pdata(struct max77663_regulator *reg)
169 {
170         return reg->dev->platform_data;
171 }
172
173 static inline struct device *_to_parent(struct max77663_regulator *reg)
174 {
175         return reg->dev->parent;
176 }
177
178 static int
179 max77663_regulator_set_fps_src(struct max77663_regulator *reg,
180                                enum max77663_regulator_fps_src fps_src)
181 {
182         struct device *parent = _to_parent(reg);
183         int ret;
184
185         if (reg->fps_reg == MAX77663_REG_FPS_NONE)
186                 return 0;
187
188         switch (fps_src) {
189         case FPS_SRC_0:
190         case FPS_SRC_1:
191         case FPS_SRC_2:
192         case FPS_SRC_NONE:
193                 break;
194         case FPS_SRC_DEF:
195                 return 0;
196         default:
197                 return -EINVAL;
198         }
199
200         ret = max77663_set_bits(parent, reg->fps_reg, FPS_SRC_MASK,
201                                 fps_src << FPS_SRC_SHIFT, 0);
202         if (ret < 0)
203                 return ret;
204
205         reg->fps_src = fps_src;
206         return 0;
207 }
208
209 static int max77663_regulator_set_fps(struct max77663_regulator *reg)
210 {
211         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
212         struct device *parent = _to_parent(reg);
213         u8 fps_val = 0, fps_mask = 0;
214         int ret = 0;
215
216         if (reg->fps_reg == MAX77663_REG_FPS_NONE)
217                 return 0;
218
219         if (reg->fps_src == FPS_SRC_NONE)
220                 return 0;
221
222         /* FPS power up period setting */
223         if (pdata->fps_pu_period != FPS_POWER_PERIOD_DEF) {
224                 fps_val |= (pdata->fps_pu_period << FPS_PU_PERIOD_SHIFT);
225                 fps_mask |= FPS_PU_PERIOD_MASK;
226         }
227
228         /* FPS power down period setting */
229         if (pdata->fps_pd_period != FPS_POWER_PERIOD_DEF) {
230                 fps_val |= (pdata->fps_pd_period << FPS_PD_PERIOD_SHIFT);
231                 fps_mask |= FPS_PD_PERIOD_MASK;
232         }
233
234         if (fps_val)
235                 ret = max77663_set_bits(parent, reg->fps_reg, fps_mask,
236                                         fps_val, 0);
237
238         return ret;
239 }
240
241 static int
242 max77663_regulator_set_fps_cfg(struct max77663_regulator *reg,
243                                struct max77663_regulator_fps_cfg *fps_cfg)
244 {
245         struct device *parent = _to_parent(reg);
246         u8 addr, val, mask;
247
248         if ((fps_cfg->src < FPS_SRC_0) || (fps_cfg->src > FPS_SRC_2))
249                 return -EINVAL;
250
251         addr = fps_cfg_reg[fps_cfg->src];
252         val = (fps_cfg->en_src << FPS_EN_SRC_SHIFT);
253         mask = FPS_EN_SRC_MASK;
254
255         if (fps_cfg->time_period != FPS_TIME_PERIOD_DEF) {
256                 val |= (fps_cfg->time_period << FPS_TIME_PERIOD_SHIFT);
257                 mask |= FPS_TIME_PERIOD_MASK;
258         }
259
260         return max77663_set_bits(parent, addr, mask, val, 0);
261 }
262
263 static int
264 max77663_regulator_set_fps_cfgs(struct max77663_regulator *reg,
265                                 struct max77663_regulator_fps_cfg *fps_cfgs,
266                                 int num_fps_cfgs)
267 {
268         int i, ret;
269
270         if (fps_cfg_init)
271                 return 0;
272
273         for (i = 0; i < num_fps_cfgs; i++) {
274                 ret = max77663_regulator_set_fps_cfg(reg, &fps_cfgs[i]);
275                 if (ret < 0)
276                         return ret;
277         }
278         fps_cfg_init = 1;
279
280         return 0;
281 }
282
283 static int
284 max77663_regulator_set_power_mode(struct max77663_regulator *reg, u8 power_mode)
285 {
286         struct device *parent = _to_parent(reg);
287         u8 addr;
288         u8 mask = reg->power_mode_mask;
289         u8 shift = reg->power_mode_shift;
290         int ret;
291
292         if (reg->type == REGULATOR_TYPE_SD)
293                 addr = reg->cfg_reg;
294         else
295                 addr = reg->volt_reg;
296
297         ret = max77663_set_bits(parent, addr, mask, power_mode << shift, 0);
298         if (ret < 0)
299                 return ret;
300
301         reg->power_mode = power_mode;
302         return ret;
303 }
304
305 static u8 max77663_regulator_get_power_mode(struct max77663_regulator *reg)
306 {
307         struct device *parent = _to_parent(reg);
308         u8 addr, val;
309         u8 mask = reg->power_mode_mask;
310         u8 shift = reg->power_mode_shift;
311         int ret;
312
313         if (reg->type == REGULATOR_TYPE_SD)
314                 addr = reg->cfg_reg;
315         else
316                 addr = reg->volt_reg;
317
318         ret = max77663_read(parent, addr, &val, 1, 0);
319         if (ret < 0)
320                 return ret;
321
322         reg->power_mode = (val & mask) >> shift;
323         return reg->power_mode;
324 }
325
326 static int max77663_regulator_do_set_voltage(struct max77663_regulator *reg,
327                                              int min_uV, int max_uV)
328 {
329         struct device *parent = _to_parent(reg);
330         u8 val;
331
332         if (min_uV < reg->min_uV || max_uV > reg->max_uV)
333                 return -EDOM;
334
335         val = (min_uV - reg->min_uV) / reg->step_uV;
336         return max77663_set_bits(parent, reg->volt_reg, reg->volt_mask, val, 0);
337 }
338
339 static int max77663_regulator_set_voltage(struct regulator_dev *rdev,
340                                           int min_uV, int max_uV)
341 {
342         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
343
344         dev_dbg(&rdev->dev, "set_voltage: name=%s, min_uV=%d, max_uV=%d\n",
345                 rdev->desc->name, min_uV, max_uV);
346         return max77663_regulator_do_set_voltage(reg, min_uV, max_uV);
347 }
348
349 static int max77663_regulator_get_voltage(struct regulator_dev *rdev)
350 {
351         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
352         struct device *parent = _to_parent(reg);
353         u8 val;
354         int volt;
355         int ret;
356
357         ret = max77663_read(parent, reg->volt_reg, &val, 1, 0);
358         if (ret < 0)
359                 return ret;
360
361         volt = (val & reg->volt_mask) * reg->step_uV + reg->min_uV;
362
363         dev_dbg(&rdev->dev, "get_voltage: name=%s, volt=%d, val=0x%02x\n",
364                 rdev->desc->name, volt, val);
365         return volt;
366 }
367
368 static int max77663_regulator_enable(struct regulator_dev *rdev)
369 {
370         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
371         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
372         int power_mode = POWER_MODE_NORMAL;
373
374         if (reg->fps_src != FPS_SRC_NONE) {
375                 dev_dbg(&rdev->dev, "enable: Regulator %s using %s\n",
376                         rdev->desc->name, fps_src_name(reg->fps_src));
377                 return 0;
378         }
379
380         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
381                         && (pdata->flags & EN2_CTRL_SD0)) {
382                 dev_dbg(&rdev->dev,
383                         "enable: Regulator %s is controlled by EN2\n",
384                         rdev->desc->name);
385                 return 0;
386         }
387
388         if (reg->regulator_mode == REGULATOR_MODE_STANDBY)
389                 power_mode = POWER_MODE_LPM;
390
391         return max77663_regulator_set_power_mode(reg, power_mode);
392 }
393
394 static int max77663_regulator_disable(struct regulator_dev *rdev)
395 {
396         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
397         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
398         int power_mode = POWER_MODE_DISABLE;
399
400         if (reg->fps_src != FPS_SRC_NONE) {
401                 dev_dbg(&rdev->dev, "disable: Regulator %s using %s\n",
402                         rdev->desc->name, fps_src_name(reg->fps_src));
403                 return 0;
404         }
405
406         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
407                         && (pdata->flags & EN2_CTRL_SD0)) {
408                 dev_dbg(&rdev->dev,
409                         "disable: Regulator %s is controlled by EN2\n",
410                         rdev->desc->name);
411                 return 0;
412         }
413
414         return max77663_regulator_set_power_mode(reg, power_mode);;
415 }
416
417 static int max77663_regulator_is_enabled(struct regulator_dev *rdev)
418 {
419         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
420         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
421         int ret = 1;
422
423         if (reg->fps_src != FPS_SRC_NONE) {
424                 dev_dbg(&rdev->dev, "is_enable: Regulator %s using %s\n",
425                         rdev->desc->name, fps_src_name(reg->fps_src));
426                 return 1;
427         }
428
429         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
430                         && (pdata->flags & EN2_CTRL_SD0)) {
431                 dev_dbg(&rdev->dev,
432                         "is_enable: Regulator %s is controlled by EN2\n",
433                         rdev->desc->name);
434                 return 1;
435         }
436
437         if (max77663_regulator_get_power_mode(reg) == POWER_MODE_DISABLE)
438                 ret = 0;
439
440         return ret;
441 }
442
443 static int max77663_regulator_set_mode(struct regulator_dev *rdev,
444                                        unsigned int mode)
445 {
446         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
447         u8 power_mode;
448         int ret;
449
450         if (mode == REGULATOR_MODE_NORMAL)
451                 power_mode = POWER_MODE_NORMAL;
452         else if (mode == REGULATOR_MODE_STANDBY)
453                 power_mode = POWER_MODE_LPM;
454         else
455                 return -EINVAL;
456
457         ret = max77663_regulator_set_power_mode(reg, power_mode);
458         if (!ret)
459                 reg->regulator_mode = mode;
460
461         return ret;
462 }
463
464 static unsigned int max77663_regulator_get_mode(struct regulator_dev *rdev)
465 {
466         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
467
468         return reg->regulator_mode;
469 }
470
471 static struct regulator_ops max77663_ldo_ops = {
472         .set_voltage = max77663_regulator_set_voltage,
473         .get_voltage = max77663_regulator_get_voltage,
474         .enable = max77663_regulator_enable,
475         .disable = max77663_regulator_disable,
476         .is_enabled = max77663_regulator_is_enabled,
477         .set_mode = max77663_regulator_set_mode,
478         .get_mode = max77663_regulator_get_mode,
479 };
480
481 static int max77663_regulator_preinit(struct max77663_regulator *reg)
482 {
483         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
484         struct device *parent = _to_parent(reg);
485         u8 val;
486         int ret;
487
488         /* Update FPS source */
489         if (reg->fps_reg == MAX77663_REG_FPS_NONE)
490                 reg->fps_src = FPS_SRC_NONE;
491         else {
492                 ret = max77663_read(parent, reg->fps_reg, &val, 1, 0);
493                 if (ret < 0) {
494                         dev_err(reg->dev,
495                                 "preinit: Failed to get FPS source\n");
496                         return ret;
497                 }
498                 reg->fps_src = (val & FPS_SRC_MASK) >> FPS_SRC_SHIFT;
499         }
500
501         /* Set initial state */
502         if (!pdata->init_apply)
503                 goto skip_init_apply;
504
505         if (pdata->init_uV >= 0) {
506                 ret = max77663_regulator_do_set_voltage(reg, pdata->init_uV,
507                                                         pdata->init_uV);
508                 if (ret < 0) {
509                         dev_err(reg->dev, "preinit: Failed to set voltage to "
510                                 "%d\n", pdata->init_uV);
511                         return ret;
512                 }
513         }
514
515         if (pdata->init_enable)
516                 val = POWER_MODE_NORMAL;
517         else
518                 val = POWER_MODE_DISABLE;
519
520         ret = max77663_regulator_set_power_mode(reg, val);
521         if (ret < 0) {
522                 dev_err(reg->dev,
523                         "preinit: Failed to set power mode to %d\n", val);
524                 return ret;
525         }
526
527
528 skip_init_apply:
529         if (reg->type == REGULATOR_TYPE_SD) {
530                 if (pdata->flags & SD_SLEW_RATE_MASK) {
531                         if (pdata->flags & SD_SLEW_RATE_SLOWEST)
532                                 val = SD_SR_13_75 << SD_SR_SHIFT;
533                         else if (pdata->flags & SD_SLEW_RATE_SLOW)
534                                 val = SD_SR_27_5 << SD_SR_SHIFT;
535                         else if (pdata->flags & SD_SLEW_RATE_FAST)
536                                 val = SD_SR_55 << SD_SR_SHIFT;
537                         else
538                                 val = SD_SR_100 << SD_SR_SHIFT;
539
540                         ret = max77663_set_bits(parent, reg->cfg_reg,
541                                                 SD_SR_MASK, val, 0);
542                         if (ret < 0) {
543                                 dev_err(reg->dev,
544                                         "preinit: Failed to set slew rate\n");
545                                 return ret;
546                         }
547                 }
548
549                 if (pdata->flags & SD_FORCED_PWM_MODE) {
550                         ret = max77663_set_bits(parent, reg->cfg_reg,
551                                                 SD_FPWM_MASK, SD_FPWM_MASK, 0);
552                         if (ret < 0) {
553                                 dev_err(reg->dev, "preinit: "
554                                         "Failed to set forced pwm mode\n");
555                                 return ret;
556                         }
557                 }
558
559                 if (pdata->flags & SD_FSRADE_DISABLE) {
560                         ret = max77663_set_bits(parent, reg->cfg_reg,
561                                                 SD_FSRADE_MASK, SD_FSRADE_MASK, 0);
562                         if (ret < 0) {
563                                 dev_err(reg->dev, "preinit: "
564                                         "Failed to set falling slew-rate discharge mode\n");
565                                 return ret;
566                         }
567                 }
568
569                 if ((reg->id == MAX77663_REGULATOR_ID_SD0)
570                                 && (pdata->flags & EN2_CTRL_SD0)) {
571                         val = POWER_MODE_DISABLE;
572                         ret = max77663_regulator_set_power_mode(reg, val);
573                         if (ret < 0) {
574                                 dev_err(reg->dev, "preinit: "
575                                         "Failed to set power mode to %d for "
576                                         "EN2_CTRL_SD0\n", val);
577                                 return ret;
578                         }
579
580                         if (reg->fps_src == FPS_SRC_NONE)
581                                 return 0;
582
583                         ret = max77663_regulator_set_fps_src(reg, FPS_SRC_NONE);
584                         if (ret < 0) {
585                                 dev_err(reg->dev, "preinit: "
586                                         "Failed to set FPSSRC to FPS_SRC_NONE "
587                                         "for EN2_CTRL_SD0\n");
588                                 return ret;
589                         }
590                 }
591         }
592
593         ret = max77663_regulator_set_fps_cfgs(reg, pdata->fps_cfgs,
594                                               pdata->num_fps_cfgs);
595         if (ret < 0) {
596                 dev_err(reg->dev, "preinit: Failed to set FPSCFG\n");
597                 return ret;
598         }
599
600         ret = max77663_regulator_set_fps_src(reg, pdata->fps_src);
601         if (ret < 0) {
602                 dev_err(reg->dev, "preinit: Failed to set FPSSRC to %d\n",
603                         pdata->fps_src);
604                 return ret;
605         }
606
607         ret = max77663_regulator_set_fps(reg);
608         if (ret < 0) {
609                 dev_err(reg->dev, "preinit: Failed to set FPS\n");
610                 return ret;
611         }
612
613         return 0;
614 }
615
616 #define REGULATOR_SD(_id, _volt_mask, _fps_reg, _min_uV, _max_uV, _step_uV) \
617         [MAX77663_REGULATOR_ID_##_id] = {                       \
618                 .id = MAX77663_REGULATOR_ID_##_id,              \
619                 .type = REGULATOR_TYPE_SD,                      \
620                 .volt_reg = MAX77663_REG_##_id,                 \
621                 .volt_mask = _volt_mask##_VOLT_MASK,            \
622                 .cfg_reg = MAX77663_REG_##_id##_CFG,            \
623                 .fps_reg = MAX77663_REG_FPS_##_fps_reg,         \
624                 .min_uV = _min_uV,                              \
625                 .max_uV = _max_uV,                              \
626                 .step_uV = _step_uV,                            \
627                 .regulator_mode = REGULATOR_MODE_NORMAL,        \
628                 .power_mode = POWER_MODE_NORMAL,                \
629                 .power_mode_mask = SD_POWER_MODE_MASK,          \
630                 .power_mode_shift = SD_POWER_MODE_SHIFT,        \
631         }
632
633 #define REGULATOR_LDO(_id, _min_uV, _max_uV, _step_uV)          \
634         [MAX77663_REGULATOR_ID_##_id] = {                       \
635                 .id = MAX77663_REGULATOR_ID_##_id,              \
636                 .type = REGULATOR_TYPE_LDO,                     \
637                 .volt_reg = MAX77663_REG_##_id##_CFG,           \
638                 .volt_mask = LDO_VOLT_MASK,                     \
639                 .cfg_reg = MAX77663_REG_##_id##_CFG2,           \
640                 .fps_reg = MAX77663_REG_FPS_##_id,              \
641                 .min_uV = _min_uV,                              \
642                 .max_uV = _max_uV,                              \
643                 .step_uV = _step_uV,                            \
644                 .regulator_mode = REGULATOR_MODE_NORMAL,        \
645                 .power_mode = POWER_MODE_NORMAL,                \
646                 .power_mode_mask = LDO_POWER_MODE_MASK,         \
647                 .power_mode_shift = LDO_POWER_MODE_SHIFT,       \
648         }
649
650 static struct max77663_regulator max77663_regs[MAX77663_REGULATOR_ID_NR] = {
651         REGULATOR_SD(SD0,    SDX, SD0,  600000, 3387500, 12500),
652         REGULATOR_SD(DVSSD0, SDX, NONE, 600000, 3387500, 12500),
653         REGULATOR_SD(SD1,    SD1, SD1,  800000, 1587500, 12500),
654         REGULATOR_SD(DVSSD1, SD1, NONE, 800000, 1587500, 12500),
655         REGULATOR_SD(SD2,    SDX, SD2,  600000, 3387500, 12500),
656         REGULATOR_SD(SD3,    SDX, SD3,  600000, 3387500, 12500),
657         REGULATOR_SD(SD4,    SDX, SD4,  600000, 3387500, 12500),
658
659         REGULATOR_LDO(LDO0, 800000, 2350000, 25000),
660         REGULATOR_LDO(LDO1, 800000, 2350000, 25000),
661         REGULATOR_LDO(LDO2, 800000, 3950000, 50000),
662         REGULATOR_LDO(LDO3, 800000, 3950000, 50000),
663         REGULATOR_LDO(LDO4, 800000, 1587500, 12500),
664         REGULATOR_LDO(LDO5, 800000, 3950000, 50000),
665         REGULATOR_LDO(LDO6, 800000, 3950000, 50000),
666         REGULATOR_LDO(LDO7, 800000, 3950000, 50000),
667         REGULATOR_LDO(LDO8, 800000, 3950000, 50000),
668 };
669
670 #define REGULATOR_DESC(_id, _name)                      \
671         [MAX77663_REGULATOR_ID_##_id] = {               \
672                 .name = max77663_rails(_name),          \
673                 .id = MAX77663_REGULATOR_ID_##_id,      \
674                 .ops = &max77663_ldo_ops,               \
675                 .type = REGULATOR_VOLTAGE,              \
676                 .owner = THIS_MODULE,                   \
677         }
678
679 static struct regulator_desc max77663_rdesc[MAX77663_REGULATOR_ID_NR] = {
680         REGULATOR_DESC(SD0, sd0),
681         REGULATOR_DESC(DVSSD0, dvssd0),
682         REGULATOR_DESC(SD1, sd1),
683         REGULATOR_DESC(DVSSD1, dvssd1),
684         REGULATOR_DESC(SD2, sd2),
685         REGULATOR_DESC(SD3, sd3),
686         REGULATOR_DESC(SD4, sd4),
687         REGULATOR_DESC(LDO0, ldo0),
688         REGULATOR_DESC(LDO1, ldo1),
689         REGULATOR_DESC(LDO2, ldo2),
690         REGULATOR_DESC(LDO3, ldo3),
691         REGULATOR_DESC(LDO4, ldo4),
692         REGULATOR_DESC(LDO5, ldo5),
693         REGULATOR_DESC(LDO6, ldo6),
694         REGULATOR_DESC(LDO7, ldo7),
695         REGULATOR_DESC(LDO8, ldo8),
696 };
697
698 static int max77663_regulator_probe(struct platform_device *pdev)
699 {
700         struct regulator_desc *rdesc;
701         struct max77663_regulator *reg;
702         struct max77663_regulator_platform_data *pdata;
703         int ret = 0;
704
705         if ((pdev->id < 0) || (pdev->id >= MAX77663_REGULATOR_ID_NR)) {
706                 dev_err(&pdev->dev, "Invalid device id %d\n", pdev->id);
707                 return -ENODEV;
708         }
709
710         rdesc = &max77663_rdesc[pdev->id];
711         reg = &max77663_regs[pdev->id];
712         reg->dev = &pdev->dev;
713         pdata = reg->dev->platform_data;
714
715         dev_dbg(&pdev->dev, "probe: name=%s\n", rdesc->name);
716
717         ret = max77663_regulator_preinit(reg);
718         if (ret) {
719                 dev_err(&pdev->dev, "probe: Failed to preinit regulator %s\n",
720                         rdesc->name);
721                 return ret;
722         }
723
724         reg->rdev = regulator_register(rdesc, &pdev->dev, &pdata->init_data,
725                                        reg);
726         if (IS_ERR(reg->rdev)) {
727                 dev_err(&pdev->dev, "probe: Failed to register regulator %s\n",
728                         rdesc->name);
729                 return PTR_ERR(reg->rdev);
730         }
731
732         return 0;
733 }
734
735 static int max77663_regulator_remove(struct platform_device *pdev)
736 {
737         struct regulator_dev *rdev = platform_get_drvdata(pdev);
738
739         regulator_unregister(rdev);
740         return 0;
741 }
742
743 static struct platform_driver max77663_regulator_driver = {
744         .probe = max77663_regulator_probe,
745         .remove = __devexit_p(max77663_regulator_remove),
746         .driver = {
747                 .name = "max77663-regulator",
748                 .owner = THIS_MODULE,
749         },
750 };
751
752 static int __init max77663_regulator_init(void)
753 {
754         return platform_driver_register(&max77663_regulator_driver);
755 }
756 subsys_initcall(max77663_regulator_init);
757
758 static void __exit max77663_reg_exit(void)
759 {
760         platform_driver_unregister(&max77663_regulator_driver);
761 }
762 module_exit(max77663_reg_exit);
763
764 MODULE_LICENSE("GPL v2");
765 MODULE_DESCRIPTION("max77663 regulator driver");
766 MODULE_VERSION("1.0");