mfd: max77663: Update the driver to new mfd core
[linux-2.6.git] / drivers / regulator / max77663-regulator.c
1 /*
2  * drivers/regulator/max77663-regulator.c
3  * Maxim LDO and Buck regulators driver
4  *
5  * Copyright 2011 Maxim Integrated Products, Inc.
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of the
11  * License, or (at your option) any later version.
12  *
13  */
14
15 #include <linux/err.h>
16 #include <linux/string.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/debugfs.h>
22 #include <linux/uaccess.h>
23 #include <linux/i2c.h>
24 #include <linux/mfd/core.h>
25 #include <linux/mfd/max77663-core.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/max77663-regulator.h>
29
30 /* Regulator types */
31 #define REGULATOR_TYPE_SD               0
32 #define REGULATOR_TYPE_LDO              1
33
34 /* SD and LDO Registers */
35 #define MAX77663_REG_SD0                0x16
36 #define MAX77663_REG_SD1                0x17
37 #define MAX77663_REG_SD2                0x18
38 #define MAX77663_REG_SD3                0x19
39 #define MAX77663_REG_SD4                0x1A
40 #define MAX77663_REG_DVSSD0             0x1B
41 #define MAX77663_REG_DVSSD1             0x1C
42 #define MAX77663_REG_SD0_CFG            0x1D
43 #define MAX77663_REG_DVSSD0_CFG         MAX77663_REG_SD0_CFG
44 #define MAX77663_REG_SD1_CFG            0x1E
45 #define MAX77663_REG_DVSSD1_CFG         MAX77663_REG_SD1_CFG
46 #define MAX77663_REG_SD2_CFG            0x1F
47 #define MAX77663_REG_SD3_CFG            0x20
48 #define MAX77663_REG_SD4_CFG            0x21
49 #define MAX77663_REG_LDO0_CFG           0x23
50 #define MAX77663_REG_LDO0_CFG2          0x24
51 #define MAX77663_REG_LDO1_CFG           0x25
52 #define MAX77663_REG_LDO1_CFG2          0x26
53 #define MAX77663_REG_LDO2_CFG           0x27
54 #define MAX77663_REG_LDO2_CFG2          0x28
55 #define MAX77663_REG_LDO3_CFG           0x29
56 #define MAX77663_REG_LDO3_CFG2          0x2A
57 #define MAX77663_REG_LDO4_CFG           0x2B
58 #define MAX77663_REG_LDO4_CFG2          0x2C
59 #define MAX77663_REG_LDO5_CFG           0x2D
60 #define MAX77663_REG_LDO5_CFG2          0x2E
61 #define MAX77663_REG_LDO6_CFG           0x2F
62 #define MAX77663_REG_LDO6_CFG2          0x30
63 #define MAX77663_REG_LDO7_CFG           0x31
64 #define MAX77663_REG_LDO7_CFG2          0x32
65 #define MAX77663_REG_LDO8_CFG           0x33
66 #define MAX77663_REG_LDO8_CFG2          0x34
67
68 /* Power Mode */
69 #define POWER_MODE_NORMAL               3
70 #define POWER_MODE_LPM                  2
71 #define POWER_MODE_GLPM                 1
72 #define POWER_MODE_DISABLE              0
73 #define SD_POWER_MODE_MASK              0x30
74 #define SD_POWER_MODE_SHIFT             4
75 #define LDO_POWER_MODE_MASK             0xC0
76 #define LDO_POWER_MODE_SHIFT            6
77
78 /* SD Slew Rate */
79 #define SD_SR_13_75                     0
80 #define SD_SR_27_5                      1
81 #define SD_SR_55                        2
82 #define SD_SR_100                       3
83 #define SD_SR_MASK                      0xC0
84 #define SD_SR_SHIFT                     6
85
86 /* SD Forced PWM Mode */
87 #define SD_FPWM_MASK                    0x04
88 #define SD_FPWM_SHIFT                   2
89
90 /* SD Failling slew rate Active-Discharge Mode */
91 #define SD_FSRADE_MASK                  0x01
92 #define SD_FSRADE_SHIFT         0
93
94 /* Voltage */
95 #define SDX_VOLT_MASK                   0xFF
96 #define SD1_VOLT_MASK                   0x3F
97 #define LDO_VOLT_MASK                   0x3F
98
99 /* FPS Registers */
100 #define MAX77663_REG_FPS_CFG0           0x43
101 #define MAX77663_REG_FPS_CFG1           0x44
102 #define MAX77663_REG_FPS_CFG2           0x45
103 #define MAX77663_REG_FPS_LDO0           0x46
104 #define MAX77663_REG_FPS_LDO1           0x47
105 #define MAX77663_REG_FPS_LDO2           0x48
106 #define MAX77663_REG_FPS_LDO3           0x49
107 #define MAX77663_REG_FPS_LDO4           0x4A
108 #define MAX77663_REG_FPS_LDO5           0x4B
109 #define MAX77663_REG_FPS_LDO6           0x4C
110 #define MAX77663_REG_FPS_LDO7           0x4D
111 #define MAX77663_REG_FPS_LDO8           0x4E
112 #define MAX77663_REG_FPS_SD0            0x4F
113 #define MAX77663_REG_FPS_SD1            0x50
114 #define MAX77663_REG_FPS_SD2            0x51
115 #define MAX77663_REG_FPS_SD3            0x52
116 #define MAX77663_REG_FPS_SD4            0x53
117 #define MAX77663_REG_FPS_NONE           0
118
119 #define FPS_TIME_PERIOD_MASK            0x38
120 #define FPS_TIME_PERIOD_SHIFT           3
121 #define FPS_EN_SRC_MASK                 0x06
122 #define FPS_EN_SRC_SHIFT                1
123 #define FPS_SW_EN_MASK                  0x01
124 #define FPS_SW_EN_SHIFT                 0
125 #define FPS_SRC_MASK                    0xC0
126 #define FPS_SRC_SHIFT                   6
127 #define FPS_PU_PERIOD_MASK              0x38
128 #define FPS_PU_PERIOD_SHIFT             3
129 #define FPS_PD_PERIOD_MASK              0x07
130 #define FPS_PD_PERIOD_SHIFT             0
131
132 enum {
133         VOLT_REG = 0,
134         CFG_REG,
135         FPS_REG,
136 };
137
138 struct max77663_register {
139         u8 addr;
140         u8 val;
141 };
142
143 struct max77663_regulator {
144         struct regulator_dev *rdev;
145         struct device *dev;
146         struct max77663_regulator_platform_data *pdata;
147
148         u8 id;
149         u8 type;
150         u32 min_uV;
151         u32 max_uV;
152         u32 step_uV;
153         u32 regulator_mode;
154
155         struct max77663_register regs[3]; /* volt, cfg, fps */
156         enum max77663_regulator_fps_src fps_src;
157
158         u8 volt_mask;
159
160         u8 power_mode;
161         u8 power_mode_mask;
162         u8 power_mode_shift;
163 };
164
165 #define fps_src_name(fps_src)   \
166         (fps_src == FPS_SRC_0 ? "FPS_SRC_0" :   \
167         fps_src == FPS_SRC_1 ? "FPS_SRC_1" :    \
168         fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
169
170 static int fps_cfg_init;
171 static struct max77663_register fps_cfg_regs[] = {
172         {
173                 .addr = MAX77663_REG_FPS_CFG0,
174         },
175         {
176                 .addr = MAX77663_REG_FPS_CFG1,
177         },
178         {
179                 .addr = MAX77663_REG_FPS_CFG2,
180         },
181 };
182
183 static inline struct max77663_regulator_platform_data
184 *_to_pdata(struct max77663_regulator *reg)
185 {
186         return reg->pdata;
187 }
188
189 static inline struct device *_to_parent(struct max77663_regulator *reg)
190 {
191         return reg->dev->parent;
192 }
193
194 static inline int max77663_regulator_cache_write(struct max77663_regulator *reg,
195                                         u8 addr, u8 mask, u8 val, u8 *cache)
196 {
197         struct device *parent = _to_parent(reg);
198         u8 new_val;
199         int ret;
200
201         new_val = (*cache & ~mask) | (val & mask);
202         if (*cache != new_val) {
203                 ret = max77663_write(parent, addr, &new_val, 1, 0);
204                 if (ret < 0)
205                         return ret;
206
207                 *cache = new_val;
208         }
209         return 0;
210 }
211
212 static int
213 max77663_regulator_set_fps_src(struct max77663_regulator *reg,
214                                enum max77663_regulator_fps_src fps_src)
215 {
216         int ret;
217
218         if (reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
219                 return 0;
220
221         switch (fps_src) {
222         case FPS_SRC_0:
223         case FPS_SRC_1:
224         case FPS_SRC_2:
225         case FPS_SRC_NONE:
226                 break;
227         case FPS_SRC_DEF:
228                 return 0;
229         default:
230                 return -EINVAL;
231         }
232
233         ret = max77663_regulator_cache_write(reg, reg->regs[FPS_REG].addr,
234                                         FPS_SRC_MASK, fps_src << FPS_SRC_SHIFT,
235                                         &reg->regs[FPS_REG].val);
236         if (ret < 0)
237                 return ret;
238
239         reg->fps_src = fps_src;
240         return 0;
241 }
242
243 static int max77663_regulator_set_fps(struct max77663_regulator *reg)
244 {
245         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
246         u8 fps_val = 0, fps_mask = 0;
247         int ret = 0;
248
249         if (reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
250                 return 0;
251
252         if (reg->fps_src == FPS_SRC_NONE)
253                 return 0;
254
255         /* FPS power up period setting */
256         if (pdata->fps_pu_period != FPS_POWER_PERIOD_DEF) {
257                 fps_val |= (pdata->fps_pu_period << FPS_PU_PERIOD_SHIFT);
258                 fps_mask |= FPS_PU_PERIOD_MASK;
259         }
260
261         /* FPS power down period setting */
262         if (pdata->fps_pd_period != FPS_POWER_PERIOD_DEF) {
263                 fps_val |= (pdata->fps_pd_period << FPS_PD_PERIOD_SHIFT);
264                 fps_mask |= FPS_PD_PERIOD_MASK;
265         }
266
267         if (fps_val)
268                 ret = max77663_regulator_cache_write(reg,
269                                         reg->regs[FPS_REG].addr, fps_mask,
270                                         fps_val, &reg->regs[FPS_REG].val);
271
272         return ret;
273 }
274
275 static int
276 max77663_regulator_set_fps_cfg(struct max77663_regulator *reg,
277                                struct max77663_regulator_fps_cfg *fps_cfg)
278 {
279         u8 val, mask;
280
281         if ((fps_cfg->src < FPS_SRC_0) || (fps_cfg->src > FPS_SRC_2))
282                 return -EINVAL;
283
284         val = (fps_cfg->en_src << FPS_EN_SRC_SHIFT);
285         mask = FPS_EN_SRC_MASK;
286
287         if (fps_cfg->time_period != FPS_TIME_PERIOD_DEF) {
288                 val |= (fps_cfg->time_period << FPS_TIME_PERIOD_SHIFT);
289                 mask |= FPS_TIME_PERIOD_MASK;
290         }
291
292         return max77663_regulator_cache_write(reg,
293                                         fps_cfg_regs[fps_cfg->src].addr, mask,
294                                         val, &fps_cfg_regs[fps_cfg->src].val);
295 }
296
297 static int
298 max77663_regulator_set_fps_cfgs(struct max77663_regulator *reg,
299                                 struct max77663_regulator_fps_cfg *fps_cfgs,
300                                 int num_fps_cfgs)
301 {
302         int i, ret;
303
304         if (fps_cfg_init)
305                 return 0;
306
307         for (i = 0; i < num_fps_cfgs; i++) {
308                 ret = max77663_regulator_set_fps_cfg(reg, &fps_cfgs[i]);
309                 if (ret < 0)
310                         return ret;
311         }
312         fps_cfg_init = 1;
313
314         return 0;
315 }
316
317 static int
318 max77663_regulator_set_power_mode(struct max77663_regulator *reg, u8 power_mode)
319 {
320         u8 mask = reg->power_mode_mask;
321         u8 shift = reg->power_mode_shift;
322         int ret;
323
324         if (reg->type == REGULATOR_TYPE_SD)
325                 ret = max77663_regulator_cache_write(reg,
326                                                      reg->regs[CFG_REG].addr,
327                                                      mask, power_mode << shift,
328                                                      &reg->regs[CFG_REG].val);
329         else
330                 ret = max77663_regulator_cache_write(reg,
331                                                      reg->regs[VOLT_REG].addr,
332                                                      mask, power_mode << shift,
333                                                      &reg->regs[VOLT_REG].val);
334
335         if (ret < 0)
336                 return ret;
337
338         reg->power_mode = power_mode;
339         return ret;
340 }
341
342 static u8 max77663_regulator_get_power_mode(struct max77663_regulator *reg)
343 {
344         u8 mask = reg->power_mode_mask;
345         u8 shift = reg->power_mode_shift;
346
347         if (reg->type == REGULATOR_TYPE_SD)
348                 reg->power_mode = (reg->regs[CFG_REG].val & mask) >> shift;
349         else
350                 reg->power_mode = (reg->regs[VOLT_REG].val & mask) >> shift;
351
352         return reg->power_mode;
353 }
354
355 static int max77663_regulator_do_set_voltage(struct max77663_regulator *reg,
356                                              int min_uV, int max_uV)
357 {
358         u8 val;
359
360         if (min_uV < reg->min_uV || max_uV > reg->max_uV)
361                 return -EDOM;
362
363         val = (min_uV - reg->min_uV) / reg->step_uV;
364         return max77663_regulator_cache_write(reg, reg->regs[VOLT_REG].addr,
365                                 reg->volt_mask, val, &reg->regs[VOLT_REG].val);
366 }
367
368 static int max77663_regulator_set_voltage(struct regulator_dev *rdev,
369                                           int min_uV, int max_uV,
370                                           unsigned *selector)
371 {
372         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
373
374         dev_dbg(&rdev->dev, "set_voltage: name=%s, min_uV=%d, max_uV=%d\n",
375                 rdev->desc->name, min_uV, max_uV);
376         return max77663_regulator_do_set_voltage(reg, min_uV, max_uV);
377 }
378
379 static int max77663_regulator_get_voltage(struct regulator_dev *rdev)
380 {
381         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
382         int volt;
383
384         volt = (reg->regs[VOLT_REG].val & reg->volt_mask)
385                 * reg->step_uV + reg->min_uV;
386
387         dev_dbg(&rdev->dev, "get_voltage: name=%s, volt=%d, val=0x%02x\n",
388                 rdev->desc->name, volt, reg->regs[VOLT_REG].val);
389         return volt;
390 }
391
392 static int max77663_regulator_enable(struct regulator_dev *rdev)
393 {
394         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
395         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
396         int power_mode = POWER_MODE_NORMAL;
397
398         if (reg->fps_src != FPS_SRC_NONE) {
399                 dev_dbg(&rdev->dev, "enable: Regulator %s using %s\n",
400                         rdev->desc->name, fps_src_name(reg->fps_src));
401                 return 0;
402         }
403
404         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
405                         && (pdata->flags & EN2_CTRL_SD0)) {
406                 dev_dbg(&rdev->dev,
407                         "enable: Regulator %s is controlled by EN2\n",
408                         rdev->desc->name);
409                 return 0;
410         }
411
412         if (reg->regulator_mode == REGULATOR_MODE_STANDBY)
413                 power_mode = POWER_MODE_LPM;
414
415         return max77663_regulator_set_power_mode(reg, power_mode);
416 }
417
418 static int max77663_regulator_disable(struct regulator_dev *rdev)
419 {
420         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
421         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
422         int power_mode = POWER_MODE_DISABLE;
423
424         if (reg->fps_src != FPS_SRC_NONE) {
425                 dev_dbg(&rdev->dev, "disable: Regulator %s using %s\n",
426                         rdev->desc->name, fps_src_name(reg->fps_src));
427                 return 0;
428         }
429
430         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
431                         && (pdata->flags & EN2_CTRL_SD0)) {
432                 dev_dbg(&rdev->dev,
433                         "disable: Regulator %s is controlled by EN2\n",
434                         rdev->desc->name);
435                 return 0;
436         }
437
438         return max77663_regulator_set_power_mode(reg, power_mode);;
439 }
440
441 static int max77663_regulator_is_enabled(struct regulator_dev *rdev)
442 {
443         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
444         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
445         int ret = 1;
446
447         if (reg->fps_src != FPS_SRC_NONE) {
448                 dev_dbg(&rdev->dev, "is_enable: Regulator %s using %s\n",
449                         rdev->desc->name, fps_src_name(reg->fps_src));
450                 return 1;
451         }
452
453         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
454                         && (pdata->flags & EN2_CTRL_SD0)) {
455                 dev_dbg(&rdev->dev,
456                         "is_enable: Regulator %s is controlled by EN2\n",
457                         rdev->desc->name);
458                 return 1;
459         }
460
461         if (max77663_regulator_get_power_mode(reg) == POWER_MODE_DISABLE)
462                 ret = 0;
463
464         return ret;
465 }
466
467 static int max77663_regulator_set_mode(struct regulator_dev *rdev,
468                                        unsigned int mode)
469 {
470         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
471         u8 power_mode;
472         int ret;
473
474         if (mode == REGULATOR_MODE_NORMAL)
475                 power_mode = POWER_MODE_NORMAL;
476         else if (mode == REGULATOR_MODE_STANDBY)
477                 power_mode = POWER_MODE_LPM;
478         else
479                 return -EINVAL;
480
481         ret = max77663_regulator_set_power_mode(reg, power_mode);
482         if (!ret)
483                 reg->regulator_mode = mode;
484
485         return ret;
486 }
487
488 static unsigned int max77663_regulator_get_mode(struct regulator_dev *rdev)
489 {
490         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
491
492         return reg->regulator_mode;
493 }
494
495 static struct regulator_ops max77663_ldo_ops = {
496         .set_voltage = max77663_regulator_set_voltage,
497         .get_voltage = max77663_regulator_get_voltage,
498         .enable = max77663_regulator_enable,
499         .disable = max77663_regulator_disable,
500         .is_enabled = max77663_regulator_is_enabled,
501         .set_mode = max77663_regulator_set_mode,
502         .get_mode = max77663_regulator_get_mode,
503 };
504
505 static int max77663_regulator_preinit(struct max77663_regulator *reg)
506 {
507         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
508         struct device *parent = _to_parent(reg);
509         int i;
510         u8 val;
511         int ret;
512
513         /* Update registers */
514         for (i = 0; i <= FPS_REG; i++) {
515                 ret = max77663_read(parent, reg->regs[i].addr,
516                                     &reg->regs[i].val, 1, 0);
517                 if (ret < 0) {
518                         dev_err(reg->dev,
519                                 "preinit: Failed to get register 0x%x\n",
520                                 reg->regs[i].addr);
521                         return ret;
522                 }
523         }
524
525         for (i = 0; i <= FPS_SRC_2; i++) {
526                 ret = max77663_read(parent, fps_cfg_regs[i].addr,
527                                     &fps_cfg_regs[i].val, 1, 0);
528                 if (ret < 0) {
529                         dev_err(reg->dev,
530                                 "preinit: Failed to get register 0x%x\n",
531                                 fps_cfg_regs[i].addr);
532                         return ret;
533                 }
534         }
535
536         /* Update FPS source */
537         if (reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
538                 reg->fps_src = FPS_SRC_NONE;
539         else
540                 reg->fps_src = (reg->regs[FPS_REG].val & FPS_SRC_MASK)
541                                 >> FPS_SRC_SHIFT;
542
543         /* Set initial state */
544         if (!pdata->init_apply)
545                 goto skip_init_apply;
546
547         if (pdata->init_uV >= 0) {
548                 ret = max77663_regulator_do_set_voltage(reg, pdata->init_uV,
549                                                         pdata->init_uV);
550                 if (ret < 0) {
551                         dev_err(reg->dev, "preinit: Failed to set voltage to "
552                                 "%d\n", pdata->init_uV);
553                         return ret;
554                 }
555         }
556
557         if (pdata->init_enable)
558                 val = POWER_MODE_NORMAL;
559         else
560                 val = POWER_MODE_DISABLE;
561
562         ret = max77663_regulator_set_power_mode(reg, val);
563         if (ret < 0) {
564                 dev_err(reg->dev,
565                         "preinit: Failed to set power mode to %d\n", val);
566                 return ret;
567         }
568
569
570 skip_init_apply:
571         if (reg->type == REGULATOR_TYPE_SD) {
572                 if (pdata->flags & SD_SLEW_RATE_MASK) {
573                         if (pdata->flags & SD_SLEW_RATE_SLOWEST)
574                                 val = SD_SR_13_75 << SD_SR_SHIFT;
575                         else if (pdata->flags & SD_SLEW_RATE_SLOW)
576                                 val = SD_SR_27_5 << SD_SR_SHIFT;
577                         else if (pdata->flags & SD_SLEW_RATE_FAST)
578                                 val = SD_SR_55 << SD_SR_SHIFT;
579                         else
580                                 val = SD_SR_100 << SD_SR_SHIFT;
581
582                         ret = max77663_regulator_cache_write(reg,
583                                         reg->regs[CFG_REG].addr, SD_SR_MASK,
584                                         val, &reg->regs[CFG_REG].val);
585                         if (ret < 0) {
586                                 dev_err(reg->dev,
587                                         "preinit: Failed to set slew rate\n");
588                                 return ret;
589                         }
590                 }
591
592                 if (pdata->flags & SD_FORCED_PWM_MODE) {
593                         ret = max77663_regulator_cache_write(reg,
594                                         reg->regs[CFG_REG].addr, SD_FPWM_MASK,
595                                         SD_FPWM_MASK, &reg->regs[CFG_REG].val);
596                         if (ret < 0) {
597                                 dev_err(reg->dev, "preinit: "
598                                         "Failed to set forced pwm mode\n");
599                                 return ret;
600                         }
601                 }
602
603                 if (pdata->flags & SD_FSRADE_DISABLE) {
604                         ret = max77663_regulator_cache_write(reg,
605                                         reg->regs[CFG_REG].addr,
606                                         SD_FSRADE_MASK, SD_FSRADE_MASK,
607                                         &reg->regs[CFG_REG].val);
608                         if (ret < 0) {
609                                 dev_err(reg->dev, "preinit: Failed to set "
610                                         "falling slew-rate discharge mode\n");
611                                 return ret;
612                         }
613                 }
614
615                 if ((reg->id == MAX77663_REGULATOR_ID_SD0)
616                                 && (pdata->flags & EN2_CTRL_SD0)) {
617                         val = POWER_MODE_DISABLE;
618                         ret = max77663_regulator_set_power_mode(reg, val);
619                         if (ret < 0) {
620                                 dev_err(reg->dev, "preinit: "
621                                         "Failed to set power mode to %d for "
622                                         "EN2_CTRL_SD0\n", val);
623                                 return ret;
624                         }
625
626                         if (reg->fps_src == FPS_SRC_NONE)
627                                 return 0;
628
629                         ret = max77663_regulator_set_fps_src(reg, FPS_SRC_NONE);
630                         if (ret < 0) {
631                                 dev_err(reg->dev, "preinit: "
632                                         "Failed to set FPSSRC to FPS_SRC_NONE "
633                                         "for EN2_CTRL_SD0\n");
634                                 return ret;
635                         }
636                 }
637         }
638
639         ret = max77663_regulator_set_fps_cfgs(reg, pdata->fps_cfgs,
640                                               pdata->num_fps_cfgs);
641         if (ret < 0) {
642                 dev_err(reg->dev, "preinit: Failed to set FPSCFG\n");
643                 return ret;
644         }
645
646         ret = max77663_regulator_set_fps_src(reg, pdata->fps_src);
647         if (ret < 0) {
648                 dev_err(reg->dev, "preinit: Failed to set FPSSRC to %d\n",
649                         pdata->fps_src);
650                 return ret;
651         }
652
653         ret = max77663_regulator_set_fps(reg);
654         if (ret < 0) {
655                 dev_err(reg->dev, "preinit: Failed to set FPS\n");
656                 return ret;
657         }
658
659         return 0;
660 }
661
662 #define REGULATOR_SD(_id, _volt_mask, _fps_reg, _min_uV, _max_uV, _step_uV) \
663         [MAX77663_REGULATOR_ID_##_id] = {                       \
664                 .id = MAX77663_REGULATOR_ID_##_id,              \
665                 .type = REGULATOR_TYPE_SD,                      \
666                 .volt_mask = _volt_mask##_VOLT_MASK,            \
667                 .regs = {                                       \
668                         [VOLT_REG] = {                          \
669                                 .addr = MAX77663_REG_##_id,     \
670                         },                                      \
671                         [CFG_REG] = {                           \
672                                 .addr = MAX77663_REG_##_id##_CFG, \
673                         },                                      \
674                         [FPS_REG] = {                           \
675                                 .addr = MAX77663_REG_FPS_##_fps_reg, \
676                         },                                      \
677                 },                                              \
678                 .min_uV = _min_uV,                              \
679                 .max_uV = _max_uV,                              \
680                 .step_uV = _step_uV,                            \
681                 .regulator_mode = REGULATOR_MODE_NORMAL,        \
682                 .power_mode = POWER_MODE_NORMAL,                \
683                 .power_mode_mask = SD_POWER_MODE_MASK,          \
684                 .power_mode_shift = SD_POWER_MODE_SHIFT,        \
685         }
686
687 #define REGULATOR_LDO(_id, _min_uV, _max_uV, _step_uV)          \
688         [MAX77663_REGULATOR_ID_##_id] = {                       \
689                 .id = MAX77663_REGULATOR_ID_##_id,              \
690                 .type = REGULATOR_TYPE_LDO,                     \
691                 .volt_mask = LDO_VOLT_MASK,                     \
692                 .regs = {                                       \
693                         [VOLT_REG] = {                          \
694                                 .addr = MAX77663_REG_##_id##_CFG, \
695                         },                                      \
696                         [CFG_REG] = {                           \
697                                 .addr = MAX77663_REG_##_id##_CFG2, \
698                         },                                      \
699                         [FPS_REG] = {                           \
700                                 .addr = MAX77663_REG_FPS_##_id, \
701                         },                                      \
702                 },                                              \
703                 .min_uV = _min_uV,                              \
704                 .max_uV = _max_uV,                              \
705                 .step_uV = _step_uV,                            \
706                 .regulator_mode = REGULATOR_MODE_NORMAL,        \
707                 .power_mode = POWER_MODE_NORMAL,                \
708                 .power_mode_mask = LDO_POWER_MODE_MASK,         \
709                 .power_mode_shift = LDO_POWER_MODE_SHIFT,       \
710         }
711
712 static struct max77663_regulator max77663_regs[MAX77663_REGULATOR_ID_NR] = {
713         REGULATOR_SD(SD0,    SDX, SD0,  600000, 3387500, 12500),
714         REGULATOR_SD(DVSSD0, SDX, NONE, 600000, 3387500, 12500),
715         REGULATOR_SD(SD1,    SD1, SD1,  800000, 1587500, 12500),
716         REGULATOR_SD(DVSSD1, SD1, NONE, 800000, 1587500, 12500),
717         REGULATOR_SD(SD2,    SDX, SD2,  600000, 3387500, 12500),
718         REGULATOR_SD(SD3,    SDX, SD3,  600000, 3387500, 12500),
719         REGULATOR_SD(SD4,    SDX, SD4,  600000, 3387500, 12500),
720
721         REGULATOR_LDO(LDO0, 800000, 2350000, 25000),
722         REGULATOR_LDO(LDO1, 800000, 2350000, 25000),
723         REGULATOR_LDO(LDO2, 800000, 3950000, 50000),
724         REGULATOR_LDO(LDO3, 800000, 3950000, 50000),
725         REGULATOR_LDO(LDO4, 800000, 1587500, 12500),
726         REGULATOR_LDO(LDO5, 800000, 3950000, 50000),
727         REGULATOR_LDO(LDO6, 800000, 3950000, 50000),
728         REGULATOR_LDO(LDO7, 800000, 3950000, 50000),
729         REGULATOR_LDO(LDO8, 800000, 3950000, 50000),
730 };
731
732 #define REGULATOR_DESC(_id, _name)                      \
733         [MAX77663_REGULATOR_ID_##_id] = {               \
734                 .name = max77663_rails(_name),          \
735                 .id = MAX77663_REGULATOR_ID_##_id,      \
736                 .ops = &max77663_ldo_ops,               \
737                 .type = REGULATOR_VOLTAGE,              \
738                 .owner = THIS_MODULE,                   \
739         }
740
741 static struct regulator_desc max77663_rdesc[MAX77663_REGULATOR_ID_NR] = {
742         REGULATOR_DESC(SD0, sd0),
743         REGULATOR_DESC(DVSSD0, dvssd0),
744         REGULATOR_DESC(SD1, sd1),
745         REGULATOR_DESC(DVSSD1, dvssd1),
746         REGULATOR_DESC(SD2, sd2),
747         REGULATOR_DESC(SD3, sd3),
748         REGULATOR_DESC(SD4, sd4),
749         REGULATOR_DESC(LDO0, ldo0),
750         REGULATOR_DESC(LDO1, ldo1),
751         REGULATOR_DESC(LDO2, ldo2),
752         REGULATOR_DESC(LDO3, ldo3),
753         REGULATOR_DESC(LDO4, ldo4),
754         REGULATOR_DESC(LDO5, ldo5),
755         REGULATOR_DESC(LDO6, ldo6),
756         REGULATOR_DESC(LDO7, ldo7),
757         REGULATOR_DESC(LDO8, ldo8),
758 };
759
760 static int max77663_regulator_probe(struct platform_device *pdev)
761 {
762         struct regulator_desc *rdesc;
763         struct max77663_regulator *reg;
764         int ret = 0;
765
766         if ((pdev->id < 0) || (pdev->id >= MAX77663_REGULATOR_ID_NR)) {
767                 dev_err(&pdev->dev, "Invalid device id %d\n", pdev->id);
768                 return -ENODEV;
769         }
770
771         rdesc = &max77663_rdesc[pdev->id];
772         reg = &max77663_regs[pdev->id];
773         reg->dev = &pdev->dev;
774         reg->pdata = mfd_get_data(pdev);
775
776         dev_dbg(&pdev->dev, "probe: name=%s\n", rdesc->name);
777
778         ret = max77663_regulator_preinit(reg);
779         if (ret) {
780                 dev_err(&pdev->dev, "probe: Failed to preinit regulator %s\n",
781                         rdesc->name);
782                 return ret;
783         }
784
785         reg->rdev = regulator_register(rdesc, &pdev->dev,
786                                        &reg->pdata->init_data, reg);
787         if (IS_ERR(reg->rdev)) {
788                 dev_err(&pdev->dev, "probe: Failed to register regulator %s\n",
789                         rdesc->name);
790                 return PTR_ERR(reg->rdev);
791         }
792
793         return 0;
794 }
795
796 static int max77663_regulator_remove(struct platform_device *pdev)
797 {
798         struct regulator_dev *rdev = platform_get_drvdata(pdev);
799
800         regulator_unregister(rdev);
801         return 0;
802 }
803
804 static struct platform_driver max77663_regulator_driver = {
805         .probe = max77663_regulator_probe,
806         .remove = __devexit_p(max77663_regulator_remove),
807         .driver = {
808                 .name = "max77663-regulator",
809                 .owner = THIS_MODULE,
810         },
811 };
812
813 static int __init max77663_regulator_init(void)
814 {
815         return platform_driver_register(&max77663_regulator_driver);
816 }
817 subsys_initcall(max77663_regulator_init);
818
819 static void __exit max77663_reg_exit(void)
820 {
821         platform_driver_unregister(&max77663_regulator_driver);
822 }
823 module_exit(max77663_reg_exit);
824
825 MODULE_LICENSE("GPL v2");
826 MODULE_DESCRIPTION("max77663 regulator driver");
827 MODULE_VERSION("1.0");