regulator: max77663: Fix power rail turn-off when change FPS source
[linux-2.6.git] / drivers / regulator / max77663-regulator.c
1 /*
2  * drivers/regulator/max77663-regulator.c
3  * Maxim LDO and Buck regulators driver
4  *
5  * Copyright 2011 Maxim Integrated Products, Inc.
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of the
11  * License, or (at your option) any later version.
12  *
13  */
14
15 #include <linux/err.h>
16 #include <linux/string.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/debugfs.h>
22 #include <linux/uaccess.h>
23 #include <linux/i2c.h>
24 #include <linux/mfd/core.h>
25 #include <linux/mfd/max77663-core.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/max77663-regulator.h>
29
30 /* Regulator types */
31 #define REGULATOR_TYPE_SD               0
32 #define REGULATOR_TYPE_LDO              1
33
34 /* SD and LDO Registers */
35 #define MAX77663_REG_SD0                0x16
36 #define MAX77663_REG_SD1                0x17
37 #define MAX77663_REG_SD2                0x18
38 #define MAX77663_REG_SD3                0x19
39 #define MAX77663_REG_SD4                0x1A
40 #define MAX77663_REG_DVSSD0             0x1B
41 #define MAX77663_REG_DVSSD1             0x1C
42 #define MAX77663_REG_SD0_CFG            0x1D
43 #define MAX77663_REG_DVSSD0_CFG         MAX77663_REG_SD0_CFG
44 #define MAX77663_REG_SD1_CFG            0x1E
45 #define MAX77663_REG_DVSSD1_CFG         MAX77663_REG_SD1_CFG
46 #define MAX77663_REG_SD2_CFG            0x1F
47 #define MAX77663_REG_SD3_CFG            0x20
48 #define MAX77663_REG_SD4_CFG            0x21
49 #define MAX77663_REG_LDO0_CFG           0x23
50 #define MAX77663_REG_LDO0_CFG2          0x24
51 #define MAX77663_REG_LDO1_CFG           0x25
52 #define MAX77663_REG_LDO1_CFG2          0x26
53 #define MAX77663_REG_LDO2_CFG           0x27
54 #define MAX77663_REG_LDO2_CFG2          0x28
55 #define MAX77663_REG_LDO3_CFG           0x29
56 #define MAX77663_REG_LDO3_CFG2          0x2A
57 #define MAX77663_REG_LDO4_CFG           0x2B
58 #define MAX77663_REG_LDO4_CFG2          0x2C
59 #define MAX77663_REG_LDO5_CFG           0x2D
60 #define MAX77663_REG_LDO5_CFG2          0x2E
61 #define MAX77663_REG_LDO6_CFG           0x2F
62 #define MAX77663_REG_LDO6_CFG2          0x30
63 #define MAX77663_REG_LDO7_CFG           0x31
64 #define MAX77663_REG_LDO7_CFG2          0x32
65 #define MAX77663_REG_LDO8_CFG           0x33
66 #define MAX77663_REG_LDO8_CFG2          0x34
67
68 /* Power Mode */
69 #define POWER_MODE_NORMAL               3
70 #define POWER_MODE_LPM                  2
71 #define POWER_MODE_GLPM                 1
72 #define POWER_MODE_DISABLE              0
73 #define SD_POWER_MODE_MASK              0x30
74 #define SD_POWER_MODE_SHIFT             4
75 #define LDO_POWER_MODE_MASK             0xC0
76 #define LDO_POWER_MODE_SHIFT            6
77
78 /* SD Slew Rate */
79 #define SD_SR_13_75                     0
80 #define SD_SR_27_5                      1
81 #define SD_SR_55                        2
82 #define SD_SR_100                       3
83 #define SD_SR_MASK                      0xC0
84 #define SD_SR_SHIFT                     6
85
86 /* SD Forced PWM Mode */
87 #define SD_FPWM_MASK                    0x04
88 #define SD_FPWM_SHIFT                   2
89
90 /* SD Failling slew rate Active-Discharge Mode */
91 #define SD_FSRADE_MASK                  0x01
92 #define SD_FSRADE_SHIFT         0
93
94 /* Voltage */
95 #define SDX_VOLT_MASK                   0xFF
96 #define SD1_VOLT_MASK                   0x3F
97 #define LDO_VOLT_MASK                   0x3F
98
99 /* FPS Registers */
100 #define MAX77663_REG_FPS_CFG0           0x43
101 #define MAX77663_REG_FPS_CFG1           0x44
102 #define MAX77663_REG_FPS_CFG2           0x45
103 #define MAX77663_REG_FPS_LDO0           0x46
104 #define MAX77663_REG_FPS_LDO1           0x47
105 #define MAX77663_REG_FPS_LDO2           0x48
106 #define MAX77663_REG_FPS_LDO3           0x49
107 #define MAX77663_REG_FPS_LDO4           0x4A
108 #define MAX77663_REG_FPS_LDO5           0x4B
109 #define MAX77663_REG_FPS_LDO6           0x4C
110 #define MAX77663_REG_FPS_LDO7           0x4D
111 #define MAX77663_REG_FPS_LDO8           0x4E
112 #define MAX77663_REG_FPS_SD0            0x4F
113 #define MAX77663_REG_FPS_SD1            0x50
114 #define MAX77663_REG_FPS_SD2            0x51
115 #define MAX77663_REG_FPS_SD3            0x52
116 #define MAX77663_REG_FPS_SD4            0x53
117 #define MAX77663_REG_FPS_NONE           0
118
119 #define FPS_TIME_PERIOD_MASK            0x38
120 #define FPS_TIME_PERIOD_SHIFT           3
121 #define FPS_EN_SRC_MASK                 0x06
122 #define FPS_EN_SRC_SHIFT                1
123 #define FPS_SW_EN_MASK                  0x01
124 #define FPS_SW_EN_SHIFT                 0
125 #define FPS_SRC_MASK                    0xC0
126 #define FPS_SRC_SHIFT                   6
127 #define FPS_PU_PERIOD_MASK              0x38
128 #define FPS_PU_PERIOD_SHIFT             3
129 #define FPS_PD_PERIOD_MASK              0x07
130 #define FPS_PD_PERIOD_SHIFT             0
131
132 /* Chip Identification Register */
133 #define MAX77663_REG_CID5               0x5D
134
135 #define CID_DIDM_MASK                   0xF0
136 #define CID_DIDM_SHIFT                  4
137
138 #define SD_SAFE_DOWN_UV                 50000 /* 50mV */
139
140 enum {
141         VOLT_REG = 0,
142         CFG_REG,
143         FPS_REG,
144 };
145
146 struct max77663_register {
147         u8 addr;
148         u8 val;
149 };
150
151 struct max77663_regulator {
152         struct regulator_dev *rdev;
153         struct device *dev;
154         struct max77663_regulator_platform_data *pdata;
155
156         u8 id;
157         u8 type;
158         u32 min_uV;
159         u32 max_uV;
160         u32 step_uV;
161         int safe_down_uV; /* for stable down scaling */
162         u32 regulator_mode;
163
164         struct max77663_register regs[3]; /* volt, cfg, fps */
165         enum max77663_regulator_fps_src fps_src;
166
167         u8 volt_mask;
168
169         u8 power_mode;
170         u8 power_mode_mask;
171         u8 power_mode_shift;
172 };
173
174 #define fps_src_name(fps_src)   \
175         (fps_src == FPS_SRC_0 ? "FPS_SRC_0" :   \
176         fps_src == FPS_SRC_1 ? "FPS_SRC_1" :    \
177         fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
178
179 static int fps_cfg_init;
180 static struct max77663_register fps_cfg_regs[] = {
181         {
182                 .addr = MAX77663_REG_FPS_CFG0,
183         },
184         {
185                 .addr = MAX77663_REG_FPS_CFG1,
186         },
187         {
188                 .addr = MAX77663_REG_FPS_CFG2,
189         },
190 };
191
192 static inline struct max77663_regulator_platform_data
193 *_to_pdata(struct max77663_regulator *reg)
194 {
195         return reg->pdata;
196 }
197
198 static inline struct device *_to_parent(struct max77663_regulator *reg)
199 {
200         return reg->dev->parent;
201 }
202
203 static inline int max77663_regulator_cache_write(struct max77663_regulator *reg,
204                                         u8 addr, u8 mask, u8 val, u8 *cache)
205 {
206         struct device *parent = _to_parent(reg);
207         u8 new_val;
208         int ret;
209
210         new_val = (*cache & ~mask) | (val & mask);
211         if (*cache != new_val) {
212                 ret = max77663_write(parent, addr, &new_val, 1, 0);
213                 if (ret < 0)
214                         return ret;
215
216                 *cache = new_val;
217         }
218         return 0;
219 }
220
221 static int
222 max77663_regulator_set_fps_src(struct max77663_regulator *reg,
223                                enum max77663_regulator_fps_src fps_src)
224 {
225         int ret;
226
227         if ((reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE) ||
228                         (reg->fps_src == fps_src))
229                 return 0;
230
231         switch (fps_src) {
232         case FPS_SRC_0:
233         case FPS_SRC_1:
234         case FPS_SRC_2:
235         case FPS_SRC_NONE:
236                 break;
237         case FPS_SRC_DEF:
238                 return 0;
239         default:
240                 return -EINVAL;
241         }
242
243         ret = max77663_regulator_cache_write(reg, reg->regs[FPS_REG].addr,
244                                         FPS_SRC_MASK, fps_src << FPS_SRC_SHIFT,
245                                         &reg->regs[FPS_REG].val);
246         if (ret < 0)
247                 return ret;
248
249         reg->fps_src = fps_src;
250         return 0;
251 }
252
253 static int max77663_regulator_set_fps(struct max77663_regulator *reg)
254 {
255         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
256         u8 fps_val = 0, fps_mask = 0;
257         int ret = 0;
258
259         if (reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
260                 return 0;
261
262         if (reg->fps_src == FPS_SRC_NONE)
263                 return 0;
264
265         /* FPS power up period setting */
266         if (pdata->fps_pu_period != FPS_POWER_PERIOD_DEF) {
267                 fps_val |= (pdata->fps_pu_period << FPS_PU_PERIOD_SHIFT);
268                 fps_mask |= FPS_PU_PERIOD_MASK;
269         }
270
271         /* FPS power down period setting */
272         if (pdata->fps_pd_period != FPS_POWER_PERIOD_DEF) {
273                 fps_val |= (pdata->fps_pd_period << FPS_PD_PERIOD_SHIFT);
274                 fps_mask |= FPS_PD_PERIOD_MASK;
275         }
276
277         if (fps_val)
278                 ret = max77663_regulator_cache_write(reg,
279                                         reg->regs[FPS_REG].addr, fps_mask,
280                                         fps_val, &reg->regs[FPS_REG].val);
281
282         return ret;
283 }
284
285 static int
286 max77663_regulator_set_fps_cfg(struct max77663_regulator *reg,
287                                struct max77663_regulator_fps_cfg *fps_cfg)
288 {
289         u8 val, mask;
290
291         if ((fps_cfg->src < FPS_SRC_0) || (fps_cfg->src > FPS_SRC_2))
292                 return -EINVAL;
293
294         val = (fps_cfg->en_src << FPS_EN_SRC_SHIFT);
295         mask = FPS_EN_SRC_MASK;
296
297         if (fps_cfg->time_period != FPS_TIME_PERIOD_DEF) {
298                 val |= (fps_cfg->time_period << FPS_TIME_PERIOD_SHIFT);
299                 mask |= FPS_TIME_PERIOD_MASK;
300         }
301
302         return max77663_regulator_cache_write(reg,
303                                         fps_cfg_regs[fps_cfg->src].addr, mask,
304                                         val, &fps_cfg_regs[fps_cfg->src].val);
305 }
306
307 static int
308 max77663_regulator_set_fps_cfgs(struct max77663_regulator *reg,
309                                 struct max77663_regulator_fps_cfg *fps_cfgs,
310                                 int num_fps_cfgs)
311 {
312         struct device *parent = _to_parent(reg);
313         int i, ret;
314
315         if (fps_cfg_init)
316                 return 0;
317
318         for (i = 0; i <= FPS_SRC_2; i++) {
319                 ret = max77663_read(parent, fps_cfg_regs[i].addr,
320                                     &fps_cfg_regs[i].val, 1, 0);
321                 if (ret < 0)
322                         return ret;
323         }
324
325         for (i = 0; i < num_fps_cfgs; i++) {
326                 ret = max77663_regulator_set_fps_cfg(reg, &fps_cfgs[i]);
327                 if (ret < 0)
328                         return ret;
329         }
330         fps_cfg_init = 1;
331
332         return 0;
333 }
334
335 static int
336 max77663_regulator_set_power_mode(struct max77663_regulator *reg, u8 power_mode)
337 {
338         u8 mask = reg->power_mode_mask;
339         u8 shift = reg->power_mode_shift;
340         int ret;
341
342         if (reg->type == REGULATOR_TYPE_SD)
343                 ret = max77663_regulator_cache_write(reg,
344                                                      reg->regs[CFG_REG].addr,
345                                                      mask, power_mode << shift,
346                                                      &reg->regs[CFG_REG].val);
347         else
348                 ret = max77663_regulator_cache_write(reg,
349                                                      reg->regs[VOLT_REG].addr,
350                                                      mask, power_mode << shift,
351                                                      &reg->regs[VOLT_REG].val);
352
353         if (ret < 0)
354                 return ret;
355
356         reg->power_mode = power_mode;
357         return ret;
358 }
359
360 static u8 max77663_regulator_get_power_mode(struct max77663_regulator *reg)
361 {
362         u8 mask = reg->power_mode_mask;
363         u8 shift = reg->power_mode_shift;
364
365         if (reg->type == REGULATOR_TYPE_SD)
366                 reg->power_mode = (reg->regs[CFG_REG].val & mask) >> shift;
367         else
368                 reg->power_mode = (reg->regs[VOLT_REG].val & mask) >> shift;
369
370         return reg->power_mode;
371 }
372
373 static int max77663_regulator_do_set_voltage(struct max77663_regulator *reg,
374                                              int min_uV, int max_uV)
375 {
376         u8 addr = reg->regs[VOLT_REG].addr;
377         u8 mask = reg->volt_mask;
378         u8 *cache = &reg->regs[VOLT_REG].val;
379         u8 val;
380         int old_uV, new_uV, safe_uV;
381         int i, steps = 1;
382         int ret = 0;
383
384         if (min_uV < reg->min_uV || max_uV > reg->max_uV)
385                 return -EDOM;
386
387         old_uV = (*cache & mask) * reg->step_uV + reg->min_uV;
388
389         if ((old_uV > min_uV) && (reg->safe_down_uV >= reg->step_uV)) {
390                 steps = DIV_ROUND_UP(old_uV - min_uV, reg->safe_down_uV);
391                 safe_uV = -reg->safe_down_uV;
392         }
393
394         if (steps == 1) {
395                 val = (min_uV - reg->min_uV) / reg->step_uV;
396                 ret = max77663_regulator_cache_write(reg, addr, mask, val,
397                                                      cache);
398         } else {
399                 for (i = 0; i < steps; i++) {
400                         if (abs(min_uV - old_uV) > abs(safe_uV))
401                                 new_uV = old_uV + safe_uV;
402                         else
403                                 new_uV = min_uV;
404
405                         dev_dbg(&reg->rdev->dev, "do_set_voltage: name=%s, "
406                                 "%d/%d, old_uV=%d, new_uV=%d\n",
407                                 reg->rdev->desc->name, i + 1, steps, old_uV,
408                                 new_uV);
409
410                         val = (new_uV - reg->min_uV) / reg->step_uV;
411                         ret = max77663_regulator_cache_write(reg, addr, mask,
412                                                              val, cache);
413                         if (ret < 0)
414                                 return ret;
415
416                         old_uV = new_uV;
417                 }
418         }
419
420         return ret;
421 }
422
423 static int max77663_regulator_set_voltage(struct regulator_dev *rdev,
424                                           int min_uV, int max_uV,
425                                           unsigned *selector)
426 {
427         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
428
429         dev_dbg(&rdev->dev, "set_voltage: name=%s, min_uV=%d, max_uV=%d\n",
430                 rdev->desc->name, min_uV, max_uV);
431         return max77663_regulator_do_set_voltage(reg, min_uV, max_uV);
432 }
433
434 static int max77663_regulator_get_voltage(struct regulator_dev *rdev)
435 {
436         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
437         int volt;
438
439         volt = (reg->regs[VOLT_REG].val & reg->volt_mask)
440                 * reg->step_uV + reg->min_uV;
441
442         dev_dbg(&rdev->dev, "get_voltage: name=%s, volt=%d, val=0x%02x\n",
443                 rdev->desc->name, volt, reg->regs[VOLT_REG].val);
444         return volt;
445 }
446
447 static int max77663_regulator_enable(struct regulator_dev *rdev)
448 {
449         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
450         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
451         int power_mode = POWER_MODE_NORMAL;
452
453         if (reg->fps_src != FPS_SRC_NONE) {
454                 dev_dbg(&rdev->dev, "enable: Regulator %s using %s\n",
455                         rdev->desc->name, fps_src_name(reg->fps_src));
456                 return 0;
457         }
458
459         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
460                         && (pdata->flags & EN2_CTRL_SD0)) {
461                 dev_dbg(&rdev->dev,
462                         "enable: Regulator %s is controlled by EN2\n",
463                         rdev->desc->name);
464                 return 0;
465         }
466
467         if (reg->regulator_mode == REGULATOR_MODE_STANDBY)
468                 power_mode = POWER_MODE_LPM;
469
470         return max77663_regulator_set_power_mode(reg, power_mode);
471 }
472
473 static int max77663_regulator_disable(struct regulator_dev *rdev)
474 {
475         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
476         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
477         int power_mode = POWER_MODE_DISABLE;
478
479         if (reg->fps_src != FPS_SRC_NONE) {
480                 dev_dbg(&rdev->dev, "disable: Regulator %s using %s\n",
481                         rdev->desc->name, fps_src_name(reg->fps_src));
482                 return 0;
483         }
484
485         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
486                         && (pdata->flags & EN2_CTRL_SD0)) {
487                 dev_dbg(&rdev->dev,
488                         "disable: Regulator %s is controlled by EN2\n",
489                         rdev->desc->name);
490                 return 0;
491         }
492
493         return max77663_regulator_set_power_mode(reg, power_mode);
494 }
495
496 static int max77663_regulator_is_enabled(struct regulator_dev *rdev)
497 {
498         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
499         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
500         int ret = 1;
501
502         if (reg->fps_src != FPS_SRC_NONE) {
503                 dev_dbg(&rdev->dev, "is_enable: Regulator %s using %s\n",
504                         rdev->desc->name, fps_src_name(reg->fps_src));
505                 return 1;
506         }
507
508         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
509                         && (pdata->flags & EN2_CTRL_SD0)) {
510                 dev_dbg(&rdev->dev,
511                         "is_enable: Regulator %s is controlled by EN2\n",
512                         rdev->desc->name);
513                 return 1;
514         }
515
516         if (max77663_regulator_get_power_mode(reg) == POWER_MODE_DISABLE)
517                 ret = 0;
518
519         return ret;
520 }
521
522 static int max77663_regulator_set_mode(struct regulator_dev *rdev,
523                                        unsigned int mode)
524 {
525         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
526         u8 power_mode;
527         int ret;
528
529         if (mode == REGULATOR_MODE_NORMAL)
530                 power_mode = POWER_MODE_NORMAL;
531         else if (mode == REGULATOR_MODE_STANDBY)
532                 power_mode = POWER_MODE_LPM;
533         else
534                 return -EINVAL;
535
536         ret = max77663_regulator_set_power_mode(reg, power_mode);
537         if (!ret)
538                 reg->regulator_mode = mode;
539
540         return ret;
541 }
542
543 static unsigned int max77663_regulator_get_mode(struct regulator_dev *rdev)
544 {
545         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
546
547         return reg->regulator_mode;
548 }
549
550 static struct regulator_ops max77663_ldo_ops = {
551         .set_voltage = max77663_regulator_set_voltage,
552         .get_voltage = max77663_regulator_get_voltage,
553         .enable = max77663_regulator_enable,
554         .disable = max77663_regulator_disable,
555         .is_enabled = max77663_regulator_is_enabled,
556         .set_mode = max77663_regulator_set_mode,
557         .get_mode = max77663_regulator_get_mode,
558 };
559
560 static int max77663_regulator_preinit(struct max77663_regulator *reg)
561 {
562         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
563         struct device *parent = _to_parent(reg);
564         int i;
565         u8 val, mask;
566         int ret;
567
568         /* Update registers */
569         for (i = 0; i <= FPS_REG; i++) {
570                 ret = max77663_read(parent, reg->regs[i].addr,
571                                     &reg->regs[i].val, 1, 0);
572                 if (ret < 0) {
573                         dev_err(reg->dev,
574                                 "preinit: Failed to get register 0x%x\n",
575                                 reg->regs[i].addr);
576                         return ret;
577                 }
578         }
579
580         /* Update FPS source */
581         if (reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
582                 reg->fps_src = FPS_SRC_NONE;
583         else
584                 reg->fps_src = (reg->regs[FPS_REG].val & FPS_SRC_MASK)
585                                 >> FPS_SRC_SHIFT;
586
587         dev_dbg(reg->dev, "preinit: initial fps_src=%s\n",
588                 fps_src_name(reg->fps_src));
589
590         /* Update power mode */
591         max77663_regulator_get_power_mode(reg);
592
593         /* Check Chip Identification */
594         ret = max77663_read(parent, MAX77663_REG_CID5, &val, 1, 0);
595         if (ret < 0) {
596                 dev_err(reg->dev, "preinit: Failed to get register 0x%x\n",
597                         MAX77663_REG_CID5);
598                 return ret;
599         }
600
601         /* If metal revision is less than rev.3,
602          * set safe_down_uV for stable down scaling. */
603         if ((reg->type == REGULATOR_TYPE_SD) &&
604                         ((val & CID_DIDM_MASK) >> CID_DIDM_SHIFT) <= 2)
605                 reg->safe_down_uV = SD_SAFE_DOWN_UV;
606         else
607                 reg->safe_down_uV = 0;
608
609         /* Set FPS */
610         ret = max77663_regulator_set_fps_cfgs(reg, pdata->fps_cfgs,
611                                               pdata->num_fps_cfgs);
612         if (ret < 0) {
613                 dev_err(reg->dev, "preinit: Failed to set FPSCFG\n");
614                 return ret;
615         }
616
617         /* To prevent power rail turn-off when change FPS source,
618          * it must set power mode to NORMAL before change FPS source to NONE
619          * from SRC_0, SRC_1 and SRC_2. */
620         if ((reg->fps_src != FPS_SRC_NONE) && (pdata->fps_src == FPS_SRC_NONE)
621                         && (reg->power_mode != POWER_MODE_NORMAL)) {
622                 ret = max77663_regulator_set_power_mode(reg, POWER_MODE_NORMAL);
623                 if (ret < 0) {
624                         dev_err(reg->dev, "preinit: Failed to "
625                                 "set power mode to POWER_MODE_NORMAL\n");
626                         return ret;
627                 }
628         }
629
630         ret = max77663_regulator_set_fps_src(reg, pdata->fps_src);
631         if (ret < 0) {
632                 dev_err(reg->dev, "preinit: Failed to set FPSSRC to %d\n",
633                         pdata->fps_src);
634                 return ret;
635         }
636
637         ret = max77663_regulator_set_fps(reg);
638         if (ret < 0) {
639                 dev_err(reg->dev, "preinit: Failed to set FPS\n");
640                 return ret;
641         }
642
643         /* Set initial state */
644         if (!pdata->init_apply)
645                 goto skip_init_apply;
646
647         if (pdata->init_uV >= 0) {
648                 ret = max77663_regulator_do_set_voltage(reg, pdata->init_uV,
649                                                         pdata->init_uV);
650                 if (ret < 0) {
651                         dev_err(reg->dev, "preinit: Failed to set voltage to "
652                                 "%d\n", pdata->init_uV);
653                         return ret;
654                 }
655         }
656
657         if (pdata->init_enable)
658                 val = POWER_MODE_NORMAL;
659         else
660                 val = POWER_MODE_DISABLE;
661
662         ret = max77663_regulator_set_power_mode(reg, val);
663         if (ret < 0) {
664                 dev_err(reg->dev,
665                         "preinit: Failed to set power mode to %d\n", val);
666                 return ret;
667         }
668
669 skip_init_apply:
670         if (reg->type == REGULATOR_TYPE_SD) {
671                 val = 0;
672                 mask = 0;
673
674                 if (pdata->flags & SD_SLEW_RATE_MASK) {
675                         mask |= SD_SR_MASK;
676                         if (pdata->flags & SD_SLEW_RATE_SLOWEST)
677                                 val |= (SD_SR_13_75 << SD_SR_SHIFT);
678                         else if (pdata->flags & SD_SLEW_RATE_SLOW)
679                                 val |= (SD_SR_27_5 << SD_SR_SHIFT);
680                         else if (pdata->flags & SD_SLEW_RATE_FAST)
681                                 val |= (SD_SR_55 << SD_SR_SHIFT);
682                         else
683                                 val |= (SD_SR_100 << SD_SR_SHIFT);
684                 }
685
686                 if (pdata->flags & SD_FORCED_PWM_MODE) {
687                         mask |= SD_FPWM_MASK;
688                         val |= SD_FPWM_MASK;
689                 }
690
691                 if (pdata->flags & SD_FSRADE_DISABLE) {
692                         mask |= SD_FSRADE_MASK;
693                         val |= SD_FSRADE_MASK;
694                 }
695
696                 ret = max77663_regulator_cache_write(reg,
697                                 reg->regs[CFG_REG].addr, mask, val,
698                                 &reg->regs[CFG_REG].val);
699                 if (ret < 0) {
700                         dev_err(reg->dev, "preinit: "
701                                 "Failed to set register 0x%x\n",
702                                 reg->regs[CFG_REG].addr);
703                         return ret;
704                 }
705
706                 if ((reg->id == MAX77663_REGULATOR_ID_SD0)
707                                 && (pdata->flags & EN2_CTRL_SD0)) {
708                         val = POWER_MODE_DISABLE;
709                         ret = max77663_regulator_set_power_mode(reg, val);
710                         if (ret < 0) {
711                                 dev_err(reg->dev, "preinit: "
712                                         "Failed to set power mode to %d for "
713                                         "EN2_CTRL_SD0\n", val);
714                                 return ret;
715                         }
716
717                         ret = max77663_regulator_set_fps_src(reg, FPS_SRC_NONE);
718                         if (ret < 0) {
719                                 dev_err(reg->dev, "preinit: "
720                                         "Failed to set FPSSRC to FPS_SRC_NONE "
721                                         "for EN2_CTRL_SD0\n");
722                                 return ret;
723                         }
724                 }
725         }
726
727         return 0;
728 }
729
730 #define REGULATOR_SD(_id, _volt_mask, _fps_reg, _min_uV, _max_uV, _step_uV) \
731         [MAX77663_REGULATOR_ID_##_id] = {                       \
732                 .id = MAX77663_REGULATOR_ID_##_id,              \
733                 .type = REGULATOR_TYPE_SD,                      \
734                 .volt_mask = _volt_mask##_VOLT_MASK,            \
735                 .regs = {                                       \
736                         [VOLT_REG] = {                          \
737                                 .addr = MAX77663_REG_##_id,     \
738                         },                                      \
739                         [CFG_REG] = {                           \
740                                 .addr = MAX77663_REG_##_id##_CFG, \
741                         },                                      \
742                         [FPS_REG] = {                           \
743                                 .addr = MAX77663_REG_FPS_##_fps_reg, \
744                         },                                      \
745                 },                                              \
746                 .min_uV = _min_uV,                              \
747                 .max_uV = _max_uV,                              \
748                 .step_uV = _step_uV,                            \
749                 .regulator_mode = REGULATOR_MODE_NORMAL,        \
750                 .power_mode = POWER_MODE_NORMAL,                \
751                 .power_mode_mask = SD_POWER_MODE_MASK,          \
752                 .power_mode_shift = SD_POWER_MODE_SHIFT,        \
753         }
754
755 #define REGULATOR_LDO(_id, _min_uV, _max_uV, _step_uV)          \
756         [MAX77663_REGULATOR_ID_##_id] = {                       \
757                 .id = MAX77663_REGULATOR_ID_##_id,              \
758                 .type = REGULATOR_TYPE_LDO,                     \
759                 .volt_mask = LDO_VOLT_MASK,                     \
760                 .regs = {                                       \
761                         [VOLT_REG] = {                          \
762                                 .addr = MAX77663_REG_##_id##_CFG, \
763                         },                                      \
764                         [CFG_REG] = {                           \
765                                 .addr = MAX77663_REG_##_id##_CFG2, \
766                         },                                      \
767                         [FPS_REG] = {                           \
768                                 .addr = MAX77663_REG_FPS_##_id, \
769                         },                                      \
770                 },                                              \
771                 .min_uV = _min_uV,                              \
772                 .max_uV = _max_uV,                              \
773                 .step_uV = _step_uV,                            \
774                 .regulator_mode = REGULATOR_MODE_NORMAL,        \
775                 .power_mode = POWER_MODE_NORMAL,                \
776                 .power_mode_mask = LDO_POWER_MODE_MASK,         \
777                 .power_mode_shift = LDO_POWER_MODE_SHIFT,       \
778         }
779
780 static struct max77663_regulator max77663_regs[MAX77663_REGULATOR_ID_NR] = {
781         REGULATOR_SD(SD0,    SDX, SD0,  600000, 3387500, 12500),
782         REGULATOR_SD(DVSSD0, SDX, NONE, 600000, 3387500, 12500),
783         REGULATOR_SD(SD1,    SD1, SD1,  800000, 1587500, 12500),
784         REGULATOR_SD(DVSSD1, SD1, NONE, 800000, 1587500, 12500),
785         REGULATOR_SD(SD2,    SDX, SD2,  600000, 3387500, 12500),
786         REGULATOR_SD(SD3,    SDX, SD3,  600000, 3387500, 12500),
787         REGULATOR_SD(SD4,    SDX, SD4,  600000, 3387500, 12500),
788
789         REGULATOR_LDO(LDO0, 800000, 2350000, 25000),
790         REGULATOR_LDO(LDO1, 800000, 2350000, 25000),
791         REGULATOR_LDO(LDO2, 800000, 3950000, 50000),
792         REGULATOR_LDO(LDO3, 800000, 3950000, 50000),
793         REGULATOR_LDO(LDO4, 800000, 1587500, 12500),
794         REGULATOR_LDO(LDO5, 800000, 3950000, 50000),
795         REGULATOR_LDO(LDO6, 800000, 3950000, 50000),
796         REGULATOR_LDO(LDO7, 800000, 3950000, 50000),
797         REGULATOR_LDO(LDO8, 800000, 3950000, 50000),
798 };
799
800 #define REGULATOR_DESC(_id, _name)                      \
801         [MAX77663_REGULATOR_ID_##_id] = {               \
802                 .name = max77663_rails(_name),          \
803                 .id = MAX77663_REGULATOR_ID_##_id,      \
804                 .ops = &max77663_ldo_ops,               \
805                 .type = REGULATOR_VOLTAGE,              \
806                 .owner = THIS_MODULE,                   \
807         }
808
809 static struct regulator_desc max77663_rdesc[MAX77663_REGULATOR_ID_NR] = {
810         REGULATOR_DESC(SD0, sd0),
811         REGULATOR_DESC(DVSSD0, dvssd0),
812         REGULATOR_DESC(SD1, sd1),
813         REGULATOR_DESC(DVSSD1, dvssd1),
814         REGULATOR_DESC(SD2, sd2),
815         REGULATOR_DESC(SD3, sd3),
816         REGULATOR_DESC(SD4, sd4),
817         REGULATOR_DESC(LDO0, ldo0),
818         REGULATOR_DESC(LDO1, ldo1),
819         REGULATOR_DESC(LDO2, ldo2),
820         REGULATOR_DESC(LDO3, ldo3),
821         REGULATOR_DESC(LDO4, ldo4),
822         REGULATOR_DESC(LDO5, ldo5),
823         REGULATOR_DESC(LDO6, ldo6),
824         REGULATOR_DESC(LDO7, ldo7),
825         REGULATOR_DESC(LDO8, ldo8),
826 };
827
828 static int max77663_regulator_probe(struct platform_device *pdev)
829 {
830         struct regulator_desc *rdesc;
831         struct max77663_regulator *reg;
832         int ret = 0;
833
834         if ((pdev->id < 0) || (pdev->id >= MAX77663_REGULATOR_ID_NR)) {
835                 dev_err(&pdev->dev, "Invalid device id %d\n", pdev->id);
836                 return -ENODEV;
837         }
838
839         rdesc = &max77663_rdesc[pdev->id];
840         reg = &max77663_regs[pdev->id];
841         reg->dev = &pdev->dev;
842         reg->pdata = dev_get_platdata(&pdev->dev);
843
844         dev_dbg(&pdev->dev, "probe: name=%s\n", rdesc->name);
845
846         ret = max77663_regulator_preinit(reg);
847         if (ret) {
848                 dev_err(&pdev->dev, "probe: Failed to preinit regulator %s\n",
849                         rdesc->name);
850                 return ret;
851         }
852
853         reg->rdev = regulator_register(rdesc, &pdev->dev,
854                                        &reg->pdata->init_data, reg);
855         if (IS_ERR(reg->rdev)) {
856                 dev_err(&pdev->dev, "probe: Failed to register regulator %s\n",
857                         rdesc->name);
858                 return PTR_ERR(reg->rdev);
859         }
860
861         return 0;
862 }
863
864 static int max77663_regulator_remove(struct platform_device *pdev)
865 {
866         struct regulator_dev *rdev = platform_get_drvdata(pdev);
867
868         regulator_unregister(rdev);
869         return 0;
870 }
871
872 static struct platform_driver max77663_regulator_driver = {
873         .probe = max77663_regulator_probe,
874         .remove = __devexit_p(max77663_regulator_remove),
875         .driver = {
876                 .name = "max77663-regulator",
877                 .owner = THIS_MODULE,
878         },
879 };
880
881 static int __init max77663_regulator_init(void)
882 {
883         return platform_driver_register(&max77663_regulator_driver);
884 }
885 subsys_initcall(max77663_regulator_init);
886
887 static void __exit max77663_reg_exit(void)
888 {
889         platform_driver_unregister(&max77663_regulator_driver);
890 }
891 module_exit(max77663_reg_exit);
892
893 MODULE_LICENSE("GPL v2");
894 MODULE_DESCRIPTION("max77663 regulator driver");
895 MODULE_VERSION("1.0");