regulator: palma: Disable smps10 boost during suspend
[linux-2.6.git] / drivers / regulator / max77663-regulator.c
1 /*
2  * drivers/regulator/max77663-regulator.c
3  * Maxim LDO and Buck regulators driver
4  *
5  * Copyright 2011-2012 Maxim Integrated Products, Inc.
6  * Copyright (C) 2011-2012 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of the
11  * License, or (at your option) any later version.
12  *
13  */
14
15 #include <linux/err.h>
16 #include <linux/string.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/debugfs.h>
22 #include <linux/uaccess.h>
23 #include <linux/i2c.h>
24 #include <linux/mfd/core.h>
25 #include <linux/mfd/max77663-core.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/max77663-regulator.h>
29
30 /* Regulator types */
31 #define REGULATOR_TYPE_SD               0
32 #define REGULATOR_TYPE_LDO_N            1
33 #define REGULATOR_TYPE_LDO_P            2
34
35 /* SD and LDO Registers */
36 #define MAX77663_REG_SD0                0x16
37 #define MAX77663_REG_SD1                0x17
38 #define MAX77663_REG_SD2                0x18
39 #define MAX77663_REG_SD3                0x19
40 #define MAX77663_REG_SD4                0x1A
41 #define MAX77663_REG_DVSSD0             0x1B
42 #define MAX77663_REG_DVSSD1             0x1C
43 #define MAX77663_REG_SD0_CFG            0x1D
44 #define MAX77663_REG_DVSSD0_CFG         MAX77663_REG_SD0_CFG
45 #define MAX77663_REG_SD1_CFG            0x1E
46 #define MAX77663_REG_DVSSD1_CFG         MAX77663_REG_SD1_CFG
47 #define MAX77663_REG_SD2_CFG            0x1F
48 #define MAX77663_REG_SD3_CFG            0x20
49 #define MAX77663_REG_SD4_CFG            0x21
50 #define MAX77663_REG_LDO0_CFG           0x23
51 #define MAX77663_REG_LDO0_CFG2          0x24
52 #define MAX77663_REG_LDO1_CFG           0x25
53 #define MAX77663_REG_LDO1_CFG2          0x26
54 #define MAX77663_REG_LDO2_CFG           0x27
55 #define MAX77663_REG_LDO2_CFG2          0x28
56 #define MAX77663_REG_LDO3_CFG           0x29
57 #define MAX77663_REG_LDO3_CFG2          0x2A
58 #define MAX77663_REG_LDO4_CFG           0x2B
59 #define MAX77663_REG_LDO4_CFG2          0x2C
60 #define MAX77663_REG_LDO5_CFG           0x2D
61 #define MAX77663_REG_LDO5_CFG2          0x2E
62 #define MAX77663_REG_LDO6_CFG           0x2F
63 #define MAX77663_REG_LDO6_CFG2          0x30
64 #define MAX77663_REG_LDO7_CFG           0x31
65 #define MAX77663_REG_LDO7_CFG2          0x32
66 #define MAX77663_REG_LDO8_CFG           0x33
67 #define MAX77663_REG_LDO8_CFG2          0x34
68 #define MAX77663_REG_LDO_CFG3           0x35
69
70 /* Power Mode */
71 #define POWER_MODE_NORMAL               3
72 #define POWER_MODE_LPM                  2
73 #define POWER_MODE_GLPM                 1
74 #define POWER_MODE_DISABLE              0
75 #define SD_POWER_MODE_MASK              0x30
76 #define SD_POWER_MODE_SHIFT             4
77 #define LDO_POWER_MODE_MASK             0xC0
78 #define LDO_POWER_MODE_SHIFT            6
79
80 /* SD Slew Rate */
81 #define SD_SR_13_75                     0
82 #define SD_SR_27_5                      1
83 #define SD_SR_55                        2
84 #define SD_SR_100                       3
85 #define SD_SR_MASK                      0xC0
86 #define SD_SR_SHIFT                     6
87
88 /* SD Forced PWM Mode */
89 #define SD_FPWM_MASK                    0x04
90 #define SD_FPWM_SHIFT                   2
91
92 /* SD Failling slew rate Active-Discharge Mode */
93 #define SD_FSRADE_MASK                  0x01
94 #define SD_FSRADE_SHIFT         0
95
96 /* LDO Configuration 3 */
97 #define TRACK4_MASK                     0x20
98 #define TRACK4_SHIFT                    5
99
100 /* Voltage */
101 #define SDX_VOLT_MASK                   0xFF
102 #define SD1_VOLT_MASK                   0x3F
103 #define LDO_VOLT_MASK                   0x3F
104
105 /* FPS Registers */
106 #define MAX77663_REG_FPS_CFG0           0x43
107 #define MAX77663_REG_FPS_CFG1           0x44
108 #define MAX77663_REG_FPS_CFG2           0x45
109 #define MAX77663_REG_FPS_LDO0           0x46
110 #define MAX77663_REG_FPS_LDO1           0x47
111 #define MAX77663_REG_FPS_LDO2           0x48
112 #define MAX77663_REG_FPS_LDO3           0x49
113 #define MAX77663_REG_FPS_LDO4           0x4A
114 #define MAX77663_REG_FPS_LDO5           0x4B
115 #define MAX77663_REG_FPS_LDO6           0x4C
116 #define MAX77663_REG_FPS_LDO7           0x4D
117 #define MAX77663_REG_FPS_LDO8           0x4E
118 #define MAX77663_REG_FPS_SD0            0x4F
119 #define MAX77663_REG_FPS_SD1            0x50
120 #define MAX77663_REG_FPS_SD2            0x51
121 #define MAX77663_REG_FPS_SD3            0x52
122 #define MAX77663_REG_FPS_SD4            0x53
123 #define MAX77663_REG_FPS_NONE           0
124
125 #define FPS_TIME_PERIOD_MASK            0x38
126 #define FPS_TIME_PERIOD_SHIFT           3
127 #define FPS_EN_SRC_MASK                 0x06
128 #define FPS_EN_SRC_SHIFT                1
129 #define FPS_SW_EN_MASK                  0x01
130 #define FPS_SW_EN_SHIFT                 0
131 #define FPS_SRC_MASK                    0xC0
132 #define FPS_SRC_SHIFT                   6
133 #define FPS_PU_PERIOD_MASK              0x38
134 #define FPS_PU_PERIOD_SHIFT             3
135 #define FPS_PD_PERIOD_MASK              0x07
136 #define FPS_PD_PERIOD_SHIFT             0
137
138 /* Chip Identification Register */
139 #define MAX77663_REG_CID5               0x5D
140
141 #define CID_DIDM_MASK                   0xF0
142 #define CID_DIDM_SHIFT                  4
143
144 #define SD_SAFE_DOWN_UV                 50000 /* 50mV */
145
146 enum {
147         VOLT_REG = 0,
148         CFG_REG,
149         FPS_REG,
150 };
151
152 struct max77663_register {
153         u8 addr;
154         u8 val;
155 };
156
157 struct max77663_regulator_info {
158         u8 id;
159         u8 type;
160         u32 min_uV;
161         u32 max_uV;
162         u32 step_uV;
163
164         struct max77663_register regs[3]; /* volt, cfg, fps */
165
166         struct regulator_desc desc;
167
168         u8 volt_mask;
169
170         u8 power_mode_mask;
171         u8 power_mode_shift;
172 };
173
174 struct max77663_regulator {
175         struct max77663_regulator_info *rinfo;
176         struct regulator_dev *rdev;
177         struct device *dev;
178         struct max77663_regulator_platform_data *pdata;
179         u32 regulator_mode;
180         u8 power_mode;
181         enum max77663_regulator_fps_src fps_src;
182         u8 val[3]; /* volt, cfg, fps */
183         int safe_down_uV; /* for stable down scaling */
184 };
185
186 #define fps_src_name(fps_src)   \
187         (fps_src == FPS_SRC_0 ? "FPS_SRC_0" :   \
188         fps_src == FPS_SRC_1 ? "FPS_SRC_1" :    \
189         fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
190
191 static int fps_cfg_init;
192 static struct max77663_register fps_cfg_regs[] = {
193         {
194                 .addr = MAX77663_REG_FPS_CFG0,
195         },
196         {
197                 .addr = MAX77663_REG_FPS_CFG1,
198         },
199         {
200                 .addr = MAX77663_REG_FPS_CFG2,
201         },
202 };
203
204 static inline struct max77663_regulator_platform_data
205 *_to_pdata(struct max77663_regulator *reg)
206 {
207         return reg->pdata;
208 }
209
210 static inline struct device *_to_parent(struct max77663_regulator *reg)
211 {
212         return reg->dev->parent;
213 }
214
215 static inline int max77663_regulator_cache_write(struct max77663_regulator *reg,
216                                         u8 addr, u8 mask, u8 val, u8 *cache)
217 {
218         struct device *parent = _to_parent(reg);
219         u8 new_val;
220         int ret;
221
222         new_val = (*cache & ~mask) | (val & mask);
223         if (*cache != new_val) {
224                 ret = max77663_write(parent, addr, &new_val, 1, 0);
225                 if (ret < 0)
226                         return ret;
227
228                 *cache = new_val;
229         }
230         return 0;
231 }
232
233 static int
234 max77663_regulator_set_fps_src(struct max77663_regulator *reg,
235                                enum max77663_regulator_fps_src fps_src)
236 {
237         int ret;
238         struct max77663_regulator_info *rinfo = reg->rinfo;
239
240         if ((rinfo->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE) ||
241                         (reg->fps_src == fps_src))
242                 return 0;
243
244         switch (fps_src) {
245         case FPS_SRC_0:
246         case FPS_SRC_1:
247         case FPS_SRC_2:
248         case FPS_SRC_NONE:
249                 break;
250         case FPS_SRC_DEF:
251                 return 0;
252         default:
253                 return -EINVAL;
254         }
255
256         ret = max77663_regulator_cache_write(reg, rinfo->regs[FPS_REG].addr,
257                                         FPS_SRC_MASK, fps_src << FPS_SRC_SHIFT,
258                                         &reg->val[FPS_REG]);
259         if (ret < 0)
260                 return ret;
261
262         reg->fps_src = fps_src;
263         return 0;
264 }
265
266 static int max77663_regulator_set_fps(struct max77663_regulator *reg)
267 {
268         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
269         struct max77663_regulator_info *rinfo = reg->rinfo;
270         u8 fps_val = 0, fps_mask = 0;
271         int ret = 0;
272
273         if (reg->rinfo->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
274                 return 0;
275
276         if (reg->fps_src == FPS_SRC_NONE)
277                 return 0;
278
279         /* FPS power up period setting */
280         if (pdata->fps_pu_period != FPS_POWER_PERIOD_DEF) {
281                 fps_val |= (pdata->fps_pu_period << FPS_PU_PERIOD_SHIFT);
282                 fps_mask |= FPS_PU_PERIOD_MASK;
283         }
284
285         /* FPS power down period setting */
286         if (pdata->fps_pd_period != FPS_POWER_PERIOD_DEF) {
287                 fps_val |= (pdata->fps_pd_period << FPS_PD_PERIOD_SHIFT);
288                 fps_mask |= FPS_PD_PERIOD_MASK;
289         }
290
291         if (fps_val || fps_mask)
292                 ret = max77663_regulator_cache_write(reg,
293                                         rinfo->regs[FPS_REG].addr, fps_mask,
294                                         fps_val, &reg->val[FPS_REG]);
295
296         return ret;
297 }
298
299 static int
300 max77663_regulator_set_fps_cfg(struct max77663_regulator *reg,
301                                struct max77663_regulator_fps_cfg *fps_cfg)
302 {
303         u8 val, mask;
304
305         if ((fps_cfg->src < FPS_SRC_0) || (fps_cfg->src > FPS_SRC_2))
306                 return -EINVAL;
307
308         val = (fps_cfg->en_src << FPS_EN_SRC_SHIFT);
309         mask = FPS_EN_SRC_MASK;
310
311         if (fps_cfg->time_period != FPS_TIME_PERIOD_DEF) {
312                 val |= (fps_cfg->time_period << FPS_TIME_PERIOD_SHIFT);
313                 mask |= FPS_TIME_PERIOD_MASK;
314         }
315
316         return max77663_regulator_cache_write(reg,
317                                         fps_cfg_regs[fps_cfg->src].addr, mask,
318                                         val, &fps_cfg_regs[fps_cfg->src].val);
319 }
320
321 static int
322 max77663_regulator_set_fps_cfgs(struct max77663_regulator *reg,
323                                 struct max77663_regulator_fps_cfg *fps_cfgs,
324                                 int num_fps_cfgs)
325 {
326         struct device *parent = _to_parent(reg);
327         int i, ret;
328
329         if (fps_cfg_init)
330                 return 0;
331
332         for (i = 0; i <= FPS_SRC_2; i++) {
333                 ret = max77663_read(parent, fps_cfg_regs[i].addr,
334                                     &fps_cfg_regs[i].val, 1, 0);
335                 if (ret < 0)
336                         return ret;
337         }
338
339         for (i = 0; i < num_fps_cfgs; i++) {
340                 ret = max77663_regulator_set_fps_cfg(reg, &fps_cfgs[i]);
341                 if (ret < 0)
342                         return ret;
343         }
344         fps_cfg_init = 1;
345
346         return 0;
347 }
348
349 static int
350 max77663_regulator_set_power_mode(struct max77663_regulator *reg, u8 power_mode)
351 {
352         struct max77663_regulator_info *rinfo = reg->rinfo;
353         u8 mask = rinfo->power_mode_mask;
354         u8 shift = rinfo->power_mode_shift;
355         int ret;
356
357         if (rinfo->type == REGULATOR_TYPE_SD)
358                 ret = max77663_regulator_cache_write(reg,
359                                                      rinfo->regs[CFG_REG].addr,
360                                                      mask, power_mode << shift,
361                                                      &reg->val[CFG_REG]);
362         else
363                 ret = max77663_regulator_cache_write(reg,
364                                                      rinfo->regs[VOLT_REG].addr,
365                                                      mask, power_mode << shift,
366                                                      &reg->val[VOLT_REG]);
367
368         if (ret < 0)
369                 return ret;
370
371         reg->power_mode = power_mode;
372         return ret;
373 }
374
375 static u8 max77663_regulator_get_power_mode(struct max77663_regulator *reg)
376 {
377         struct max77663_regulator_info *rinfo = reg->rinfo;
378         u8 mask = rinfo->power_mode_mask;
379         u8 shift = rinfo->power_mode_shift;
380
381         if (rinfo->type == REGULATOR_TYPE_SD)
382                 reg->power_mode = (reg->val[CFG_REG] & mask) >> shift;
383         else
384                 reg->power_mode = (reg->val[VOLT_REG] & mask) >> shift;
385
386         return reg->power_mode;
387 }
388
389 static int max77663_regulator_do_set_voltage(struct max77663_regulator *reg,
390                                              int min_uV, int max_uV)
391 {
392         struct max77663_regulator_info *rinfo = reg->rinfo;
393         u8 addr = rinfo->regs[VOLT_REG].addr;
394         u8 mask = rinfo->volt_mask;
395         u8 *cache = &reg->val[VOLT_REG];
396         u8 val;
397         int old_uV, new_uV, safe_uV;
398         int i, steps = 1;
399         int ret = 0;
400
401         if (min_uV < rinfo->min_uV || max_uV > rinfo->max_uV)
402                 return -EDOM;
403
404         old_uV = (*cache & mask) * rinfo->step_uV + rinfo->min_uV;
405
406         if ((old_uV > min_uV) && (reg->safe_down_uV >= rinfo->step_uV)) {
407                 steps = DIV_ROUND_UP(old_uV - min_uV, reg->safe_down_uV);
408                 safe_uV = -reg->safe_down_uV;
409         }
410
411         if (steps == 1) {
412                 val = (min_uV - rinfo->min_uV) / rinfo->step_uV;
413                 ret = max77663_regulator_cache_write(reg, addr, mask, val,
414                                                      cache);
415         } else {
416                 for (i = 0; i < steps; i++) {
417                         if (abs(min_uV - old_uV) > abs(safe_uV))
418                                 new_uV = old_uV + safe_uV;
419                         else
420                                 new_uV = min_uV;
421
422                         dev_dbg(&reg->rdev->dev, "do_set_voltage: name=%s, "
423                                 "%d/%d, old_uV=%d, new_uV=%d\n",
424                                 reg->rdev->desc->name, i + 1, steps, old_uV,
425                                 new_uV);
426
427                         val = (new_uV - rinfo->min_uV) / rinfo->step_uV;
428                         ret = max77663_regulator_cache_write(reg, addr, mask,
429                                                              val, cache);
430                         if (ret < 0)
431                                 return ret;
432
433                         old_uV = new_uV;
434                 }
435         }
436
437         return ret;
438 }
439
440 static int max77663_regulator_set_voltage(struct regulator_dev *rdev,
441                                           int min_uV, int max_uV,
442                                           unsigned *selector)
443 {
444         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
445
446         dev_dbg(&rdev->dev, "set_voltage: name=%s, min_uV=%d, max_uV=%d\n",
447                 rdev->desc->name, min_uV, max_uV);
448         return max77663_regulator_do_set_voltage(reg, min_uV, max_uV);
449 }
450
451 static int max77663_regulator_get_voltage(struct regulator_dev *rdev)
452 {
453         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
454         struct max77663_regulator_info *rinfo = reg->rinfo;
455         int volt;
456
457         volt = (reg->val[VOLT_REG] & rinfo->volt_mask)
458                 * rinfo->step_uV + rinfo->min_uV;
459
460         dev_dbg(&rdev->dev, "get_voltage: name=%s, volt=%d, val=0x%02x\n",
461                 rdev->desc->name, volt, reg->val[VOLT_REG]);
462         return volt;
463 }
464
465 static int max77663_regulator_enable(struct regulator_dev *rdev)
466 {
467         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
468         struct max77663_regulator_info *rinfo = reg->rinfo;
469         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
470         int power_mode = (pdata->flags & GLPM_ENABLE) ?
471                          POWER_MODE_GLPM : POWER_MODE_NORMAL;
472
473         if (reg->fps_src != FPS_SRC_NONE) {
474                 dev_dbg(&rdev->dev, "enable: Regulator %s using %s\n",
475                         rdev->desc->name, fps_src_name(reg->fps_src));
476                 return 0;
477         }
478
479         if ((rinfo->id == MAX77663_REGULATOR_ID_SD0)
480                         && (pdata->flags & EN2_CTRL_SD0)) {
481                 dev_dbg(&rdev->dev,
482                         "enable: Regulator %s is controlled by EN2\n",
483                         rdev->desc->name);
484                 return 0;
485         }
486
487         /* N-Channel LDOs don't support Low-Power mode. */
488         if ((rinfo->type != REGULATOR_TYPE_LDO_N) &&
489                         (reg->regulator_mode == REGULATOR_MODE_STANDBY))
490                 power_mode = POWER_MODE_LPM;
491
492         return max77663_regulator_set_power_mode(reg, power_mode);
493 }
494
495 static int max77663_regulator_disable(struct regulator_dev *rdev)
496 {
497         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
498         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
499         struct max77663_regulator_info *rinfo = reg->rinfo;
500         int power_mode = POWER_MODE_DISABLE;
501
502         if (reg->fps_src != FPS_SRC_NONE) {
503                 dev_dbg(&rdev->dev, "disable: Regulator %s using %s\n",
504                         rdev->desc->name, fps_src_name(reg->fps_src));
505                 return 0;
506         }
507
508         if ((rinfo->id == MAX77663_REGULATOR_ID_SD0)
509                         && (pdata->flags & EN2_CTRL_SD0)) {
510                 dev_dbg(&rdev->dev,
511                         "disable: Regulator %s is controlled by EN2\n",
512                         rdev->desc->name);
513                 return 0;
514         }
515
516         return max77663_regulator_set_power_mode(reg, power_mode);
517 }
518
519 static int max77663_regulator_is_enabled(struct regulator_dev *rdev)
520 {
521         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
522         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
523         struct max77663_regulator_info *rinfo = reg->rinfo;
524         int ret = 1;
525
526         if (reg->fps_src != FPS_SRC_NONE) {
527                 dev_dbg(&rdev->dev, "is_enable: Regulator %s using %s\n",
528                         rdev->desc->name, fps_src_name(reg->fps_src));
529                 return 1;
530         }
531
532         if ((rinfo->id == MAX77663_REGULATOR_ID_SD0)
533                         && (pdata->flags & EN2_CTRL_SD0)) {
534                 dev_dbg(&rdev->dev,
535                         "is_enable: Regulator %s is controlled by EN2\n",
536                         rdev->desc->name);
537                 return 1;
538         }
539
540         if (max77663_regulator_get_power_mode(reg) == POWER_MODE_DISABLE)
541                 ret = 0;
542
543         return ret;
544 }
545
546 static int max77663_regulator_set_mode(struct regulator_dev *rdev,
547                                        unsigned int mode)
548 {
549         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
550         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
551         struct max77663_regulator_info *rinfo = reg->rinfo;
552         u8 power_mode;
553         int ret;
554
555         if (mode == REGULATOR_MODE_NORMAL)
556                 power_mode = (pdata->flags & GLPM_ENABLE) ?
557                              POWER_MODE_GLPM : POWER_MODE_NORMAL;
558         else if (mode == REGULATOR_MODE_STANDBY) {
559                 /* N-Channel LDOs don't support Low-Power mode. */
560                 power_mode = (rinfo->type != REGULATOR_TYPE_LDO_N) ?
561                              POWER_MODE_LPM : POWER_MODE_NORMAL;
562         } else
563                 return -EINVAL;
564
565         ret = max77663_regulator_set_power_mode(reg, power_mode);
566         if (!ret)
567                 reg->regulator_mode = mode;
568
569         return ret;
570 }
571
572 static unsigned int max77663_regulator_get_mode(struct regulator_dev *rdev)
573 {
574         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
575
576         return reg->regulator_mode;
577 }
578
579 static struct regulator_ops max77663_ldo_ops = {
580         .set_voltage = max77663_regulator_set_voltage,
581         .get_voltage = max77663_regulator_get_voltage,
582         .enable = max77663_regulator_enable,
583         .disable = max77663_regulator_disable,
584         .is_enabled = max77663_regulator_is_enabled,
585         .set_mode = max77663_regulator_set_mode,
586         .get_mode = max77663_regulator_get_mode,
587 };
588
589 static int max77663_regulator_preinit(struct max77663_regulator *reg)
590 {
591         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
592         struct max77663_regulator_info *rinfo = reg->rinfo;
593         struct device *parent = _to_parent(reg);
594         int i;
595         u8 val, mask;
596         int ret;
597
598         /* Update registers */
599         for (i = 0; i <= FPS_REG; i++) {
600                 ret = max77663_read(parent, rinfo->regs[i].addr,
601                                     &reg->val[i], 1, 0);
602                 if (ret < 0) {
603                         dev_err(reg->dev,
604                                 "preinit: Failed to get register 0x%x\n",
605                                 rinfo->regs[i].addr);
606                         return ret;
607                 }
608         }
609
610         /* Update FPS source */
611         if (rinfo->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
612                 reg->fps_src = FPS_SRC_NONE;
613         else
614                 reg->fps_src = (reg->val[FPS_REG] & FPS_SRC_MASK)
615                                 >> FPS_SRC_SHIFT;
616
617         dev_dbg(reg->dev, "preinit: initial fps_src=%s\n",
618                 fps_src_name(reg->fps_src));
619
620         /* Update power mode */
621         max77663_regulator_get_power_mode(reg);
622
623         /* Check Chip Identification */
624         ret = max77663_read(parent, MAX77663_REG_CID5, &val, 1, 0);
625         if (ret < 0) {
626                 dev_err(reg->dev, "preinit: Failed to get register 0x%x\n",
627                         MAX77663_REG_CID5);
628                 return ret;
629         }
630
631         /* If metal revision is less than rev.3,
632          * set safe_down_uV for stable down scaling. */
633         if ((rinfo->type == REGULATOR_TYPE_SD) &&
634                         ((val & CID_DIDM_MASK) >> CID_DIDM_SHIFT) <= 2)
635                 reg->safe_down_uV = SD_SAFE_DOWN_UV;
636         else
637                 reg->safe_down_uV = 0;
638
639         /* Set FPS */
640         ret = max77663_regulator_set_fps_cfgs(reg, pdata->fps_cfgs,
641                                               pdata->num_fps_cfgs);
642         if (ret < 0) {
643                 dev_err(reg->dev, "preinit: Failed to set FPSCFG\n");
644                 return ret;
645         }
646
647         /* N-Channel LDOs don't support Low-Power mode. */
648         if ((rinfo->type == REGULATOR_TYPE_LDO_N) &&
649                         (pdata->flags & GLPM_ENABLE))
650                 pdata->flags &= ~GLPM_ENABLE;
651
652         /* To prevent power rail turn-off when change FPS source,
653          * it must set power mode to NORMAL before change FPS source to NONE
654          * from SRC_0, SRC_1 and SRC_2. */
655         if ((reg->fps_src != FPS_SRC_NONE) && (pdata->fps_src == FPS_SRC_NONE)
656                         && (reg->power_mode != POWER_MODE_NORMAL)) {
657                 val = (pdata->flags & GLPM_ENABLE) ?
658                       POWER_MODE_GLPM : POWER_MODE_NORMAL;
659                 ret = max77663_regulator_set_power_mode(reg, val);
660                 if (ret < 0) {
661                         dev_err(reg->dev, "preinit: Failed to "
662                                 "set power mode to POWER_MODE_NORMAL\n");
663                         return ret;
664                 }
665         }
666
667         ret = max77663_regulator_set_fps_src(reg, pdata->fps_src);
668         if (ret < 0) {
669                 dev_err(reg->dev, "preinit: Failed to set FPSSRC to %d\n",
670                         pdata->fps_src);
671                 return ret;
672         }
673
674         ret = max77663_regulator_set_fps(reg);
675         if (ret < 0) {
676                 dev_err(reg->dev, "preinit: Failed to set FPS\n");
677                 return ret;
678         }
679
680         if (rinfo->type == REGULATOR_TYPE_SD) {
681                 val = 0;
682                 mask = 0;
683
684                 if (pdata->flags & SD_SLEW_RATE_MASK) {
685                         mask |= SD_SR_MASK;
686                         if (pdata->flags & SD_SLEW_RATE_SLOWEST)
687                                 val |= (SD_SR_13_75 << SD_SR_SHIFT);
688                         else if (pdata->flags & SD_SLEW_RATE_SLOW)
689                                 val |= (SD_SR_27_5 << SD_SR_SHIFT);
690                         else if (pdata->flags & SD_SLEW_RATE_FAST)
691                                 val |= (SD_SR_55 << SD_SR_SHIFT);
692                         else
693                                 val |= (SD_SR_100 << SD_SR_SHIFT);
694                 }
695
696                 mask |= SD_FPWM_MASK;
697                 if (pdata->flags & SD_FORCED_PWM_MODE)
698                         val |= SD_FPWM_MASK;
699
700                 mask |= SD_FSRADE_MASK;
701                 if (pdata->flags & SD_FSRADE_DISABLE)
702                         val |= SD_FSRADE_MASK;
703
704                 ret = max77663_regulator_cache_write(reg,
705                                 rinfo->regs[CFG_REG].addr, mask, val,
706                                 &reg->val[CFG_REG]);
707                 if (ret < 0) {
708                         dev_err(reg->dev, "preinit: "
709                                 "Failed to set register 0x%x\n",
710                                 rinfo->regs[CFG_REG].addr);
711                         return ret;
712                 }
713
714                 if ((rinfo->id == MAX77663_REGULATOR_ID_SD0)
715                                 && (pdata->flags & EN2_CTRL_SD0)) {
716                         val = POWER_MODE_DISABLE;
717                         ret = max77663_regulator_set_power_mode(reg, val);
718                         if (ret < 0) {
719                                 dev_err(reg->dev, "preinit: "
720                                         "Failed to set power mode to %d for "
721                                         "EN2_CTRL_SD0\n", val);
722                                 return ret;
723                         }
724
725                         ret = max77663_regulator_set_fps_src(reg, FPS_SRC_NONE);
726                         if (ret < 0) {
727                                 dev_err(reg->dev, "preinit: "
728                                         "Failed to set FPSSRC to FPS_SRC_NONE "
729                                         "for EN2_CTRL_SD0\n");
730                                 return ret;
731                         }
732                 }
733         }
734
735         if ((rinfo->id == MAX77663_REGULATOR_ID_LDO4)
736                         && (pdata->flags & LDO4_EN_TRACKING)) {
737                 val = TRACK4_MASK;
738                 ret = max77663_write(parent, MAX77663_REG_LDO_CFG3, &val, 1, 0);
739                 if (ret < 0) {
740                         dev_err(reg->dev, "preinit: "
741                                 "Failed to set register 0x%x\n",
742                                 MAX77663_REG_LDO_CFG3);
743                         return ret;
744                 }
745         }
746
747         return 0;
748 }
749
750 #define REGULATOR_SD(_id, _volt_mask, _fps_reg, _min_uV, _max_uV, _step_uV) \
751         [MAX77663_REGULATOR_ID_##_id] = {                       \
752                 .id = MAX77663_REGULATOR_ID_##_id,              \
753                 .type = REGULATOR_TYPE_SD,                      \
754                 .volt_mask = _volt_mask##_VOLT_MASK,            \
755                 .regs = {                                       \
756                         [VOLT_REG] = {                          \
757                                 .addr = MAX77663_REG_##_id,     \
758                         },                                      \
759                         [CFG_REG] = {                           \
760                                 .addr = MAX77663_REG_##_id##_CFG, \
761                         },                                      \
762                         [FPS_REG] = {                           \
763                                 .addr = MAX77663_REG_FPS_##_fps_reg, \
764                         },                                      \
765                 },                                              \
766                 .min_uV = _min_uV,                              \
767                 .max_uV = _max_uV,                              \
768                 .step_uV = _step_uV,                            \
769                 .power_mode_mask = SD_POWER_MODE_MASK,          \
770                 .power_mode_shift = SD_POWER_MODE_SHIFT,        \
771                 .desc = {                                       \
772                         .name = max77663_rails(_id),            \
773                         .id = MAX77663_REGULATOR_ID_##_id,      \
774                         .ops = &max77663_ldo_ops,               \
775                         .type = REGULATOR_VOLTAGE,              \
776                         .owner = THIS_MODULE,                   \
777                 },                                              \
778         }
779
780 #define REGULATOR_LDO(_id, _type, _min_uV, _max_uV, _step_uV)   \
781         [MAX77663_REGULATOR_ID_##_id] = {                       \
782                 .id = MAX77663_REGULATOR_ID_##_id,              \
783                 .type = REGULATOR_TYPE_LDO_##_type,             \
784                 .volt_mask = LDO_VOLT_MASK,                     \
785                 .regs = {                                       \
786                         [VOLT_REG] = {                          \
787                                 .addr = MAX77663_REG_##_id##_CFG, \
788                         },                                      \
789                         [CFG_REG] = {                           \
790                                 .addr = MAX77663_REG_##_id##_CFG2, \
791                         },                                      \
792                         [FPS_REG] = {                           \
793                                 .addr = MAX77663_REG_FPS_##_id, \
794                         },                                      \
795                 },                                              \
796                 .min_uV = _min_uV,                              \
797                 .max_uV = _max_uV,                              \
798                 .step_uV = _step_uV,                            \
799                 .power_mode_mask = LDO_POWER_MODE_MASK,         \
800                 .power_mode_shift = LDO_POWER_MODE_SHIFT,       \
801                 .desc = {                                       \
802                         .name = max77663_rails(_id),            \
803                         .id = MAX77663_REGULATOR_ID_##_id,      \
804                         .ops = &max77663_ldo_ops,               \
805                         .type = REGULATOR_VOLTAGE,              \
806                         .owner = THIS_MODULE,                   \
807                 },                                              \
808         }
809
810 static struct max77663_regulator_info max77663_regs_info[MAX77663_REGULATOR_ID_NR] = {
811         REGULATOR_SD(SD0,    SDX, SD0,  600000, 3387500, 12500),
812         REGULATOR_SD(DVSSD0, SDX, NONE, 600000, 3387500, 12500),
813         REGULATOR_SD(SD1,    SD1, SD1,  800000, 1587500, 12500),
814         REGULATOR_SD(DVSSD1, SD1, NONE, 800000, 1587500, 12500),
815         REGULATOR_SD(SD2,    SDX, SD2,  600000, 3387500, 12500),
816         REGULATOR_SD(SD3,    SDX, SD3,  600000, 3387500, 12500),
817         REGULATOR_SD(SD4,    SDX, SD4,  600000, 3387500, 12500),
818
819         REGULATOR_LDO(LDO0, N, 800000, 2350000, 25000),
820         REGULATOR_LDO(LDO1, N, 800000, 2350000, 25000),
821         REGULATOR_LDO(LDO2, P, 800000, 3950000, 50000),
822         REGULATOR_LDO(LDO3, P, 800000, 3950000, 50000),
823         REGULATOR_LDO(LDO4, P, 800000, 1587500, 12500),
824         REGULATOR_LDO(LDO5, P, 800000, 3950000, 50000),
825         REGULATOR_LDO(LDO6, P, 800000, 3950000, 50000),
826         REGULATOR_LDO(LDO7, N, 800000, 3950000, 50000),
827         REGULATOR_LDO(LDO8, N, 800000, 3950000, 50000),
828 };
829
830 static int max77663_regulator_probe(struct platform_device *pdev)
831 {
832         struct max77663_platform_data *pdata =
833                                         dev_get_platdata(pdev->dev.parent);
834         struct regulator_desc *rdesc;
835         struct max77663_regulator *reg;
836         struct max77663_regulator *max_regs;
837         struct max77663_regulator_platform_data *reg_pdata;
838         int ret = 0;
839         int id;
840         int reg_id;
841         int reg_count;
842
843         if (!pdata) {
844                 dev_err(&pdev->dev, "No Platform data\n");
845                 return -ENODEV;
846         }
847
848         reg_count = pdata->num_regulator_pdata;
849         max_regs = devm_kzalloc(&pdev->dev,
850                         reg_count * sizeof(*max_regs), GFP_KERNEL);
851         if (!max_regs) {
852                 dev_err(&pdev->dev, "mem alloc for reg failed\n");
853                 return -ENOMEM;
854         }
855
856         for (id = 0; id < reg_count; ++id) {
857                 reg_pdata = pdata->regulator_pdata[id];
858                 if (!reg_pdata) {
859                         dev_err(&pdev->dev,
860                                 "Regulator pltform data not there\n");
861                         goto clean_exit;
862                 }
863
864                 reg_id = reg_pdata->id;
865                 reg  = &max_regs[id];
866                 rdesc = &max77663_regs_info[reg_id].desc;
867                 reg->rinfo = &max77663_regs_info[reg_id];
868                 reg->dev = &pdev->dev;
869                 reg->pdata = reg_pdata;
870                 reg->regulator_mode = REGULATOR_MODE_NORMAL;
871                 reg->power_mode = POWER_MODE_NORMAL;
872
873                 dev_dbg(&pdev->dev, "probe: name=%s\n", rdesc->name);
874
875                 ret = max77663_regulator_preinit(reg);
876                 if (ret) {
877                         dev_err(&pdev->dev, "Failed to preinit regulator %s\n",
878                                 rdesc->name);
879                         goto clean_exit;
880                 }
881
882                 reg->rdev = regulator_register(rdesc, &pdev->dev,
883                                         reg->pdata->reg_init_data, reg, NULL);
884                 if (IS_ERR(reg->rdev)) {
885                         dev_err(&pdev->dev, "Failed to register regulator %s\n",
886                         rdesc->name);
887                         ret = PTR_ERR(reg->rdev);
888                         goto clean_exit;
889                 }
890         }
891         platform_set_drvdata(pdev, max_regs);
892
893         return 0;
894
895 clean_exit:
896         while (--id >= 0) {
897                 reg  = &max_regs[id];
898                 regulator_unregister(reg->rdev);
899         }
900         return ret;
901 }
902
903 static int max77663_regulator_remove(struct platform_device *pdev)
904 {
905         struct max77663_regulator *max_regs = platform_get_drvdata(pdev);
906         struct max77663_regulator *reg;
907         struct max77663_platform_data *pdata =
908                                         dev_get_platdata(pdev->dev.parent);
909         int reg_count;
910
911         if (!pdata)
912                 return 0;
913
914         reg_count = pdata->num_regulator_pdata;
915         while (--reg_count >= 0) {
916                 reg  = &max_regs[reg_count];
917                 regulator_unregister(reg->rdev);
918         }
919
920         return 0;
921 }
922
923 static struct platform_driver max77663_regulator_driver = {
924         .probe = max77663_regulator_probe,
925         .remove = __devexit_p(max77663_regulator_remove),
926         .driver = {
927                 .name = "max77663-pmic",
928                 .owner = THIS_MODULE,
929         },
930 };
931
932 static int __init max77663_regulator_init(void)
933 {
934         return platform_driver_register(&max77663_regulator_driver);
935 }
936 subsys_initcall(max77663_regulator_init);
937
938 static void __exit max77663_reg_exit(void)
939 {
940         platform_driver_unregister(&max77663_regulator_driver);
941 }
942 module_exit(max77663_reg_exit);
943
944 MODULE_LICENSE("GPL v2");
945 MODULE_DESCRIPTION("max77663 regulator driver");
946 MODULE_VERSION("1.0");