b2fe962b0887203ff629017ffbc327417d23b1e8
[linux-2.6.git] / drivers / regulator / max77663-regulator.c
1 /*
2  * drivers/regulator/max77663-regulator.c
3  * Maxim LDO and Buck regulators driver
4  *
5  * Copyright 2011 Maxim Integrated Products, Inc.
6  * Copyright (C) 2011 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of the
11  * License, or (at your option) any later version.
12  *
13  */
14
15 #include <linux/err.h>
16 #include <linux/string.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/debugfs.h>
22 #include <linux/uaccess.h>
23 #include <linux/i2c.h>
24 #include <linux/mfd/max77663-core.h>
25 #include <linux/regulator/driver.h>
26 #include <linux/regulator/machine.h>
27 #include <linux/regulator/max77663-regulator.h>
28
29 /* Regulator types */
30 #define REGULATOR_TYPE_SD               0
31 #define REGULATOR_TYPE_LDO              1
32
33 /* SD and LDO Registers */
34 #define MAX77663_REG_SD0                0x16
35 #define MAX77663_REG_SD1                0x17
36 #define MAX77663_REG_SD2                0x18
37 #define MAX77663_REG_SD3                0x19
38 #define MAX77663_REG_SD4                0x1A
39 #define MAX77663_REG_DVSSD0             0x1B
40 #define MAX77663_REG_DVSSD1             0x1C
41 #define MAX77663_REG_SD0_CFG            0x1D
42 #define MAX77663_REG_DVSSD0_CFG         MAX77663_REG_SD0_CFG
43 #define MAX77663_REG_SD1_CFG            0x1E
44 #define MAX77663_REG_DVSSD1_CFG         MAX77663_REG_SD1_CFG
45 #define MAX77663_REG_SD2_CFG            0x1F
46 #define MAX77663_REG_SD3_CFG            0x20
47 #define MAX77663_REG_SD4_CFG            0x21
48 #define MAX77663_REG_LDO0_CFG           0x23
49 #define MAX77663_REG_LDO0_CFG2          0x24
50 #define MAX77663_REG_LDO1_CFG           0x25
51 #define MAX77663_REG_LDO1_CFG2          0x26
52 #define MAX77663_REG_LDO2_CFG           0x27
53 #define MAX77663_REG_LDO2_CFG2          0x28
54 #define MAX77663_REG_LDO3_CFG           0x29
55 #define MAX77663_REG_LDO3_CFG2          0x2A
56 #define MAX77663_REG_LDO4_CFG           0x2B
57 #define MAX77663_REG_LDO4_CFG2          0x2C
58 #define MAX77663_REG_LDO5_CFG           0x2D
59 #define MAX77663_REG_LDO5_CFG2          0x2E
60 #define MAX77663_REG_LDO6_CFG           0x2F
61 #define MAX77663_REG_LDO6_CFG2          0x30
62 #define MAX77663_REG_LDO7_CFG           0x31
63 #define MAX77663_REG_LDO7_CFG2          0x32
64 #define MAX77663_REG_LDO8_CFG           0x33
65 #define MAX77663_REG_LDO8_CFG2          0x34
66
67 /* Power Mode */
68 #define POWER_MODE_NORMAL               3
69 #define POWER_MODE_LPM                  2
70 #define POWER_MODE_GLPM                 1
71 #define POWER_MODE_DISABLE              0
72 #define SD_POWER_MODE_MASK              0x30
73 #define SD_POWER_MODE_SHIFT             4
74 #define LDO_POWER_MODE_MASK             0xC0
75 #define LDO_POWER_MODE_SHIFT            6
76
77 /* SD Slew Rate */
78 #define SD_SR_13_75                     0
79 #define SD_SR_27_5                      1
80 #define SD_SR_55                        2
81 #define SD_SR_100                       3
82 #define SD_SR_MASK                      0xC0
83 #define SD_SR_SHIFT                     6
84
85 /* SD Forced PWM Mode */
86 #define SD_FPWM_MASK                    0x04
87 #define SD_FPWM_SHIFT                   2
88
89 /* SD Failling slew rate Active-Discharge Mode */
90 #define SD_FSRADE_MASK                  0x01
91 #define SD_FSRADE_SHIFT         0
92
93 /* Voltage */
94 #define SDX_VOLT_MASK                   0xFF
95 #define SD1_VOLT_MASK                   0x3F
96 #define LDO_VOLT_MASK                   0x3F
97
98 /* FPS Registers */
99 #define MAX77663_REG_FPS_CFG0           0x43
100 #define MAX77663_REG_FPS_CFG1           0x44
101 #define MAX77663_REG_FPS_CFG2           0x45
102 #define MAX77663_REG_FPS_LDO0           0x46
103 #define MAX77663_REG_FPS_LDO1           0x47
104 #define MAX77663_REG_FPS_LDO2           0x48
105 #define MAX77663_REG_FPS_LDO3           0x49
106 #define MAX77663_REG_FPS_LDO4           0x4A
107 #define MAX77663_REG_FPS_LDO5           0x4B
108 #define MAX77663_REG_FPS_LDO6           0x4C
109 #define MAX77663_REG_FPS_LDO7           0x4D
110 #define MAX77663_REG_FPS_LDO8           0x4E
111 #define MAX77663_REG_FPS_SD0            0x4F
112 #define MAX77663_REG_FPS_SD1            0x50
113 #define MAX77663_REG_FPS_SD2            0x51
114 #define MAX77663_REG_FPS_SD3            0x52
115 #define MAX77663_REG_FPS_SD4            0x53
116 #define MAX77663_REG_FPS_NONE           0
117
118 #define FPS_TIME_PERIOD_MASK            0x38
119 #define FPS_TIME_PERIOD_SHIFT           3
120 #define FPS_EN_SRC_MASK                 0x06
121 #define FPS_EN_SRC_SHIFT                1
122 #define FPS_SW_EN_MASK                  0x01
123 #define FPS_SW_EN_SHIFT                 0
124 #define FPS_SRC_MASK                    0xC0
125 #define FPS_SRC_SHIFT                   6
126 #define FPS_PU_PERIOD_MASK              0x38
127 #define FPS_PU_PERIOD_SHIFT             3
128 #define FPS_PD_PERIOD_MASK              0x07
129 #define FPS_PD_PERIOD_SHIFT             0
130
131 enum {
132         VOLT_REG = 0,
133         CFG_REG,
134         FPS_REG,
135 };
136
137 struct max77663_register {
138         u8 addr;
139         u8 val;
140 };
141
142 struct max77663_regulator {
143         struct regulator_dev *rdev;
144         struct device *dev;
145
146         u8 id;
147         u8 type;
148         u32 min_uV;
149         u32 max_uV;
150         u32 step_uV;
151         u32 regulator_mode;
152
153         struct max77663_register regs[3]; /* volt, cfg, fps */
154         enum max77663_regulator_fps_src fps_src;
155
156         u8 volt_mask;
157
158         u8 power_mode;
159         u8 power_mode_mask;
160         u8 power_mode_shift;
161 };
162
163 #define fps_src_name(fps_src)   \
164         (fps_src == FPS_SRC_0 ? "FPS_SRC_0" :   \
165         fps_src == FPS_SRC_1 ? "FPS_SRC_1" :    \
166         fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
167
168 static int fps_cfg_init;
169 static struct max77663_register fps_cfg_regs[] = {
170         {
171                 .addr = MAX77663_REG_FPS_CFG0,
172         },
173         {
174                 .addr = MAX77663_REG_FPS_CFG1,
175         },
176         {
177                 .addr = MAX77663_REG_FPS_CFG2,
178         },
179 };
180
181 static inline struct max77663_regulator_platform_data
182 *_to_pdata(struct max77663_regulator *reg)
183 {
184         return reg->dev->platform_data;
185 }
186
187 static inline struct device *_to_parent(struct max77663_regulator *reg)
188 {
189         return reg->dev->parent;
190 }
191
192 static inline int max77663_regulator_cache_write(struct max77663_regulator *reg,
193                                         u8 addr, u8 mask, u8 val, u8 *cache)
194 {
195         struct device *parent = _to_parent(reg);
196         u8 new_val;
197         int ret;
198
199         new_val = (*cache & ~mask) | (val & mask);
200         if (*cache != new_val) {
201                 ret = max77663_write(parent, addr, &new_val, 1, 0);
202                 if (ret < 0)
203                         return ret;
204
205                 *cache = new_val;
206         }
207         return 0;
208 }
209
210 static int
211 max77663_regulator_set_fps_src(struct max77663_regulator *reg,
212                                enum max77663_regulator_fps_src fps_src)
213 {
214         int ret;
215
216         if (reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
217                 return 0;
218
219         switch (fps_src) {
220         case FPS_SRC_0:
221         case FPS_SRC_1:
222         case FPS_SRC_2:
223         case FPS_SRC_NONE:
224                 break;
225         case FPS_SRC_DEF:
226                 return 0;
227         default:
228                 return -EINVAL;
229         }
230
231         ret = max77663_regulator_cache_write(reg, reg->regs[FPS_REG].addr,
232                                         FPS_SRC_MASK, fps_src << FPS_SRC_SHIFT,
233                                         &reg->regs[FPS_REG].val);
234         if (ret < 0)
235                 return ret;
236
237         reg->fps_src = fps_src;
238         return 0;
239 }
240
241 static int max77663_regulator_set_fps(struct max77663_regulator *reg)
242 {
243         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
244         u8 fps_val = 0, fps_mask = 0;
245         int ret = 0;
246
247         if (reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
248                 return 0;
249
250         if (reg->fps_src == FPS_SRC_NONE)
251                 return 0;
252
253         /* FPS power up period setting */
254         if (pdata->fps_pu_period != FPS_POWER_PERIOD_DEF) {
255                 fps_val |= (pdata->fps_pu_period << FPS_PU_PERIOD_SHIFT);
256                 fps_mask |= FPS_PU_PERIOD_MASK;
257         }
258
259         /* FPS power down period setting */
260         if (pdata->fps_pd_period != FPS_POWER_PERIOD_DEF) {
261                 fps_val |= (pdata->fps_pd_period << FPS_PD_PERIOD_SHIFT);
262                 fps_mask |= FPS_PD_PERIOD_MASK;
263         }
264
265         if (fps_val)
266                 ret = max77663_regulator_cache_write(reg,
267                                         reg->regs[FPS_REG].addr, fps_mask,
268                                         fps_val, &reg->regs[FPS_REG].val);
269
270         return ret;
271 }
272
273 static int
274 max77663_regulator_set_fps_cfg(struct max77663_regulator *reg,
275                                struct max77663_regulator_fps_cfg *fps_cfg)
276 {
277         u8 val, mask;
278
279         if ((fps_cfg->src < FPS_SRC_0) || (fps_cfg->src > FPS_SRC_2))
280                 return -EINVAL;
281
282         val = (fps_cfg->en_src << FPS_EN_SRC_SHIFT);
283         mask = FPS_EN_SRC_MASK;
284
285         if (fps_cfg->time_period != FPS_TIME_PERIOD_DEF) {
286                 val |= (fps_cfg->time_period << FPS_TIME_PERIOD_SHIFT);
287                 mask |= FPS_TIME_PERIOD_MASK;
288         }
289
290         return max77663_regulator_cache_write(reg,
291                                         fps_cfg_regs[fps_cfg->src].addr, mask,
292                                         val, &fps_cfg_regs[fps_cfg->src].val);
293 }
294
295 static int
296 max77663_regulator_set_fps_cfgs(struct max77663_regulator *reg,
297                                 struct max77663_regulator_fps_cfg *fps_cfgs,
298                                 int num_fps_cfgs)
299 {
300         int i, ret;
301
302         if (fps_cfg_init)
303                 return 0;
304
305         for (i = 0; i < num_fps_cfgs; i++) {
306                 ret = max77663_regulator_set_fps_cfg(reg, &fps_cfgs[i]);
307                 if (ret < 0)
308                         return ret;
309         }
310         fps_cfg_init = 1;
311
312         return 0;
313 }
314
315 static int
316 max77663_regulator_set_power_mode(struct max77663_regulator *reg, u8 power_mode)
317 {
318         u8 mask = reg->power_mode_mask;
319         u8 shift = reg->power_mode_shift;
320         int ret;
321
322         if (reg->type == REGULATOR_TYPE_SD)
323                 ret = max77663_regulator_cache_write(reg,
324                                                      reg->regs[CFG_REG].addr,
325                                                      mask, power_mode << shift,
326                                                      &reg->regs[CFG_REG].val);
327         else
328                 ret = max77663_regulator_cache_write(reg,
329                                                      reg->regs[VOLT_REG].addr,
330                                                      mask, power_mode << shift,
331                                                      &reg->regs[VOLT_REG].val);
332
333         if (ret < 0)
334                 return ret;
335
336         reg->power_mode = power_mode;
337         return ret;
338 }
339
340 static u8 max77663_regulator_get_power_mode(struct max77663_regulator *reg)
341 {
342         u8 mask = reg->power_mode_mask;
343         u8 shift = reg->power_mode_shift;
344
345         if (reg->type == REGULATOR_TYPE_SD)
346                 reg->power_mode = (reg->regs[CFG_REG].val & mask) >> shift;
347         else
348                 reg->power_mode = (reg->regs[VOLT_REG].val & mask) >> shift;
349
350         return reg->power_mode;
351 }
352
353 static int max77663_regulator_do_set_voltage(struct max77663_regulator *reg,
354                                              int min_uV, int max_uV)
355 {
356         u8 val;
357
358         if (min_uV < reg->min_uV || max_uV > reg->max_uV)
359                 return -EDOM;
360
361         val = (min_uV - reg->min_uV) / reg->step_uV;
362         return max77663_regulator_cache_write(reg, reg->regs[VOLT_REG].addr,
363                                 reg->volt_mask, val, &reg->regs[VOLT_REG].val);
364 }
365
366 static int max77663_regulator_set_voltage(struct regulator_dev *rdev,
367                                           int min_uV, int max_uV,
368                                           unsigned *selector)
369 {
370         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
371
372         dev_dbg(&rdev->dev, "set_voltage: name=%s, min_uV=%d, max_uV=%d\n",
373                 rdev->desc->name, min_uV, max_uV);
374         return max77663_regulator_do_set_voltage(reg, min_uV, max_uV);
375 }
376
377 static int max77663_regulator_get_voltage(struct regulator_dev *rdev)
378 {
379         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
380         int volt;
381
382         volt = (reg->regs[VOLT_REG].val & reg->volt_mask)
383                 * reg->step_uV + reg->min_uV;
384
385         dev_dbg(&rdev->dev, "get_voltage: name=%s, volt=%d, val=0x%02x\n",
386                 rdev->desc->name, volt, reg->regs[VOLT_REG].val);
387         return volt;
388 }
389
390 static int max77663_regulator_enable(struct regulator_dev *rdev)
391 {
392         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
393         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
394         int power_mode = POWER_MODE_NORMAL;
395
396         if (reg->fps_src != FPS_SRC_NONE) {
397                 dev_dbg(&rdev->dev, "enable: Regulator %s using %s\n",
398                         rdev->desc->name, fps_src_name(reg->fps_src));
399                 return 0;
400         }
401
402         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
403                         && (pdata->flags & EN2_CTRL_SD0)) {
404                 dev_dbg(&rdev->dev,
405                         "enable: Regulator %s is controlled by EN2\n",
406                         rdev->desc->name);
407                 return 0;
408         }
409
410         if (reg->regulator_mode == REGULATOR_MODE_STANDBY)
411                 power_mode = POWER_MODE_LPM;
412
413         return max77663_regulator_set_power_mode(reg, power_mode);
414 }
415
416 static int max77663_regulator_disable(struct regulator_dev *rdev)
417 {
418         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
419         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
420         int power_mode = POWER_MODE_DISABLE;
421
422         if (reg->fps_src != FPS_SRC_NONE) {
423                 dev_dbg(&rdev->dev, "disable: Regulator %s using %s\n",
424                         rdev->desc->name, fps_src_name(reg->fps_src));
425                 return 0;
426         }
427
428         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
429                         && (pdata->flags & EN2_CTRL_SD0)) {
430                 dev_dbg(&rdev->dev,
431                         "disable: Regulator %s is controlled by EN2\n",
432                         rdev->desc->name);
433                 return 0;
434         }
435
436         return max77663_regulator_set_power_mode(reg, power_mode);;
437 }
438
439 static int max77663_regulator_is_enabled(struct regulator_dev *rdev)
440 {
441         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
442         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
443         int ret = 1;
444
445         if (reg->fps_src != FPS_SRC_NONE) {
446                 dev_dbg(&rdev->dev, "is_enable: Regulator %s using %s\n",
447                         rdev->desc->name, fps_src_name(reg->fps_src));
448                 return 1;
449         }
450
451         if ((reg->id == MAX77663_REGULATOR_ID_SD0)
452                         && (pdata->flags & EN2_CTRL_SD0)) {
453                 dev_dbg(&rdev->dev,
454                         "is_enable: Regulator %s is controlled by EN2\n",
455                         rdev->desc->name);
456                 return 1;
457         }
458
459         if (max77663_regulator_get_power_mode(reg) == POWER_MODE_DISABLE)
460                 ret = 0;
461
462         return ret;
463 }
464
465 static int max77663_regulator_set_mode(struct regulator_dev *rdev,
466                                        unsigned int mode)
467 {
468         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
469         u8 power_mode;
470         int ret;
471
472         if (mode == REGULATOR_MODE_NORMAL)
473                 power_mode = POWER_MODE_NORMAL;
474         else if (mode == REGULATOR_MODE_STANDBY)
475                 power_mode = POWER_MODE_LPM;
476         else
477                 return -EINVAL;
478
479         ret = max77663_regulator_set_power_mode(reg, power_mode);
480         if (!ret)
481                 reg->regulator_mode = mode;
482
483         return ret;
484 }
485
486 static unsigned int max77663_regulator_get_mode(struct regulator_dev *rdev)
487 {
488         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
489
490         return reg->regulator_mode;
491 }
492
493 static struct regulator_ops max77663_ldo_ops = {
494         .set_voltage = max77663_regulator_set_voltage,
495         .get_voltage = max77663_regulator_get_voltage,
496         .enable = max77663_regulator_enable,
497         .disable = max77663_regulator_disable,
498         .is_enabled = max77663_regulator_is_enabled,
499         .set_mode = max77663_regulator_set_mode,
500         .get_mode = max77663_regulator_get_mode,
501 };
502
503 static int max77663_regulator_preinit(struct max77663_regulator *reg)
504 {
505         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
506         struct device *parent = _to_parent(reg);
507         int i;
508         u8 val;
509         int ret;
510
511         /* Update registers */
512         for (i = 0; i <= FPS_REG; i++) {
513                 ret = max77663_read(parent, reg->regs[i].addr,
514                                     &reg->regs[i].val, 1, 0);
515                 if (ret < 0) {
516                         dev_err(reg->dev,
517                                 "preinit: Failed to get register 0x%x\n",
518                                 reg->regs[i].addr);
519                         return ret;
520                 }
521         }
522
523         for (i = 0; i <= FPS_SRC_2; i++) {
524                 ret = max77663_read(parent, fps_cfg_regs[i].addr,
525                                     &fps_cfg_regs[i].val, 1, 0);
526                 if (ret < 0) {
527                         dev_err(reg->dev,
528                                 "preinit: Failed to get register 0x%x\n",
529                                 fps_cfg_regs[i].addr);
530                         return ret;
531                 }
532         }
533
534         /* Update FPS source */
535         if (reg->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
536                 reg->fps_src = FPS_SRC_NONE;
537         else
538                 reg->fps_src = (reg->regs[FPS_REG].val & FPS_SRC_MASK)
539                                 >> FPS_SRC_SHIFT;
540
541         /* Set initial state */
542         if (!pdata->init_apply)
543                 goto skip_init_apply;
544
545         if (pdata->init_uV >= 0) {
546                 ret = max77663_regulator_do_set_voltage(reg, pdata->init_uV,
547                                                         pdata->init_uV);
548                 if (ret < 0) {
549                         dev_err(reg->dev, "preinit: Failed to set voltage to "
550                                 "%d\n", pdata->init_uV);
551                         return ret;
552                 }
553         }
554
555         if (pdata->init_enable)
556                 val = POWER_MODE_NORMAL;
557         else
558                 val = POWER_MODE_DISABLE;
559
560         ret = max77663_regulator_set_power_mode(reg, val);
561         if (ret < 0) {
562                 dev_err(reg->dev,
563                         "preinit: Failed to set power mode to %d\n", val);
564                 return ret;
565         }
566
567
568 skip_init_apply:
569         if (reg->type == REGULATOR_TYPE_SD) {
570                 if (pdata->flags & SD_SLEW_RATE_MASK) {
571                         if (pdata->flags & SD_SLEW_RATE_SLOWEST)
572                                 val = SD_SR_13_75 << SD_SR_SHIFT;
573                         else if (pdata->flags & SD_SLEW_RATE_SLOW)
574                                 val = SD_SR_27_5 << SD_SR_SHIFT;
575                         else if (pdata->flags & SD_SLEW_RATE_FAST)
576                                 val = SD_SR_55 << SD_SR_SHIFT;
577                         else
578                                 val = SD_SR_100 << SD_SR_SHIFT;
579
580                         ret = max77663_regulator_cache_write(reg,
581                                         reg->regs[CFG_REG].addr, SD_SR_MASK,
582                                         val, &reg->regs[CFG_REG].val);
583                         if (ret < 0) {
584                                 dev_err(reg->dev,
585                                         "preinit: Failed to set slew rate\n");
586                                 return ret;
587                         }
588                 }
589
590                 if (pdata->flags & SD_FORCED_PWM_MODE) {
591                         ret = max77663_regulator_cache_write(reg,
592                                         reg->regs[CFG_REG].addr, SD_FPWM_MASK,
593                                         SD_FPWM_MASK, &reg->regs[CFG_REG].val);
594                         if (ret < 0) {
595                                 dev_err(reg->dev, "preinit: "
596                                         "Failed to set forced pwm mode\n");
597                                 return ret;
598                         }
599                 }
600
601                 if (pdata->flags & SD_FSRADE_DISABLE) {
602                         ret = max77663_regulator_cache_write(reg,
603                                         reg->regs[CFG_REG].addr,
604                                         SD_FSRADE_MASK, SD_FSRADE_MASK,
605                                         &reg->regs[CFG_REG].val);
606                         if (ret < 0) {
607                                 dev_err(reg->dev, "preinit: Failed to set "
608                                         "falling slew-rate discharge mode\n");
609                                 return ret;
610                         }
611                 }
612
613                 if ((reg->id == MAX77663_REGULATOR_ID_SD0)
614                                 && (pdata->flags & EN2_CTRL_SD0)) {
615                         val = POWER_MODE_DISABLE;
616                         ret = max77663_regulator_set_power_mode(reg, val);
617                         if (ret < 0) {
618                                 dev_err(reg->dev, "preinit: "
619                                         "Failed to set power mode to %d for "
620                                         "EN2_CTRL_SD0\n", val);
621                                 return ret;
622                         }
623
624                         if (reg->fps_src == FPS_SRC_NONE)
625                                 return 0;
626
627                         ret = max77663_regulator_set_fps_src(reg, FPS_SRC_NONE);
628                         if (ret < 0) {
629                                 dev_err(reg->dev, "preinit: "
630                                         "Failed to set FPSSRC to FPS_SRC_NONE "
631                                         "for EN2_CTRL_SD0\n");
632                                 return ret;
633                         }
634                 }
635         }
636
637         ret = max77663_regulator_set_fps_cfgs(reg, pdata->fps_cfgs,
638                                               pdata->num_fps_cfgs);
639         if (ret < 0) {
640                 dev_err(reg->dev, "preinit: Failed to set FPSCFG\n");
641                 return ret;
642         }
643
644         ret = max77663_regulator_set_fps_src(reg, pdata->fps_src);
645         if (ret < 0) {
646                 dev_err(reg->dev, "preinit: Failed to set FPSSRC to %d\n",
647                         pdata->fps_src);
648                 return ret;
649         }
650
651         ret = max77663_regulator_set_fps(reg);
652         if (ret < 0) {
653                 dev_err(reg->dev, "preinit: Failed to set FPS\n");
654                 return ret;
655         }
656
657         return 0;
658 }
659
660 #define REGULATOR_SD(_id, _volt_mask, _fps_reg, _min_uV, _max_uV, _step_uV) \
661         [MAX77663_REGULATOR_ID_##_id] = {                       \
662                 .id = MAX77663_REGULATOR_ID_##_id,              \
663                 .type = REGULATOR_TYPE_SD,                      \
664                 .volt_mask = _volt_mask##_VOLT_MASK,            \
665                 .regs = {                                       \
666                         [VOLT_REG] = {                          \
667                                 .addr = MAX77663_REG_##_id,     \
668                         },                                      \
669                         [CFG_REG] = {                           \
670                                 .addr = MAX77663_REG_##_id##_CFG, \
671                         },                                      \
672                         [FPS_REG] = {                           \
673                                 .addr = MAX77663_REG_FPS_##_fps_reg, \
674                         },                                      \
675                 },                                              \
676                 .min_uV = _min_uV,                              \
677                 .max_uV = _max_uV,                              \
678                 .step_uV = _step_uV,                            \
679                 .regulator_mode = REGULATOR_MODE_NORMAL,        \
680                 .power_mode = POWER_MODE_NORMAL,                \
681                 .power_mode_mask = SD_POWER_MODE_MASK,          \
682                 .power_mode_shift = SD_POWER_MODE_SHIFT,        \
683         }
684
685 #define REGULATOR_LDO(_id, _min_uV, _max_uV, _step_uV)          \
686         [MAX77663_REGULATOR_ID_##_id] = {                       \
687                 .id = MAX77663_REGULATOR_ID_##_id,              \
688                 .type = REGULATOR_TYPE_LDO,                     \
689                 .volt_mask = LDO_VOLT_MASK,                     \
690                 .regs = {                                       \
691                         [VOLT_REG] = {                          \
692                                 .addr = MAX77663_REG_##_id##_CFG, \
693                         },                                      \
694                         [CFG_REG] = {                           \
695                                 .addr = MAX77663_REG_##_id##_CFG2, \
696                         },                                      \
697                         [FPS_REG] = {                           \
698                                 .addr = MAX77663_REG_FPS_##_id, \
699                         },                                      \
700                 },                                              \
701                 .min_uV = _min_uV,                              \
702                 .max_uV = _max_uV,                              \
703                 .step_uV = _step_uV,                            \
704                 .regulator_mode = REGULATOR_MODE_NORMAL,        \
705                 .power_mode = POWER_MODE_NORMAL,                \
706                 .power_mode_mask = LDO_POWER_MODE_MASK,         \
707                 .power_mode_shift = LDO_POWER_MODE_SHIFT,       \
708         }
709
710 static struct max77663_regulator max77663_regs[MAX77663_REGULATOR_ID_NR] = {
711         REGULATOR_SD(SD0,    SDX, SD0,  600000, 3387500, 12500),
712         REGULATOR_SD(DVSSD0, SDX, NONE, 600000, 3387500, 12500),
713         REGULATOR_SD(SD1,    SD1, SD1,  800000, 1587500, 12500),
714         REGULATOR_SD(DVSSD1, SD1, NONE, 800000, 1587500, 12500),
715         REGULATOR_SD(SD2,    SDX, SD2,  600000, 3387500, 12500),
716         REGULATOR_SD(SD3,    SDX, SD3,  600000, 3387500, 12500),
717         REGULATOR_SD(SD4,    SDX, SD4,  600000, 3387500, 12500),
718
719         REGULATOR_LDO(LDO0, 800000, 2350000, 25000),
720         REGULATOR_LDO(LDO1, 800000, 2350000, 25000),
721         REGULATOR_LDO(LDO2, 800000, 3950000, 50000),
722         REGULATOR_LDO(LDO3, 800000, 3950000, 50000),
723         REGULATOR_LDO(LDO4, 800000, 1587500, 12500),
724         REGULATOR_LDO(LDO5, 800000, 3950000, 50000),
725         REGULATOR_LDO(LDO6, 800000, 3950000, 50000),
726         REGULATOR_LDO(LDO7, 800000, 3950000, 50000),
727         REGULATOR_LDO(LDO8, 800000, 3950000, 50000),
728 };
729
730 #define REGULATOR_DESC(_id, _name)                      \
731         [MAX77663_REGULATOR_ID_##_id] = {               \
732                 .name = max77663_rails(_name),          \
733                 .id = MAX77663_REGULATOR_ID_##_id,      \
734                 .ops = &max77663_ldo_ops,               \
735                 .type = REGULATOR_VOLTAGE,              \
736                 .owner = THIS_MODULE,                   \
737         }
738
739 static struct regulator_desc max77663_rdesc[MAX77663_REGULATOR_ID_NR] = {
740         REGULATOR_DESC(SD0, sd0),
741         REGULATOR_DESC(DVSSD0, dvssd0),
742         REGULATOR_DESC(SD1, sd1),
743         REGULATOR_DESC(DVSSD1, dvssd1),
744         REGULATOR_DESC(SD2, sd2),
745         REGULATOR_DESC(SD3, sd3),
746         REGULATOR_DESC(SD4, sd4),
747         REGULATOR_DESC(LDO0, ldo0),
748         REGULATOR_DESC(LDO1, ldo1),
749         REGULATOR_DESC(LDO2, ldo2),
750         REGULATOR_DESC(LDO3, ldo3),
751         REGULATOR_DESC(LDO4, ldo4),
752         REGULATOR_DESC(LDO5, ldo5),
753         REGULATOR_DESC(LDO6, ldo6),
754         REGULATOR_DESC(LDO7, ldo7),
755         REGULATOR_DESC(LDO8, ldo8),
756 };
757
758 static int max77663_regulator_probe(struct platform_device *pdev)
759 {
760         struct regulator_desc *rdesc;
761         struct max77663_regulator *reg;
762         struct max77663_regulator_platform_data *pdata;
763         int ret = 0;
764
765         if ((pdev->id < 0) || (pdev->id >= MAX77663_REGULATOR_ID_NR)) {
766                 dev_err(&pdev->dev, "Invalid device id %d\n", pdev->id);
767                 return -ENODEV;
768         }
769
770         rdesc = &max77663_rdesc[pdev->id];
771         reg = &max77663_regs[pdev->id];
772         reg->dev = &pdev->dev;
773         pdata = reg->dev->platform_data;
774
775         dev_dbg(&pdev->dev, "probe: name=%s\n", rdesc->name);
776
777         ret = max77663_regulator_preinit(reg);
778         if (ret) {
779                 dev_err(&pdev->dev, "probe: Failed to preinit regulator %s\n",
780                         rdesc->name);
781                 return ret;
782         }
783
784         reg->rdev = regulator_register(rdesc, &pdev->dev, &pdata->init_data,
785                                        reg);
786         if (IS_ERR(reg->rdev)) {
787                 dev_err(&pdev->dev, "probe: Failed to register regulator %s\n",
788                         rdesc->name);
789                 return PTR_ERR(reg->rdev);
790         }
791
792         return 0;
793 }
794
795 static int max77663_regulator_remove(struct platform_device *pdev)
796 {
797         struct regulator_dev *rdev = platform_get_drvdata(pdev);
798
799         regulator_unregister(rdev);
800         return 0;
801 }
802
803 static struct platform_driver max77663_regulator_driver = {
804         .probe = max77663_regulator_probe,
805         .remove = __devexit_p(max77663_regulator_remove),
806         .driver = {
807                 .name = "max77663-regulator",
808                 .owner = THIS_MODULE,
809         },
810 };
811
812 static int __init max77663_regulator_init(void)
813 {
814         return platform_driver_register(&max77663_regulator_driver);
815 }
816 subsys_initcall(max77663_regulator_init);
817
818 static void __exit max77663_reg_exit(void)
819 {
820         platform_driver_unregister(&max77663_regulator_driver);
821 }
822 module_exit(max77663_reg_exit);
823
824 MODULE_LICENSE("GPL v2");
825 MODULE_DESCRIPTION("max77663 regulator driver");
826 MODULE_VERSION("1.0");