regulator: palmas: fix build warnings
[linux-2.6.git] / drivers / regulator / max77663-regulator.c
1 /*
2  * drivers/regulator/max77663-regulator.c
3  * Maxim LDO and Buck regulators driver
4  *
5  * Copyright 2011-2012 Maxim Integrated Products, Inc.
6  * Copyright (C) 2011-2012 NVIDIA Corporation
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of the
11  * License, or (at your option) any later version.
12  *
13  */
14
15 #include <linux/err.h>
16 #include <linux/string.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/slab.h>
21 #include <linux/debugfs.h>
22 #include <linux/uaccess.h>
23 #include <linux/i2c.h>
24 #include <linux/mfd/core.h>
25 #include <linux/mfd/max77663-core.h>
26 #include <linux/regulator/driver.h>
27 #include <linux/regulator/machine.h>
28 #include <linux/regulator/max77663-regulator.h>
29
30 /* Regulator types */
31 #define REGULATOR_TYPE_SD               0
32 #define REGULATOR_TYPE_LDO_N            1
33 #define REGULATOR_TYPE_LDO_P            2
34
35 /* SD and LDO Registers */
36 #define MAX77663_REG_SD0                0x16
37 #define MAX77663_REG_SD1                0x17
38 #define MAX77663_REG_SD2                0x18
39 #define MAX77663_REG_SD3                0x19
40 #define MAX77663_REG_SD4                0x1A
41 #define MAX77663_REG_DVSSD0             0x1B
42 #define MAX77663_REG_DVSSD1             0x1C
43 #define MAX77663_REG_SD0_CFG            0x1D
44 #define MAX77663_REG_DVSSD0_CFG         MAX77663_REG_SD0_CFG
45 #define MAX77663_REG_SD1_CFG            0x1E
46 #define MAX77663_REG_DVSSD1_CFG         MAX77663_REG_SD1_CFG
47 #define MAX77663_REG_SD2_CFG            0x1F
48 #define MAX77663_REG_SD3_CFG            0x20
49 #define MAX77663_REG_SD4_CFG            0x21
50 #define MAX77663_REG_LDO0_CFG           0x23
51 #define MAX77663_REG_LDO0_CFG2          0x24
52 #define MAX77663_REG_LDO1_CFG           0x25
53 #define MAX77663_REG_LDO1_CFG2          0x26
54 #define MAX77663_REG_LDO2_CFG           0x27
55 #define MAX77663_REG_LDO2_CFG2          0x28
56 #define MAX77663_REG_LDO3_CFG           0x29
57 #define MAX77663_REG_LDO3_CFG2          0x2A
58 #define MAX77663_REG_LDO4_CFG           0x2B
59 #define MAX77663_REG_LDO4_CFG2          0x2C
60 #define MAX77663_REG_LDO5_CFG           0x2D
61 #define MAX77663_REG_LDO5_CFG2          0x2E
62 #define MAX77663_REG_LDO6_CFG           0x2F
63 #define MAX77663_REG_LDO6_CFG2          0x30
64 #define MAX77663_REG_LDO7_CFG           0x31
65 #define MAX77663_REG_LDO7_CFG2          0x32
66 #define MAX77663_REG_LDO8_CFG           0x33
67 #define MAX77663_REG_LDO8_CFG2          0x34
68 #define MAX77663_REG_LDO_CFG3           0x35
69
70 /* Power Mode */
71 #define POWER_MODE_NORMAL               3
72 #define POWER_MODE_LPM                  2
73 #define POWER_MODE_GLPM                 1
74 #define POWER_MODE_DISABLE              0
75 #define SD_POWER_MODE_MASK              0x30
76 #define SD_POWER_MODE_SHIFT             4
77 #define LDO_POWER_MODE_MASK             0xC0
78 #define LDO_POWER_MODE_SHIFT            6
79
80 /* SD Slew Rate */
81 #define SD_SR_13_75                     0
82 #define SD_SR_27_5                      1
83 #define SD_SR_55                        2
84 #define SD_SR_100                       3
85 #define SD_SR_MASK                      0xC0
86 #define SD_SR_SHIFT                     6
87
88 /* SD Forced PWM Mode */
89 #define SD_FPWM_MASK                    0x04
90 #define SD_FPWM_SHIFT                   2
91
92 /* SD Failling slew rate Active-Discharge Mode */
93 #define SD_FSRADE_MASK                  0x01
94 #define SD_FSRADE_SHIFT         0
95
96 /* LDO Configuration 3 */
97 #define TRACK4_MASK                     0x20
98 #define TRACK4_SHIFT                    5
99
100 /* Voltage */
101 #define SDX_VOLT_MASK                   0xFF
102 #define SD0_VOLT_MASK                   0x3F
103 #define SD1_VOLT_MASK                   0x3F
104 #define LDO_VOLT_MASK                   0x3F
105
106 /* FPS Registers */
107 #define MAX77663_REG_FPS_CFG0           0x43
108 #define MAX77663_REG_FPS_CFG1           0x44
109 #define MAX77663_REG_FPS_CFG2           0x45
110 #define MAX77663_REG_FPS_LDO0           0x46
111 #define MAX77663_REG_FPS_LDO1           0x47
112 #define MAX77663_REG_FPS_LDO2           0x48
113 #define MAX77663_REG_FPS_LDO3           0x49
114 #define MAX77663_REG_FPS_LDO4           0x4A
115 #define MAX77663_REG_FPS_LDO5           0x4B
116 #define MAX77663_REG_FPS_LDO6           0x4C
117 #define MAX77663_REG_FPS_LDO7           0x4D
118 #define MAX77663_REG_FPS_LDO8           0x4E
119 #define MAX77663_REG_FPS_SD0            0x4F
120 #define MAX77663_REG_FPS_SD1            0x50
121 #define MAX77663_REG_FPS_SD2            0x51
122 #define MAX77663_REG_FPS_SD3            0x52
123 #define MAX77663_REG_FPS_SD4            0x53
124 #define MAX77663_REG_FPS_NONE           0
125
126 #define FPS_TIME_PERIOD_MASK            0x38
127 #define FPS_TIME_PERIOD_SHIFT           3
128 #define FPS_EN_SRC_MASK                 0x06
129 #define FPS_EN_SRC_SHIFT                1
130 #define FPS_SW_EN_MASK                  0x01
131 #define FPS_SW_EN_SHIFT                 0
132 #define FPS_SRC_MASK                    0xC0
133 #define FPS_SRC_SHIFT                   6
134 #define FPS_PU_PERIOD_MASK              0x38
135 #define FPS_PU_PERIOD_SHIFT             3
136 #define FPS_PD_PERIOD_MASK              0x07
137 #define FPS_PD_PERIOD_SHIFT             0
138
139 /* Chip Identification Register */
140 #define MAX77663_REG_CID5               0x5D
141
142 #define CID_DIDM_MASK                   0xF0
143 #define CID_DIDM_SHIFT                  4
144
145 #define SD_SAFE_DOWN_UV                 50000 /* 50mV */
146
147 enum {
148         VOLT_REG = 0,
149         CFG_REG,
150         FPS_REG,
151 };
152
153 struct max77663_register {
154         u8 addr;
155         u8 val;
156 };
157
158 struct max77663_regulator_info {
159         u8 id;
160         u8 type;
161         u32 min_uV;
162         u32 max_uV;
163         u32 step_uV;
164
165         struct max77663_register regs[3]; /* volt, cfg, fps */
166
167         struct regulator_desc desc;
168
169         u8 volt_mask;
170
171         u8 power_mode_mask;
172         u8 power_mode_shift;
173 };
174
175 struct max77663_regulator {
176         struct max77663_regulator_info *rinfo;
177         struct regulator_dev *rdev;
178         struct device *dev;
179         struct max77663_regulator_platform_data *pdata;
180         u32 regulator_mode;
181         u8 power_mode;
182         enum max77663_regulator_fps_src fps_src;
183         u8 val[3]; /* volt, cfg, fps */
184         int safe_down_uV; /* for stable down scaling */
185 };
186
187 #define fps_src_name(fps_src)   \
188         (fps_src == FPS_SRC_0 ? "FPS_SRC_0" :   \
189         fps_src == FPS_SRC_1 ? "FPS_SRC_1" :    \
190         fps_src == FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
191
192 static int fps_cfg_init;
193 static struct max77663_register fps_cfg_regs[] = {
194         {
195                 .addr = MAX77663_REG_FPS_CFG0,
196         },
197         {
198                 .addr = MAX77663_REG_FPS_CFG1,
199         },
200         {
201                 .addr = MAX77663_REG_FPS_CFG2,
202         },
203 };
204
205 static inline struct max77663_regulator_platform_data
206 *_to_pdata(struct max77663_regulator *reg)
207 {
208         return reg->pdata;
209 }
210
211 static inline struct device *_to_parent(struct max77663_regulator *reg)
212 {
213         return reg->dev->parent;
214 }
215
216 static inline int max77663_regulator_cache_write(struct max77663_regulator *reg,
217                                         u8 addr, u8 mask, u8 val, u8 *cache)
218 {
219         struct device *parent = _to_parent(reg);
220         u8 new_val;
221         int ret;
222
223         new_val = (*cache & ~mask) | (val & mask);
224         if (*cache != new_val) {
225                 ret = max77663_write(parent, addr, &new_val, 1, 0);
226                 if (ret < 0)
227                         return ret;
228
229                 *cache = new_val;
230         }
231         return 0;
232 }
233
234 static int
235 max77663_regulator_set_fps_src(struct max77663_regulator *reg,
236                                enum max77663_regulator_fps_src fps_src)
237 {
238         int ret;
239         struct max77663_regulator_info *rinfo = reg->rinfo;
240
241         if ((rinfo->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE) ||
242                         (reg->fps_src == fps_src))
243                 return 0;
244
245         switch (fps_src) {
246         case FPS_SRC_0:
247         case FPS_SRC_1:
248         case FPS_SRC_2:
249         case FPS_SRC_NONE:
250                 break;
251         case FPS_SRC_DEF:
252                 return 0;
253         default:
254                 return -EINVAL;
255         }
256
257         ret = max77663_regulator_cache_write(reg, rinfo->regs[FPS_REG].addr,
258                                         FPS_SRC_MASK, fps_src << FPS_SRC_SHIFT,
259                                         &reg->val[FPS_REG]);
260         if (ret < 0)
261                 return ret;
262
263         reg->fps_src = fps_src;
264         return 0;
265 }
266
267 static int max77663_regulator_set_fps(struct max77663_regulator *reg)
268 {
269         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
270         struct max77663_regulator_info *rinfo = reg->rinfo;
271         u8 fps_val = 0, fps_mask = 0;
272         int ret = 0;
273
274         if (reg->rinfo->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
275                 return 0;
276
277         if (reg->fps_src == FPS_SRC_NONE)
278                 return 0;
279
280         /* FPS power up period setting */
281         if (pdata->fps_pu_period != FPS_POWER_PERIOD_DEF) {
282                 fps_val |= (pdata->fps_pu_period << FPS_PU_PERIOD_SHIFT);
283                 fps_mask |= FPS_PU_PERIOD_MASK;
284         }
285
286         /* FPS power down period setting */
287         if (pdata->fps_pd_period != FPS_POWER_PERIOD_DEF) {
288                 fps_val |= (pdata->fps_pd_period << FPS_PD_PERIOD_SHIFT);
289                 fps_mask |= FPS_PD_PERIOD_MASK;
290         }
291
292         if (fps_val || fps_mask)
293                 ret = max77663_regulator_cache_write(reg,
294                                         rinfo->regs[FPS_REG].addr, fps_mask,
295                                         fps_val, &reg->val[FPS_REG]);
296
297         return ret;
298 }
299
300 static int
301 max77663_regulator_set_fps_cfg(struct max77663_regulator *reg,
302                                struct max77663_regulator_fps_cfg *fps_cfg)
303 {
304         u8 val, mask;
305
306         if ((fps_cfg->src < FPS_SRC_0) || (fps_cfg->src > FPS_SRC_2))
307                 return -EINVAL;
308
309         val = (fps_cfg->en_src << FPS_EN_SRC_SHIFT);
310         mask = FPS_EN_SRC_MASK;
311
312         if (fps_cfg->time_period != FPS_TIME_PERIOD_DEF) {
313                 val |= (fps_cfg->time_period << FPS_TIME_PERIOD_SHIFT);
314                 mask |= FPS_TIME_PERIOD_MASK;
315         }
316
317         return max77663_regulator_cache_write(reg,
318                                         fps_cfg_regs[fps_cfg->src].addr, mask,
319                                         val, &fps_cfg_regs[fps_cfg->src].val);
320 }
321
322 static int
323 max77663_regulator_set_fps_cfgs(struct max77663_regulator *reg,
324                                 struct max77663_regulator_fps_cfg *fps_cfgs,
325                                 int num_fps_cfgs)
326 {
327         struct device *parent = _to_parent(reg);
328         int i, ret;
329
330         if (fps_cfg_init)
331                 return 0;
332
333         for (i = 0; i <= FPS_SRC_2; i++) {
334                 ret = max77663_read(parent, fps_cfg_regs[i].addr,
335                                     &fps_cfg_regs[i].val, 1, 0);
336                 if (ret < 0)
337                         return ret;
338         }
339
340         for (i = 0; i < num_fps_cfgs; i++) {
341                 ret = max77663_regulator_set_fps_cfg(reg, &fps_cfgs[i]);
342                 if (ret < 0)
343                         return ret;
344         }
345         fps_cfg_init = 1;
346
347         return 0;
348 }
349
350 static int
351 max77663_regulator_set_power_mode(struct max77663_regulator *reg, u8 power_mode)
352 {
353         struct max77663_regulator_info *rinfo = reg->rinfo;
354         u8 mask = rinfo->power_mode_mask;
355         u8 shift = rinfo->power_mode_shift;
356         int ret;
357
358         if (rinfo->type == REGULATOR_TYPE_SD)
359                 ret = max77663_regulator_cache_write(reg,
360                                                      rinfo->regs[CFG_REG].addr,
361                                                      mask, power_mode << shift,
362                                                      &reg->val[CFG_REG]);
363         else
364                 ret = max77663_regulator_cache_write(reg,
365                                                      rinfo->regs[VOLT_REG].addr,
366                                                      mask, power_mode << shift,
367                                                      &reg->val[VOLT_REG]);
368
369         if (ret < 0)
370                 return ret;
371
372         reg->power_mode = power_mode;
373         return ret;
374 }
375
376 static u8 max77663_regulator_get_power_mode(struct max77663_regulator *reg)
377 {
378         struct max77663_regulator_info *rinfo = reg->rinfo;
379         u8 mask = rinfo->power_mode_mask;
380         u8 shift = rinfo->power_mode_shift;
381
382         if (rinfo->type == REGULATOR_TYPE_SD)
383                 reg->power_mode = (reg->val[CFG_REG] & mask) >> shift;
384         else
385                 reg->power_mode = (reg->val[VOLT_REG] & mask) >> shift;
386
387         return reg->power_mode;
388 }
389
390 static int max77663_regulator_do_set_voltage(struct max77663_regulator *reg,
391                                              int min_uV, int max_uV)
392 {
393         struct max77663_regulator_info *rinfo = reg->rinfo;
394         u8 addr = rinfo->regs[VOLT_REG].addr;
395         u8 mask = rinfo->volt_mask;
396         u8 *cache = &reg->val[VOLT_REG];
397         u8 val;
398         int old_uV, new_uV, safe_uV;
399         int i, steps = 1;
400         int ret = 0;
401
402         if (min_uV < rinfo->min_uV || max_uV > rinfo->max_uV)
403                 return -EDOM;
404
405         old_uV = (*cache & mask) * rinfo->step_uV + rinfo->min_uV;
406
407         if ((old_uV > min_uV) && (reg->safe_down_uV >= rinfo->step_uV)) {
408                 steps = DIV_ROUND_UP(old_uV - min_uV, reg->safe_down_uV);
409                 safe_uV = -reg->safe_down_uV;
410         }
411
412         if (steps == 1) {
413                 val = (min_uV - rinfo->min_uV) / rinfo->step_uV;
414                 ret = max77663_regulator_cache_write(reg, addr, mask, val,
415                                                      cache);
416         } else {
417                 for (i = 0; i < steps; i++) {
418                         if (abs(min_uV - old_uV) > abs(safe_uV))
419                                 new_uV = old_uV + safe_uV;
420                         else
421                                 new_uV = min_uV;
422
423                         dev_dbg(&reg->rdev->dev, "do_set_voltage: name=%s, "
424                                 "%d/%d, old_uV=%d, new_uV=%d\n",
425                                 reg->rdev->desc->name, i + 1, steps, old_uV,
426                                 new_uV);
427
428                         val = (new_uV - rinfo->min_uV) / rinfo->step_uV;
429                         ret = max77663_regulator_cache_write(reg, addr, mask,
430                                                              val, cache);
431                         if (ret < 0)
432                                 return ret;
433
434                         old_uV = new_uV;
435                 }
436         }
437
438         return ret;
439 }
440
441 static int max77663_regulator_set_voltage(struct regulator_dev *rdev,
442                                           int min_uV, int max_uV,
443                                           unsigned *selector)
444 {
445         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
446
447         dev_dbg(&rdev->dev, "set_voltage: name=%s, min_uV=%d, max_uV=%d\n",
448                 rdev->desc->name, min_uV, max_uV);
449         return max77663_regulator_do_set_voltage(reg, min_uV, max_uV);
450 }
451
452 static int max77663_regulator_get_voltage(struct regulator_dev *rdev)
453 {
454         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
455         struct max77663_regulator_info *rinfo = reg->rinfo;
456         int volt;
457
458         volt = (reg->val[VOLT_REG] & rinfo->volt_mask)
459                 * rinfo->step_uV + rinfo->min_uV;
460
461         dev_dbg(&rdev->dev, "get_voltage: name=%s, volt=%d, val=0x%02x\n",
462                 rdev->desc->name, volt, reg->val[VOLT_REG]);
463         return volt;
464 }
465
466 static int max77663_regulator_enable(struct regulator_dev *rdev)
467 {
468         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
469         struct max77663_regulator_info *rinfo = reg->rinfo;
470         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
471         int power_mode = (pdata->flags & GLPM_ENABLE) ?
472                          POWER_MODE_GLPM : POWER_MODE_NORMAL;
473
474         if (reg->fps_src != FPS_SRC_NONE) {
475                 dev_dbg(&rdev->dev, "enable: Regulator %s using %s\n",
476                         rdev->desc->name, fps_src_name(reg->fps_src));
477                 return 0;
478         }
479
480         if ((rinfo->id == MAX77663_REGULATOR_ID_SD0)
481                         && (pdata->flags & EN2_CTRL_SD0)) {
482                 dev_dbg(&rdev->dev,
483                         "enable: Regulator %s is controlled by EN2\n",
484                         rdev->desc->name);
485                 return 0;
486         }
487
488         /* N-Channel LDOs don't support Low-Power mode. */
489         if ((rinfo->type != REGULATOR_TYPE_LDO_N) &&
490                         (reg->regulator_mode == REGULATOR_MODE_STANDBY))
491                 power_mode = POWER_MODE_LPM;
492
493         return max77663_regulator_set_power_mode(reg, power_mode);
494 }
495
496 static int max77663_regulator_disable(struct regulator_dev *rdev)
497 {
498         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
499         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
500         struct max77663_regulator_info *rinfo = reg->rinfo;
501         int power_mode = POWER_MODE_DISABLE;
502
503         if (reg->fps_src != FPS_SRC_NONE) {
504                 dev_dbg(&rdev->dev, "disable: Regulator %s using %s\n",
505                         rdev->desc->name, fps_src_name(reg->fps_src));
506                 return 0;
507         }
508
509         if ((rinfo->id == MAX77663_REGULATOR_ID_SD0)
510                         && (pdata->flags & EN2_CTRL_SD0)) {
511                 dev_dbg(&rdev->dev,
512                         "disable: Regulator %s is controlled by EN2\n",
513                         rdev->desc->name);
514                 return 0;
515         }
516
517         return max77663_regulator_set_power_mode(reg, power_mode);
518 }
519
520 static int max77663_regulator_is_enabled(struct regulator_dev *rdev)
521 {
522         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
523         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
524         struct max77663_regulator_info *rinfo = reg->rinfo;
525         int ret = 1;
526
527         if (reg->fps_src != FPS_SRC_NONE) {
528                 dev_dbg(&rdev->dev, "is_enable: Regulator %s using %s\n",
529                         rdev->desc->name, fps_src_name(reg->fps_src));
530                 return 1;
531         }
532
533         if ((rinfo->id == MAX77663_REGULATOR_ID_SD0)
534                         && (pdata->flags & EN2_CTRL_SD0)) {
535                 dev_dbg(&rdev->dev,
536                         "is_enable: Regulator %s is controlled by EN2\n",
537                         rdev->desc->name);
538                 return 1;
539         }
540
541         if (max77663_regulator_get_power_mode(reg) == POWER_MODE_DISABLE)
542                 ret = 0;
543
544         return ret;
545 }
546
547 static int max77663_regulator_set_mode(struct regulator_dev *rdev,
548                                        unsigned int mode)
549 {
550         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
551         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
552         struct max77663_regulator_info *rinfo = reg->rinfo;
553         u8 power_mode;
554         int ret;
555
556         if (mode == REGULATOR_MODE_NORMAL)
557                 power_mode = (pdata->flags & GLPM_ENABLE) ?
558                              POWER_MODE_GLPM : POWER_MODE_NORMAL;
559         else if (mode == REGULATOR_MODE_STANDBY) {
560                 /* N-Channel LDOs don't support Low-Power mode. */
561                 power_mode = (rinfo->type != REGULATOR_TYPE_LDO_N) ?
562                              POWER_MODE_LPM : POWER_MODE_NORMAL;
563         } else
564                 return -EINVAL;
565
566         ret = max77663_regulator_set_power_mode(reg, power_mode);
567         if (!ret)
568                 reg->regulator_mode = mode;
569
570         return ret;
571 }
572
573 static unsigned int max77663_regulator_get_mode(struct regulator_dev *rdev)
574 {
575         struct max77663_regulator *reg = rdev_get_drvdata(rdev);
576
577         return reg->regulator_mode;
578 }
579
580 static struct regulator_ops max77663_ldo_ops = {
581         .set_voltage = max77663_regulator_set_voltage,
582         .get_voltage = max77663_regulator_get_voltage,
583         .enable = max77663_regulator_enable,
584         .disable = max77663_regulator_disable,
585         .is_enabled = max77663_regulator_is_enabled,
586         .set_mode = max77663_regulator_set_mode,
587         .get_mode = max77663_regulator_get_mode,
588 };
589
590 static int max77663_regulator_preinit(struct max77663_regulator *reg)
591 {
592         struct max77663_regulator_platform_data *pdata = _to_pdata(reg);
593         struct max77663_regulator_info *rinfo = reg->rinfo;
594         struct device *parent = _to_parent(reg);
595         int i;
596         u8 val, mask;
597         int ret;
598
599         /* Update registers */
600         for (i = 0; i <= FPS_REG; i++) {
601                 ret = max77663_read(parent, rinfo->regs[i].addr,
602                                     &reg->val[i], 1, 0);
603                 if (ret < 0) {
604                         dev_err(reg->dev,
605                                 "preinit: Failed to get register 0x%x\n",
606                                 rinfo->regs[i].addr);
607                         return ret;
608                 }
609         }
610
611         /* Update FPS source */
612         if (rinfo->regs[FPS_REG].addr == MAX77663_REG_FPS_NONE)
613                 reg->fps_src = FPS_SRC_NONE;
614         else
615                 reg->fps_src = (reg->val[FPS_REG] & FPS_SRC_MASK)
616                                 >> FPS_SRC_SHIFT;
617
618         dev_dbg(reg->dev, "preinit: initial fps_src=%s\n",
619                 fps_src_name(reg->fps_src));
620
621         /* Update power mode */
622         max77663_regulator_get_power_mode(reg);
623
624         /* Check Chip Identification */
625         ret = max77663_read(parent, MAX77663_REG_CID5, &val, 1, 0);
626         if (ret < 0) {
627                 dev_err(reg->dev, "preinit: Failed to get register 0x%x\n",
628                         MAX77663_REG_CID5);
629                 return ret;
630         }
631
632         /* If metal revision is less than rev.3,
633          * set safe_down_uV for stable down scaling. */
634         if ((rinfo->type == REGULATOR_TYPE_SD) &&
635                         ((val & CID_DIDM_MASK) >> CID_DIDM_SHIFT) <= 2)
636                 reg->safe_down_uV = SD_SAFE_DOWN_UV;
637         else
638                 reg->safe_down_uV = 0;
639
640         /* Set FPS */
641         ret = max77663_regulator_set_fps_cfgs(reg, pdata->fps_cfgs,
642                                               pdata->num_fps_cfgs);
643         if (ret < 0) {
644                 dev_err(reg->dev, "preinit: Failed to set FPSCFG\n");
645                 return ret;
646         }
647
648         /* N-Channel LDOs don't support Low-Power mode. */
649         if ((rinfo->type == REGULATOR_TYPE_LDO_N) &&
650                         (pdata->flags & GLPM_ENABLE))
651                 pdata->flags &= ~GLPM_ENABLE;
652
653         /* To prevent power rail turn-off when change FPS source,
654          * it must set power mode to NORMAL before change FPS source to NONE
655          * from SRC_0, SRC_1 and SRC_2. */
656         if ((reg->fps_src != FPS_SRC_NONE) && (pdata->fps_src == FPS_SRC_NONE)
657                         && (reg->power_mode != POWER_MODE_NORMAL)) {
658                 val = (pdata->flags & GLPM_ENABLE) ?
659                       POWER_MODE_GLPM : POWER_MODE_NORMAL;
660                 ret = max77663_regulator_set_power_mode(reg, val);
661                 if (ret < 0) {
662                         dev_err(reg->dev, "preinit: Failed to "
663                                 "set power mode to POWER_MODE_NORMAL\n");
664                         return ret;
665                 }
666         }
667
668         ret = max77663_regulator_set_fps_src(reg, pdata->fps_src);
669         if (ret < 0) {
670                 dev_err(reg->dev, "preinit: Failed to set FPSSRC to %d\n",
671                         pdata->fps_src);
672                 return ret;
673         }
674
675         ret = max77663_regulator_set_fps(reg);
676         if (ret < 0) {
677                 dev_err(reg->dev, "preinit: Failed to set FPS\n");
678                 return ret;
679         }
680
681         if (rinfo->type == REGULATOR_TYPE_SD) {
682                 val = 0;
683                 mask = 0;
684
685                 if (pdata->flags & SD_SLEW_RATE_MASK) {
686                         mask |= SD_SR_MASK;
687                         if (pdata->flags & SD_SLEW_RATE_SLOWEST)
688                                 val |= (SD_SR_13_75 << SD_SR_SHIFT);
689                         else if (pdata->flags & SD_SLEW_RATE_SLOW)
690                                 val |= (SD_SR_27_5 << SD_SR_SHIFT);
691                         else if (pdata->flags & SD_SLEW_RATE_FAST)
692                                 val |= (SD_SR_55 << SD_SR_SHIFT);
693                         else
694                                 val |= (SD_SR_100 << SD_SR_SHIFT);
695                 }
696
697                 mask |= SD_FPWM_MASK;
698                 if (pdata->flags & SD_FORCED_PWM_MODE)
699                         val |= SD_FPWM_MASK;
700
701                 mask |= SD_FSRADE_MASK;
702                 if (pdata->flags & SD_FSRADE_DISABLE)
703                         val |= SD_FSRADE_MASK;
704
705                 ret = max77663_regulator_cache_write(reg,
706                                 rinfo->regs[CFG_REG].addr, mask, val,
707                                 &reg->val[CFG_REG]);
708                 if (ret < 0) {
709                         dev_err(reg->dev, "preinit: "
710                                 "Failed to set register 0x%x\n",
711                                 rinfo->regs[CFG_REG].addr);
712                         return ret;
713                 }
714
715                 if ((rinfo->id == MAX77663_REGULATOR_ID_SD0)
716                                 && (pdata->flags & EN2_CTRL_SD0)) {
717                         val = POWER_MODE_DISABLE;
718                         ret = max77663_regulator_set_power_mode(reg, val);
719                         if (ret < 0) {
720                                 dev_err(reg->dev, "preinit: "
721                                         "Failed to set power mode to %d for "
722                                         "EN2_CTRL_SD0\n", val);
723                                 return ret;
724                         }
725
726                         ret = max77663_regulator_set_fps_src(reg, FPS_SRC_NONE);
727                         if (ret < 0) {
728                                 dev_err(reg->dev, "preinit: "
729                                         "Failed to set FPSSRC to FPS_SRC_NONE "
730                                         "for EN2_CTRL_SD0\n");
731                                 return ret;
732                         }
733                 }
734         }
735
736         if ((rinfo->id == MAX77663_REGULATOR_ID_LDO4)
737                         && (pdata->flags & LDO4_EN_TRACKING)) {
738                 val = TRACK4_MASK;
739                 ret = max77663_write(parent, MAX77663_REG_LDO_CFG3, &val, 1, 0);
740                 if (ret < 0) {
741                         dev_err(reg->dev, "preinit: "
742                                 "Failed to set register 0x%x\n",
743                                 MAX77663_REG_LDO_CFG3);
744                         return ret;
745                 }
746         }
747
748         return 0;
749 }
750
751 #define REGULATOR_SD(_id, _volt_mask, _fps_reg, _min_uV, _max_uV, _step_uV) \
752         [MAX77663_REGULATOR_ID_##_id] = {                       \
753                 .id = MAX77663_REGULATOR_ID_##_id,              \
754                 .type = REGULATOR_TYPE_SD,                      \
755                 .volt_mask = _volt_mask##_VOLT_MASK,            \
756                 .regs = {                                       \
757                         [VOLT_REG] = {                          \
758                                 .addr = MAX77663_REG_##_id,     \
759                         },                                      \
760                         [CFG_REG] = {                           \
761                                 .addr = MAX77663_REG_##_id##_CFG, \
762                         },                                      \
763                         [FPS_REG] = {                           \
764                                 .addr = MAX77663_REG_FPS_##_fps_reg, \
765                         },                                      \
766                 },                                              \
767                 .min_uV = _min_uV,                              \
768                 .max_uV = _max_uV,                              \
769                 .step_uV = _step_uV,                            \
770                 .power_mode_mask = SD_POWER_MODE_MASK,          \
771                 .power_mode_shift = SD_POWER_MODE_SHIFT,        \
772                 .desc = {                                       \
773                         .name = max77663_rails(_id),            \
774                         .id = MAX77663_REGULATOR_ID_##_id,      \
775                         .ops = &max77663_ldo_ops,               \
776                         .type = REGULATOR_VOLTAGE,              \
777                         .owner = THIS_MODULE,                   \
778                 },                                              \
779         }
780
781 #define REGULATOR_LDO(_id, _type, _min_uV, _max_uV, _step_uV)   \
782         [MAX77663_REGULATOR_ID_##_id] = {                       \
783                 .id = MAX77663_REGULATOR_ID_##_id,              \
784                 .type = REGULATOR_TYPE_LDO_##_type,             \
785                 .volt_mask = LDO_VOLT_MASK,                     \
786                 .regs = {                                       \
787                         [VOLT_REG] = {                          \
788                                 .addr = MAX77663_REG_##_id##_CFG, \
789                         },                                      \
790                         [CFG_REG] = {                           \
791                                 .addr = MAX77663_REG_##_id##_CFG2, \
792                         },                                      \
793                         [FPS_REG] = {                           \
794                                 .addr = MAX77663_REG_FPS_##_id, \
795                         },                                      \
796                 },                                              \
797                 .min_uV = _min_uV,                              \
798                 .max_uV = _max_uV,                              \
799                 .step_uV = _step_uV,                            \
800                 .power_mode_mask = LDO_POWER_MODE_MASK,         \
801                 .power_mode_shift = LDO_POWER_MODE_SHIFT,       \
802                 .desc = {                                       \
803                         .name = max77663_rails(_id),            \
804                         .id = MAX77663_REGULATOR_ID_##_id,      \
805                         .ops = &max77663_ldo_ops,               \
806                         .type = REGULATOR_VOLTAGE,              \
807                         .owner = THIS_MODULE,                   \
808                 },                                              \
809         }
810
811 static struct max77663_regulator_info max77663_regs_info[MAX77663_REGULATOR_ID_NR] = {
812         REGULATOR_SD(SD0,    SDX, SD0,  600000, 3387500, 12500),
813         REGULATOR_SD(DVSSD0, SDX, NONE, 600000, 3387500, 12500),
814         REGULATOR_SD(SD1,    SD1, SD1,  800000, 1587500, 12500),
815         REGULATOR_SD(DVSSD1, SD1, NONE, 800000, 1587500, 12500),
816         REGULATOR_SD(SD2,    SDX, SD2,  600000, 3387500, 12500),
817         REGULATOR_SD(SD3,    SDX, SD3,  600000, 3387500, 12500),
818         REGULATOR_SD(SD4,    SDX, SD4,  600000, 3387500, 12500),
819
820         REGULATOR_LDO(LDO0, N, 800000, 2350000, 25000),
821         REGULATOR_LDO(LDO1, N, 800000, 2350000, 25000),
822         REGULATOR_LDO(LDO2, P, 800000, 3950000, 50000),
823         REGULATOR_LDO(LDO3, P, 800000, 3950000, 50000),
824         REGULATOR_LDO(LDO4, P, 800000, 1587500, 12500),
825         REGULATOR_LDO(LDO5, P, 800000, 3950000, 50000),
826         REGULATOR_LDO(LDO6, P, 800000, 3950000, 50000),
827         REGULATOR_LDO(LDO7, N, 800000, 3950000, 50000),
828         REGULATOR_LDO(LDO8, N, 800000, 3950000, 50000),
829 };
830
831 static int max77663_regulator_probe(struct platform_device *pdev)
832 {
833         struct max77663_platform_data *pdata =
834                                         dev_get_platdata(pdev->dev.parent);
835         struct regulator_desc *rdesc;
836         struct max77663_regulator *reg;
837         struct max77663_regulator *max_regs;
838         struct max77663_regulator_platform_data *reg_pdata;
839         int ret = 0;
840         int id;
841         int reg_id;
842         int reg_count;
843         u8 val;
844
845         if (!pdata) {
846                 dev_err(&pdev->dev, "No Platform data\n");
847                 return -ENODEV;
848         }
849
850         reg_count = pdata->num_regulator_pdata;
851         max_regs = devm_kzalloc(&pdev->dev,
852                         reg_count * sizeof(*max_regs), GFP_KERNEL);
853         if (!max_regs) {
854                 dev_err(&pdev->dev, "mem alloc for reg failed\n");
855                 return -ENOMEM;
856         }
857
858         ret = max77663_read_chip_version(pdev->dev.parent, &val);
859         if (ret == MAX77663_DRV_24) {
860                 max77663_regs_info[MAX77663_REGULATOR_ID_SD0].volt_mask =
861                                                                 SD0_VOLT_MASK;
862                 max77663_regs_info[MAX77663_REGULATOR_ID_SD0].min_uV = 800000;
863                 max77663_regs_info[MAX77663_REGULATOR_ID_SD0].max_uV = 1587500;
864                 max77663_regs_info[MAX77663_REGULATOR_ID_SD1].volt_mask =
865                                                                 SDX_VOLT_MASK;
866                 max77663_regs_info[MAX77663_REGULATOR_ID_SD1].min_uV = 600000;
867                 max77663_regs_info[MAX77663_REGULATOR_ID_SD1].max_uV = 3387500;
868         }
869
870         for (id = 0; id < reg_count; ++id) {
871                 reg_pdata = pdata->regulator_pdata[id];
872                 if (!reg_pdata) {
873                         dev_err(&pdev->dev,
874                                 "Regulator pltform data not there\n");
875                         goto clean_exit;
876                 }
877
878                 reg_id = reg_pdata->id;
879                 reg  = &max_regs[id];
880                 rdesc = &max77663_regs_info[reg_id].desc;
881                 reg->rinfo = &max77663_regs_info[reg_id];
882                 reg->dev = &pdev->dev;
883                 reg->pdata = reg_pdata;
884                 reg->regulator_mode = REGULATOR_MODE_NORMAL;
885                 reg->power_mode = POWER_MODE_NORMAL;
886
887                 dev_dbg(&pdev->dev, "probe: name=%s\n", rdesc->name);
888
889                 ret = max77663_regulator_preinit(reg);
890                 if (ret) {
891                         dev_err(&pdev->dev, "Failed to preinit regulator %s\n",
892                                 rdesc->name);
893                         goto clean_exit;
894                 }
895
896                 reg->rdev = regulator_register(rdesc, &pdev->dev,
897                                         reg->pdata->reg_init_data, reg, NULL);
898                 if (IS_ERR(reg->rdev)) {
899                         dev_err(&pdev->dev, "Failed to register regulator %s\n",
900                         rdesc->name);
901                         ret = PTR_ERR(reg->rdev);
902                         goto clean_exit;
903                 }
904         }
905         platform_set_drvdata(pdev, max_regs);
906
907         return 0;
908
909 clean_exit:
910         while (--id >= 0) {
911                 reg  = &max_regs[id];
912                 regulator_unregister(reg->rdev);
913         }
914         return ret;
915 }
916
917 static int max77663_regulator_remove(struct platform_device *pdev)
918 {
919         struct max77663_regulator *max_regs = platform_get_drvdata(pdev);
920         struct max77663_regulator *reg;
921         struct max77663_platform_data *pdata =
922                                         dev_get_platdata(pdev->dev.parent);
923         int reg_count;
924
925         if (!pdata)
926                 return 0;
927
928         reg_count = pdata->num_regulator_pdata;
929         while (--reg_count >= 0) {
930                 reg  = &max_regs[reg_count];
931                 regulator_unregister(reg->rdev);
932         }
933
934         return 0;
935 }
936
937 static struct platform_driver max77663_regulator_driver = {
938         .probe = max77663_regulator_probe,
939         .remove = __devexit_p(max77663_regulator_remove),
940         .driver = {
941                 .name = "max77663-pmic",
942                 .owner = THIS_MODULE,
943         },
944 };
945
946 static int __init max77663_regulator_init(void)
947 {
948         return platform_driver_register(&max77663_regulator_driver);
949 }
950 subsys_initcall(max77663_regulator_init);
951
952 static void __exit max77663_reg_exit(void)
953 {
954         platform_driver_unregister(&max77663_regulator_driver);
955 }
956 module_exit(max77663_reg_exit);
957
958 MODULE_LICENSE("GPL v2");
959 MODULE_DESCRIPTION("max77663 regulator driver");
960 MODULE_VERSION("1.0");