Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas...
[linux-2.6.git] / drivers / rapidio / switches / tsi57x.c
1 /*
2  * RapidIO Tsi57x switch family support
3  *
4  * Copyright 2009-2010 Integrated Device Technology, Inc.
5  * Alexandre Bounine <alexandre.bounine@idt.com>
6  *  - Added EM support
7  *  - Modified switch operations initialization.
8  *
9  * Copyright 2005 MontaVista Software, Inc.
10  * Matt Porter <mporter@kernel.crashing.org>
11  *
12  * This program is free software; you can redistribute  it and/or modify it
13  * under  the terms of  the GNU General  Public License as published by the
14  * Free Software Foundation;  either version 2 of the  License, or (at your
15  * option) any later version.
16  */
17
18 #include <linux/rio.h>
19 #include <linux/rio_drv.h>
20 #include <linux/rio_ids.h>
21 #include <linux/delay.h>
22 #include "../rio.h"
23
24 /* Global (broadcast) route registers */
25 #define SPBC_ROUTE_CFG_DESTID   0x10070
26 #define SPBC_ROUTE_CFG_PORT     0x10074
27
28 /* Per port route registers */
29 #define SPP_ROUTE_CFG_DESTID(n) (0x11070 + 0x100*n)
30 #define SPP_ROUTE_CFG_PORT(n)   (0x11074 + 0x100*n)
31
32 #define TSI578_SP_MODE(n)       (0x11004 + n*0x100)
33 #define TSI578_SP_MODE_GLBL     0x10004
34 #define  TSI578_SP_MODE_PW_DIS  0x08000000
35 #define  TSI578_SP_MODE_LUT_512 0x01000000
36
37 #define TSI578_SP_CTL_INDEP(n)  (0x13004 + n*0x100)
38 #define TSI578_SP_LUT_PEINF(n)  (0x13010 + n*0x100)
39 #define TSI578_SP_CS_TX(n)      (0x13014 + n*0x100)
40 #define TSI578_SP_INT_STATUS(n) (0x13018 + n*0x100)
41
42 #define TSI578_GLBL_ROUTE_BASE  0x10078
43
44 static int
45 tsi57x_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
46                        u16 table, u16 route_destid, u8 route_port)
47 {
48         if (table == RIO_GLOBAL_TABLE) {
49                 rio_mport_write_config_32(mport, destid, hopcount,
50                                           SPBC_ROUTE_CFG_DESTID, route_destid);
51                 rio_mport_write_config_32(mport, destid, hopcount,
52                                           SPBC_ROUTE_CFG_PORT, route_port);
53         } else {
54                 rio_mport_write_config_32(mport, destid, hopcount,
55                                 SPP_ROUTE_CFG_DESTID(table), route_destid);
56                 rio_mport_write_config_32(mport, destid, hopcount,
57                                 SPP_ROUTE_CFG_PORT(table), route_port);
58         }
59
60         udelay(10);
61
62         return 0;
63 }
64
65 static int
66 tsi57x_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
67                        u16 table, u16 route_destid, u8 *route_port)
68 {
69         int ret = 0;
70         u32 result;
71
72         if (table == RIO_GLOBAL_TABLE) {
73                 /* Use local RT of the ingress port to avoid possible
74                    race condition */
75                 rio_mport_read_config_32(mport, destid, hopcount,
76                         RIO_SWP_INFO_CAR, &result);
77                 table = (result & RIO_SWP_INFO_PORT_NUM_MASK);
78         }
79
80         rio_mport_write_config_32(mport, destid, hopcount,
81                                 SPP_ROUTE_CFG_DESTID(table), route_destid);
82         rio_mport_read_config_32(mport, destid, hopcount,
83                                 SPP_ROUTE_CFG_PORT(table), &result);
84
85         *route_port = (u8)result;
86         if (*route_port > 15)
87                 ret = -1;
88
89         return ret;
90 }
91
92 static int
93 tsi57x_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
94                        u16 table)
95 {
96         u32 route_idx;
97         u32 lut_size;
98
99         lut_size = (mport->sys_size) ? 0x1ff : 0xff;
100
101         if (table == RIO_GLOBAL_TABLE) {
102                 rio_mport_write_config_32(mport, destid, hopcount,
103                                           SPBC_ROUTE_CFG_DESTID, 0x80000000);
104                 for (route_idx = 0; route_idx <= lut_size; route_idx++)
105                         rio_mport_write_config_32(mport, destid, hopcount,
106                                                   SPBC_ROUTE_CFG_PORT,
107                                                   RIO_INVALID_ROUTE);
108         } else {
109                 rio_mport_write_config_32(mport, destid, hopcount,
110                                 SPP_ROUTE_CFG_DESTID(table), 0x80000000);
111                 for (route_idx = 0; route_idx <= lut_size; route_idx++)
112                         rio_mport_write_config_32(mport, destid, hopcount,
113                                 SPP_ROUTE_CFG_PORT(table) , RIO_INVALID_ROUTE);
114         }
115
116         return 0;
117 }
118
119 static int
120 tsi57x_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
121                        u8 sw_domain)
122 {
123         u32 regval;
124
125         /*
126          * Switch domain configuration operates only at global level
127          */
128
129         /* Turn off flat (LUT_512) mode */
130         rio_mport_read_config_32(mport, destid, hopcount,
131                                  TSI578_SP_MODE_GLBL, &regval);
132         rio_mport_write_config_32(mport, destid, hopcount, TSI578_SP_MODE_GLBL,
133                                   regval & ~TSI578_SP_MODE_LUT_512);
134         /* Set switch domain base */
135         rio_mport_write_config_32(mport, destid, hopcount,
136                                   TSI578_GLBL_ROUTE_BASE,
137                                   (u32)(sw_domain << 24));
138         return 0;
139 }
140
141 static int
142 tsi57x_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
143                        u8 *sw_domain)
144 {
145         u32 regval;
146
147         /*
148          * Switch domain configuration operates only at global level
149          */
150         rio_mport_read_config_32(mport, destid, hopcount,
151                                 TSI578_GLBL_ROUTE_BASE, &regval);
152
153         *sw_domain = (u8)(regval >> 24);
154
155         return 0;
156 }
157
158 static int
159 tsi57x_em_init(struct rio_dev *rdev)
160 {
161         u32 regval;
162         int portnum;
163
164         pr_debug("TSI578 %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
165
166         for (portnum = 0;
167              portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) {
168                 /* Make sure that Port-Writes are enabled (for all ports) */
169                 rio_read_config_32(rdev,
170                                 TSI578_SP_MODE(portnum), &regval);
171                 rio_write_config_32(rdev,
172                                 TSI578_SP_MODE(portnum),
173                                 regval & ~TSI578_SP_MODE_PW_DIS);
174
175                 /* Clear all pending interrupts */
176                 rio_read_config_32(rdev,
177                                 rdev->phys_efptr +
178                                         RIO_PORT_N_ERR_STS_CSR(portnum),
179                                 &regval);
180                 rio_write_config_32(rdev,
181                                 rdev->phys_efptr +
182                                         RIO_PORT_N_ERR_STS_CSR(portnum),
183                                 regval & 0x07120214);
184
185                 rio_read_config_32(rdev,
186                                 TSI578_SP_INT_STATUS(portnum), &regval);
187                 rio_write_config_32(rdev,
188                                 TSI578_SP_INT_STATUS(portnum),
189                                 regval & 0x000700bd);
190
191                 /* Enable all interrupts to allow ports to send a port-write */
192                 rio_read_config_32(rdev,
193                                 TSI578_SP_CTL_INDEP(portnum), &regval);
194                 rio_write_config_32(rdev,
195                                 TSI578_SP_CTL_INDEP(portnum),
196                                 regval | 0x000b0000);
197
198                 /* Skip next (odd) port if the current port is in x4 mode */
199                 rio_read_config_32(rdev,
200                                 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
201                                 &regval);
202                 if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4)
203                         portnum++;
204         }
205
206         /* set TVAL = ~50us */
207         rio_write_config_32(rdev,
208                 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x9a << 8);
209
210         return 0;
211 }
212
213 static int
214 tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
215 {
216         struct rio_mport *mport = rdev->net->hport;
217         u32 intstat, err_status;
218         int sendcount, checkcount;
219         u8 route_port;
220         u32 regval;
221
222         rio_read_config_32(rdev,
223                         rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum),
224                         &err_status);
225
226         if ((err_status & RIO_PORT_N_ERR_STS_PORT_OK) &&
227             (err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES |
228                           RIO_PORT_N_ERR_STS_PW_INP_ES))) {
229                 /* Remove any queued packets by locking/unlocking port */
230                 rio_read_config_32(rdev,
231                         rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
232                         &regval);
233                 if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) {
234                         rio_write_config_32(rdev,
235                                 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
236                                 regval | RIO_PORT_N_CTL_LOCKOUT);
237                         udelay(50);
238                         rio_write_config_32(rdev,
239                                 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
240                                 regval);
241                 }
242
243                 /* Read from link maintenance response register to clear
244                  * valid bit
245                  */
246                 rio_read_config_32(rdev,
247                         rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum),
248                         &regval);
249
250                 /* Send a Packet-Not-Accepted/Link-Request-Input-Status control
251                  * symbol to recover from IES/OES
252                  */
253                 sendcount = 3;
254                 while (sendcount) {
255                         rio_write_config_32(rdev,
256                                           TSI578_SP_CS_TX(portnum), 0x40fc8000);
257                         checkcount = 3;
258                         while (checkcount--) {
259                                 udelay(50);
260                                 rio_read_config_32(rdev,
261                                         rdev->phys_efptr +
262                                                 RIO_PORT_N_MNT_RSP_CSR(portnum),
263                                         &regval);
264                                 if (regval & RIO_PORT_N_MNT_RSP_RVAL)
265                                         goto exit_es;
266                         }
267
268                         sendcount--;
269                 }
270         }
271
272 exit_es:
273         /* Clear implementation specific error status bits */
274         rio_read_config_32(rdev, TSI578_SP_INT_STATUS(portnum), &intstat);
275         pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n",
276                  rdev->destid, rdev->hopcount, portnum, intstat);
277
278         if (intstat & 0x10000) {
279                 rio_read_config_32(rdev,
280                                 TSI578_SP_LUT_PEINF(portnum), &regval);
281                 regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24);
282                 route_port = rdev->rswitch->route_table[regval];
283                 pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n",
284                         rio_name(rdev), portnum, regval);
285                 tsi57x_route_add_entry(mport, rdev->destid, rdev->hopcount,
286                                 RIO_GLOBAL_TABLE, regval, route_port);
287         }
288
289         rio_write_config_32(rdev, TSI578_SP_INT_STATUS(portnum),
290                             intstat & 0x000700bd);
291
292         return 0;
293 }
294
295 static int tsi57x_switch_init(struct rio_dev *rdev, int do_enum)
296 {
297         pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
298         rdev->rswitch->add_entry = tsi57x_route_add_entry;
299         rdev->rswitch->get_entry = tsi57x_route_get_entry;
300         rdev->rswitch->clr_table = tsi57x_route_clr_table;
301         rdev->rswitch->set_domain = tsi57x_set_domain;
302         rdev->rswitch->get_domain = tsi57x_get_domain;
303         rdev->rswitch->em_init = tsi57x_em_init;
304         rdev->rswitch->em_handle = tsi57x_em_handler;
305
306         if (do_enum) {
307                 /* Ensure that default routing is disabled on startup */
308                 rio_write_config_32(rdev, RIO_STD_RTE_DEFAULT_PORT,
309                                     RIO_INVALID_ROUTE);
310         }
311
312         return 0;
313 }
314
315 DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI572, tsi57x_switch_init);
316 DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI574, tsi57x_switch_init);
317 DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI577, tsi57x_switch_init);
318 DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI578, tsi57x_switch_init);