PCI: introduce reset_resource()
[linux-2.6.git] / drivers / pci / setup-bus.c
1 /*
2  *      drivers/pci/setup-bus.c
3  *
4  * Extruded from code written by
5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
6  *      David Mosberger (davidm@cs.arizona.edu)
7  *      David Miller (davem@redhat.com)
8  *
9  * Support routines for initializing a PCI subsystem.
10  */
11
12 /*
13  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14  *           PCI-PCI bridges cleanup, sorted resource allocation.
15  * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16  *           Converted to allocation in 3 passes, which gives
17  *           tighter packing. Prefetchable range support.
18  */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
28 #include "pci.h"
29
30 struct resource_list_x {
31         struct resource_list_x *next;
32         struct resource *res;
33         struct pci_dev *dev;
34         resource_size_t start;
35         resource_size_t end;
36         unsigned long flags;
37 };
38
39 #define free_list(type, head) do {                      \
40         struct type *list, *tmp;                        \
41         for (list = (head)->next; list;) {              \
42                 tmp = list;                             \
43                 list = list->next;                      \
44                 kfree(tmp);                             \
45         }                                               \
46         (head)->next = NULL;                            \
47 } while (0)
48
49 static void add_to_failed_list(struct resource_list_x *head,
50                                  struct pci_dev *dev, struct resource *res)
51 {
52         struct resource_list_x *list = head;
53         struct resource_list_x *ln = list->next;
54         struct resource_list_x *tmp;
55
56         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
57         if (!tmp) {
58                 pr_warning("add_to_failed_list: kmalloc() failed!\n");
59                 return;
60         }
61
62         tmp->next = ln;
63         tmp->res = res;
64         tmp->dev = dev;
65         tmp->start = res->start;
66         tmp->end = res->end;
67         tmp->flags = res->flags;
68         list->next = tmp;
69 }
70
71 static void __dev_sort_resources(struct pci_dev *dev,
72                                  struct resource_list *head)
73 {
74         u16 class = dev->class >> 8;
75
76         /* Don't touch classless devices or host bridges or ioapics.  */
77         if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
78                 return;
79
80         /* Don't touch ioapic devices already enabled by firmware */
81         if (class == PCI_CLASS_SYSTEM_PIC) {
82                 u16 command;
83                 pci_read_config_word(dev, PCI_COMMAND, &command);
84                 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
85                         return;
86         }
87
88         pdev_sort_resources(dev, head);
89 }
90
91 static inline void reset_resource(struct resource *res)
92 {
93         res->start = 0;
94         res->end = 0;
95         res->flags = 0;
96 }
97
98 static void __assign_resources_sorted(struct resource_list *head,
99                                  struct resource_list_x *fail_head)
100 {
101         struct resource *res;
102         struct resource_list *list, *tmp;
103         int idx;
104
105         for (list = head->next; list;) {
106                 res = list->res;
107                 idx = res - &list->dev->resource[0];
108
109                 if (pci_assign_resource(list->dev, idx)) {
110                         if (fail_head && !pci_is_root_bus(list->dev->bus)) {
111                                 /*
112                                  * if the failed res is for ROM BAR, and it will
113                                  * be enabled later, don't add it to the list
114                                  */
115                                 if (!((idx == PCI_ROM_RESOURCE) &&
116                                       (!(res->flags & IORESOURCE_ROM_ENABLE))))
117                                         add_to_failed_list(fail_head, list->dev, res);
118                         }
119                         reset_resource(res);
120                 }
121                 tmp = list;
122                 list = list->next;
123                 kfree(tmp);
124         }
125 }
126
127 static void pdev_assign_resources_sorted(struct pci_dev *dev,
128                                  struct resource_list_x *fail_head)
129 {
130         struct resource_list head;
131
132         head.next = NULL;
133         __dev_sort_resources(dev, &head);
134         __assign_resources_sorted(&head, fail_head);
135
136 }
137
138 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
139                                          struct resource_list_x *fail_head)
140 {
141         struct pci_dev *dev;
142         struct resource_list head;
143
144         head.next = NULL;
145         list_for_each_entry(dev, &bus->devices, bus_list)
146                 __dev_sort_resources(dev, &head);
147
148         __assign_resources_sorted(&head, fail_head);
149 }
150
151 void pci_setup_cardbus(struct pci_bus *bus)
152 {
153         struct pci_dev *bridge = bus->self;
154         struct resource *res;
155         struct pci_bus_region region;
156
157         dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
158                  bus->secondary, bus->subordinate);
159
160         res = bus->resource[0];
161         pcibios_resource_to_bus(bridge, &region, res);
162         if (res->flags & IORESOURCE_IO) {
163                 /*
164                  * The IO resource is allocated a range twice as large as it
165                  * would normally need.  This allows us to set both IO regs.
166                  */
167                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
168                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
169                                         region.start);
170                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
171                                         region.end);
172         }
173
174         res = bus->resource[1];
175         pcibios_resource_to_bus(bridge, &region, res);
176         if (res->flags & IORESOURCE_IO) {
177                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
178                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
179                                         region.start);
180                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
181                                         region.end);
182         }
183
184         res = bus->resource[2];
185         pcibios_resource_to_bus(bridge, &region, res);
186         if (res->flags & IORESOURCE_MEM) {
187                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
188                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
189                                         region.start);
190                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
191                                         region.end);
192         }
193
194         res = bus->resource[3];
195         pcibios_resource_to_bus(bridge, &region, res);
196         if (res->flags & IORESOURCE_MEM) {
197                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
198                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
199                                         region.start);
200                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
201                                         region.end);
202         }
203 }
204 EXPORT_SYMBOL(pci_setup_cardbus);
205
206 /* Initialize bridges with base/limit values we have collected.
207    PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
208    requires that if there is no I/O ports or memory behind the
209    bridge, corresponding range must be turned off by writing base
210    value greater than limit to the bridge's base/limit registers.
211
212    Note: care must be taken when updating I/O base/limit registers
213    of bridges which support 32-bit I/O. This update requires two
214    config space writes, so it's quite possible that an I/O window of
215    the bridge will have some undesirable address (e.g. 0) after the
216    first write. Ditto 64-bit prefetchable MMIO.  */
217 static void pci_setup_bridge_io(struct pci_bus *bus)
218 {
219         struct pci_dev *bridge = bus->self;
220         struct resource *res;
221         struct pci_bus_region region;
222         u32 l, io_upper16;
223
224         /* Set up the top and bottom of the PCI I/O segment for this bus. */
225         res = bus->resource[0];
226         pcibios_resource_to_bus(bridge, &region, res);
227         if (res->flags & IORESOURCE_IO) {
228                 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
229                 l &= 0xffff0000;
230                 l |= (region.start >> 8) & 0x00f0;
231                 l |= region.end & 0xf000;
232                 /* Set up upper 16 bits of I/O base/limit. */
233                 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
234                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
235         } else {
236                 /* Clear upper 16 bits of I/O base/limit. */
237                 io_upper16 = 0;
238                 l = 0x00f0;
239                 dev_info(&bridge->dev, "  bridge window [io  disabled]\n");
240         }
241         /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
242         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
243         /* Update lower 16 bits of I/O base/limit. */
244         pci_write_config_dword(bridge, PCI_IO_BASE, l);
245         /* Update upper 16 bits of I/O base/limit. */
246         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
247 }
248
249 static void pci_setup_bridge_mmio(struct pci_bus *bus)
250 {
251         struct pci_dev *bridge = bus->self;
252         struct resource *res;
253         struct pci_bus_region region;
254         u32 l;
255
256         /* Set up the top and bottom of the PCI Memory segment for this bus. */
257         res = bus->resource[1];
258         pcibios_resource_to_bus(bridge, &region, res);
259         if (res->flags & IORESOURCE_MEM) {
260                 l = (region.start >> 16) & 0xfff0;
261                 l |= region.end & 0xfff00000;
262                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
263         } else {
264                 l = 0x0000fff0;
265                 dev_info(&bridge->dev, "  bridge window [mem disabled]\n");
266         }
267         pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
268 }
269
270 static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
271 {
272         struct pci_dev *bridge = bus->self;
273         struct resource *res;
274         struct pci_bus_region region;
275         u32 l, bu, lu;
276
277         /* Clear out the upper 32 bits of PREF limit.
278            If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
279            disables PREF range, which is ok. */
280         pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
281
282         /* Set up PREF base/limit. */
283         bu = lu = 0;
284         res = bus->resource[2];
285         pcibios_resource_to_bus(bridge, &region, res);
286         if (res->flags & IORESOURCE_PREFETCH) {
287                 l = (region.start >> 16) & 0xfff0;
288                 l |= region.end & 0xfff00000;
289                 if (res->flags & IORESOURCE_MEM_64) {
290                         bu = upper_32_bits(region.start);
291                         lu = upper_32_bits(region.end);
292                 }
293                 dev_info(&bridge->dev, "  bridge window %pR\n", res);
294         } else {
295                 l = 0x0000fff0;
296                 dev_info(&bridge->dev, "  bridge window [mem pref disabled]\n");
297         }
298         pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
299
300         /* Set the upper 32 bits of PREF base & limit. */
301         pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
302         pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
303 }
304
305 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
306 {
307         struct pci_dev *bridge = bus->self;
308
309         dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
310                  bus->secondary, bus->subordinate);
311
312         if (type & IORESOURCE_IO)
313                 pci_setup_bridge_io(bus);
314
315         if (type & IORESOURCE_MEM)
316                 pci_setup_bridge_mmio(bus);
317
318         if (type & IORESOURCE_PREFETCH)
319                 pci_setup_bridge_mmio_pref(bus);
320
321         pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
322 }
323
324 static void pci_setup_bridge(struct pci_bus *bus)
325 {
326         unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
327                                   IORESOURCE_PREFETCH;
328
329         __pci_setup_bridge(bus, type);
330 }
331
332 /* Check whether the bridge supports optional I/O and
333    prefetchable memory ranges. If not, the respective
334    base/limit registers must be read-only and read as 0. */
335 static void pci_bridge_check_ranges(struct pci_bus *bus)
336 {
337         u16 io;
338         u32 pmem;
339         struct pci_dev *bridge = bus->self;
340         struct resource *b_res;
341
342         b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
343         b_res[1].flags |= IORESOURCE_MEM;
344
345         pci_read_config_word(bridge, PCI_IO_BASE, &io);
346         if (!io) {
347                 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
348                 pci_read_config_word(bridge, PCI_IO_BASE, &io);
349                 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
350         }
351         if (io)
352                 b_res[0].flags |= IORESOURCE_IO;
353         /*  DECchip 21050 pass 2 errata: the bridge may miss an address
354             disconnect boundary by one PCI data phase.
355             Workaround: do not use prefetching on this device. */
356         if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
357                 return;
358         pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
359         if (!pmem) {
360                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
361                                                0xfff0fff0);
362                 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
363                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
364         }
365         if (pmem) {
366                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
367                 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
368                     PCI_PREF_RANGE_TYPE_64) {
369                         b_res[2].flags |= IORESOURCE_MEM_64;
370                         b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
371                 }
372         }
373
374         /* double check if bridge does support 64 bit pref */
375         if (b_res[2].flags & IORESOURCE_MEM_64) {
376                 u32 mem_base_hi, tmp;
377                 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
378                                          &mem_base_hi);
379                 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
380                                                0xffffffff);
381                 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
382                 if (!tmp)
383                         b_res[2].flags &= ~IORESOURCE_MEM_64;
384                 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
385                                        mem_base_hi);
386         }
387 }
388
389 /* Helper function for sizing routines: find first available
390    bus resource of a given type. Note: we intentionally skip
391    the bus resources which have already been assigned (that is,
392    have non-NULL parent resource). */
393 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
394 {
395         int i;
396         struct resource *r;
397         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
398                                   IORESOURCE_PREFETCH;
399
400         pci_bus_for_each_resource(bus, r, i) {
401                 if (r == &ioport_resource || r == &iomem_resource)
402                         continue;
403                 if (r && (r->flags & type_mask) == type && !r->parent)
404                         return r;
405         }
406         return NULL;
407 }
408
409 static resource_size_t calculate_iosize(resource_size_t size,
410                 resource_size_t min_size,
411                 resource_size_t size1,
412                 resource_size_t old_size,
413                 resource_size_t align)
414 {
415         if (size < min_size)
416                 size = min_size;
417         if (old_size == 1 )
418                 old_size = 0;
419         /* To be fixed in 2.5: we should have sort of HAVE_ISA
420            flag in the struct pci_bus. */
421 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
422         size = (size & 0xff) + ((size & ~0xffUL) << 2);
423 #endif
424         size = ALIGN(size + size1, align);
425         if (size < old_size)
426                 size = old_size;
427         return size;
428 }
429
430 static resource_size_t calculate_memsize(resource_size_t size,
431                 resource_size_t min_size,
432                 resource_size_t size1,
433                 resource_size_t old_size,
434                 resource_size_t align)
435 {
436         if (size < min_size)
437                 size = min_size;
438         if (old_size == 1 )
439                 old_size = 0;
440         if (size < old_size)
441                 size = old_size;
442         size = ALIGN(size + size1, align);
443         return size;
444 }
445
446 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
447    since these windows have 4K granularity and the IO ranges
448    of non-bridge PCI devices are limited to 256 bytes.
449    We must be careful with the ISA aliasing though. */
450 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size)
451 {
452         struct pci_dev *dev;
453         struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
454         unsigned long size = 0, size1 = 0;
455
456         if (!b_res)
457                 return;
458
459         list_for_each_entry(dev, &bus->devices, bus_list) {
460                 int i;
461
462                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
463                         struct resource *r = &dev->resource[i];
464                         unsigned long r_size;
465
466                         if (r->parent || !(r->flags & IORESOURCE_IO))
467                                 continue;
468                         r_size = resource_size(r);
469
470                         if (r_size < 0x400)
471                                 /* Might be re-aligned for ISA */
472                                 size += r_size;
473                         else
474                                 size1 += r_size;
475                 }
476         }
477         size = calculate_iosize(size, min_size, size1,
478                         resource_size(b_res), 4096);
479         if (!size) {
480                 if (b_res->start || b_res->end)
481                         dev_info(&bus->self->dev, "disabling bridge window "
482                                  "%pR to [bus %02x-%02x] (unused)\n", b_res,
483                                  bus->secondary, bus->subordinate);
484                 b_res->flags = 0;
485                 return;
486         }
487         /* Alignment of the IO window is always 4K */
488         b_res->start = 4096;
489         b_res->end = b_res->start + size - 1;
490         b_res->flags |= IORESOURCE_STARTALIGN;
491 }
492
493 /* Calculate the size of the bus and minimal alignment which
494    guarantees that all child resources fit in this size. */
495 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
496                          unsigned long type, resource_size_t min_size)
497 {
498         struct pci_dev *dev;
499         resource_size_t min_align, align, size;
500         resource_size_t aligns[12];     /* Alignments from 1Mb to 2Gb */
501         int order, max_order;
502         struct resource *b_res = find_free_bus_resource(bus, type);
503         unsigned int mem64_mask = 0;
504
505         if (!b_res)
506                 return 0;
507
508         memset(aligns, 0, sizeof(aligns));
509         max_order = 0;
510         size = 0;
511
512         mem64_mask = b_res->flags & IORESOURCE_MEM_64;
513         b_res->flags &= ~IORESOURCE_MEM_64;
514
515         list_for_each_entry(dev, &bus->devices, bus_list) {
516                 int i;
517
518                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
519                         struct resource *r = &dev->resource[i];
520                         resource_size_t r_size;
521
522                         if (r->parent || (r->flags & mask) != type)
523                                 continue;
524                         r_size = resource_size(r);
525                         /* For bridges size != alignment */
526                         align = pci_resource_alignment(dev, r);
527                         order = __ffs(align) - 20;
528                         if (order > 11) {
529                                 dev_warn(&dev->dev, "disabling BAR %d: %pR "
530                                          "(bad alignment %#llx)\n", i, r,
531                                          (unsigned long long) align);
532                                 r->flags = 0;
533                                 continue;
534                         }
535                         size += r_size;
536                         if (order < 0)
537                                 order = 0;
538                         /* Exclude ranges with size > align from
539                            calculation of the alignment. */
540                         if (r_size == align)
541                                 aligns[order] += align;
542                         if (order > max_order)
543                                 max_order = order;
544                         mem64_mask &= r->flags & IORESOURCE_MEM_64;
545                 }
546         }
547         align = 0;
548         min_align = 0;
549         for (order = 0; order <= max_order; order++) {
550                 resource_size_t align1 = 1;
551
552                 align1 <<= (order + 20);
553
554                 if (!align)
555                         min_align = align1;
556                 else if (ALIGN(align + min_align, min_align) < align1)
557                         min_align = align1 >> 1;
558                 align += aligns[order];
559         }
560         size = calculate_memsize(size, min_size, 0, resource_size(b_res), align);
561         if (!size) {
562                 if (b_res->start || b_res->end)
563                         dev_info(&bus->self->dev, "disabling bridge window "
564                                  "%pR to [bus %02x-%02x] (unused)\n", b_res,
565                                  bus->secondary, bus->subordinate);
566                 b_res->flags = 0;
567                 return 1;
568         }
569         b_res->start = min_align;
570         b_res->end = size + min_align - 1;
571         b_res->flags |= IORESOURCE_STARTALIGN;
572         b_res->flags |= mem64_mask;
573         return 1;
574 }
575
576 static void pci_bus_size_cardbus(struct pci_bus *bus)
577 {
578         struct pci_dev *bridge = bus->self;
579         struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
580         u16 ctrl;
581
582         /*
583          * Reserve some resources for CardBus.  We reserve
584          * a fixed amount of bus space for CardBus bridges.
585          */
586         b_res[0].start = 0;
587         b_res[0].end = pci_cardbus_io_size - 1;
588         b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
589
590         b_res[1].start = 0;
591         b_res[1].end = pci_cardbus_io_size - 1;
592         b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
593
594         /*
595          * Check whether prefetchable memory is supported
596          * by this bridge.
597          */
598         pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
599         if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
600                 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
601                 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
602                 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
603         }
604
605         /*
606          * If we have prefetchable memory support, allocate
607          * two regions.  Otherwise, allocate one region of
608          * twice the size.
609          */
610         if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
611                 b_res[2].start = 0;
612                 b_res[2].end = pci_cardbus_mem_size - 1;
613                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
614
615                 b_res[3].start = 0;
616                 b_res[3].end = pci_cardbus_mem_size - 1;
617                 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
618         } else {
619                 b_res[3].start = 0;
620                 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
621                 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
622         }
623 }
624
625 void __ref pci_bus_size_bridges(struct pci_bus *bus)
626 {
627         struct pci_dev *dev;
628         unsigned long mask, prefmask;
629         resource_size_t min_mem_size = 0, min_io_size = 0;
630
631         list_for_each_entry(dev, &bus->devices, bus_list) {
632                 struct pci_bus *b = dev->subordinate;
633                 if (!b)
634                         continue;
635
636                 switch (dev->class >> 8) {
637                 case PCI_CLASS_BRIDGE_CARDBUS:
638                         pci_bus_size_cardbus(b);
639                         break;
640
641                 case PCI_CLASS_BRIDGE_PCI:
642                 default:
643                         pci_bus_size_bridges(b);
644                         break;
645                 }
646         }
647
648         /* The root bus? */
649         if (!bus->self)
650                 return;
651
652         switch (bus->self->class >> 8) {
653         case PCI_CLASS_BRIDGE_CARDBUS:
654                 /* don't size cardbuses yet. */
655                 break;
656
657         case PCI_CLASS_BRIDGE_PCI:
658                 pci_bridge_check_ranges(bus);
659                 if (bus->self->is_hotplug_bridge) {
660                         min_io_size  = pci_hotplug_io_size;
661                         min_mem_size = pci_hotplug_mem_size;
662                 }
663         default:
664                 pbus_size_io(bus, min_io_size);
665                 /* If the bridge supports prefetchable range, size it
666                    separately. If it doesn't, or its prefetchable window
667                    has already been allocated by arch code, try
668                    non-prefetchable range for both types of PCI memory
669                    resources. */
670                 mask = IORESOURCE_MEM;
671                 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
672                 if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size))
673                         mask = prefmask; /* Success, size non-prefetch only. */
674                 else
675                         min_mem_size += min_mem_size;
676                 pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size);
677                 break;
678         }
679 }
680 EXPORT_SYMBOL(pci_bus_size_bridges);
681
682 static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
683                                          struct resource_list_x *fail_head)
684 {
685         struct pci_bus *b;
686         struct pci_dev *dev;
687
688         pbus_assign_resources_sorted(bus, fail_head);
689
690         list_for_each_entry(dev, &bus->devices, bus_list) {
691                 b = dev->subordinate;
692                 if (!b)
693                         continue;
694
695                 __pci_bus_assign_resources(b, fail_head);
696
697                 switch (dev->class >> 8) {
698                 case PCI_CLASS_BRIDGE_PCI:
699                         if (!pci_is_enabled(dev))
700                                 pci_setup_bridge(b);
701                         break;
702
703                 case PCI_CLASS_BRIDGE_CARDBUS:
704                         pci_setup_cardbus(b);
705                         break;
706
707                 default:
708                         dev_info(&dev->dev, "not setting up bridge for bus "
709                                  "%04x:%02x\n", pci_domain_nr(b), b->number);
710                         break;
711                 }
712         }
713 }
714
715 void __ref pci_bus_assign_resources(const struct pci_bus *bus)
716 {
717         __pci_bus_assign_resources(bus, NULL);
718 }
719 EXPORT_SYMBOL(pci_bus_assign_resources);
720
721 static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
722                                          struct resource_list_x *fail_head)
723 {
724         struct pci_bus *b;
725
726         pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
727
728         b = bridge->subordinate;
729         if (!b)
730                 return;
731
732         __pci_bus_assign_resources(b, fail_head);
733
734         switch (bridge->class >> 8) {
735         case PCI_CLASS_BRIDGE_PCI:
736                 pci_setup_bridge(b);
737                 break;
738
739         case PCI_CLASS_BRIDGE_CARDBUS:
740                 pci_setup_cardbus(b);
741                 break;
742
743         default:
744                 dev_info(&bridge->dev, "not setting up bridge for bus "
745                          "%04x:%02x\n", pci_domain_nr(b), b->number);
746                 break;
747         }
748 }
749 static void pci_bridge_release_resources(struct pci_bus *bus,
750                                           unsigned long type)
751 {
752         int idx;
753         bool changed = false;
754         struct pci_dev *dev;
755         struct resource *r;
756         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
757                                   IORESOURCE_PREFETCH;
758
759         dev = bus->self;
760         for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
761              idx++) {
762                 r = &dev->resource[idx];
763                 if ((r->flags & type_mask) != type)
764                         continue;
765                 if (!r->parent)
766                         continue;
767                 /*
768                  * if there are children under that, we should release them
769                  *  all
770                  */
771                 release_child_resources(r);
772                 if (!release_resource(r)) {
773                         dev_printk(KERN_DEBUG, &dev->dev,
774                                  "resource %d %pR released\n", idx, r);
775                         /* keep the old size */
776                         r->end = resource_size(r) - 1;
777                         r->start = 0;
778                         r->flags = 0;
779                         changed = true;
780                 }
781         }
782
783         if (changed) {
784                 /* avoiding touch the one without PREF */
785                 if (type & IORESOURCE_PREFETCH)
786                         type = IORESOURCE_PREFETCH;
787                 __pci_setup_bridge(bus, type);
788         }
789 }
790
791 enum release_type {
792         leaf_only,
793         whole_subtree,
794 };
795 /*
796  * try to release pci bridge resources that is from leaf bridge,
797  * so we can allocate big new one later
798  */
799 static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
800                                                    unsigned long type,
801                                                    enum release_type rel_type)
802 {
803         struct pci_dev *dev;
804         bool is_leaf_bridge = true;
805
806         list_for_each_entry(dev, &bus->devices, bus_list) {
807                 struct pci_bus *b = dev->subordinate;
808                 if (!b)
809                         continue;
810
811                 is_leaf_bridge = false;
812
813                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
814                         continue;
815
816                 if (rel_type == whole_subtree)
817                         pci_bus_release_bridge_resources(b, type,
818                                                  whole_subtree);
819         }
820
821         if (pci_is_root_bus(bus))
822                 return;
823
824         if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
825                 return;
826
827         if ((rel_type == whole_subtree) || is_leaf_bridge)
828                 pci_bridge_release_resources(bus, type);
829 }
830
831 static void pci_bus_dump_res(struct pci_bus *bus)
832 {
833         struct resource *res;
834         int i;
835
836         pci_bus_for_each_resource(bus, res, i) {
837                 if (!res || !res->end || !res->flags)
838                         continue;
839
840                 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
841         }
842 }
843
844 static void pci_bus_dump_resources(struct pci_bus *bus)
845 {
846         struct pci_bus *b;
847         struct pci_dev *dev;
848
849
850         pci_bus_dump_res(bus);
851
852         list_for_each_entry(dev, &bus->devices, bus_list) {
853                 b = dev->subordinate;
854                 if (!b)
855                         continue;
856
857                 pci_bus_dump_resources(b);
858         }
859 }
860
861 void __init
862 pci_assign_unassigned_resources(void)
863 {
864         struct pci_bus *bus;
865
866         /* Depth first, calculate sizes and alignments of all
867            subordinate buses. */
868         list_for_each_entry(bus, &pci_root_buses, node) {
869                 pci_bus_size_bridges(bus);
870         }
871         /* Depth last, allocate resources and update the hardware. */
872         list_for_each_entry(bus, &pci_root_buses, node) {
873                 pci_bus_assign_resources(bus);
874                 pci_enable_bridges(bus);
875         }
876
877         /* dump the resource on buses */
878         list_for_each_entry(bus, &pci_root_buses, node) {
879                 pci_bus_dump_resources(bus);
880         }
881 }
882
883 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
884 {
885         struct pci_bus *parent = bridge->subordinate;
886         int tried_times = 0;
887         struct resource_list_x head, *list;
888         int retval;
889         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
890                                   IORESOURCE_PREFETCH;
891
892         head.next = NULL;
893
894 again:
895         pci_bus_size_bridges(parent);
896         __pci_bridge_assign_resources(bridge, &head);
897
898         tried_times++;
899
900         if (!head.next)
901                 goto enable_all;
902
903         if (tried_times >= 2) {
904                 /* still fail, don't need to try more */
905                 free_list(resource_list_x, &head);
906                 goto enable_all;
907         }
908
909         printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
910                          tried_times + 1);
911
912         /*
913          * Try to release leaf bridge's resources that doesn't fit resource of
914          * child device under that bridge
915          */
916         for (list = head.next; list;) {
917                 struct pci_bus *bus = list->dev->bus;
918                 unsigned long flags = list->flags;
919
920                 pci_bus_release_bridge_resources(bus, flags & type_mask,
921                                                  whole_subtree);
922                 list = list->next;
923         }
924         /* restore size and flags */
925         for (list = head.next; list;) {
926                 struct resource *res = list->res;
927
928                 res->start = list->start;
929                 res->end = list->end;
930                 res->flags = list->flags;
931                 if (list->dev->subordinate)
932                         res->flags = 0;
933
934                 list = list->next;
935         }
936         free_list(resource_list_x, &head);
937
938         goto again;
939
940 enable_all:
941         retval = pci_reenable_device(bridge);
942         pci_set_master(bridge);
943         pci_enable_bridges(parent);
944 }
945 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);