intel-iommu: Disable PMRs after we enable translation, not before
[linux-2.6.git] / drivers / pci / intel-iommu.c
1 /*
2  * Copyright (c) 2006, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15  * Place - Suite 330, Boston, MA 02111-1307 USA.
16  *
17  * Copyright (C) 2006-2008 Intel Corporation
18  * Author: Ashok Raj <ashok.raj@intel.com>
19  * Author: Shaohua Li <shaohua.li@intel.com>
20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21  * Author: Fenghua Yu <fenghua.yu@intel.com>
22  */
23
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <linux/dmi.h>
41 #include <asm/cacheflush.h>
42 #include <asm/iommu.h>
43 #include "pci.h"
44
45 #define ROOT_SIZE               VTD_PAGE_SIZE
46 #define CONTEXT_SIZE            VTD_PAGE_SIZE
47
48 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
49 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50
51 #define IOAPIC_RANGE_START      (0xfee00000)
52 #define IOAPIC_RANGE_END        (0xfeefffff)
53 #define IOVA_START_ADDR         (0x1000)
54
55 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56
57 #define MAX_AGAW_WIDTH 64
58
59 #define __DOMAIN_MAX_PFN(gaw)  ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
60 #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
61
62 /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
63    to match. That way, we can use 'unsigned long' for PFNs with impunity. */
64 #define DOMAIN_MAX_PFN(gaw)     ((unsigned long) min_t(uint64_t, \
65                                 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
66 #define DOMAIN_MAX_ADDR(gaw)    (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
67
68 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
69 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
70 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
71
72
73 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
74    are never going to work. */
75 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
76 {
77         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
78 }
79
80 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
81 {
82         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
83 }
84 static inline unsigned long page_to_dma_pfn(struct page *pg)
85 {
86         return mm_to_dma_pfn(page_to_pfn(pg));
87 }
88 static inline unsigned long virt_to_dma_pfn(void *p)
89 {
90         return page_to_dma_pfn(virt_to_page(p));
91 }
92
93 /* global iommu list, set NULL for ignored DMAR units */
94 static struct intel_iommu **g_iommus;
95
96 static int rwbf_quirk;
97
98 /*
99  * 0: Present
100  * 1-11: Reserved
101  * 12-63: Context Ptr (12 - (haw-1))
102  * 64-127: Reserved
103  */
104 struct root_entry {
105         u64     val;
106         u64     rsvd1;
107 };
108 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
109 static inline bool root_present(struct root_entry *root)
110 {
111         return (root->val & 1);
112 }
113 static inline void set_root_present(struct root_entry *root)
114 {
115         root->val |= 1;
116 }
117 static inline void set_root_value(struct root_entry *root, unsigned long value)
118 {
119         root->val |= value & VTD_PAGE_MASK;
120 }
121
122 static inline struct context_entry *
123 get_context_addr_from_root(struct root_entry *root)
124 {
125         return (struct context_entry *)
126                 (root_present(root)?phys_to_virt(
127                 root->val & VTD_PAGE_MASK) :
128                 NULL);
129 }
130
131 /*
132  * low 64 bits:
133  * 0: present
134  * 1: fault processing disable
135  * 2-3: translation type
136  * 12-63: address space root
137  * high 64 bits:
138  * 0-2: address width
139  * 3-6: aval
140  * 8-23: domain id
141  */
142 struct context_entry {
143         u64 lo;
144         u64 hi;
145 };
146
147 static inline bool context_present(struct context_entry *context)
148 {
149         return (context->lo & 1);
150 }
151 static inline void context_set_present(struct context_entry *context)
152 {
153         context->lo |= 1;
154 }
155
156 static inline void context_set_fault_enable(struct context_entry *context)
157 {
158         context->lo &= (((u64)-1) << 2) | 1;
159 }
160
161 static inline void context_set_translation_type(struct context_entry *context,
162                                                 unsigned long value)
163 {
164         context->lo &= (((u64)-1) << 4) | 3;
165         context->lo |= (value & 3) << 2;
166 }
167
168 static inline void context_set_address_root(struct context_entry *context,
169                                             unsigned long value)
170 {
171         context->lo |= value & VTD_PAGE_MASK;
172 }
173
174 static inline void context_set_address_width(struct context_entry *context,
175                                              unsigned long value)
176 {
177         context->hi |= value & 7;
178 }
179
180 static inline void context_set_domain_id(struct context_entry *context,
181                                          unsigned long value)
182 {
183         context->hi |= (value & ((1 << 16) - 1)) << 8;
184 }
185
186 static inline void context_clear_entry(struct context_entry *context)
187 {
188         context->lo = 0;
189         context->hi = 0;
190 }
191
192 /*
193  * 0: readable
194  * 1: writable
195  * 2-6: reserved
196  * 7: super page
197  * 8-10: available
198  * 11: snoop behavior
199  * 12-63: Host physcial address
200  */
201 struct dma_pte {
202         u64 val;
203 };
204
205 static inline void dma_clear_pte(struct dma_pte *pte)
206 {
207         pte->val = 0;
208 }
209
210 static inline void dma_set_pte_readable(struct dma_pte *pte)
211 {
212         pte->val |= DMA_PTE_READ;
213 }
214
215 static inline void dma_set_pte_writable(struct dma_pte *pte)
216 {
217         pte->val |= DMA_PTE_WRITE;
218 }
219
220 static inline void dma_set_pte_snp(struct dma_pte *pte)
221 {
222         pte->val |= DMA_PTE_SNP;
223 }
224
225 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
226 {
227         pte->val = (pte->val & ~3) | (prot & 3);
228 }
229
230 static inline u64 dma_pte_addr(struct dma_pte *pte)
231 {
232 #ifdef CONFIG_64BIT
233         return pte->val & VTD_PAGE_MASK;
234 #else
235         /* Must have a full atomic 64-bit read */
236         return  __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
237 #endif
238 }
239
240 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
241 {
242         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
243 }
244
245 static inline bool dma_pte_present(struct dma_pte *pte)
246 {
247         return (pte->val & 3) != 0;
248 }
249
250 static inline int first_pte_in_page(struct dma_pte *pte)
251 {
252         return !((unsigned long)pte & ~VTD_PAGE_MASK);
253 }
254
255 /*
256  * This domain is a statically identity mapping domain.
257  *      1. This domain creats a static 1:1 mapping to all usable memory.
258  *      2. It maps to each iommu if successful.
259  *      3. Each iommu mapps to this domain if successful.
260  */
261 static struct dmar_domain *si_domain;
262 static int hw_pass_through = 1;
263
264 /* devices under the same p2p bridge are owned in one domain */
265 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
266
267 /* domain represents a virtual machine, more than one devices
268  * across iommus may be owned in one domain, e.g. kvm guest.
269  */
270 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
271
272 /* si_domain contains mulitple devices */
273 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
274
275 struct dmar_domain {
276         int     id;                     /* domain id */
277         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
278
279         struct list_head devices;       /* all devices' list */
280         struct iova_domain iovad;       /* iova's that belong to this domain */
281
282         struct dma_pte  *pgd;           /* virtual address */
283         int             gaw;            /* max guest address width */
284
285         /* adjusted guest address width, 0 is level 2 30-bit */
286         int             agaw;
287
288         int             flags;          /* flags to find out type of domain */
289
290         int             iommu_coherency;/* indicate coherency of iommu access */
291         int             iommu_snooping; /* indicate snooping control feature*/
292         int             iommu_count;    /* reference count of iommu */
293         spinlock_t      iommu_lock;     /* protect iommu set in domain */
294         u64             max_addr;       /* maximum mapped address */
295 };
296
297 /* PCI domain-device relationship */
298 struct device_domain_info {
299         struct list_head link;  /* link to domain siblings */
300         struct list_head global; /* link to global list */
301         int segment;            /* PCI domain */
302         u8 bus;                 /* PCI bus number */
303         u8 devfn;               /* PCI devfn number */
304         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
305         struct intel_iommu *iommu; /* IOMMU used by this device */
306         struct dmar_domain *domain; /* pointer to domain */
307 };
308
309 static void flush_unmaps_timeout(unsigned long data);
310
311 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
312
313 #define HIGH_WATER_MARK 250
314 struct deferred_flush_tables {
315         int next;
316         struct iova *iova[HIGH_WATER_MARK];
317         struct dmar_domain *domain[HIGH_WATER_MARK];
318 };
319
320 static struct deferred_flush_tables *deferred_flush;
321
322 /* bitmap for indexing intel_iommus */
323 static int g_num_of_iommus;
324
325 static DEFINE_SPINLOCK(async_umap_flush_lock);
326 static LIST_HEAD(unmaps_to_do);
327
328 static int timer_on;
329 static long list_size;
330
331 static void domain_remove_dev_info(struct dmar_domain *domain);
332
333 #ifdef CONFIG_DMAR_DEFAULT_ON
334 int dmar_disabled = 0;
335 #else
336 int dmar_disabled = 1;
337 #endif /*CONFIG_DMAR_DEFAULT_ON*/
338
339 static int __initdata dmar_map_gfx = 1;
340 static int dmar_forcedac;
341 static int intel_iommu_strict;
342
343 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
344 static DEFINE_SPINLOCK(device_domain_lock);
345 static LIST_HEAD(device_domain_list);
346
347 static struct iommu_ops intel_iommu_ops;
348
349 static int __init intel_iommu_setup(char *str)
350 {
351         if (!str)
352                 return -EINVAL;
353         while (*str) {
354                 if (!strncmp(str, "on", 2)) {
355                         dmar_disabled = 0;
356                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
357                 } else if (!strncmp(str, "off", 3)) {
358                         dmar_disabled = 1;
359                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
360                 } else if (!strncmp(str, "igfx_off", 8)) {
361                         dmar_map_gfx = 0;
362                         printk(KERN_INFO
363                                 "Intel-IOMMU: disable GFX device mapping\n");
364                 } else if (!strncmp(str, "forcedac", 8)) {
365                         printk(KERN_INFO
366                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
367                         dmar_forcedac = 1;
368                 } else if (!strncmp(str, "strict", 6)) {
369                         printk(KERN_INFO
370                                 "Intel-IOMMU: disable batched IOTLB flush\n");
371                         intel_iommu_strict = 1;
372                 }
373
374                 str += strcspn(str, ",");
375                 while (*str == ',')
376                         str++;
377         }
378         return 0;
379 }
380 __setup("intel_iommu=", intel_iommu_setup);
381
382 static struct kmem_cache *iommu_domain_cache;
383 static struct kmem_cache *iommu_devinfo_cache;
384 static struct kmem_cache *iommu_iova_cache;
385
386 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
387 {
388         unsigned int flags;
389         void *vaddr;
390
391         /* trying to avoid low memory issues */
392         flags = current->flags & PF_MEMALLOC;
393         current->flags |= PF_MEMALLOC;
394         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
395         current->flags &= (~PF_MEMALLOC | flags);
396         return vaddr;
397 }
398
399
400 static inline void *alloc_pgtable_page(void)
401 {
402         unsigned int flags;
403         void *vaddr;
404
405         /* trying to avoid low memory issues */
406         flags = current->flags & PF_MEMALLOC;
407         current->flags |= PF_MEMALLOC;
408         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
409         current->flags &= (~PF_MEMALLOC | flags);
410         return vaddr;
411 }
412
413 static inline void free_pgtable_page(void *vaddr)
414 {
415         free_page((unsigned long)vaddr);
416 }
417
418 static inline void *alloc_domain_mem(void)
419 {
420         return iommu_kmem_cache_alloc(iommu_domain_cache);
421 }
422
423 static void free_domain_mem(void *vaddr)
424 {
425         kmem_cache_free(iommu_domain_cache, vaddr);
426 }
427
428 static inline void * alloc_devinfo_mem(void)
429 {
430         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
431 }
432
433 static inline void free_devinfo_mem(void *vaddr)
434 {
435         kmem_cache_free(iommu_devinfo_cache, vaddr);
436 }
437
438 struct iova *alloc_iova_mem(void)
439 {
440         return iommu_kmem_cache_alloc(iommu_iova_cache);
441 }
442
443 void free_iova_mem(struct iova *iova)
444 {
445         kmem_cache_free(iommu_iova_cache, iova);
446 }
447
448
449 static inline int width_to_agaw(int width);
450
451 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
452 {
453         unsigned long sagaw;
454         int agaw = -1;
455
456         sagaw = cap_sagaw(iommu->cap);
457         for (agaw = width_to_agaw(max_gaw);
458              agaw >= 0; agaw--) {
459                 if (test_bit(agaw, &sagaw))
460                         break;
461         }
462
463         return agaw;
464 }
465
466 /*
467  * Calculate max SAGAW for each iommu.
468  */
469 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
470 {
471         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
472 }
473
474 /*
475  * calculate agaw for each iommu.
476  * "SAGAW" may be different across iommus, use a default agaw, and
477  * get a supported less agaw for iommus that don't support the default agaw.
478  */
479 int iommu_calculate_agaw(struct intel_iommu *iommu)
480 {
481         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
482 }
483
484 /* This functionin only returns single iommu in a domain */
485 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
486 {
487         int iommu_id;
488
489         /* si_domain and vm domain should not get here. */
490         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
491         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
492
493         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
494         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
495                 return NULL;
496
497         return g_iommus[iommu_id];
498 }
499
500 static void domain_update_iommu_coherency(struct dmar_domain *domain)
501 {
502         int i;
503
504         domain->iommu_coherency = 1;
505
506         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
507         for (; i < g_num_of_iommus; ) {
508                 if (!ecap_coherent(g_iommus[i]->ecap)) {
509                         domain->iommu_coherency = 0;
510                         break;
511                 }
512                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
513         }
514 }
515
516 static void domain_update_iommu_snooping(struct dmar_domain *domain)
517 {
518         int i;
519
520         domain->iommu_snooping = 1;
521
522         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
523         for (; i < g_num_of_iommus; ) {
524                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
525                         domain->iommu_snooping = 0;
526                         break;
527                 }
528                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
529         }
530 }
531
532 /* Some capabilities may be different across iommus */
533 static void domain_update_iommu_cap(struct dmar_domain *domain)
534 {
535         domain_update_iommu_coherency(domain);
536         domain_update_iommu_snooping(domain);
537 }
538
539 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
540 {
541         struct dmar_drhd_unit *drhd = NULL;
542         int i;
543
544         for_each_drhd_unit(drhd) {
545                 if (drhd->ignored)
546                         continue;
547                 if (segment != drhd->segment)
548                         continue;
549
550                 for (i = 0; i < drhd->devices_cnt; i++) {
551                         if (drhd->devices[i] &&
552                             drhd->devices[i]->bus->number == bus &&
553                             drhd->devices[i]->devfn == devfn)
554                                 return drhd->iommu;
555                         if (drhd->devices[i] &&
556                             drhd->devices[i]->subordinate &&
557                             drhd->devices[i]->subordinate->number <= bus &&
558                             drhd->devices[i]->subordinate->subordinate >= bus)
559                                 return drhd->iommu;
560                 }
561
562                 if (drhd->include_all)
563                         return drhd->iommu;
564         }
565
566         return NULL;
567 }
568
569 static void domain_flush_cache(struct dmar_domain *domain,
570                                void *addr, int size)
571 {
572         if (!domain->iommu_coherency)
573                 clflush_cache_range(addr, size);
574 }
575
576 /* Gets context entry for a given bus and devfn */
577 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
578                 u8 bus, u8 devfn)
579 {
580         struct root_entry *root;
581         struct context_entry *context;
582         unsigned long phy_addr;
583         unsigned long flags;
584
585         spin_lock_irqsave(&iommu->lock, flags);
586         root = &iommu->root_entry[bus];
587         context = get_context_addr_from_root(root);
588         if (!context) {
589                 context = (struct context_entry *)alloc_pgtable_page();
590                 if (!context) {
591                         spin_unlock_irqrestore(&iommu->lock, flags);
592                         return NULL;
593                 }
594                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
595                 phy_addr = virt_to_phys((void *)context);
596                 set_root_value(root, phy_addr);
597                 set_root_present(root);
598                 __iommu_flush_cache(iommu, root, sizeof(*root));
599         }
600         spin_unlock_irqrestore(&iommu->lock, flags);
601         return &context[devfn];
602 }
603
604 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
605 {
606         struct root_entry *root;
607         struct context_entry *context;
608         int ret;
609         unsigned long flags;
610
611         spin_lock_irqsave(&iommu->lock, flags);
612         root = &iommu->root_entry[bus];
613         context = get_context_addr_from_root(root);
614         if (!context) {
615                 ret = 0;
616                 goto out;
617         }
618         ret = context_present(&context[devfn]);
619 out:
620         spin_unlock_irqrestore(&iommu->lock, flags);
621         return ret;
622 }
623
624 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
625 {
626         struct root_entry *root;
627         struct context_entry *context;
628         unsigned long flags;
629
630         spin_lock_irqsave(&iommu->lock, flags);
631         root = &iommu->root_entry[bus];
632         context = get_context_addr_from_root(root);
633         if (context) {
634                 context_clear_entry(&context[devfn]);
635                 __iommu_flush_cache(iommu, &context[devfn], \
636                         sizeof(*context));
637         }
638         spin_unlock_irqrestore(&iommu->lock, flags);
639 }
640
641 static void free_context_table(struct intel_iommu *iommu)
642 {
643         struct root_entry *root;
644         int i;
645         unsigned long flags;
646         struct context_entry *context;
647
648         spin_lock_irqsave(&iommu->lock, flags);
649         if (!iommu->root_entry) {
650                 goto out;
651         }
652         for (i = 0; i < ROOT_ENTRY_NR; i++) {
653                 root = &iommu->root_entry[i];
654                 context = get_context_addr_from_root(root);
655                 if (context)
656                         free_pgtable_page(context);
657         }
658         free_pgtable_page(iommu->root_entry);
659         iommu->root_entry = NULL;
660 out:
661         spin_unlock_irqrestore(&iommu->lock, flags);
662 }
663
664 /* page table handling */
665 #define LEVEL_STRIDE            (9)
666 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
667
668 static inline int agaw_to_level(int agaw)
669 {
670         return agaw + 2;
671 }
672
673 static inline int agaw_to_width(int agaw)
674 {
675         return 30 + agaw * LEVEL_STRIDE;
676
677 }
678
679 static inline int width_to_agaw(int width)
680 {
681         return (width - 30) / LEVEL_STRIDE;
682 }
683
684 static inline unsigned int level_to_offset_bits(int level)
685 {
686         return (level - 1) * LEVEL_STRIDE;
687 }
688
689 static inline int pfn_level_offset(unsigned long pfn, int level)
690 {
691         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
692 }
693
694 static inline unsigned long level_mask(int level)
695 {
696         return -1UL << level_to_offset_bits(level);
697 }
698
699 static inline unsigned long level_size(int level)
700 {
701         return 1UL << level_to_offset_bits(level);
702 }
703
704 static inline unsigned long align_to_level(unsigned long pfn, int level)
705 {
706         return (pfn + level_size(level) - 1) & level_mask(level);
707 }
708
709 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
710                                       unsigned long pfn)
711 {
712         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
713         struct dma_pte *parent, *pte = NULL;
714         int level = agaw_to_level(domain->agaw);
715         int offset;
716
717         BUG_ON(!domain->pgd);
718         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
719         parent = domain->pgd;
720
721         while (level > 0) {
722                 void *tmp_page;
723
724                 offset = pfn_level_offset(pfn, level);
725                 pte = &parent[offset];
726                 if (level == 1)
727                         break;
728
729                 if (!dma_pte_present(pte)) {
730                         uint64_t pteval;
731
732                         tmp_page = alloc_pgtable_page();
733
734                         if (!tmp_page)
735                                 return NULL;
736
737                         domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
738                         pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
739                         if (cmpxchg64(&pte->val, 0ULL, pteval)) {
740                                 /* Someone else set it while we were thinking; use theirs. */
741                                 free_pgtable_page(tmp_page);
742                         } else {
743                                 dma_pte_addr(pte);
744                                 domain_flush_cache(domain, pte, sizeof(*pte));
745                         }
746                 }
747                 parent = phys_to_virt(dma_pte_addr(pte));
748                 level--;
749         }
750
751         return pte;
752 }
753
754 /* return address's pte at specific level */
755 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
756                                          unsigned long pfn,
757                                          int level)
758 {
759         struct dma_pte *parent, *pte = NULL;
760         int total = agaw_to_level(domain->agaw);
761         int offset;
762
763         parent = domain->pgd;
764         while (level <= total) {
765                 offset = pfn_level_offset(pfn, total);
766                 pte = &parent[offset];
767                 if (level == total)
768                         return pte;
769
770                 if (!dma_pte_present(pte))
771                         break;
772                 parent = phys_to_virt(dma_pte_addr(pte));
773                 total--;
774         }
775         return NULL;
776 }
777
778 /* clear last level pte, a tlb flush should be followed */
779 static void dma_pte_clear_range(struct dmar_domain *domain,
780                                 unsigned long start_pfn,
781                                 unsigned long last_pfn)
782 {
783         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
784         struct dma_pte *first_pte, *pte;
785
786         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
787         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
788         BUG_ON(start_pfn > last_pfn);
789
790         /* we don't need lock here; nobody else touches the iova range */
791         do {
792                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
793                 if (!pte) {
794                         start_pfn = align_to_level(start_pfn + 1, 2);
795                         continue;
796                 }
797                 do { 
798                         dma_clear_pte(pte);
799                         start_pfn++;
800                         pte++;
801                 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
802
803                 domain_flush_cache(domain, first_pte,
804                                    (void *)pte - (void *)first_pte);
805
806         } while (start_pfn && start_pfn <= last_pfn);
807 }
808
809 /* free page table pages. last level pte should already be cleared */
810 static void dma_pte_free_pagetable(struct dmar_domain *domain,
811                                    unsigned long start_pfn,
812                                    unsigned long last_pfn)
813 {
814         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
815         struct dma_pte *first_pte, *pte;
816         int total = agaw_to_level(domain->agaw);
817         int level;
818         unsigned long tmp;
819
820         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
821         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
822         BUG_ON(start_pfn > last_pfn);
823
824         /* We don't need lock here; nobody else touches the iova range */
825         level = 2;
826         while (level <= total) {
827                 tmp = align_to_level(start_pfn, level);
828
829                 /* If we can't even clear one PTE at this level, we're done */
830                 if (tmp + level_size(level) - 1 > last_pfn)
831                         return;
832
833                 do {
834                         first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
835                         if (!pte) {
836                                 tmp = align_to_level(tmp + 1, level + 1);
837                                 continue;
838                         }
839                         do {
840                                 if (dma_pte_present(pte)) {
841                                         free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
842                                         dma_clear_pte(pte);
843                                 }
844                                 pte++;
845                                 tmp += level_size(level);
846                         } while (!first_pte_in_page(pte) &&
847                                  tmp + level_size(level) - 1 <= last_pfn);
848
849                         domain_flush_cache(domain, first_pte,
850                                            (void *)pte - (void *)first_pte);
851                         
852                 } while (tmp && tmp + level_size(level) - 1 <= last_pfn);
853                 level++;
854         }
855         /* free pgd */
856         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
857                 free_pgtable_page(domain->pgd);
858                 domain->pgd = NULL;
859         }
860 }
861
862 /* iommu handling */
863 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
864 {
865         struct root_entry *root;
866         unsigned long flags;
867
868         root = (struct root_entry *)alloc_pgtable_page();
869         if (!root)
870                 return -ENOMEM;
871
872         __iommu_flush_cache(iommu, root, ROOT_SIZE);
873
874         spin_lock_irqsave(&iommu->lock, flags);
875         iommu->root_entry = root;
876         spin_unlock_irqrestore(&iommu->lock, flags);
877
878         return 0;
879 }
880
881 static void iommu_set_root_entry(struct intel_iommu *iommu)
882 {
883         void *addr;
884         u32 sts;
885         unsigned long flag;
886
887         addr = iommu->root_entry;
888
889         spin_lock_irqsave(&iommu->register_lock, flag);
890         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
891
892         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
893
894         /* Make sure hardware complete it */
895         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
896                       readl, (sts & DMA_GSTS_RTPS), sts);
897
898         spin_unlock_irqrestore(&iommu->register_lock, flag);
899 }
900
901 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
902 {
903         u32 val;
904         unsigned long flag;
905
906         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
907                 return;
908
909         spin_lock_irqsave(&iommu->register_lock, flag);
910         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
911
912         /* Make sure hardware complete it */
913         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
914                       readl, (!(val & DMA_GSTS_WBFS)), val);
915
916         spin_unlock_irqrestore(&iommu->register_lock, flag);
917 }
918
919 /* return value determine if we need a write buffer flush */
920 static void __iommu_flush_context(struct intel_iommu *iommu,
921                                   u16 did, u16 source_id, u8 function_mask,
922                                   u64 type)
923 {
924         u64 val = 0;
925         unsigned long flag;
926
927         switch (type) {
928         case DMA_CCMD_GLOBAL_INVL:
929                 val = DMA_CCMD_GLOBAL_INVL;
930                 break;
931         case DMA_CCMD_DOMAIN_INVL:
932                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
933                 break;
934         case DMA_CCMD_DEVICE_INVL:
935                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
936                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
937                 break;
938         default:
939                 BUG();
940         }
941         val |= DMA_CCMD_ICC;
942
943         spin_lock_irqsave(&iommu->register_lock, flag);
944         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
945
946         /* Make sure hardware complete it */
947         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
948                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
949
950         spin_unlock_irqrestore(&iommu->register_lock, flag);
951 }
952
953 /* return value determine if we need a write buffer flush */
954 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
955                                 u64 addr, unsigned int size_order, u64 type)
956 {
957         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
958         u64 val = 0, val_iva = 0;
959         unsigned long flag;
960
961         switch (type) {
962         case DMA_TLB_GLOBAL_FLUSH:
963                 /* global flush doesn't need set IVA_REG */
964                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
965                 break;
966         case DMA_TLB_DSI_FLUSH:
967                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
968                 break;
969         case DMA_TLB_PSI_FLUSH:
970                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
971                 /* Note: always flush non-leaf currently */
972                 val_iva = size_order | addr;
973                 break;
974         default:
975                 BUG();
976         }
977         /* Note: set drain read/write */
978 #if 0
979         /*
980          * This is probably to be super secure.. Looks like we can
981          * ignore it without any impact.
982          */
983         if (cap_read_drain(iommu->cap))
984                 val |= DMA_TLB_READ_DRAIN;
985 #endif
986         if (cap_write_drain(iommu->cap))
987                 val |= DMA_TLB_WRITE_DRAIN;
988
989         spin_lock_irqsave(&iommu->register_lock, flag);
990         /* Note: Only uses first TLB reg currently */
991         if (val_iva)
992                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
993         dmar_writeq(iommu->reg + tlb_offset + 8, val);
994
995         /* Make sure hardware complete it */
996         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
997                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
998
999         spin_unlock_irqrestore(&iommu->register_lock, flag);
1000
1001         /* check IOTLB invalidation granularity */
1002         if (DMA_TLB_IAIG(val) == 0)
1003                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1004         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1005                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
1006                         (unsigned long long)DMA_TLB_IIRG(type),
1007                         (unsigned long long)DMA_TLB_IAIG(val));
1008 }
1009
1010 static struct device_domain_info *iommu_support_dev_iotlb(
1011         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1012 {
1013         int found = 0;
1014         unsigned long flags;
1015         struct device_domain_info *info;
1016         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1017
1018         if (!ecap_dev_iotlb_support(iommu->ecap))
1019                 return NULL;
1020
1021         if (!iommu->qi)
1022                 return NULL;
1023
1024         spin_lock_irqsave(&device_domain_lock, flags);
1025         list_for_each_entry(info, &domain->devices, link)
1026                 if (info->bus == bus && info->devfn == devfn) {
1027                         found = 1;
1028                         break;
1029                 }
1030         spin_unlock_irqrestore(&device_domain_lock, flags);
1031
1032         if (!found || !info->dev)
1033                 return NULL;
1034
1035         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1036                 return NULL;
1037
1038         if (!dmar_find_matched_atsr_unit(info->dev))
1039                 return NULL;
1040
1041         info->iommu = iommu;
1042
1043         return info;
1044 }
1045
1046 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1047 {
1048         if (!info)
1049                 return;
1050
1051         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1052 }
1053
1054 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1055 {
1056         if (!info->dev || !pci_ats_enabled(info->dev))
1057                 return;
1058
1059         pci_disable_ats(info->dev);
1060 }
1061
1062 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1063                                   u64 addr, unsigned mask)
1064 {
1065         u16 sid, qdep;
1066         unsigned long flags;
1067         struct device_domain_info *info;
1068
1069         spin_lock_irqsave(&device_domain_lock, flags);
1070         list_for_each_entry(info, &domain->devices, link) {
1071                 if (!info->dev || !pci_ats_enabled(info->dev))
1072                         continue;
1073
1074                 sid = info->bus << 8 | info->devfn;
1075                 qdep = pci_ats_queue_depth(info->dev);
1076                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1077         }
1078         spin_unlock_irqrestore(&device_domain_lock, flags);
1079 }
1080
1081 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1082                                   unsigned long pfn, unsigned int pages)
1083 {
1084         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1085         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1086
1087         BUG_ON(pages == 0);
1088
1089         /*
1090          * Fallback to domain selective flush if no PSI support or the size is
1091          * too big.
1092          * PSI requires page size to be 2 ^ x, and the base address is naturally
1093          * aligned to the size
1094          */
1095         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1096                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1097                                                 DMA_TLB_DSI_FLUSH);
1098         else
1099                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1100                                                 DMA_TLB_PSI_FLUSH);
1101
1102         /*
1103          * In caching mode, domain ID 0 is reserved for non-present to present
1104          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1105          */
1106         if (!cap_caching_mode(iommu->cap) || did)
1107                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1108 }
1109
1110 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1111 {
1112         u32 pmen;
1113         unsigned long flags;
1114
1115         spin_lock_irqsave(&iommu->register_lock, flags);
1116         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1117         pmen &= ~DMA_PMEN_EPM;
1118         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1119
1120         /* wait for the protected region status bit to clear */
1121         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1122                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1123
1124         spin_unlock_irqrestore(&iommu->register_lock, flags);
1125 }
1126
1127 static int iommu_enable_translation(struct intel_iommu *iommu)
1128 {
1129         u32 sts;
1130         unsigned long flags;
1131
1132         spin_lock_irqsave(&iommu->register_lock, flags);
1133         iommu->gcmd |= DMA_GCMD_TE;
1134         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1135
1136         /* Make sure hardware complete it */
1137         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1138                       readl, (sts & DMA_GSTS_TES), sts);
1139
1140         spin_unlock_irqrestore(&iommu->register_lock, flags);
1141         return 0;
1142 }
1143
1144 static int iommu_disable_translation(struct intel_iommu *iommu)
1145 {
1146         u32 sts;
1147         unsigned long flag;
1148
1149         spin_lock_irqsave(&iommu->register_lock, flag);
1150         iommu->gcmd &= ~DMA_GCMD_TE;
1151         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1152
1153         /* Make sure hardware complete it */
1154         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1155                       readl, (!(sts & DMA_GSTS_TES)), sts);
1156
1157         spin_unlock_irqrestore(&iommu->register_lock, flag);
1158         return 0;
1159 }
1160
1161
1162 static int iommu_init_domains(struct intel_iommu *iommu)
1163 {
1164         unsigned long ndomains;
1165         unsigned long nlongs;
1166
1167         ndomains = cap_ndoms(iommu->cap);
1168         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1169         nlongs = BITS_TO_LONGS(ndomains);
1170
1171         spin_lock_init(&iommu->lock);
1172
1173         /* TBD: there might be 64K domains,
1174          * consider other allocation for future chip
1175          */
1176         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1177         if (!iommu->domain_ids) {
1178                 printk(KERN_ERR "Allocating domain id array failed\n");
1179                 return -ENOMEM;
1180         }
1181         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1182                         GFP_KERNEL);
1183         if (!iommu->domains) {
1184                 printk(KERN_ERR "Allocating domain array failed\n");
1185                 return -ENOMEM;
1186         }
1187
1188         /*
1189          * if Caching mode is set, then invalid translations are tagged
1190          * with domainid 0. Hence we need to pre-allocate it.
1191          */
1192         if (cap_caching_mode(iommu->cap))
1193                 set_bit(0, iommu->domain_ids);
1194         return 0;
1195 }
1196
1197
1198 static void domain_exit(struct dmar_domain *domain);
1199 static void vm_domain_exit(struct dmar_domain *domain);
1200
1201 void free_dmar_iommu(struct intel_iommu *iommu)
1202 {
1203         struct dmar_domain *domain;
1204         int i;
1205         unsigned long flags;
1206
1207         if ((iommu->domains) && (iommu->domain_ids)) {
1208                 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1209                 for (; i < cap_ndoms(iommu->cap); ) {
1210                         domain = iommu->domains[i];
1211                         clear_bit(i, iommu->domain_ids);
1212
1213                         spin_lock_irqsave(&domain->iommu_lock, flags);
1214                         if (--domain->iommu_count == 0) {
1215                                 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1216                                         vm_domain_exit(domain);
1217                                 else
1218                                         domain_exit(domain);
1219                         }
1220                         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1221
1222                         i = find_next_bit(iommu->domain_ids,
1223                                 cap_ndoms(iommu->cap), i+1);
1224                 }
1225         }
1226
1227         if (iommu->gcmd & DMA_GCMD_TE)
1228                 iommu_disable_translation(iommu);
1229
1230         if (iommu->irq) {
1231                 set_irq_data(iommu->irq, NULL);
1232                 /* This will mask the irq */
1233                 free_irq(iommu->irq, iommu);
1234                 destroy_irq(iommu->irq);
1235         }
1236
1237         kfree(iommu->domains);
1238         kfree(iommu->domain_ids);
1239
1240         g_iommus[iommu->seq_id] = NULL;
1241
1242         /* if all iommus are freed, free g_iommus */
1243         for (i = 0; i < g_num_of_iommus; i++) {
1244                 if (g_iommus[i])
1245                         break;
1246         }
1247
1248         if (i == g_num_of_iommus)
1249                 kfree(g_iommus);
1250
1251         /* free context mapping */
1252         free_context_table(iommu);
1253 }
1254
1255 static struct dmar_domain *alloc_domain(void)
1256 {
1257         struct dmar_domain *domain;
1258
1259         domain = alloc_domain_mem();
1260         if (!domain)
1261                 return NULL;
1262
1263         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1264         domain->flags = 0;
1265
1266         return domain;
1267 }
1268
1269 static int iommu_attach_domain(struct dmar_domain *domain,
1270                                struct intel_iommu *iommu)
1271 {
1272         int num;
1273         unsigned long ndomains;
1274         unsigned long flags;
1275
1276         ndomains = cap_ndoms(iommu->cap);
1277
1278         spin_lock_irqsave(&iommu->lock, flags);
1279
1280         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1281         if (num >= ndomains) {
1282                 spin_unlock_irqrestore(&iommu->lock, flags);
1283                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1284                 return -ENOMEM;
1285         }
1286
1287         domain->id = num;
1288         set_bit(num, iommu->domain_ids);
1289         set_bit(iommu->seq_id, &domain->iommu_bmp);
1290         iommu->domains[num] = domain;
1291         spin_unlock_irqrestore(&iommu->lock, flags);
1292
1293         return 0;
1294 }
1295
1296 static void iommu_detach_domain(struct dmar_domain *domain,
1297                                 struct intel_iommu *iommu)
1298 {
1299         unsigned long flags;
1300         int num, ndomains;
1301         int found = 0;
1302
1303         spin_lock_irqsave(&iommu->lock, flags);
1304         ndomains = cap_ndoms(iommu->cap);
1305         num = find_first_bit(iommu->domain_ids, ndomains);
1306         for (; num < ndomains; ) {
1307                 if (iommu->domains[num] == domain) {
1308                         found = 1;
1309                         break;
1310                 }
1311                 num = find_next_bit(iommu->domain_ids,
1312                                     cap_ndoms(iommu->cap), num+1);
1313         }
1314
1315         if (found) {
1316                 clear_bit(num, iommu->domain_ids);
1317                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1318                 iommu->domains[num] = NULL;
1319         }
1320         spin_unlock_irqrestore(&iommu->lock, flags);
1321 }
1322
1323 static struct iova_domain reserved_iova_list;
1324 static struct lock_class_key reserved_rbtree_key;
1325
1326 static void dmar_init_reserved_ranges(void)
1327 {
1328         struct pci_dev *pdev = NULL;
1329         struct iova *iova;
1330         int i;
1331
1332         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1333
1334         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1335                 &reserved_rbtree_key);
1336
1337         /* IOAPIC ranges shouldn't be accessed by DMA */
1338         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1339                 IOVA_PFN(IOAPIC_RANGE_END));
1340         if (!iova)
1341                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1342
1343         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1344         for_each_pci_dev(pdev) {
1345                 struct resource *r;
1346
1347                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1348                         r = &pdev->resource[i];
1349                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1350                                 continue;
1351                         iova = reserve_iova(&reserved_iova_list,
1352                                             IOVA_PFN(r->start),
1353                                             IOVA_PFN(r->end));
1354                         if (!iova)
1355                                 printk(KERN_ERR "Reserve iova failed\n");
1356                 }
1357         }
1358
1359 }
1360
1361 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1362 {
1363         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1364 }
1365
1366 static inline int guestwidth_to_adjustwidth(int gaw)
1367 {
1368         int agaw;
1369         int r = (gaw - 12) % 9;
1370
1371         if (r == 0)
1372                 agaw = gaw;
1373         else
1374                 agaw = gaw + 9 - r;
1375         if (agaw > 64)
1376                 agaw = 64;
1377         return agaw;
1378 }
1379
1380 static int domain_init(struct dmar_domain *domain, int guest_width)
1381 {
1382         struct intel_iommu *iommu;
1383         int adjust_width, agaw;
1384         unsigned long sagaw;
1385
1386         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1387         spin_lock_init(&domain->iommu_lock);
1388
1389         domain_reserve_special_ranges(domain);
1390
1391         /* calculate AGAW */
1392         iommu = domain_get_iommu(domain);
1393         if (guest_width > cap_mgaw(iommu->cap))
1394                 guest_width = cap_mgaw(iommu->cap);
1395         domain->gaw = guest_width;
1396         adjust_width = guestwidth_to_adjustwidth(guest_width);
1397         agaw = width_to_agaw(adjust_width);
1398         sagaw = cap_sagaw(iommu->cap);
1399         if (!test_bit(agaw, &sagaw)) {
1400                 /* hardware doesn't support it, choose a bigger one */
1401                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1402                 agaw = find_next_bit(&sagaw, 5, agaw);
1403                 if (agaw >= 5)
1404                         return -ENODEV;
1405         }
1406         domain->agaw = agaw;
1407         INIT_LIST_HEAD(&domain->devices);
1408
1409         if (ecap_coherent(iommu->ecap))
1410                 domain->iommu_coherency = 1;
1411         else
1412                 domain->iommu_coherency = 0;
1413
1414         if (ecap_sc_support(iommu->ecap))
1415                 domain->iommu_snooping = 1;
1416         else
1417                 domain->iommu_snooping = 0;
1418
1419         domain->iommu_count = 1;
1420
1421         /* always allocate the top pgd */
1422         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1423         if (!domain->pgd)
1424                 return -ENOMEM;
1425         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1426         return 0;
1427 }
1428
1429 static void domain_exit(struct dmar_domain *domain)
1430 {
1431         struct dmar_drhd_unit *drhd;
1432         struct intel_iommu *iommu;
1433
1434         /* Domain 0 is reserved, so dont process it */
1435         if (!domain)
1436                 return;
1437
1438         domain_remove_dev_info(domain);
1439         /* destroy iovas */
1440         put_iova_domain(&domain->iovad);
1441
1442         /* clear ptes */
1443         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1444
1445         /* free page tables */
1446         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1447
1448         for_each_active_iommu(iommu, drhd)
1449                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1450                         iommu_detach_domain(domain, iommu);
1451
1452         free_domain_mem(domain);
1453 }
1454
1455 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1456                                  u8 bus, u8 devfn, int translation)
1457 {
1458         struct context_entry *context;
1459         unsigned long flags;
1460         struct intel_iommu *iommu;
1461         struct dma_pte *pgd;
1462         unsigned long num;
1463         unsigned long ndomains;
1464         int id;
1465         int agaw;
1466         struct device_domain_info *info = NULL;
1467
1468         pr_debug("Set context mapping for %02x:%02x.%d\n",
1469                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1470
1471         BUG_ON(!domain->pgd);
1472         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1473                translation != CONTEXT_TT_MULTI_LEVEL);
1474
1475         iommu = device_to_iommu(segment, bus, devfn);
1476         if (!iommu)
1477                 return -ENODEV;
1478
1479         context = device_to_context_entry(iommu, bus, devfn);
1480         if (!context)
1481                 return -ENOMEM;
1482         spin_lock_irqsave(&iommu->lock, flags);
1483         if (context_present(context)) {
1484                 spin_unlock_irqrestore(&iommu->lock, flags);
1485                 return 0;
1486         }
1487
1488         id = domain->id;
1489         pgd = domain->pgd;
1490
1491         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1492             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1493                 int found = 0;
1494
1495                 /* find an available domain id for this device in iommu */
1496                 ndomains = cap_ndoms(iommu->cap);
1497                 num = find_first_bit(iommu->domain_ids, ndomains);
1498                 for (; num < ndomains; ) {
1499                         if (iommu->domains[num] == domain) {
1500                                 id = num;
1501                                 found = 1;
1502                                 break;
1503                         }
1504                         num = find_next_bit(iommu->domain_ids,
1505                                             cap_ndoms(iommu->cap), num+1);
1506                 }
1507
1508                 if (found == 0) {
1509                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1510                         if (num >= ndomains) {
1511                                 spin_unlock_irqrestore(&iommu->lock, flags);
1512                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1513                                 return -EFAULT;
1514                         }
1515
1516                         set_bit(num, iommu->domain_ids);
1517                         iommu->domains[num] = domain;
1518                         id = num;
1519                 }
1520
1521                 /* Skip top levels of page tables for
1522                  * iommu which has less agaw than default.
1523                  */
1524                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1525                         pgd = phys_to_virt(dma_pte_addr(pgd));
1526                         if (!dma_pte_present(pgd)) {
1527                                 spin_unlock_irqrestore(&iommu->lock, flags);
1528                                 return -ENOMEM;
1529                         }
1530                 }
1531         }
1532
1533         context_set_domain_id(context, id);
1534
1535         if (translation != CONTEXT_TT_PASS_THROUGH) {
1536                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1537                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1538                                      CONTEXT_TT_MULTI_LEVEL;
1539         }
1540         /*
1541          * In pass through mode, AW must be programmed to indicate the largest
1542          * AGAW value supported by hardware. And ASR is ignored by hardware.
1543          */
1544         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1545                 context_set_address_width(context, iommu->msagaw);
1546         else {
1547                 context_set_address_root(context, virt_to_phys(pgd));
1548                 context_set_address_width(context, iommu->agaw);
1549         }
1550
1551         context_set_translation_type(context, translation);
1552         context_set_fault_enable(context);
1553         context_set_present(context);
1554         domain_flush_cache(domain, context, sizeof(*context));
1555
1556         /*
1557          * It's a non-present to present mapping. If hardware doesn't cache
1558          * non-present entry we only need to flush the write-buffer. If the
1559          * _does_ cache non-present entries, then it does so in the special
1560          * domain #0, which we have to flush:
1561          */
1562         if (cap_caching_mode(iommu->cap)) {
1563                 iommu->flush.flush_context(iommu, 0,
1564                                            (((u16)bus) << 8) | devfn,
1565                                            DMA_CCMD_MASK_NOBIT,
1566                                            DMA_CCMD_DEVICE_INVL);
1567                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1568         } else {
1569                 iommu_flush_write_buffer(iommu);
1570         }
1571         iommu_enable_dev_iotlb(info);
1572         spin_unlock_irqrestore(&iommu->lock, flags);
1573
1574         spin_lock_irqsave(&domain->iommu_lock, flags);
1575         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1576                 domain->iommu_count++;
1577                 domain_update_iommu_cap(domain);
1578         }
1579         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1580         return 0;
1581 }
1582
1583 static int
1584 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1585                         int translation)
1586 {
1587         int ret;
1588         struct pci_dev *tmp, *parent;
1589
1590         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1591                                          pdev->bus->number, pdev->devfn,
1592                                          translation);
1593         if (ret)
1594                 return ret;
1595
1596         /* dependent device mapping */
1597         tmp = pci_find_upstream_pcie_bridge(pdev);
1598         if (!tmp)
1599                 return 0;
1600         /* Secondary interface's bus number and devfn 0 */
1601         parent = pdev->bus->self;
1602         while (parent != tmp) {
1603                 ret = domain_context_mapping_one(domain,
1604                                                  pci_domain_nr(parent->bus),
1605                                                  parent->bus->number,
1606                                                  parent->devfn, translation);
1607                 if (ret)
1608                         return ret;
1609                 parent = parent->bus->self;
1610         }
1611         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1612                 return domain_context_mapping_one(domain,
1613                                         pci_domain_nr(tmp->subordinate),
1614                                         tmp->subordinate->number, 0,
1615                                         translation);
1616         else /* this is a legacy PCI bridge */
1617                 return domain_context_mapping_one(domain,
1618                                                   pci_domain_nr(tmp->bus),
1619                                                   tmp->bus->number,
1620                                                   tmp->devfn,
1621                                                   translation);
1622 }
1623
1624 static int domain_context_mapped(struct pci_dev *pdev)
1625 {
1626         int ret;
1627         struct pci_dev *tmp, *parent;
1628         struct intel_iommu *iommu;
1629
1630         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1631                                 pdev->devfn);
1632         if (!iommu)
1633                 return -ENODEV;
1634
1635         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1636         if (!ret)
1637                 return ret;
1638         /* dependent device mapping */
1639         tmp = pci_find_upstream_pcie_bridge(pdev);
1640         if (!tmp)
1641                 return ret;
1642         /* Secondary interface's bus number and devfn 0 */
1643         parent = pdev->bus->self;
1644         while (parent != tmp) {
1645                 ret = device_context_mapped(iommu, parent->bus->number,
1646                                             parent->devfn);
1647                 if (!ret)
1648                         return ret;
1649                 parent = parent->bus->self;
1650         }
1651         if (tmp->is_pcie)
1652                 return device_context_mapped(iommu, tmp->subordinate->number,
1653                                              0);
1654         else
1655                 return device_context_mapped(iommu, tmp->bus->number,
1656                                              tmp->devfn);
1657 }
1658
1659 /* Returns a number of VTD pages, but aligned to MM page size */
1660 static inline unsigned long aligned_nrpages(unsigned long host_addr,
1661                                             size_t size)
1662 {
1663         host_addr &= ~PAGE_MASK;
1664         return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1665 }
1666
1667 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1668                             struct scatterlist *sg, unsigned long phys_pfn,
1669                             unsigned long nr_pages, int prot)
1670 {
1671         struct dma_pte *first_pte = NULL, *pte = NULL;
1672         phys_addr_t uninitialized_var(pteval);
1673         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1674         unsigned long sg_res;
1675
1676         BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1677
1678         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1679                 return -EINVAL;
1680
1681         prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1682
1683         if (sg)
1684                 sg_res = 0;
1685         else {
1686                 sg_res = nr_pages + 1;
1687                 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1688         }
1689
1690         while (nr_pages--) {
1691                 uint64_t tmp;
1692
1693                 if (!sg_res) {
1694                         sg_res = aligned_nrpages(sg->offset, sg->length);
1695                         sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1696                         sg->dma_length = sg->length;
1697                         pteval = page_to_phys(sg_page(sg)) | prot;
1698                 }
1699                 if (!pte) {
1700                         first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1701                         if (!pte)
1702                                 return -ENOMEM;
1703                 }
1704                 /* We don't need lock here, nobody else
1705                  * touches the iova range
1706                  */
1707                 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1708                 if (tmp) {
1709                         static int dumps = 5;
1710                         printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1711                                iov_pfn, tmp, (unsigned long long)pteval);
1712                         if (dumps) {
1713                                 dumps--;
1714                                 debug_dma_dump_mappings(NULL);
1715                         }
1716                         WARN_ON(1);
1717                 }
1718                 pte++;
1719                 if (!nr_pages || first_pte_in_page(pte)) {
1720                         domain_flush_cache(domain, first_pte,
1721                                            (void *)pte - (void *)first_pte);
1722                         pte = NULL;
1723                 }
1724                 iov_pfn++;
1725                 pteval += VTD_PAGE_SIZE;
1726                 sg_res--;
1727                 if (!sg_res)
1728                         sg = sg_next(sg);
1729         }
1730         return 0;
1731 }
1732
1733 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1734                                     struct scatterlist *sg, unsigned long nr_pages,
1735                                     int prot)
1736 {
1737         return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1738 }
1739
1740 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1741                                      unsigned long phys_pfn, unsigned long nr_pages,
1742                                      int prot)
1743 {
1744         return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1745 }
1746
1747 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1748 {
1749         if (!iommu)
1750                 return;
1751
1752         clear_context_table(iommu, bus, devfn);
1753         iommu->flush.flush_context(iommu, 0, 0, 0,
1754                                            DMA_CCMD_GLOBAL_INVL);
1755         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1756 }
1757
1758 static void domain_remove_dev_info(struct dmar_domain *domain)
1759 {
1760         struct device_domain_info *info;
1761         unsigned long flags;
1762         struct intel_iommu *iommu;
1763
1764         spin_lock_irqsave(&device_domain_lock, flags);
1765         while (!list_empty(&domain->devices)) {
1766                 info = list_entry(domain->devices.next,
1767                         struct device_domain_info, link);
1768                 list_del(&info->link);
1769                 list_del(&info->global);
1770                 if (info->dev)
1771                         info->dev->dev.archdata.iommu = NULL;
1772                 spin_unlock_irqrestore(&device_domain_lock, flags);
1773
1774                 iommu_disable_dev_iotlb(info);
1775                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1776                 iommu_detach_dev(iommu, info->bus, info->devfn);
1777                 free_devinfo_mem(info);
1778
1779                 spin_lock_irqsave(&device_domain_lock, flags);
1780         }
1781         spin_unlock_irqrestore(&device_domain_lock, flags);
1782 }
1783
1784 /*
1785  * find_domain
1786  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1787  */
1788 static struct dmar_domain *
1789 find_domain(struct pci_dev *pdev)
1790 {
1791         struct device_domain_info *info;
1792
1793         /* No lock here, assumes no domain exit in normal case */
1794         info = pdev->dev.archdata.iommu;
1795         if (info)
1796                 return info->domain;
1797         return NULL;
1798 }
1799
1800 /* domain is initialized */
1801 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1802 {
1803         struct dmar_domain *domain, *found = NULL;
1804         struct intel_iommu *iommu;
1805         struct dmar_drhd_unit *drhd;
1806         struct device_domain_info *info, *tmp;
1807         struct pci_dev *dev_tmp;
1808         unsigned long flags;
1809         int bus = 0, devfn = 0;
1810         int segment;
1811         int ret;
1812
1813         domain = find_domain(pdev);
1814         if (domain)
1815                 return domain;
1816
1817         segment = pci_domain_nr(pdev->bus);
1818
1819         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1820         if (dev_tmp) {
1821                 if (dev_tmp->is_pcie) {
1822                         bus = dev_tmp->subordinate->number;
1823                         devfn = 0;
1824                 } else {
1825                         bus = dev_tmp->bus->number;
1826                         devfn = dev_tmp->devfn;
1827                 }
1828                 spin_lock_irqsave(&device_domain_lock, flags);
1829                 list_for_each_entry(info, &device_domain_list, global) {
1830                         if (info->segment == segment &&
1831                             info->bus == bus && info->devfn == devfn) {
1832                                 found = info->domain;
1833                                 break;
1834                         }
1835                 }
1836                 spin_unlock_irqrestore(&device_domain_lock, flags);
1837                 /* pcie-pci bridge already has a domain, uses it */
1838                 if (found) {
1839                         domain = found;
1840                         goto found_domain;
1841                 }
1842         }
1843
1844         domain = alloc_domain();
1845         if (!domain)
1846                 goto error;
1847
1848         /* Allocate new domain for the device */
1849         drhd = dmar_find_matched_drhd_unit(pdev);
1850         if (!drhd) {
1851                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1852                         pci_name(pdev));
1853                 return NULL;
1854         }
1855         iommu = drhd->iommu;
1856
1857         ret = iommu_attach_domain(domain, iommu);
1858         if (ret) {
1859                 domain_exit(domain);
1860                 goto error;
1861         }
1862
1863         if (domain_init(domain, gaw)) {
1864                 domain_exit(domain);
1865                 goto error;
1866         }
1867
1868         /* register pcie-to-pci device */
1869         if (dev_tmp) {
1870                 info = alloc_devinfo_mem();
1871                 if (!info) {
1872                         domain_exit(domain);
1873                         goto error;
1874                 }
1875                 info->segment = segment;
1876                 info->bus = bus;
1877                 info->devfn = devfn;
1878                 info->dev = NULL;
1879                 info->domain = domain;
1880                 /* This domain is shared by devices under p2p bridge */
1881                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1882
1883                 /* pcie-to-pci bridge already has a domain, uses it */
1884                 found = NULL;
1885                 spin_lock_irqsave(&device_domain_lock, flags);
1886                 list_for_each_entry(tmp, &device_domain_list, global) {
1887                         if (tmp->segment == segment &&
1888                             tmp->bus == bus && tmp->devfn == devfn) {
1889                                 found = tmp->domain;
1890                                 break;
1891                         }
1892                 }
1893                 if (found) {
1894                         free_devinfo_mem(info);
1895                         domain_exit(domain);
1896                         domain = found;
1897                 } else {
1898                         list_add(&info->link, &domain->devices);
1899                         list_add(&info->global, &device_domain_list);
1900                 }
1901                 spin_unlock_irqrestore(&device_domain_lock, flags);
1902         }
1903
1904 found_domain:
1905         info = alloc_devinfo_mem();
1906         if (!info)
1907                 goto error;
1908         info->segment = segment;
1909         info->bus = pdev->bus->number;
1910         info->devfn = pdev->devfn;
1911         info->dev = pdev;
1912         info->domain = domain;
1913         spin_lock_irqsave(&device_domain_lock, flags);
1914         /* somebody is fast */
1915         found = find_domain(pdev);
1916         if (found != NULL) {
1917                 spin_unlock_irqrestore(&device_domain_lock, flags);
1918                 if (found != domain) {
1919                         domain_exit(domain);
1920                         domain = found;
1921                 }
1922                 free_devinfo_mem(info);
1923                 return domain;
1924         }
1925         list_add(&info->link, &domain->devices);
1926         list_add(&info->global, &device_domain_list);
1927         pdev->dev.archdata.iommu = info;
1928         spin_unlock_irqrestore(&device_domain_lock, flags);
1929         return domain;
1930 error:
1931         /* recheck it here, maybe others set it */
1932         return find_domain(pdev);
1933 }
1934
1935 static int iommu_identity_mapping;
1936
1937 static int iommu_domain_identity_map(struct dmar_domain *domain,
1938                                      unsigned long long start,
1939                                      unsigned long long end)
1940 {
1941         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1942         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1943
1944         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1945                           dma_to_mm_pfn(last_vpfn))) {
1946                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1947                 return -ENOMEM;
1948         }
1949
1950         pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1951                  start, end, domain->id);
1952         /*
1953          * RMRR range might have overlap with physical memory range,
1954          * clear it first
1955          */
1956         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1957
1958         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1959                                   last_vpfn - first_vpfn + 1,
1960                                   DMA_PTE_READ|DMA_PTE_WRITE);
1961 }
1962
1963 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1964                                       unsigned long long start,
1965                                       unsigned long long end)
1966 {
1967         struct dmar_domain *domain;
1968         int ret;
1969
1970         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1971         if (!domain)
1972                 return -ENOMEM;
1973
1974         /* For _hardware_ passthrough, don't bother. But for software
1975            passthrough, we do it anyway -- it may indicate a memory
1976            range which is reserved in E820, so which didn't get set
1977            up to start with in si_domain */
1978         if (domain == si_domain && hw_pass_through) {
1979                 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
1980                        pci_name(pdev), start, end);
1981                 return 0;
1982         }
1983
1984         printk(KERN_INFO
1985                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1986                pci_name(pdev), start, end);
1987         
1988         if (end >> agaw_to_width(domain->agaw)) {
1989                 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
1990                      "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
1991                      agaw_to_width(domain->agaw),
1992                      dmi_get_system_info(DMI_BIOS_VENDOR),
1993                      dmi_get_system_info(DMI_BIOS_VERSION),
1994                      dmi_get_system_info(DMI_PRODUCT_VERSION));
1995                 ret = -EIO;
1996                 goto error;
1997         }
1998
1999         ret = iommu_domain_identity_map(domain, start, end);
2000         if (ret)
2001                 goto error;
2002
2003         /* context entry init */
2004         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2005         if (ret)
2006                 goto error;
2007
2008         return 0;
2009
2010  error:
2011         domain_exit(domain);
2012         return ret;
2013 }
2014
2015 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2016         struct pci_dev *pdev)
2017 {
2018         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2019                 return 0;
2020         return iommu_prepare_identity_map(pdev, rmrr->base_address,
2021                 rmrr->end_address + 1);
2022 }
2023
2024 #ifdef CONFIG_DMAR_FLOPPY_WA
2025 static inline void iommu_prepare_isa(void)
2026 {
2027         struct pci_dev *pdev;
2028         int ret;
2029
2030         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2031         if (!pdev)
2032                 return;
2033
2034         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2035         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2036
2037         if (ret)
2038                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2039                        "floppy might not work\n");
2040
2041 }
2042 #else
2043 static inline void iommu_prepare_isa(void)
2044 {
2045         return;
2046 }
2047 #endif /* !CONFIG_DMAR_FLPY_WA */
2048
2049 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2050
2051 static int __init si_domain_work_fn(unsigned long start_pfn,
2052                                     unsigned long end_pfn, void *datax)
2053 {
2054         int *ret = datax;
2055
2056         *ret = iommu_domain_identity_map(si_domain,
2057                                          (uint64_t)start_pfn << PAGE_SHIFT,
2058                                          (uint64_t)end_pfn << PAGE_SHIFT);
2059         return *ret;
2060
2061 }
2062
2063 static int __init si_domain_init(int hw)
2064 {
2065         struct dmar_drhd_unit *drhd;
2066         struct intel_iommu *iommu;
2067         int nid, ret = 0;
2068
2069         si_domain = alloc_domain();
2070         if (!si_domain)
2071                 return -EFAULT;
2072
2073         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2074
2075         for_each_active_iommu(iommu, drhd) {
2076                 ret = iommu_attach_domain(si_domain, iommu);
2077                 if (ret) {
2078                         domain_exit(si_domain);
2079                         return -EFAULT;
2080                 }
2081         }
2082
2083         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2084                 domain_exit(si_domain);
2085                 return -EFAULT;
2086         }
2087
2088         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2089
2090         if (hw)
2091                 return 0;
2092
2093         for_each_online_node(nid) {
2094                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2095                 if (ret)
2096                         return ret;
2097         }
2098
2099         return 0;
2100 }
2101
2102 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2103                                           struct pci_dev *pdev);
2104 static int identity_mapping(struct pci_dev *pdev)
2105 {
2106         struct device_domain_info *info;
2107
2108         if (likely(!iommu_identity_mapping))
2109                 return 0;
2110
2111
2112         list_for_each_entry(info, &si_domain->devices, link)
2113                 if (info->dev == pdev)
2114                         return 1;
2115         return 0;
2116 }
2117
2118 static int domain_add_dev_info(struct dmar_domain *domain,
2119                                struct pci_dev *pdev,
2120                                int translation)
2121 {
2122         struct device_domain_info *info;
2123         unsigned long flags;
2124         int ret;
2125
2126         info = alloc_devinfo_mem();
2127         if (!info)
2128                 return -ENOMEM;
2129
2130         ret = domain_context_mapping(domain, pdev, translation);
2131         if (ret) {
2132                 free_devinfo_mem(info);
2133                 return ret;
2134         }
2135
2136         info->segment = pci_domain_nr(pdev->bus);
2137         info->bus = pdev->bus->number;
2138         info->devfn = pdev->devfn;
2139         info->dev = pdev;
2140         info->domain = domain;
2141
2142         spin_lock_irqsave(&device_domain_lock, flags);
2143         list_add(&info->link, &domain->devices);
2144         list_add(&info->global, &device_domain_list);
2145         pdev->dev.archdata.iommu = info;
2146         spin_unlock_irqrestore(&device_domain_lock, flags);
2147
2148         return 0;
2149 }
2150
2151 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2152 {
2153         if (iommu_identity_mapping == 2)
2154                 return IS_GFX_DEVICE(pdev);
2155
2156         /*
2157          * We want to start off with all devices in the 1:1 domain, and
2158          * take them out later if we find they can't access all of memory.
2159          *
2160          * However, we can't do this for PCI devices behind bridges,
2161          * because all PCI devices behind the same bridge will end up
2162          * with the same source-id on their transactions.
2163          *
2164          * Practically speaking, we can't change things around for these
2165          * devices at run-time, because we can't be sure there'll be no
2166          * DMA transactions in flight for any of their siblings.
2167          * 
2168          * So PCI devices (unless they're on the root bus) as well as
2169          * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2170          * the 1:1 domain, just in _case_ one of their siblings turns out
2171          * not to be able to map all of memory.
2172          */
2173         if (!pdev->is_pcie) {
2174                 if (!pci_is_root_bus(pdev->bus))
2175                         return 0;
2176                 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2177                         return 0;
2178         } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2179                 return 0;
2180
2181         /* 
2182          * At boot time, we don't yet know if devices will be 64-bit capable.
2183          * Assume that they will -- if they turn out not to be, then we can 
2184          * take them out of the 1:1 domain later.
2185          */
2186         if (!startup)
2187                 return pdev->dma_mask > DMA_BIT_MASK(32);
2188
2189         return 1;
2190 }
2191
2192 static int __init iommu_prepare_static_identity_mapping(int hw)
2193 {
2194         struct pci_dev *pdev = NULL;
2195         int ret;
2196
2197         ret = si_domain_init(hw);
2198         if (ret)
2199                 return -EFAULT;
2200
2201         for_each_pci_dev(pdev) {
2202                 if (iommu_should_identity_map(pdev, 1)) {
2203                         printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2204                                hw ? "hardware" : "software", pci_name(pdev));
2205
2206                         ret = domain_add_dev_info(si_domain, pdev,
2207                                                      hw ? CONTEXT_TT_PASS_THROUGH :
2208                                                      CONTEXT_TT_MULTI_LEVEL);
2209                         if (ret)
2210                                 return ret;
2211                 }
2212         }
2213
2214         return 0;
2215 }
2216
2217 int __init init_dmars(void)
2218 {
2219         struct dmar_drhd_unit *drhd;
2220         struct dmar_rmrr_unit *rmrr;
2221         struct pci_dev *pdev;
2222         struct intel_iommu *iommu;
2223         int i, ret;
2224
2225         /*
2226          * for each drhd
2227          *    allocate root
2228          *    initialize and program root entry to not present
2229          * endfor
2230          */
2231         for_each_drhd_unit(drhd) {
2232                 g_num_of_iommus++;
2233                 /*
2234                  * lock not needed as this is only incremented in the single
2235                  * threaded kernel __init code path all other access are read
2236                  * only
2237                  */
2238         }
2239
2240         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2241                         GFP_KERNEL);
2242         if (!g_iommus) {
2243                 printk(KERN_ERR "Allocating global iommu array failed\n");
2244                 ret = -ENOMEM;
2245                 goto error;
2246         }
2247
2248         deferred_flush = kzalloc(g_num_of_iommus *
2249                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2250         if (!deferred_flush) {
2251                 ret = -ENOMEM;
2252                 goto error;
2253         }
2254
2255         for_each_drhd_unit(drhd) {
2256                 if (drhd->ignored)
2257                         continue;
2258
2259                 iommu = drhd->iommu;
2260                 g_iommus[iommu->seq_id] = iommu;
2261
2262                 ret = iommu_init_domains(iommu);
2263                 if (ret)
2264                         goto error;
2265
2266                 /*
2267                  * TBD:
2268                  * we could share the same root & context tables
2269                  * amoung all IOMMU's. Need to Split it later.
2270                  */
2271                 ret = iommu_alloc_root_entry(iommu);
2272                 if (ret) {
2273                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2274                         goto error;
2275                 }
2276                 if (!ecap_pass_through(iommu->ecap))
2277                         hw_pass_through = 0;
2278         }
2279
2280         /*
2281          * Start from the sane iommu hardware state.
2282          */
2283         for_each_drhd_unit(drhd) {
2284                 if (drhd->ignored)
2285                         continue;
2286
2287                 iommu = drhd->iommu;
2288
2289                 /*
2290                  * If the queued invalidation is already initialized by us
2291                  * (for example, while enabling interrupt-remapping) then
2292                  * we got the things already rolling from a sane state.
2293                  */
2294                 if (iommu->qi)
2295                         continue;
2296
2297                 /*
2298                  * Clear any previous faults.
2299                  */
2300                 dmar_fault(-1, iommu);
2301                 /*
2302                  * Disable queued invalidation if supported and already enabled
2303                  * before OS handover.
2304                  */
2305                 dmar_disable_qi(iommu);
2306         }
2307
2308         for_each_drhd_unit(drhd) {
2309                 if (drhd->ignored)
2310                         continue;
2311
2312                 iommu = drhd->iommu;
2313
2314                 if (dmar_enable_qi(iommu)) {
2315                         /*
2316                          * Queued Invalidate not enabled, use Register Based
2317                          * Invalidate
2318                          */
2319                         iommu->flush.flush_context = __iommu_flush_context;
2320                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2321                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2322                                "invalidation\n",
2323                                (unsigned long long)drhd->reg_base_addr);
2324                 } else {
2325                         iommu->flush.flush_context = qi_flush_context;
2326                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2327                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2328                                "invalidation\n",
2329                                (unsigned long long)drhd->reg_base_addr);
2330                 }
2331         }
2332
2333         if (iommu_pass_through)
2334                 iommu_identity_mapping = 1;
2335 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2336         else
2337                 iommu_identity_mapping = 2;
2338 #endif
2339         /*
2340          * If pass through is not set or not enabled, setup context entries for
2341          * identity mappings for rmrr, gfx, and isa and may fall back to static
2342          * identity mapping if iommu_identity_mapping is set.
2343          */
2344         if (iommu_identity_mapping) {
2345                 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
2346                 if (ret) {
2347                         printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2348                         goto error;
2349                 }
2350         }
2351         /*
2352          * For each rmrr
2353          *   for each dev attached to rmrr
2354          *   do
2355          *     locate drhd for dev, alloc domain for dev
2356          *     allocate free domain
2357          *     allocate page table entries for rmrr
2358          *     if context not allocated for bus
2359          *           allocate and init context
2360          *           set present in root table for this bus
2361          *     init context with domain, translation etc
2362          *    endfor
2363          * endfor
2364          */
2365         printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2366         for_each_rmrr_units(rmrr) {
2367                 for (i = 0; i < rmrr->devices_cnt; i++) {
2368                         pdev = rmrr->devices[i];
2369                         /*
2370                          * some BIOS lists non-exist devices in DMAR
2371                          * table.
2372                          */
2373                         if (!pdev)
2374                                 continue;
2375                         ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2376                         if (ret)
2377                                 printk(KERN_ERR
2378                                        "IOMMU: mapping reserved region failed\n");
2379                 }
2380         }
2381
2382         iommu_prepare_isa();
2383
2384         /*
2385          * for each drhd
2386          *   enable fault log
2387          *   global invalidate context cache
2388          *   global invalidate iotlb
2389          *   enable translation
2390          */
2391         for_each_drhd_unit(drhd) {
2392                 if (drhd->ignored)
2393                         continue;
2394                 iommu = drhd->iommu;
2395
2396                 iommu_flush_write_buffer(iommu);
2397
2398                 ret = dmar_set_interrupt(iommu);
2399                 if (ret)
2400                         goto error;
2401
2402                 iommu_set_root_entry(iommu);
2403
2404                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2405                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2406
2407                 ret = iommu_enable_translation(iommu);
2408                 if (ret)
2409                         goto error;
2410
2411                 iommu_disable_protect_mem_regions(iommu);
2412         }
2413
2414         return 0;
2415 error:
2416         for_each_drhd_unit(drhd) {
2417                 if (drhd->ignored)
2418                         continue;
2419                 iommu = drhd->iommu;
2420                 free_iommu(iommu);
2421         }
2422         kfree(g_iommus);
2423         return ret;
2424 }
2425
2426 /* This takes a number of _MM_ pages, not VTD pages */
2427 static struct iova *intel_alloc_iova(struct device *dev,
2428                                      struct dmar_domain *domain,
2429                                      unsigned long nrpages, uint64_t dma_mask)
2430 {
2431         struct pci_dev *pdev = to_pci_dev(dev);
2432         struct iova *iova = NULL;
2433
2434         /* Restrict dma_mask to the width that the iommu can handle */
2435         dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2436
2437         if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2438                 /*
2439                  * First try to allocate an io virtual address in
2440                  * DMA_BIT_MASK(32) and if that fails then try allocating
2441                  * from higher range
2442                  */
2443                 iova = alloc_iova(&domain->iovad, nrpages,
2444                                   IOVA_PFN(DMA_BIT_MASK(32)), 1);
2445                 if (iova)
2446                         return iova;
2447         }
2448         iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2449         if (unlikely(!iova)) {
2450                 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2451                        nrpages, pci_name(pdev));
2452                 return NULL;
2453         }
2454
2455         return iova;
2456 }
2457
2458 static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2459 {
2460         struct dmar_domain *domain;
2461         int ret;
2462
2463         domain = get_domain_for_dev(pdev,
2464                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2465         if (!domain) {
2466                 printk(KERN_ERR
2467                         "Allocating domain for %s failed", pci_name(pdev));
2468                 return NULL;
2469         }
2470
2471         /* make sure context mapping is ok */
2472         if (unlikely(!domain_context_mapped(pdev))) {
2473                 ret = domain_context_mapping(domain, pdev,
2474                                              CONTEXT_TT_MULTI_LEVEL);
2475                 if (ret) {
2476                         printk(KERN_ERR
2477                                 "Domain context map for %s failed",
2478                                 pci_name(pdev));
2479                         return NULL;
2480                 }
2481         }
2482
2483         return domain;
2484 }
2485
2486 static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2487 {
2488         struct device_domain_info *info;
2489
2490         /* No lock here, assumes no domain exit in normal case */
2491         info = dev->dev.archdata.iommu;
2492         if (likely(info))
2493                 return info->domain;
2494
2495         return __get_valid_domain_for_dev(dev);
2496 }
2497
2498 static int iommu_dummy(struct pci_dev *pdev)
2499 {
2500         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2501 }
2502
2503 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2504 static int iommu_no_mapping(struct device *dev)
2505 {
2506         struct pci_dev *pdev;
2507         int found;
2508
2509         if (unlikely(dev->bus != &pci_bus_type))
2510                 return 1;
2511
2512         pdev = to_pci_dev(dev);
2513         if (iommu_dummy(pdev))
2514                 return 1;
2515
2516         if (!iommu_identity_mapping)
2517                 return 0;
2518
2519         found = identity_mapping(pdev);
2520         if (found) {
2521                 if (iommu_should_identity_map(pdev, 0))
2522                         return 1;
2523                 else {
2524                         /*
2525                          * 32 bit DMA is removed from si_domain and fall back
2526                          * to non-identity mapping.
2527                          */
2528                         domain_remove_one_dev_info(si_domain, pdev);
2529                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2530                                pci_name(pdev));
2531                         return 0;
2532                 }
2533         } else {
2534                 /*
2535                  * In case of a detached 64 bit DMA device from vm, the device
2536                  * is put into si_domain for identity mapping.
2537                  */
2538                 if (iommu_should_identity_map(pdev, 0)) {
2539                         int ret;
2540                         ret = domain_add_dev_info(si_domain, pdev,
2541                                                   hw_pass_through ?
2542                                                   CONTEXT_TT_PASS_THROUGH :
2543                                                   CONTEXT_TT_MULTI_LEVEL);
2544                         if (!ret) {
2545                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2546                                        pci_name(pdev));
2547                                 return 1;
2548                         }
2549                 }
2550         }
2551
2552         return 0;
2553 }
2554
2555 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2556                                      size_t size, int dir, u64 dma_mask)
2557 {
2558         struct pci_dev *pdev = to_pci_dev(hwdev);
2559         struct dmar_domain *domain;
2560         phys_addr_t start_paddr;
2561         struct iova *iova;
2562         int prot = 0;
2563         int ret;
2564         struct intel_iommu *iommu;
2565         unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2566
2567         BUG_ON(dir == DMA_NONE);
2568
2569         if (iommu_no_mapping(hwdev))
2570                 return paddr;
2571
2572         domain = get_valid_domain_for_dev(pdev);
2573         if (!domain)
2574                 return 0;
2575
2576         iommu = domain_get_iommu(domain);
2577         size = aligned_nrpages(paddr, size);
2578
2579         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2580                                 pdev->dma_mask);
2581         if (!iova)
2582                 goto error;
2583
2584         /*
2585          * Check if DMAR supports zero-length reads on write only
2586          * mappings..
2587          */
2588         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2589                         !cap_zlr(iommu->cap))
2590                 prot |= DMA_PTE_READ;
2591         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2592                 prot |= DMA_PTE_WRITE;
2593         /*
2594          * paddr - (paddr + size) might be partial page, we should map the whole
2595          * page.  Note: if two part of one page are separately mapped, we
2596          * might have two guest_addr mapping to the same host paddr, but this
2597          * is not a big problem
2598          */
2599         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2600                                  mm_to_dma_pfn(paddr_pfn), size, prot);
2601         if (ret)
2602                 goto error;
2603
2604         /* it's a non-present to present mapping. Only flush if caching mode */
2605         if (cap_caching_mode(iommu->cap))
2606                 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2607         else
2608                 iommu_flush_write_buffer(iommu);
2609
2610         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2611         start_paddr += paddr & ~PAGE_MASK;
2612         return start_paddr;
2613
2614 error:
2615         if (iova)
2616                 __free_iova(&domain->iovad, iova);
2617         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2618                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2619         return 0;
2620 }
2621
2622 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2623                                  unsigned long offset, size_t size,
2624                                  enum dma_data_direction dir,
2625                                  struct dma_attrs *attrs)
2626 {
2627         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2628                                   dir, to_pci_dev(dev)->dma_mask);
2629 }
2630
2631 static void flush_unmaps(void)
2632 {
2633         int i, j;
2634
2635         timer_on = 0;
2636
2637         /* just flush them all */
2638         for (i = 0; i < g_num_of_iommus; i++) {
2639                 struct intel_iommu *iommu = g_iommus[i];
2640                 if (!iommu)
2641                         continue;
2642
2643                 if (!deferred_flush[i].next)
2644                         continue;
2645
2646                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2647                                          DMA_TLB_GLOBAL_FLUSH);
2648                 for (j = 0; j < deferred_flush[i].next; j++) {
2649                         unsigned long mask;
2650                         struct iova *iova = deferred_flush[i].iova[j];
2651
2652                         mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
2653                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2654                                         (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
2655                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2656                 }
2657                 deferred_flush[i].next = 0;
2658         }
2659
2660         list_size = 0;
2661 }
2662
2663 static void flush_unmaps_timeout(unsigned long data)
2664 {
2665         unsigned long flags;
2666
2667         spin_lock_irqsave(&async_umap_flush_lock, flags);
2668         flush_unmaps();
2669         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2670 }
2671
2672 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2673 {
2674         unsigned long flags;
2675         int next, iommu_id;
2676         struct intel_iommu *iommu;
2677
2678         spin_lock_irqsave(&async_umap_flush_lock, flags);
2679         if (list_size == HIGH_WATER_MARK)
2680                 flush_unmaps();
2681
2682         iommu = domain_get_iommu(dom);
2683         iommu_id = iommu->seq_id;
2684
2685         next = deferred_flush[iommu_id].next;
2686         deferred_flush[iommu_id].domain[next] = dom;
2687         deferred_flush[iommu_id].iova[next] = iova;
2688         deferred_flush[iommu_id].next++;
2689
2690         if (!timer_on) {
2691                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2692                 timer_on = 1;
2693         }
2694         list_size++;
2695         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2696 }
2697
2698 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2699                              size_t size, enum dma_data_direction dir,
2700                              struct dma_attrs *attrs)
2701 {
2702         struct pci_dev *pdev = to_pci_dev(dev);
2703         struct dmar_domain *domain;
2704         unsigned long start_pfn, last_pfn;
2705         struct iova *iova;
2706         struct intel_iommu *iommu;
2707
2708         if (iommu_no_mapping(dev))
2709                 return;
2710
2711         domain = find_domain(pdev);
2712         BUG_ON(!domain);
2713
2714         iommu = domain_get_iommu(domain);
2715
2716         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2717         if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2718                       (unsigned long long)dev_addr))
2719                 return;
2720
2721         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2722         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2723
2724         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2725                  pci_name(pdev), start_pfn, last_pfn);
2726
2727         /*  clear the whole page */
2728         dma_pte_clear_range(domain, start_pfn, last_pfn);
2729
2730         /* free page tables */
2731         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2732
2733         if (intel_iommu_strict) {
2734                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2735                                       last_pfn - start_pfn + 1);
2736                 /* free iova */
2737                 __free_iova(&domain->iovad, iova);
2738         } else {
2739                 add_unmap(domain, iova);
2740                 /*
2741                  * queue up the release of the unmap to save the 1/6th of the
2742                  * cpu used up by the iotlb flush operation...
2743                  */
2744         }
2745 }
2746
2747 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2748                                   dma_addr_t *dma_handle, gfp_t flags)
2749 {
2750         void *vaddr;
2751         int order;
2752
2753         size = PAGE_ALIGN(size);
2754         order = get_order(size);
2755         flags &= ~(GFP_DMA | GFP_DMA32);
2756
2757         vaddr = (void *)__get_free_pages(flags, order);
2758         if (!vaddr)
2759                 return NULL;
2760         memset(vaddr, 0, size);
2761
2762         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2763                                          DMA_BIDIRECTIONAL,
2764                                          hwdev->coherent_dma_mask);
2765         if (*dma_handle)
2766                 return vaddr;
2767         free_pages((unsigned long)vaddr, order);
2768         return NULL;
2769 }
2770
2771 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2772                                 dma_addr_t dma_handle)
2773 {
2774         int order;
2775
2776         size = PAGE_ALIGN(size);
2777         order = get_order(size);
2778
2779         intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
2780         free_pages((unsigned long)vaddr, order);
2781 }
2782
2783 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2784                            int nelems, enum dma_data_direction dir,
2785                            struct dma_attrs *attrs)
2786 {
2787         struct pci_dev *pdev = to_pci_dev(hwdev);
2788         struct dmar_domain *domain;
2789         unsigned long start_pfn, last_pfn;
2790         struct iova *iova;
2791         struct intel_iommu *iommu;
2792
2793         if (iommu_no_mapping(hwdev))
2794                 return;
2795
2796         domain = find_domain(pdev);
2797         BUG_ON(!domain);
2798
2799         iommu = domain_get_iommu(domain);
2800
2801         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2802         if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2803                       (unsigned long long)sglist[0].dma_address))
2804                 return;
2805
2806         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2807         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2808
2809         /*  clear the whole page */
2810         dma_pte_clear_range(domain, start_pfn, last_pfn);
2811
2812         /* free page tables */
2813         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2814
2815         if (intel_iommu_strict) {
2816                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2817                                       last_pfn - start_pfn + 1);
2818                 /* free iova */
2819                 __free_iova(&domain->iovad, iova);
2820         } else {
2821                 add_unmap(domain, iova);
2822                 /*
2823                  * queue up the release of the unmap to save the 1/6th of the
2824                  * cpu used up by the iotlb flush operation...
2825                  */
2826         }
2827 }
2828
2829 static int intel_nontranslate_map_sg(struct device *hddev,
2830         struct scatterlist *sglist, int nelems, int dir)
2831 {
2832         int i;
2833         struct scatterlist *sg;
2834
2835         for_each_sg(sglist, sg, nelems, i) {
2836                 BUG_ON(!sg_page(sg));
2837                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2838                 sg->dma_length = sg->length;
2839         }
2840         return nelems;
2841 }
2842
2843 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2844                         enum dma_data_direction dir, struct dma_attrs *attrs)
2845 {
2846         int i;
2847         struct pci_dev *pdev = to_pci_dev(hwdev);
2848         struct dmar_domain *domain;
2849         size_t size = 0;
2850         int prot = 0;
2851         size_t offset_pfn = 0;
2852         struct iova *iova = NULL;
2853         int ret;
2854         struct scatterlist *sg;
2855         unsigned long start_vpfn;
2856         struct intel_iommu *iommu;
2857
2858         BUG_ON(dir == DMA_NONE);
2859         if (iommu_no_mapping(hwdev))
2860                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2861
2862         domain = get_valid_domain_for_dev(pdev);
2863         if (!domain)
2864                 return 0;
2865
2866         iommu = domain_get_iommu(domain);
2867
2868         for_each_sg(sglist, sg, nelems, i)
2869                 size += aligned_nrpages(sg->offset, sg->length);
2870
2871         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2872                                 pdev->dma_mask);
2873         if (!iova) {
2874                 sglist->dma_length = 0;
2875                 return 0;
2876         }
2877
2878         /*
2879          * Check if DMAR supports zero-length reads on write only
2880          * mappings..
2881          */
2882         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2883                         !cap_zlr(iommu->cap))
2884                 prot |= DMA_PTE_READ;
2885         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2886                 prot |= DMA_PTE_WRITE;
2887
2888         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2889
2890         ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
2891         if (unlikely(ret)) {
2892                 /*  clear the page */
2893                 dma_pte_clear_range(domain, start_vpfn,
2894                                     start_vpfn + size - 1);
2895                 /* free page tables */
2896                 dma_pte_free_pagetable(domain, start_vpfn,
2897                                        start_vpfn + size - 1);
2898                 /* free iova */
2899                 __free_iova(&domain->iovad, iova);
2900                 return 0;
2901         }
2902
2903         /* it's a non-present to present mapping. Only flush if caching mode */
2904         if (cap_caching_mode(iommu->cap))
2905                 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2906         else
2907                 iommu_flush_write_buffer(iommu);
2908
2909         return nelems;
2910 }
2911
2912 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2913 {
2914         return !dma_addr;
2915 }
2916
2917 struct dma_map_ops intel_dma_ops = {
2918         .alloc_coherent = intel_alloc_coherent,
2919         .free_coherent = intel_free_coherent,
2920         .map_sg = intel_map_sg,
2921         .unmap_sg = intel_unmap_sg,
2922         .map_page = intel_map_page,
2923         .unmap_page = intel_unmap_page,
2924         .mapping_error = intel_mapping_error,
2925 };
2926
2927 static inline int iommu_domain_cache_init(void)
2928 {
2929         int ret = 0;
2930
2931         iommu_domain_cache = kmem_cache_create("iommu_domain",
2932                                          sizeof(struct dmar_domain),
2933                                          0,
2934                                          SLAB_HWCACHE_ALIGN,
2935
2936                                          NULL);
2937         if (!iommu_domain_cache) {
2938                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2939                 ret = -ENOMEM;
2940         }
2941
2942         return ret;
2943 }
2944
2945 static inline int iommu_devinfo_cache_init(void)
2946 {
2947         int ret = 0;
2948
2949         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2950                                          sizeof(struct device_domain_info),
2951                                          0,
2952                                          SLAB_HWCACHE_ALIGN,
2953                                          NULL);
2954         if (!iommu_devinfo_cache) {
2955                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2956                 ret = -ENOMEM;
2957         }
2958
2959         return ret;
2960 }
2961
2962 static inline int iommu_iova_cache_init(void)
2963 {
2964         int ret = 0;
2965
2966         iommu_iova_cache = kmem_cache_create("iommu_iova",
2967                                          sizeof(struct iova),
2968                                          0,
2969                                          SLAB_HWCACHE_ALIGN,
2970                                          NULL);
2971         if (!iommu_iova_cache) {
2972                 printk(KERN_ERR "Couldn't create iova cache\n");
2973                 ret = -ENOMEM;
2974         }
2975
2976         return ret;
2977 }
2978
2979 static int __init iommu_init_mempool(void)
2980 {
2981         int ret;
2982         ret = iommu_iova_cache_init();
2983         if (ret)
2984                 return ret;
2985
2986         ret = iommu_domain_cache_init();
2987         if (ret)
2988                 goto domain_error;
2989
2990         ret = iommu_devinfo_cache_init();
2991         if (!ret)
2992                 return ret;
2993
2994         kmem_cache_destroy(iommu_domain_cache);
2995 domain_error:
2996         kmem_cache_destroy(iommu_iova_cache);
2997
2998         return -ENOMEM;
2999 }
3000
3001 static void __init iommu_exit_mempool(void)
3002 {
3003         kmem_cache_destroy(iommu_devinfo_cache);
3004         kmem_cache_destroy(iommu_domain_cache);
3005         kmem_cache_destroy(iommu_iova_cache);
3006
3007 }
3008
3009 static void __init init_no_remapping_devices(void)
3010 {
3011         struct dmar_drhd_unit *drhd;
3012
3013         for_each_drhd_unit(drhd) {
3014                 if (!drhd->include_all) {
3015                         int i;
3016                         for (i = 0; i < drhd->devices_cnt; i++)
3017                                 if (drhd->devices[i] != NULL)
3018                                         break;
3019                         /* ignore DMAR unit if no pci devices exist */
3020                         if (i == drhd->devices_cnt)
3021                                 drhd->ignored = 1;
3022                 }
3023         }
3024
3025         if (dmar_map_gfx)
3026                 return;
3027
3028         for_each_drhd_unit(drhd) {
3029                 int i;
3030                 if (drhd->ignored || drhd->include_all)
3031                         continue;
3032
3033                 for (i = 0; i < drhd->devices_cnt; i++)
3034                         if (drhd->devices[i] &&
3035                                 !IS_GFX_DEVICE(drhd->devices[i]))
3036                                 break;
3037
3038                 if (i < drhd->devices_cnt)
3039                         continue;
3040
3041                 /* bypass IOMMU if it is just for gfx devices */
3042                 drhd->ignored = 1;
3043                 for (i = 0; i < drhd->devices_cnt; i++) {
3044                         if (!drhd->devices[i])
3045                                 continue;
3046                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3047                 }
3048         }
3049 }
3050
3051 #ifdef CONFIG_SUSPEND
3052 static int init_iommu_hw(void)
3053 {
3054         struct dmar_drhd_unit *drhd;
3055         struct intel_iommu *iommu = NULL;
3056
3057         for_each_active_iommu(iommu, drhd)
3058                 if (iommu->qi)
3059                         dmar_reenable_qi(iommu);
3060
3061         for_each_active_iommu(iommu, drhd) {
3062                 iommu_flush_write_buffer(iommu);
3063
3064                 iommu_set_root_entry(iommu);
3065
3066                 iommu->flush.flush_context(iommu, 0, 0, 0,
3067                                            DMA_CCMD_GLOBAL_INVL);
3068                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3069                                          DMA_TLB_GLOBAL_FLUSH);
3070                 iommu_enable_translation(iommu);
3071                 iommu_disable_protect_mem_regions(iommu);
3072         }
3073
3074         return 0;
3075 }
3076
3077 static void iommu_flush_all(void)
3078 {
3079         struct dmar_drhd_unit *drhd;
3080         struct intel_iommu *iommu;
3081
3082         for_each_active_iommu(iommu, drhd) {
3083                 iommu->flush.flush_context(iommu, 0, 0, 0,
3084                                            DMA_CCMD_GLOBAL_INVL);
3085                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3086                                          DMA_TLB_GLOBAL_FLUSH);
3087         }
3088 }
3089
3090 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3091 {
3092         struct dmar_drhd_unit *drhd;
3093         struct intel_iommu *iommu = NULL;
3094         unsigned long flag;
3095
3096         for_each_active_iommu(iommu, drhd) {
3097                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3098                                                  GFP_ATOMIC);
3099                 if (!iommu->iommu_state)
3100                         goto nomem;
3101         }
3102
3103         iommu_flush_all();
3104
3105         for_each_active_iommu(iommu, drhd) {
3106                 iommu_disable_translation(iommu);
3107
3108                 spin_lock_irqsave(&iommu->register_lock, flag);
3109
3110                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3111                         readl(iommu->reg + DMAR_FECTL_REG);
3112                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3113                         readl(iommu->reg + DMAR_FEDATA_REG);
3114                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3115                         readl(iommu->reg + DMAR_FEADDR_REG);
3116                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3117                         readl(iommu->reg + DMAR_FEUADDR_REG);
3118
3119                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3120         }
3121         return 0;
3122
3123 nomem:
3124         for_each_active_iommu(iommu, drhd)
3125                 kfree(iommu->iommu_state);
3126
3127         return -ENOMEM;
3128 }
3129
3130 static int iommu_resume(struct sys_device *dev)
3131 {
3132         struct dmar_drhd_unit *drhd;
3133         struct intel_iommu *iommu = NULL;
3134         unsigned long flag;
3135
3136         if (init_iommu_hw()) {
3137                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3138                 return -EIO;
3139         }
3140
3141         for_each_active_iommu(iommu, drhd) {
3142
3143                 spin_lock_irqsave(&iommu->register_lock, flag);
3144
3145                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3146                         iommu->reg + DMAR_FECTL_REG);
3147                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3148                         iommu->reg + DMAR_FEDATA_REG);
3149                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3150                         iommu->reg + DMAR_FEADDR_REG);
3151                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3152                         iommu->reg + DMAR_FEUADDR_REG);
3153
3154                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3155         }
3156
3157         for_each_active_iommu(iommu, drhd)
3158                 kfree(iommu->iommu_state);
3159
3160         return 0;
3161 }
3162
3163 static struct sysdev_class iommu_sysclass = {
3164         .name           = "iommu",
3165         .resume         = iommu_resume,
3166         .suspend        = iommu_suspend,
3167 };
3168
3169 static struct sys_device device_iommu = {
3170         .cls    = &iommu_sysclass,
3171 };
3172
3173 static int __init init_iommu_sysfs(void)
3174 {
3175         int error;
3176
3177         error = sysdev_class_register(&iommu_sysclass);
3178         if (error)
3179                 return error;
3180
3181         error = sysdev_register(&device_iommu);
3182         if (error)
3183                 sysdev_class_unregister(&iommu_sysclass);
3184
3185         return error;
3186 }
3187
3188 #else
3189 static int __init init_iommu_sysfs(void)
3190 {
3191         return 0;
3192 }
3193 #endif  /* CONFIG_PM */
3194
3195 int __init intel_iommu_init(void)
3196 {
3197         int ret = 0;
3198
3199         if (dmar_table_init())
3200                 return  -ENODEV;
3201
3202         if (dmar_dev_scope_init())
3203                 return  -ENODEV;
3204
3205         /*
3206          * Check the need for DMA-remapping initialization now.
3207          * Above initialization will also be used by Interrupt-remapping.
3208          */
3209         if (no_iommu || swiotlb || dmar_disabled)
3210                 return -ENODEV;
3211
3212         iommu_init_mempool();
3213         dmar_init_reserved_ranges();
3214
3215         init_no_remapping_devices();
3216
3217         ret = init_dmars();
3218         if (ret) {
3219                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3220                 put_iova_domain(&reserved_iova_list);
3221                 iommu_exit_mempool();
3222                 return ret;
3223         }
3224         printk(KERN_INFO
3225         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3226
3227         init_timer(&unmap_timer);
3228         force_iommu = 1;
3229         dma_ops = &intel_dma_ops;
3230
3231         init_iommu_sysfs();
3232
3233         register_iommu(&intel_iommu_ops);
3234
3235         return 0;
3236 }
3237
3238 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3239                                            struct pci_dev *pdev)
3240 {
3241         struct pci_dev *tmp, *parent;
3242
3243         if (!iommu || !pdev)
3244                 return;
3245
3246         /* dependent device detach */
3247         tmp = pci_find_upstream_pcie_bridge(pdev);
3248         /* Secondary interface's bus number and devfn 0 */
3249         if (tmp) {
3250                 parent = pdev->bus->self;
3251                 while (parent != tmp) {
3252                         iommu_detach_dev(iommu, parent->bus->number,
3253                                          parent->devfn);
3254                         parent = parent->bus->self;
3255                 }
3256                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3257                         iommu_detach_dev(iommu,
3258                                 tmp->subordinate->number, 0);
3259                 else /* this is a legacy PCI bridge */
3260                         iommu_detach_dev(iommu, tmp->bus->number,
3261                                          tmp->devfn);
3262         }
3263 }
3264
3265 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3266                                           struct pci_dev *pdev)
3267 {
3268         struct device_domain_info *info;
3269         struct intel_iommu *iommu;
3270         unsigned long flags;
3271         int found = 0;
3272         struct list_head *entry, *tmp;
3273
3274         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3275                                 pdev->devfn);
3276         if (!iommu)
3277                 return;
3278
3279         spin_lock_irqsave(&device_domain_lock, flags);
3280         list_for_each_safe(entry, tmp, &domain->devices) {
3281                 info = list_entry(entry, struct device_domain_info, link);
3282                 /* No need to compare PCI domain; it has to be the same */
3283                 if (info->bus == pdev->bus->number &&
3284                     info->devfn == pdev->devfn) {
3285                         list_del(&info->link);
3286                         list_del(&info->global);
3287                         if (info->dev)
3288                                 info->dev->dev.archdata.iommu = NULL;
3289                         spin_unlock_irqrestore(&device_domain_lock, flags);
3290
3291                         iommu_disable_dev_iotlb(info);
3292                         iommu_detach_dev(iommu, info->bus, info->devfn);
3293                         iommu_detach_dependent_devices(iommu, pdev);
3294                         free_devinfo_mem(info);
3295
3296                         spin_lock_irqsave(&device_domain_lock, flags);
3297
3298                         if (found)
3299                                 break;
3300                         else
3301                                 continue;
3302                 }
3303
3304                 /* if there is no other devices under the same iommu
3305                  * owned by this domain, clear this iommu in iommu_bmp
3306                  * update iommu count and coherency
3307                  */
3308                 if (iommu == device_to_iommu(info->segment, info->bus,
3309                                             info->devfn))
3310                         found = 1;
3311         }
3312
3313         if (found == 0) {
3314                 unsigned long tmp_flags;
3315                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3316                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3317                 domain->iommu_count--;
3318                 domain_update_iommu_cap(domain);
3319                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3320         }
3321
3322         spin_unlock_irqrestore(&device_domain_lock, flags);
3323 }
3324
3325 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3326 {
3327         struct device_domain_info *info;
3328         struct intel_iommu *iommu;
3329         unsigned long flags1, flags2;
3330
3331         spin_lock_irqsave(&device_domain_lock, flags1);
3332         while (!list_empty(&domain->devices)) {
3333                 info = list_entry(domain->devices.next,
3334                         struct device_domain_info, link);
3335                 list_del(&info->link);
3336                 list_del(&info->global);
3337                 if (info->dev)
3338                         info->dev->dev.archdata.iommu = NULL;
3339
3340                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3341
3342                 iommu_disable_dev_iotlb(info);
3343                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3344                 iommu_detach_dev(iommu, info->bus, info->devfn);
3345                 iommu_detach_dependent_devices(iommu, info->dev);
3346
3347                 /* clear this iommu in iommu_bmp, update iommu count
3348                  * and capabilities
3349                  */
3350                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3351                 if (test_and_clear_bit(iommu->seq_id,
3352                                        &domain->iommu_bmp)) {
3353                         domain->iommu_count--;
3354                         domain_update_iommu_cap(domain);
3355                 }
3356                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3357
3358                 free_devinfo_mem(info);
3359                 spin_lock_irqsave(&device_domain_lock, flags1);
3360         }
3361         spin_unlock_irqrestore(&device_domain_lock, flags1);
3362 }
3363
3364 /* domain id for virtual machine, it won't be set in context */
3365 static unsigned long vm_domid;
3366
3367 static int vm_domain_min_agaw(struct dmar_domain *domain)
3368 {
3369         int i;
3370         int min_agaw = domain->agaw;
3371
3372         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3373         for (; i < g_num_of_iommus; ) {
3374                 if (min_agaw > g_iommus[i]->agaw)
3375                         min_agaw = g_iommus[i]->agaw;
3376
3377                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3378         }
3379
3380         return min_agaw;
3381 }
3382
3383 static struct dmar_domain *iommu_alloc_vm_domain(void)
3384 {
3385         struct dmar_domain *domain;
3386
3387         domain = alloc_domain_mem();
3388         if (!domain)
3389                 return NULL;
3390
3391         domain->id = vm_domid++;
3392         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3393         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3394
3395         return domain;
3396 }
3397
3398 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3399 {
3400         int adjust_width;
3401
3402         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3403         spin_lock_init(&domain->iommu_lock);
3404
3405         domain_reserve_special_ranges(domain);
3406
3407         /* calculate AGAW */
3408         domain->gaw = guest_width;
3409         adjust_width = guestwidth_to_adjustwidth(guest_width);
3410         domain->agaw = width_to_agaw(adjust_width);
3411
3412         INIT_LIST_HEAD(&domain->devices);
3413
3414         domain->iommu_count = 0;
3415         domain->iommu_coherency = 0;
3416         domain->iommu_snooping = 0;
3417         domain->max_addr = 0;
3418
3419         /* always allocate the top pgd */
3420         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3421         if (!domain->pgd)
3422                 return -ENOMEM;
3423         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3424         return 0;
3425 }
3426
3427 static void iommu_free_vm_domain(struct dmar_domain *domain)
3428 {
3429         unsigned long flags;
3430         struct dmar_drhd_unit *drhd;
3431         struct intel_iommu *iommu;
3432         unsigned long i;
3433         unsigned long ndomains;
3434
3435         for_each_drhd_unit(drhd) {
3436                 if (drhd->ignored)
3437                         continue;
3438                 iommu = drhd->iommu;
3439
3440                 ndomains = cap_ndoms(iommu->cap);
3441                 i = find_first_bit(iommu->domain_ids, ndomains);
3442                 for (; i < ndomains; ) {
3443                         if (iommu->domains[i] == domain) {
3444                                 spin_lock_irqsave(&iommu->lock, flags);
3445                                 clear_bit(i, iommu->domain_ids);
3446                                 iommu->domains[i] = NULL;
3447                                 spin_unlock_irqrestore(&iommu->lock, flags);
3448                                 break;
3449                         }
3450                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3451                 }
3452         }
3453 }
3454
3455 static void vm_domain_exit(struct dmar_domain *domain)
3456 {
3457         /* Domain 0 is reserved, so dont process it */
3458         if (!domain)
3459                 return;
3460
3461         vm_domain_remove_all_dev_info(domain);
3462         /* destroy iovas */
3463         put_iova_domain(&domain->iovad);
3464
3465         /* clear ptes */
3466         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3467
3468         /* free page tables */
3469         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3470
3471         iommu_free_vm_domain(domain);
3472         free_domain_mem(domain);
3473 }
3474
3475 static int intel_iommu_domain_init(struct iommu_domain *domain)
3476 {
3477         struct dmar_domain *dmar_domain;
3478
3479         dmar_domain = iommu_alloc_vm_domain();
3480         if (!dmar_domain) {
3481                 printk(KERN_ERR
3482                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3483                 return -ENOMEM;
3484         }
3485         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3486                 printk(KERN_ERR
3487                         "intel_iommu_domain_init() failed\n");
3488                 vm_domain_exit(dmar_domain);
3489                 return -ENOMEM;
3490         }
3491         domain->priv = dmar_domain;
3492
3493         return 0;
3494 }
3495
3496 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3497 {
3498         struct dmar_domain *dmar_domain = domain->priv;
3499
3500         domain->priv = NULL;
3501         vm_domain_exit(dmar_domain);
3502 }
3503
3504 static int intel_iommu_attach_device(struct iommu_domain *domain,
3505                                      struct device *dev)
3506 {
3507         struct dmar_domain *dmar_domain = domain->priv;
3508         struct pci_dev *pdev = to_pci_dev(dev);
3509         struct intel_iommu *iommu;
3510         int addr_width;
3511         u64 end;
3512
3513         /* normally pdev is not mapped */
3514         if (unlikely(domain_context_mapped(pdev))) {
3515                 struct dmar_domain *old_domain;
3516
3517                 old_domain = find_domain(pdev);
3518                 if (old_domain) {
3519                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3520                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3521                                 domain_remove_one_dev_info(old_domain, pdev);
3522                         else
3523                                 domain_remove_dev_info(old_domain);
3524                 }
3525         }
3526
3527         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3528                                 pdev->devfn);
3529         if (!iommu)
3530                 return -ENODEV;
3531
3532         /* check if this iommu agaw is sufficient for max mapped address */
3533         addr_width = agaw_to_width(iommu->agaw);
3534         end = DOMAIN_MAX_ADDR(addr_width);
3535         end = end & VTD_PAGE_MASK;
3536         if (end < dmar_domain->max_addr) {
3537                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3538                        "sufficient for the mapped address (%llx)\n",
3539                        __func__, iommu->agaw, dmar_domain->max_addr);
3540                 return -EFAULT;
3541         }
3542
3543         return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3544 }
3545
3546 static void intel_iommu_detach_device(struct iommu_domain *domain,
3547                                       struct device *dev)
3548 {
3549         struct dmar_domain *dmar_domain = domain->priv;
3550         struct pci_dev *pdev = to_pci_dev(dev);
3551
3552         domain_remove_one_dev_info(dmar_domain, pdev);
3553 }
3554
3555 static int intel_iommu_map_range(struct iommu_domain *domain,
3556                                  unsigned long iova, phys_addr_t hpa,
3557                                  size_t size, int iommu_prot)
3558 {
3559         struct dmar_domain *dmar_domain = domain->priv;
3560         u64 max_addr;
3561         int addr_width;
3562         int prot = 0;
3563         int ret;
3564
3565         if (iommu_prot & IOMMU_READ)
3566                 prot |= DMA_PTE_READ;
3567         if (iommu_prot & IOMMU_WRITE)
3568                 prot |= DMA_PTE_WRITE;
3569         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3570                 prot |= DMA_PTE_SNP;
3571
3572         max_addr = iova + size;
3573         if (dmar_domain->max_addr < max_addr) {
3574                 int min_agaw;
3575                 u64 end;
3576
3577                 /* check if minimum agaw is sufficient for mapped address */
3578                 min_agaw = vm_domain_min_agaw(dmar_domain);
3579                 addr_width = agaw_to_width(min_agaw);
3580                 end = DOMAIN_MAX_ADDR(addr_width);
3581                 end = end & VTD_PAGE_MASK;
3582                 if (end < max_addr) {
3583                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3584                                "sufficient for the mapped address (%llx)\n",
3585                                __func__, min_agaw, max_addr);
3586                         return -EFAULT;
3587                 }
3588                 dmar_domain->max_addr = max_addr;
3589         }
3590         /* Round up size to next multiple of PAGE_SIZE, if it and
3591            the low bits of hpa would take us onto the next page */
3592         size = aligned_nrpages(hpa, size);
3593         ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3594                                  hpa >> VTD_PAGE_SHIFT, size, prot);
3595         return ret;
3596 }
3597
3598 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3599                                     unsigned long iova, size_t size)
3600 {
3601         struct dmar_domain *dmar_domain = domain->priv;
3602
3603         if (!size)
3604                 return;
3605
3606         dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3607                             (iova + size - 1) >> VTD_PAGE_SHIFT);
3608
3609         if (dmar_domain->max_addr == iova + size)
3610                 dmar_domain->max_addr = iova;
3611 }
3612
3613 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3614                                             unsigned long iova)
3615 {
3616         struct dmar_domain *dmar_domain = domain->priv;
3617         struct dma_pte *pte;
3618         u64 phys = 0;
3619
3620         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3621         if (pte)
3622                 phys = dma_pte_addr(pte);
3623
3624         return phys;
3625 }
3626
3627 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3628                                       unsigned long cap)
3629 {
3630         struct dmar_domain *dmar_domain = domain->priv;
3631
3632         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3633                 return dmar_domain->iommu_snooping;
3634
3635         return 0;
3636 }
3637
3638 static struct iommu_ops intel_iommu_ops = {
3639         .domain_init    = intel_iommu_domain_init,
3640         .domain_destroy = intel_iommu_domain_destroy,
3641         .attach_dev     = intel_iommu_attach_device,
3642         .detach_dev     = intel_iommu_detach_device,
3643         .map            = intel_iommu_map_range,
3644         .unmap          = intel_iommu_unmap_range,
3645         .iova_to_phys   = intel_iommu_iova_to_phys,
3646         .domain_has_cap = intel_iommu_domain_has_cap,
3647 };
3648
3649 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3650 {
3651         /*
3652          * Mobile 4 Series Chipset neglects to set RWBF capability,
3653          * but needs it:
3654          */
3655         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3656         rwbf_quirk = 1;
3657 }
3658
3659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);