intel-iommu: double kfree()
[linux-2.6.git] / drivers / pci / intel-iommu.c
1 /*
2  * Copyright (c) 2006, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15  * Place - Suite 330, Boston, MA 02111-1307 USA.
16  *
17  * Copyright (C) 2006-2008 Intel Corporation
18  * Author: Ashok Raj <ashok.raj@intel.com>
19  * Author: Shaohua Li <shaohua.li@intel.com>
20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21  * Author: Fenghua Yu <fenghua.yu@intel.com>
22  */
23
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
42 #include "pci.h"
43
44 #define ROOT_SIZE               VTD_PAGE_SIZE
45 #define CONTEXT_SIZE            VTD_PAGE_SIZE
46
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50 #define IOAPIC_RANGE_START      (0xfee00000)
51 #define IOAPIC_RANGE_END        (0xfeefffff)
52 #define IOVA_START_ADDR         (0x1000)
53
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
56 #define MAX_AGAW_WIDTH 64
57
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
59 #define DOMAIN_MAX_PFN(gaw)  ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
60
61 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
62 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
63 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
64
65
66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67    are never going to work. */
68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
69 {
70         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
71 }
72
73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
74 {
75         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
76 }
77 static inline unsigned long page_to_dma_pfn(struct page *pg)
78 {
79         return mm_to_dma_pfn(page_to_pfn(pg));
80 }
81 static inline unsigned long virt_to_dma_pfn(void *p)
82 {
83         return page_to_dma_pfn(virt_to_page(p));
84 }
85
86 /* global iommu list, set NULL for ignored DMAR units */
87 static struct intel_iommu **g_iommus;
88
89 static int rwbf_quirk;
90
91 /*
92  * 0: Present
93  * 1-11: Reserved
94  * 12-63: Context Ptr (12 - (haw-1))
95  * 64-127: Reserved
96  */
97 struct root_entry {
98         u64     val;
99         u64     rsvd1;
100 };
101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102 static inline bool root_present(struct root_entry *root)
103 {
104         return (root->val & 1);
105 }
106 static inline void set_root_present(struct root_entry *root)
107 {
108         root->val |= 1;
109 }
110 static inline void set_root_value(struct root_entry *root, unsigned long value)
111 {
112         root->val |= value & VTD_PAGE_MASK;
113 }
114
115 static inline struct context_entry *
116 get_context_addr_from_root(struct root_entry *root)
117 {
118         return (struct context_entry *)
119                 (root_present(root)?phys_to_virt(
120                 root->val & VTD_PAGE_MASK) :
121                 NULL);
122 }
123
124 /*
125  * low 64 bits:
126  * 0: present
127  * 1: fault processing disable
128  * 2-3: translation type
129  * 12-63: address space root
130  * high 64 bits:
131  * 0-2: address width
132  * 3-6: aval
133  * 8-23: domain id
134  */
135 struct context_entry {
136         u64 lo;
137         u64 hi;
138 };
139
140 static inline bool context_present(struct context_entry *context)
141 {
142         return (context->lo & 1);
143 }
144 static inline void context_set_present(struct context_entry *context)
145 {
146         context->lo |= 1;
147 }
148
149 static inline void context_set_fault_enable(struct context_entry *context)
150 {
151         context->lo &= (((u64)-1) << 2) | 1;
152 }
153
154 static inline void context_set_translation_type(struct context_entry *context,
155                                                 unsigned long value)
156 {
157         context->lo &= (((u64)-1) << 4) | 3;
158         context->lo |= (value & 3) << 2;
159 }
160
161 static inline void context_set_address_root(struct context_entry *context,
162                                             unsigned long value)
163 {
164         context->lo |= value & VTD_PAGE_MASK;
165 }
166
167 static inline void context_set_address_width(struct context_entry *context,
168                                              unsigned long value)
169 {
170         context->hi |= value & 7;
171 }
172
173 static inline void context_set_domain_id(struct context_entry *context,
174                                          unsigned long value)
175 {
176         context->hi |= (value & ((1 << 16) - 1)) << 8;
177 }
178
179 static inline void context_clear_entry(struct context_entry *context)
180 {
181         context->lo = 0;
182         context->hi = 0;
183 }
184
185 /*
186  * 0: readable
187  * 1: writable
188  * 2-6: reserved
189  * 7: super page
190  * 8-10: available
191  * 11: snoop behavior
192  * 12-63: Host physcial address
193  */
194 struct dma_pte {
195         u64 val;
196 };
197
198 static inline void dma_clear_pte(struct dma_pte *pte)
199 {
200         pte->val = 0;
201 }
202
203 static inline void dma_set_pte_readable(struct dma_pte *pte)
204 {
205         pte->val |= DMA_PTE_READ;
206 }
207
208 static inline void dma_set_pte_writable(struct dma_pte *pte)
209 {
210         pte->val |= DMA_PTE_WRITE;
211 }
212
213 static inline void dma_set_pte_snp(struct dma_pte *pte)
214 {
215         pte->val |= DMA_PTE_SNP;
216 }
217
218 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
219 {
220         pte->val = (pte->val & ~3) | (prot & 3);
221 }
222
223 static inline u64 dma_pte_addr(struct dma_pte *pte)
224 {
225 #ifdef CONFIG_64BIT
226         return pte->val & VTD_PAGE_MASK;
227 #else
228         /* Must have a full atomic 64-bit read */
229         return  __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
230 #endif
231 }
232
233 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
234 {
235         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
236 }
237
238 static inline bool dma_pte_present(struct dma_pte *pte)
239 {
240         return (pte->val & 3) != 0;
241 }
242
243 static inline int first_pte_in_page(struct dma_pte *pte)
244 {
245         return !((unsigned long)pte & ~VTD_PAGE_MASK);
246 }
247
248 /*
249  * This domain is a statically identity mapping domain.
250  *      1. This domain creats a static 1:1 mapping to all usable memory.
251  *      2. It maps to each iommu if successful.
252  *      3. Each iommu mapps to this domain if successful.
253  */
254 struct dmar_domain *si_domain;
255
256 /* devices under the same p2p bridge are owned in one domain */
257 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
258
259 /* domain represents a virtual machine, more than one devices
260  * across iommus may be owned in one domain, e.g. kvm guest.
261  */
262 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
263
264 /* si_domain contains mulitple devices */
265 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
266
267 struct dmar_domain {
268         int     id;                     /* domain id */
269         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
270
271         struct list_head devices;       /* all devices' list */
272         struct iova_domain iovad;       /* iova's that belong to this domain */
273
274         struct dma_pte  *pgd;           /* virtual address */
275         int             gaw;            /* max guest address width */
276
277         /* adjusted guest address width, 0 is level 2 30-bit */
278         int             agaw;
279
280         int             flags;          /* flags to find out type of domain */
281
282         int             iommu_coherency;/* indicate coherency of iommu access */
283         int             iommu_snooping; /* indicate snooping control feature*/
284         int             iommu_count;    /* reference count of iommu */
285         spinlock_t      iommu_lock;     /* protect iommu set in domain */
286         u64             max_addr;       /* maximum mapped address */
287 };
288
289 /* PCI domain-device relationship */
290 struct device_domain_info {
291         struct list_head link;  /* link to domain siblings */
292         struct list_head global; /* link to global list */
293         int segment;            /* PCI domain */
294         u8 bus;                 /* PCI bus number */
295         u8 devfn;               /* PCI devfn number */
296         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
297         struct intel_iommu *iommu; /* IOMMU used by this device */
298         struct dmar_domain *domain; /* pointer to domain */
299 };
300
301 static void flush_unmaps_timeout(unsigned long data);
302
303 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
304
305 #define HIGH_WATER_MARK 250
306 struct deferred_flush_tables {
307         int next;
308         struct iova *iova[HIGH_WATER_MARK];
309         struct dmar_domain *domain[HIGH_WATER_MARK];
310 };
311
312 static struct deferred_flush_tables *deferred_flush;
313
314 /* bitmap for indexing intel_iommus */
315 static int g_num_of_iommus;
316
317 static DEFINE_SPINLOCK(async_umap_flush_lock);
318 static LIST_HEAD(unmaps_to_do);
319
320 static int timer_on;
321 static long list_size;
322
323 static void domain_remove_dev_info(struct dmar_domain *domain);
324
325 #ifdef CONFIG_DMAR_DEFAULT_ON
326 int dmar_disabled = 0;
327 #else
328 int dmar_disabled = 1;
329 #endif /*CONFIG_DMAR_DEFAULT_ON*/
330
331 static int __initdata dmar_map_gfx = 1;
332 static int dmar_forcedac;
333 static int intel_iommu_strict;
334
335 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
336 static DEFINE_SPINLOCK(device_domain_lock);
337 static LIST_HEAD(device_domain_list);
338
339 static struct iommu_ops intel_iommu_ops;
340
341 static int __init intel_iommu_setup(char *str)
342 {
343         if (!str)
344                 return -EINVAL;
345         while (*str) {
346                 if (!strncmp(str, "on", 2)) {
347                         dmar_disabled = 0;
348                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
349                 } else if (!strncmp(str, "off", 3)) {
350                         dmar_disabled = 1;
351                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
352                 } else if (!strncmp(str, "igfx_off", 8)) {
353                         dmar_map_gfx = 0;
354                         printk(KERN_INFO
355                                 "Intel-IOMMU: disable GFX device mapping\n");
356                 } else if (!strncmp(str, "forcedac", 8)) {
357                         printk(KERN_INFO
358                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
359                         dmar_forcedac = 1;
360                 } else if (!strncmp(str, "strict", 6)) {
361                         printk(KERN_INFO
362                                 "Intel-IOMMU: disable batched IOTLB flush\n");
363                         intel_iommu_strict = 1;
364                 }
365
366                 str += strcspn(str, ",");
367                 while (*str == ',')
368                         str++;
369         }
370         return 0;
371 }
372 __setup("intel_iommu=", intel_iommu_setup);
373
374 static struct kmem_cache *iommu_domain_cache;
375 static struct kmem_cache *iommu_devinfo_cache;
376 static struct kmem_cache *iommu_iova_cache;
377
378 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
379 {
380         unsigned int flags;
381         void *vaddr;
382
383         /* trying to avoid low memory issues */
384         flags = current->flags & PF_MEMALLOC;
385         current->flags |= PF_MEMALLOC;
386         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
387         current->flags &= (~PF_MEMALLOC | flags);
388         return vaddr;
389 }
390
391
392 static inline void *alloc_pgtable_page(void)
393 {
394         unsigned int flags;
395         void *vaddr;
396
397         /* trying to avoid low memory issues */
398         flags = current->flags & PF_MEMALLOC;
399         current->flags |= PF_MEMALLOC;
400         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
401         current->flags &= (~PF_MEMALLOC | flags);
402         return vaddr;
403 }
404
405 static inline void free_pgtable_page(void *vaddr)
406 {
407         free_page((unsigned long)vaddr);
408 }
409
410 static inline void *alloc_domain_mem(void)
411 {
412         return iommu_kmem_cache_alloc(iommu_domain_cache);
413 }
414
415 static void free_domain_mem(void *vaddr)
416 {
417         kmem_cache_free(iommu_domain_cache, vaddr);
418 }
419
420 static inline void * alloc_devinfo_mem(void)
421 {
422         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
423 }
424
425 static inline void free_devinfo_mem(void *vaddr)
426 {
427         kmem_cache_free(iommu_devinfo_cache, vaddr);
428 }
429
430 struct iova *alloc_iova_mem(void)
431 {
432         return iommu_kmem_cache_alloc(iommu_iova_cache);
433 }
434
435 void free_iova_mem(struct iova *iova)
436 {
437         kmem_cache_free(iommu_iova_cache, iova);
438 }
439
440
441 static inline int width_to_agaw(int width);
442
443 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
444 {
445         unsigned long sagaw;
446         int agaw = -1;
447
448         sagaw = cap_sagaw(iommu->cap);
449         for (agaw = width_to_agaw(max_gaw);
450              agaw >= 0; agaw--) {
451                 if (test_bit(agaw, &sagaw))
452                         break;
453         }
454
455         return agaw;
456 }
457
458 /*
459  * Calculate max SAGAW for each iommu.
460  */
461 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
462 {
463         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
464 }
465
466 /*
467  * calculate agaw for each iommu.
468  * "SAGAW" may be different across iommus, use a default agaw, and
469  * get a supported less agaw for iommus that don't support the default agaw.
470  */
471 int iommu_calculate_agaw(struct intel_iommu *iommu)
472 {
473         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
474 }
475
476 /* This functionin only returns single iommu in a domain */
477 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
478 {
479         int iommu_id;
480
481         /* si_domain and vm domain should not get here. */
482         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
483         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
484
485         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
486         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
487                 return NULL;
488
489         return g_iommus[iommu_id];
490 }
491
492 static void domain_update_iommu_coherency(struct dmar_domain *domain)
493 {
494         int i;
495
496         domain->iommu_coherency = 1;
497
498         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
499         for (; i < g_num_of_iommus; ) {
500                 if (!ecap_coherent(g_iommus[i]->ecap)) {
501                         domain->iommu_coherency = 0;
502                         break;
503                 }
504                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
505         }
506 }
507
508 static void domain_update_iommu_snooping(struct dmar_domain *domain)
509 {
510         int i;
511
512         domain->iommu_snooping = 1;
513
514         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
515         for (; i < g_num_of_iommus; ) {
516                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
517                         domain->iommu_snooping = 0;
518                         break;
519                 }
520                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
521         }
522 }
523
524 /* Some capabilities may be different across iommus */
525 static void domain_update_iommu_cap(struct dmar_domain *domain)
526 {
527         domain_update_iommu_coherency(domain);
528         domain_update_iommu_snooping(domain);
529 }
530
531 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
532 {
533         struct dmar_drhd_unit *drhd = NULL;
534         int i;
535
536         for_each_drhd_unit(drhd) {
537                 if (drhd->ignored)
538                         continue;
539                 if (segment != drhd->segment)
540                         continue;
541
542                 for (i = 0; i < drhd->devices_cnt; i++) {
543                         if (drhd->devices[i] &&
544                             drhd->devices[i]->bus->number == bus &&
545                             drhd->devices[i]->devfn == devfn)
546                                 return drhd->iommu;
547                         if (drhd->devices[i] &&
548                             drhd->devices[i]->subordinate &&
549                             drhd->devices[i]->subordinate->number <= bus &&
550                             drhd->devices[i]->subordinate->subordinate >= bus)
551                                 return drhd->iommu;
552                 }
553
554                 if (drhd->include_all)
555                         return drhd->iommu;
556         }
557
558         return NULL;
559 }
560
561 static void domain_flush_cache(struct dmar_domain *domain,
562                                void *addr, int size)
563 {
564         if (!domain->iommu_coherency)
565                 clflush_cache_range(addr, size);
566 }
567
568 /* Gets context entry for a given bus and devfn */
569 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
570                 u8 bus, u8 devfn)
571 {
572         struct root_entry *root;
573         struct context_entry *context;
574         unsigned long phy_addr;
575         unsigned long flags;
576
577         spin_lock_irqsave(&iommu->lock, flags);
578         root = &iommu->root_entry[bus];
579         context = get_context_addr_from_root(root);
580         if (!context) {
581                 context = (struct context_entry *)alloc_pgtable_page();
582                 if (!context) {
583                         spin_unlock_irqrestore(&iommu->lock, flags);
584                         return NULL;
585                 }
586                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
587                 phy_addr = virt_to_phys((void *)context);
588                 set_root_value(root, phy_addr);
589                 set_root_present(root);
590                 __iommu_flush_cache(iommu, root, sizeof(*root));
591         }
592         spin_unlock_irqrestore(&iommu->lock, flags);
593         return &context[devfn];
594 }
595
596 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
597 {
598         struct root_entry *root;
599         struct context_entry *context;
600         int ret;
601         unsigned long flags;
602
603         spin_lock_irqsave(&iommu->lock, flags);
604         root = &iommu->root_entry[bus];
605         context = get_context_addr_from_root(root);
606         if (!context) {
607                 ret = 0;
608                 goto out;
609         }
610         ret = context_present(&context[devfn]);
611 out:
612         spin_unlock_irqrestore(&iommu->lock, flags);
613         return ret;
614 }
615
616 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
617 {
618         struct root_entry *root;
619         struct context_entry *context;
620         unsigned long flags;
621
622         spin_lock_irqsave(&iommu->lock, flags);
623         root = &iommu->root_entry[bus];
624         context = get_context_addr_from_root(root);
625         if (context) {
626                 context_clear_entry(&context[devfn]);
627                 __iommu_flush_cache(iommu, &context[devfn], \
628                         sizeof(*context));
629         }
630         spin_unlock_irqrestore(&iommu->lock, flags);
631 }
632
633 static void free_context_table(struct intel_iommu *iommu)
634 {
635         struct root_entry *root;
636         int i;
637         unsigned long flags;
638         struct context_entry *context;
639
640         spin_lock_irqsave(&iommu->lock, flags);
641         if (!iommu->root_entry) {
642                 goto out;
643         }
644         for (i = 0; i < ROOT_ENTRY_NR; i++) {
645                 root = &iommu->root_entry[i];
646                 context = get_context_addr_from_root(root);
647                 if (context)
648                         free_pgtable_page(context);
649         }
650         free_pgtable_page(iommu->root_entry);
651         iommu->root_entry = NULL;
652 out:
653         spin_unlock_irqrestore(&iommu->lock, flags);
654 }
655
656 /* page table handling */
657 #define LEVEL_STRIDE            (9)
658 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
659
660 static inline int agaw_to_level(int agaw)
661 {
662         return agaw + 2;
663 }
664
665 static inline int agaw_to_width(int agaw)
666 {
667         return 30 + agaw * LEVEL_STRIDE;
668
669 }
670
671 static inline int width_to_agaw(int width)
672 {
673         return (width - 30) / LEVEL_STRIDE;
674 }
675
676 static inline unsigned int level_to_offset_bits(int level)
677 {
678         return (level - 1) * LEVEL_STRIDE;
679 }
680
681 static inline int pfn_level_offset(unsigned long pfn, int level)
682 {
683         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
684 }
685
686 static inline unsigned long level_mask(int level)
687 {
688         return -1UL << level_to_offset_bits(level);
689 }
690
691 static inline unsigned long level_size(int level)
692 {
693         return 1UL << level_to_offset_bits(level);
694 }
695
696 static inline unsigned long align_to_level(unsigned long pfn, int level)
697 {
698         return (pfn + level_size(level) - 1) & level_mask(level);
699 }
700
701 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
702                                       unsigned long pfn)
703 {
704         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
705         struct dma_pte *parent, *pte = NULL;
706         int level = agaw_to_level(domain->agaw);
707         int offset;
708
709         BUG_ON(!domain->pgd);
710         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
711         parent = domain->pgd;
712
713         while (level > 0) {
714                 void *tmp_page;
715
716                 offset = pfn_level_offset(pfn, level);
717                 pte = &parent[offset];
718                 if (level == 1)
719                         break;
720
721                 if (!dma_pte_present(pte)) {
722                         uint64_t pteval;
723
724                         tmp_page = alloc_pgtable_page();
725
726                         if (!tmp_page)
727                                 return NULL;
728
729                         domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
730                         pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
731                         if (cmpxchg64(&pte->val, 0ULL, pteval)) {
732                                 /* Someone else set it while we were thinking; use theirs. */
733                                 free_pgtable_page(tmp_page);
734                         } else {
735                                 dma_pte_addr(pte);
736                                 domain_flush_cache(domain, pte, sizeof(*pte));
737                         }
738                 }
739                 parent = phys_to_virt(dma_pte_addr(pte));
740                 level--;
741         }
742
743         return pte;
744 }
745
746 /* return address's pte at specific level */
747 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
748                                          unsigned long pfn,
749                                          int level)
750 {
751         struct dma_pte *parent, *pte = NULL;
752         int total = agaw_to_level(domain->agaw);
753         int offset;
754
755         parent = domain->pgd;
756         while (level <= total) {
757                 offset = pfn_level_offset(pfn, total);
758                 pte = &parent[offset];
759                 if (level == total)
760                         return pte;
761
762                 if (!dma_pte_present(pte))
763                         break;
764                 parent = phys_to_virt(dma_pte_addr(pte));
765                 total--;
766         }
767         return NULL;
768 }
769
770 /* clear last level pte, a tlb flush should be followed */
771 static void dma_pte_clear_range(struct dmar_domain *domain,
772                                 unsigned long start_pfn,
773                                 unsigned long last_pfn)
774 {
775         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
776         struct dma_pte *first_pte, *pte;
777
778         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
779         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
780
781         /* we don't need lock here; nobody else touches the iova range */
782         while (start_pfn <= last_pfn) {
783                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
784                 if (!pte) {
785                         start_pfn = align_to_level(start_pfn + 1, 2);
786                         continue;
787                 }
788                 do { 
789                         dma_clear_pte(pte);
790                         start_pfn++;
791                         pte++;
792                 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
793
794                 domain_flush_cache(domain, first_pte,
795                                    (void *)pte - (void *)first_pte);
796         }
797 }
798
799 /* free page table pages. last level pte should already be cleared */
800 static void dma_pte_free_pagetable(struct dmar_domain *domain,
801                                    unsigned long start_pfn,
802                                    unsigned long last_pfn)
803 {
804         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
805         struct dma_pte *first_pte, *pte;
806         int total = agaw_to_level(domain->agaw);
807         int level;
808         unsigned long tmp;
809
810         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
811         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
812
813         /* We don't need lock here; nobody else touches the iova range */
814         level = 2;
815         while (level <= total) {
816                 tmp = align_to_level(start_pfn, level);
817
818                 /* If we can't even clear one PTE at this level, we're done */
819                 if (tmp + level_size(level) - 1 > last_pfn)
820                         return;
821
822                 while (tmp + level_size(level) - 1 <= last_pfn) {
823                         first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
824                         if (!pte) {
825                                 tmp = align_to_level(tmp + 1, level + 1);
826                                 continue;
827                         }
828                         do {
829                                 if (dma_pte_present(pte)) {
830                                         free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
831                                         dma_clear_pte(pte);
832                                 }
833                                 pte++;
834                                 tmp += level_size(level);
835                         } while (!first_pte_in_page(pte) &&
836                                  tmp + level_size(level) - 1 <= last_pfn);
837
838                         domain_flush_cache(domain, first_pte,
839                                            (void *)pte - (void *)first_pte);
840                         
841                 }
842                 level++;
843         }
844         /* free pgd */
845         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
846                 free_pgtable_page(domain->pgd);
847                 domain->pgd = NULL;
848         }
849 }
850
851 /* iommu handling */
852 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
853 {
854         struct root_entry *root;
855         unsigned long flags;
856
857         root = (struct root_entry *)alloc_pgtable_page();
858         if (!root)
859                 return -ENOMEM;
860
861         __iommu_flush_cache(iommu, root, ROOT_SIZE);
862
863         spin_lock_irqsave(&iommu->lock, flags);
864         iommu->root_entry = root;
865         spin_unlock_irqrestore(&iommu->lock, flags);
866
867         return 0;
868 }
869
870 static void iommu_set_root_entry(struct intel_iommu *iommu)
871 {
872         void *addr;
873         u32 sts;
874         unsigned long flag;
875
876         addr = iommu->root_entry;
877
878         spin_lock_irqsave(&iommu->register_lock, flag);
879         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
880
881         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
882
883         /* Make sure hardware complete it */
884         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
885                       readl, (sts & DMA_GSTS_RTPS), sts);
886
887         spin_unlock_irqrestore(&iommu->register_lock, flag);
888 }
889
890 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
891 {
892         u32 val;
893         unsigned long flag;
894
895         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
896                 return;
897
898         spin_lock_irqsave(&iommu->register_lock, flag);
899         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
900
901         /* Make sure hardware complete it */
902         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
903                       readl, (!(val & DMA_GSTS_WBFS)), val);
904
905         spin_unlock_irqrestore(&iommu->register_lock, flag);
906 }
907
908 /* return value determine if we need a write buffer flush */
909 static void __iommu_flush_context(struct intel_iommu *iommu,
910                                   u16 did, u16 source_id, u8 function_mask,
911                                   u64 type)
912 {
913         u64 val = 0;
914         unsigned long flag;
915
916         switch (type) {
917         case DMA_CCMD_GLOBAL_INVL:
918                 val = DMA_CCMD_GLOBAL_INVL;
919                 break;
920         case DMA_CCMD_DOMAIN_INVL:
921                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
922                 break;
923         case DMA_CCMD_DEVICE_INVL:
924                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
925                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
926                 break;
927         default:
928                 BUG();
929         }
930         val |= DMA_CCMD_ICC;
931
932         spin_lock_irqsave(&iommu->register_lock, flag);
933         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
934
935         /* Make sure hardware complete it */
936         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
937                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
938
939         spin_unlock_irqrestore(&iommu->register_lock, flag);
940 }
941
942 /* return value determine if we need a write buffer flush */
943 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
944                                 u64 addr, unsigned int size_order, u64 type)
945 {
946         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
947         u64 val = 0, val_iva = 0;
948         unsigned long flag;
949
950         switch (type) {
951         case DMA_TLB_GLOBAL_FLUSH:
952                 /* global flush doesn't need set IVA_REG */
953                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
954                 break;
955         case DMA_TLB_DSI_FLUSH:
956                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
957                 break;
958         case DMA_TLB_PSI_FLUSH:
959                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
960                 /* Note: always flush non-leaf currently */
961                 val_iva = size_order | addr;
962                 break;
963         default:
964                 BUG();
965         }
966         /* Note: set drain read/write */
967 #if 0
968         /*
969          * This is probably to be super secure.. Looks like we can
970          * ignore it without any impact.
971          */
972         if (cap_read_drain(iommu->cap))
973                 val |= DMA_TLB_READ_DRAIN;
974 #endif
975         if (cap_write_drain(iommu->cap))
976                 val |= DMA_TLB_WRITE_DRAIN;
977
978         spin_lock_irqsave(&iommu->register_lock, flag);
979         /* Note: Only uses first TLB reg currently */
980         if (val_iva)
981                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
982         dmar_writeq(iommu->reg + tlb_offset + 8, val);
983
984         /* Make sure hardware complete it */
985         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
986                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
987
988         spin_unlock_irqrestore(&iommu->register_lock, flag);
989
990         /* check IOTLB invalidation granularity */
991         if (DMA_TLB_IAIG(val) == 0)
992                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
993         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
994                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
995                         (unsigned long long)DMA_TLB_IIRG(type),
996                         (unsigned long long)DMA_TLB_IAIG(val));
997 }
998
999 static struct device_domain_info *iommu_support_dev_iotlb(
1000         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1001 {
1002         int found = 0;
1003         unsigned long flags;
1004         struct device_domain_info *info;
1005         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1006
1007         if (!ecap_dev_iotlb_support(iommu->ecap))
1008                 return NULL;
1009
1010         if (!iommu->qi)
1011                 return NULL;
1012
1013         spin_lock_irqsave(&device_domain_lock, flags);
1014         list_for_each_entry(info, &domain->devices, link)
1015                 if (info->bus == bus && info->devfn == devfn) {
1016                         found = 1;
1017                         break;
1018                 }
1019         spin_unlock_irqrestore(&device_domain_lock, flags);
1020
1021         if (!found || !info->dev)
1022                 return NULL;
1023
1024         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1025                 return NULL;
1026
1027         if (!dmar_find_matched_atsr_unit(info->dev))
1028                 return NULL;
1029
1030         info->iommu = iommu;
1031
1032         return info;
1033 }
1034
1035 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1036 {
1037         if (!info)
1038                 return;
1039
1040         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1041 }
1042
1043 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1044 {
1045         if (!info->dev || !pci_ats_enabled(info->dev))
1046                 return;
1047
1048         pci_disable_ats(info->dev);
1049 }
1050
1051 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1052                                   u64 addr, unsigned mask)
1053 {
1054         u16 sid, qdep;
1055         unsigned long flags;
1056         struct device_domain_info *info;
1057
1058         spin_lock_irqsave(&device_domain_lock, flags);
1059         list_for_each_entry(info, &domain->devices, link) {
1060                 if (!info->dev || !pci_ats_enabled(info->dev))
1061                         continue;
1062
1063                 sid = info->bus << 8 | info->devfn;
1064                 qdep = pci_ats_queue_depth(info->dev);
1065                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1066         }
1067         spin_unlock_irqrestore(&device_domain_lock, flags);
1068 }
1069
1070 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1071                                   unsigned long pfn, unsigned int pages)
1072 {
1073         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1074         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1075
1076         BUG_ON(pages == 0);
1077
1078         /*
1079          * Fallback to domain selective flush if no PSI support or the size is
1080          * too big.
1081          * PSI requires page size to be 2 ^ x, and the base address is naturally
1082          * aligned to the size
1083          */
1084         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1085                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1086                                                 DMA_TLB_DSI_FLUSH);
1087         else
1088                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1089                                                 DMA_TLB_PSI_FLUSH);
1090
1091         /*
1092          * In caching mode, domain ID 0 is reserved for non-present to present
1093          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1094          */
1095         if (!cap_caching_mode(iommu->cap) || did)
1096                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1097 }
1098
1099 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1100 {
1101         u32 pmen;
1102         unsigned long flags;
1103
1104         spin_lock_irqsave(&iommu->register_lock, flags);
1105         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1106         pmen &= ~DMA_PMEN_EPM;
1107         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1108
1109         /* wait for the protected region status bit to clear */
1110         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1111                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1112
1113         spin_unlock_irqrestore(&iommu->register_lock, flags);
1114 }
1115
1116 static int iommu_enable_translation(struct intel_iommu *iommu)
1117 {
1118         u32 sts;
1119         unsigned long flags;
1120
1121         spin_lock_irqsave(&iommu->register_lock, flags);
1122         iommu->gcmd |= DMA_GCMD_TE;
1123         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1124
1125         /* Make sure hardware complete it */
1126         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1127                       readl, (sts & DMA_GSTS_TES), sts);
1128
1129         spin_unlock_irqrestore(&iommu->register_lock, flags);
1130         return 0;
1131 }
1132
1133 static int iommu_disable_translation(struct intel_iommu *iommu)
1134 {
1135         u32 sts;
1136         unsigned long flag;
1137
1138         spin_lock_irqsave(&iommu->register_lock, flag);
1139         iommu->gcmd &= ~DMA_GCMD_TE;
1140         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1141
1142         /* Make sure hardware complete it */
1143         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1144                       readl, (!(sts & DMA_GSTS_TES)), sts);
1145
1146         spin_unlock_irqrestore(&iommu->register_lock, flag);
1147         return 0;
1148 }
1149
1150
1151 static int iommu_init_domains(struct intel_iommu *iommu)
1152 {
1153         unsigned long ndomains;
1154         unsigned long nlongs;
1155
1156         ndomains = cap_ndoms(iommu->cap);
1157         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1158         nlongs = BITS_TO_LONGS(ndomains);
1159
1160         /* TBD: there might be 64K domains,
1161          * consider other allocation for future chip
1162          */
1163         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1164         if (!iommu->domain_ids) {
1165                 printk(KERN_ERR "Allocating domain id array failed\n");
1166                 return -ENOMEM;
1167         }
1168         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1169                         GFP_KERNEL);
1170         if (!iommu->domains) {
1171                 printk(KERN_ERR "Allocating domain array failed\n");
1172                 kfree(iommu->domain_ids);
1173                 return -ENOMEM;
1174         }
1175
1176         spin_lock_init(&iommu->lock);
1177
1178         /*
1179          * if Caching mode is set, then invalid translations are tagged
1180          * with domainid 0. Hence we need to pre-allocate it.
1181          */
1182         if (cap_caching_mode(iommu->cap))
1183                 set_bit(0, iommu->domain_ids);
1184         return 0;
1185 }
1186
1187
1188 static void domain_exit(struct dmar_domain *domain);
1189 static void vm_domain_exit(struct dmar_domain *domain);
1190
1191 void free_dmar_iommu(struct intel_iommu *iommu)
1192 {
1193         struct dmar_domain *domain;
1194         int i;
1195         unsigned long flags;
1196
1197         i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1198         for (; i < cap_ndoms(iommu->cap); ) {
1199                 domain = iommu->domains[i];
1200                 clear_bit(i, iommu->domain_ids);
1201
1202                 spin_lock_irqsave(&domain->iommu_lock, flags);
1203                 if (--domain->iommu_count == 0) {
1204                         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1205                                 vm_domain_exit(domain);
1206                         else
1207                                 domain_exit(domain);
1208                 }
1209                 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1210
1211                 i = find_next_bit(iommu->domain_ids,
1212                         cap_ndoms(iommu->cap), i+1);
1213         }
1214
1215         if (iommu->gcmd & DMA_GCMD_TE)
1216                 iommu_disable_translation(iommu);
1217
1218         if (iommu->irq) {
1219                 set_irq_data(iommu->irq, NULL);
1220                 /* This will mask the irq */
1221                 free_irq(iommu->irq, iommu);
1222                 destroy_irq(iommu->irq);
1223         }
1224
1225         kfree(iommu->domains);
1226         kfree(iommu->domain_ids);
1227
1228         g_iommus[iommu->seq_id] = NULL;
1229
1230         /* if all iommus are freed, free g_iommus */
1231         for (i = 0; i < g_num_of_iommus; i++) {
1232                 if (g_iommus[i])
1233                         break;
1234         }
1235
1236         if (i == g_num_of_iommus)
1237                 kfree(g_iommus);
1238
1239         /* free context mapping */
1240         free_context_table(iommu);
1241 }
1242
1243 static struct dmar_domain *alloc_domain(void)
1244 {
1245         struct dmar_domain *domain;
1246
1247         domain = alloc_domain_mem();
1248         if (!domain)
1249                 return NULL;
1250
1251         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1252         domain->flags = 0;
1253
1254         return domain;
1255 }
1256
1257 static int iommu_attach_domain(struct dmar_domain *domain,
1258                                struct intel_iommu *iommu)
1259 {
1260         int num;
1261         unsigned long ndomains;
1262         unsigned long flags;
1263
1264         ndomains = cap_ndoms(iommu->cap);
1265
1266         spin_lock_irqsave(&iommu->lock, flags);
1267
1268         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1269         if (num >= ndomains) {
1270                 spin_unlock_irqrestore(&iommu->lock, flags);
1271                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1272                 return -ENOMEM;
1273         }
1274
1275         domain->id = num;
1276         set_bit(num, iommu->domain_ids);
1277         set_bit(iommu->seq_id, &domain->iommu_bmp);
1278         iommu->domains[num] = domain;
1279         spin_unlock_irqrestore(&iommu->lock, flags);
1280
1281         return 0;
1282 }
1283
1284 static void iommu_detach_domain(struct dmar_domain *domain,
1285                                 struct intel_iommu *iommu)
1286 {
1287         unsigned long flags;
1288         int num, ndomains;
1289         int found = 0;
1290
1291         spin_lock_irqsave(&iommu->lock, flags);
1292         ndomains = cap_ndoms(iommu->cap);
1293         num = find_first_bit(iommu->domain_ids, ndomains);
1294         for (; num < ndomains; ) {
1295                 if (iommu->domains[num] == domain) {
1296                         found = 1;
1297                         break;
1298                 }
1299                 num = find_next_bit(iommu->domain_ids,
1300                                     cap_ndoms(iommu->cap), num+1);
1301         }
1302
1303         if (found) {
1304                 clear_bit(num, iommu->domain_ids);
1305                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1306                 iommu->domains[num] = NULL;
1307         }
1308         spin_unlock_irqrestore(&iommu->lock, flags);
1309 }
1310
1311 static struct iova_domain reserved_iova_list;
1312 static struct lock_class_key reserved_rbtree_key;
1313
1314 static void dmar_init_reserved_ranges(void)
1315 {
1316         struct pci_dev *pdev = NULL;
1317         struct iova *iova;
1318         int i;
1319
1320         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1321
1322         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1323                 &reserved_rbtree_key);
1324
1325         /* IOAPIC ranges shouldn't be accessed by DMA */
1326         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1327                 IOVA_PFN(IOAPIC_RANGE_END));
1328         if (!iova)
1329                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1330
1331         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1332         for_each_pci_dev(pdev) {
1333                 struct resource *r;
1334
1335                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1336                         r = &pdev->resource[i];
1337                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1338                                 continue;
1339                         iova = reserve_iova(&reserved_iova_list,
1340                                             IOVA_PFN(r->start),
1341                                             IOVA_PFN(r->end));
1342                         if (!iova)
1343                                 printk(KERN_ERR "Reserve iova failed\n");
1344                 }
1345         }
1346
1347 }
1348
1349 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1350 {
1351         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1352 }
1353
1354 static inline int guestwidth_to_adjustwidth(int gaw)
1355 {
1356         int agaw;
1357         int r = (gaw - 12) % 9;
1358
1359         if (r == 0)
1360                 agaw = gaw;
1361         else
1362                 agaw = gaw + 9 - r;
1363         if (agaw > 64)
1364                 agaw = 64;
1365         return agaw;
1366 }
1367
1368 static int domain_init(struct dmar_domain *domain, int guest_width)
1369 {
1370         struct intel_iommu *iommu;
1371         int adjust_width, agaw;
1372         unsigned long sagaw;
1373
1374         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1375         spin_lock_init(&domain->iommu_lock);
1376
1377         domain_reserve_special_ranges(domain);
1378
1379         /* calculate AGAW */
1380         iommu = domain_get_iommu(domain);
1381         if (guest_width > cap_mgaw(iommu->cap))
1382                 guest_width = cap_mgaw(iommu->cap);
1383         domain->gaw = guest_width;
1384         adjust_width = guestwidth_to_adjustwidth(guest_width);
1385         agaw = width_to_agaw(adjust_width);
1386         sagaw = cap_sagaw(iommu->cap);
1387         if (!test_bit(agaw, &sagaw)) {
1388                 /* hardware doesn't support it, choose a bigger one */
1389                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1390                 agaw = find_next_bit(&sagaw, 5, agaw);
1391                 if (agaw >= 5)
1392                         return -ENODEV;
1393         }
1394         domain->agaw = agaw;
1395         INIT_LIST_HEAD(&domain->devices);
1396
1397         if (ecap_coherent(iommu->ecap))
1398                 domain->iommu_coherency = 1;
1399         else
1400                 domain->iommu_coherency = 0;
1401
1402         if (ecap_sc_support(iommu->ecap))
1403                 domain->iommu_snooping = 1;
1404         else
1405                 domain->iommu_snooping = 0;
1406
1407         domain->iommu_count = 1;
1408
1409         /* always allocate the top pgd */
1410         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1411         if (!domain->pgd)
1412                 return -ENOMEM;
1413         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1414         return 0;
1415 }
1416
1417 static void domain_exit(struct dmar_domain *domain)
1418 {
1419         struct dmar_drhd_unit *drhd;
1420         struct intel_iommu *iommu;
1421
1422         /* Domain 0 is reserved, so dont process it */
1423         if (!domain)
1424                 return;
1425
1426         domain_remove_dev_info(domain);
1427         /* destroy iovas */
1428         put_iova_domain(&domain->iovad);
1429
1430         /* clear ptes */
1431         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1432
1433         /* free page tables */
1434         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1435
1436         for_each_active_iommu(iommu, drhd)
1437                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1438                         iommu_detach_domain(domain, iommu);
1439
1440         free_domain_mem(domain);
1441 }
1442
1443 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1444                                  u8 bus, u8 devfn, int translation)
1445 {
1446         struct context_entry *context;
1447         unsigned long flags;
1448         struct intel_iommu *iommu;
1449         struct dma_pte *pgd;
1450         unsigned long num;
1451         unsigned long ndomains;
1452         int id;
1453         int agaw;
1454         struct device_domain_info *info = NULL;
1455
1456         pr_debug("Set context mapping for %02x:%02x.%d\n",
1457                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1458
1459         BUG_ON(!domain->pgd);
1460         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1461                translation != CONTEXT_TT_MULTI_LEVEL);
1462
1463         iommu = device_to_iommu(segment, bus, devfn);
1464         if (!iommu)
1465                 return -ENODEV;
1466
1467         context = device_to_context_entry(iommu, bus, devfn);
1468         if (!context)
1469                 return -ENOMEM;
1470         spin_lock_irqsave(&iommu->lock, flags);
1471         if (context_present(context)) {
1472                 spin_unlock_irqrestore(&iommu->lock, flags);
1473                 return 0;
1474         }
1475
1476         id = domain->id;
1477         pgd = domain->pgd;
1478
1479         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1480             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1481                 int found = 0;
1482
1483                 /* find an available domain id for this device in iommu */
1484                 ndomains = cap_ndoms(iommu->cap);
1485                 num = find_first_bit(iommu->domain_ids, ndomains);
1486                 for (; num < ndomains; ) {
1487                         if (iommu->domains[num] == domain) {
1488                                 id = num;
1489                                 found = 1;
1490                                 break;
1491                         }
1492                         num = find_next_bit(iommu->domain_ids,
1493                                             cap_ndoms(iommu->cap), num+1);
1494                 }
1495
1496                 if (found == 0) {
1497                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1498                         if (num >= ndomains) {
1499                                 spin_unlock_irqrestore(&iommu->lock, flags);
1500                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1501                                 return -EFAULT;
1502                         }
1503
1504                         set_bit(num, iommu->domain_ids);
1505                         set_bit(iommu->seq_id, &domain->iommu_bmp);
1506                         iommu->domains[num] = domain;
1507                         id = num;
1508                 }
1509
1510                 /* Skip top levels of page tables for
1511                  * iommu which has less agaw than default.
1512                  */
1513                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1514                         pgd = phys_to_virt(dma_pte_addr(pgd));
1515                         if (!dma_pte_present(pgd)) {
1516                                 spin_unlock_irqrestore(&iommu->lock, flags);
1517                                 return -ENOMEM;
1518                         }
1519                 }
1520         }
1521
1522         context_set_domain_id(context, id);
1523
1524         if (translation != CONTEXT_TT_PASS_THROUGH) {
1525                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1526                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1527                                      CONTEXT_TT_MULTI_LEVEL;
1528         }
1529         /*
1530          * In pass through mode, AW must be programmed to indicate the largest
1531          * AGAW value supported by hardware. And ASR is ignored by hardware.
1532          */
1533         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1534                 context_set_address_width(context, iommu->msagaw);
1535         else {
1536                 context_set_address_root(context, virt_to_phys(pgd));
1537                 context_set_address_width(context, iommu->agaw);
1538         }
1539
1540         context_set_translation_type(context, translation);
1541         context_set_fault_enable(context);
1542         context_set_present(context);
1543         domain_flush_cache(domain, context, sizeof(*context));
1544
1545         /*
1546          * It's a non-present to present mapping. If hardware doesn't cache
1547          * non-present entry we only need to flush the write-buffer. If the
1548          * _does_ cache non-present entries, then it does so in the special
1549          * domain #0, which we have to flush:
1550          */
1551         if (cap_caching_mode(iommu->cap)) {
1552                 iommu->flush.flush_context(iommu, 0,
1553                                            (((u16)bus) << 8) | devfn,
1554                                            DMA_CCMD_MASK_NOBIT,
1555                                            DMA_CCMD_DEVICE_INVL);
1556                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1557         } else {
1558                 iommu_flush_write_buffer(iommu);
1559         }
1560         iommu_enable_dev_iotlb(info);
1561         spin_unlock_irqrestore(&iommu->lock, flags);
1562
1563         spin_lock_irqsave(&domain->iommu_lock, flags);
1564         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1565                 domain->iommu_count++;
1566                 domain_update_iommu_cap(domain);
1567         }
1568         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1569         return 0;
1570 }
1571
1572 static int
1573 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1574                         int translation)
1575 {
1576         int ret;
1577         struct pci_dev *tmp, *parent;
1578
1579         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1580                                          pdev->bus->number, pdev->devfn,
1581                                          translation);
1582         if (ret)
1583                 return ret;
1584
1585         /* dependent device mapping */
1586         tmp = pci_find_upstream_pcie_bridge(pdev);
1587         if (!tmp)
1588                 return 0;
1589         /* Secondary interface's bus number and devfn 0 */
1590         parent = pdev->bus->self;
1591         while (parent != tmp) {
1592                 ret = domain_context_mapping_one(domain,
1593                                                  pci_domain_nr(parent->bus),
1594                                                  parent->bus->number,
1595                                                  parent->devfn, translation);
1596                 if (ret)
1597                         return ret;
1598                 parent = parent->bus->self;
1599         }
1600         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1601                 return domain_context_mapping_one(domain,
1602                                         pci_domain_nr(tmp->subordinate),
1603                                         tmp->subordinate->number, 0,
1604                                         translation);
1605         else /* this is a legacy PCI bridge */
1606                 return domain_context_mapping_one(domain,
1607                                                   pci_domain_nr(tmp->bus),
1608                                                   tmp->bus->number,
1609                                                   tmp->devfn,
1610                                                   translation);
1611 }
1612
1613 static int domain_context_mapped(struct pci_dev *pdev)
1614 {
1615         int ret;
1616         struct pci_dev *tmp, *parent;
1617         struct intel_iommu *iommu;
1618
1619         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1620                                 pdev->devfn);
1621         if (!iommu)
1622                 return -ENODEV;
1623
1624         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1625         if (!ret)
1626                 return ret;
1627         /* dependent device mapping */
1628         tmp = pci_find_upstream_pcie_bridge(pdev);
1629         if (!tmp)
1630                 return ret;
1631         /* Secondary interface's bus number and devfn 0 */
1632         parent = pdev->bus->self;
1633         while (parent != tmp) {
1634                 ret = device_context_mapped(iommu, parent->bus->number,
1635                                             parent->devfn);
1636                 if (!ret)
1637                         return ret;
1638                 parent = parent->bus->self;
1639         }
1640         if (tmp->is_pcie)
1641                 return device_context_mapped(iommu, tmp->subordinate->number,
1642                                              0);
1643         else
1644                 return device_context_mapped(iommu, tmp->bus->number,
1645                                              tmp->devfn);
1646 }
1647
1648 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1649                             struct scatterlist *sg, unsigned long phys_pfn,
1650                             unsigned long nr_pages, int prot)
1651 {
1652         struct dma_pte *first_pte = NULL, *pte = NULL;
1653         phys_addr_t uninitialized_var(pteval);
1654         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1655         unsigned long sg_res;
1656
1657         BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1658
1659         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1660                 return -EINVAL;
1661
1662         prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1663
1664         if (sg)
1665                 sg_res = 0;
1666         else {
1667                 sg_res = nr_pages + 1;
1668                 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1669         }
1670
1671         while (nr_pages--) {
1672                 uint64_t tmp;
1673
1674                 if (!sg_res) {
1675                         sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT;
1676                         sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1677                         sg->dma_length = sg->length;
1678                         pteval = page_to_phys(sg_page(sg)) | prot;
1679                 }
1680                 if (!pte) {
1681                         first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1682                         if (!pte)
1683                                 return -ENOMEM;
1684                 }
1685                 /* We don't need lock here, nobody else
1686                  * touches the iova range
1687                  */
1688                 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1689                 if (tmp) {
1690                         static int dumps = 5;
1691                         printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1692                                iov_pfn, tmp, (unsigned long long)pteval);
1693                         if (dumps) {
1694                                 dumps--;
1695                                 debug_dma_dump_mappings(NULL);
1696                         }
1697                         WARN_ON(1);
1698                 }
1699                 pte++;
1700                 if (!nr_pages || first_pte_in_page(pte)) {
1701                         domain_flush_cache(domain, first_pte,
1702                                            (void *)pte - (void *)first_pte);
1703                         pte = NULL;
1704                 }
1705                 iov_pfn++;
1706                 pteval += VTD_PAGE_SIZE;
1707                 sg_res--;
1708                 if (!sg_res)
1709                         sg = sg_next(sg);
1710         }
1711         return 0;
1712 }
1713
1714 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1715                                     struct scatterlist *sg, unsigned long nr_pages,
1716                                     int prot)
1717 {
1718         return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1719 }
1720
1721 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1722                                      unsigned long phys_pfn, unsigned long nr_pages,
1723                                      int prot)
1724 {
1725         return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1726 }
1727
1728 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1729 {
1730         if (!iommu)
1731                 return;
1732
1733         clear_context_table(iommu, bus, devfn);
1734         iommu->flush.flush_context(iommu, 0, 0, 0,
1735                                            DMA_CCMD_GLOBAL_INVL);
1736         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1737 }
1738
1739 static void domain_remove_dev_info(struct dmar_domain *domain)
1740 {
1741         struct device_domain_info *info;
1742         unsigned long flags;
1743         struct intel_iommu *iommu;
1744
1745         spin_lock_irqsave(&device_domain_lock, flags);
1746         while (!list_empty(&domain->devices)) {
1747                 info = list_entry(domain->devices.next,
1748                         struct device_domain_info, link);
1749                 list_del(&info->link);
1750                 list_del(&info->global);
1751                 if (info->dev)
1752                         info->dev->dev.archdata.iommu = NULL;
1753                 spin_unlock_irqrestore(&device_domain_lock, flags);
1754
1755                 iommu_disable_dev_iotlb(info);
1756                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1757                 iommu_detach_dev(iommu, info->bus, info->devfn);
1758                 free_devinfo_mem(info);
1759
1760                 spin_lock_irqsave(&device_domain_lock, flags);
1761         }
1762         spin_unlock_irqrestore(&device_domain_lock, flags);
1763 }
1764
1765 /*
1766  * find_domain
1767  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1768  */
1769 static struct dmar_domain *
1770 find_domain(struct pci_dev *pdev)
1771 {
1772         struct device_domain_info *info;
1773
1774         /* No lock here, assumes no domain exit in normal case */
1775         info = pdev->dev.archdata.iommu;
1776         if (info)
1777                 return info->domain;
1778         return NULL;
1779 }
1780
1781 /* domain is initialized */
1782 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1783 {
1784         struct dmar_domain *domain, *found = NULL;
1785         struct intel_iommu *iommu;
1786         struct dmar_drhd_unit *drhd;
1787         struct device_domain_info *info, *tmp;
1788         struct pci_dev *dev_tmp;
1789         unsigned long flags;
1790         int bus = 0, devfn = 0;
1791         int segment;
1792         int ret;
1793
1794         domain = find_domain(pdev);
1795         if (domain)
1796                 return domain;
1797
1798         segment = pci_domain_nr(pdev->bus);
1799
1800         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1801         if (dev_tmp) {
1802                 if (dev_tmp->is_pcie) {
1803                         bus = dev_tmp->subordinate->number;
1804                         devfn = 0;
1805                 } else {
1806                         bus = dev_tmp->bus->number;
1807                         devfn = dev_tmp->devfn;
1808                 }
1809                 spin_lock_irqsave(&device_domain_lock, flags);
1810                 list_for_each_entry(info, &device_domain_list, global) {
1811                         if (info->segment == segment &&
1812                             info->bus == bus && info->devfn == devfn) {
1813                                 found = info->domain;
1814                                 break;
1815                         }
1816                 }
1817                 spin_unlock_irqrestore(&device_domain_lock, flags);
1818                 /* pcie-pci bridge already has a domain, uses it */
1819                 if (found) {
1820                         domain = found;
1821                         goto found_domain;
1822                 }
1823         }
1824
1825         domain = alloc_domain();
1826         if (!domain)
1827                 goto error;
1828
1829         /* Allocate new domain for the device */
1830         drhd = dmar_find_matched_drhd_unit(pdev);
1831         if (!drhd) {
1832                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1833                         pci_name(pdev));
1834                 return NULL;
1835         }
1836         iommu = drhd->iommu;
1837
1838         ret = iommu_attach_domain(domain, iommu);
1839         if (ret) {
1840                 domain_exit(domain);
1841                 goto error;
1842         }
1843
1844         if (domain_init(domain, gaw)) {
1845                 domain_exit(domain);
1846                 goto error;
1847         }
1848
1849         /* register pcie-to-pci device */
1850         if (dev_tmp) {
1851                 info = alloc_devinfo_mem();
1852                 if (!info) {
1853                         domain_exit(domain);
1854                         goto error;
1855                 }
1856                 info->segment = segment;
1857                 info->bus = bus;
1858                 info->devfn = devfn;
1859                 info->dev = NULL;
1860                 info->domain = domain;
1861                 /* This domain is shared by devices under p2p bridge */
1862                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1863
1864                 /* pcie-to-pci bridge already has a domain, uses it */
1865                 found = NULL;
1866                 spin_lock_irqsave(&device_domain_lock, flags);
1867                 list_for_each_entry(tmp, &device_domain_list, global) {
1868                         if (tmp->segment == segment &&
1869                             tmp->bus == bus && tmp->devfn == devfn) {
1870                                 found = tmp->domain;
1871                                 break;
1872                         }
1873                 }
1874                 if (found) {
1875                         free_devinfo_mem(info);
1876                         domain_exit(domain);
1877                         domain = found;
1878                 } else {
1879                         list_add(&info->link, &domain->devices);
1880                         list_add(&info->global, &device_domain_list);
1881                 }
1882                 spin_unlock_irqrestore(&device_domain_lock, flags);
1883         }
1884
1885 found_domain:
1886         info = alloc_devinfo_mem();
1887         if (!info)
1888                 goto error;
1889         info->segment = segment;
1890         info->bus = pdev->bus->number;
1891         info->devfn = pdev->devfn;
1892         info->dev = pdev;
1893         info->domain = domain;
1894         spin_lock_irqsave(&device_domain_lock, flags);
1895         /* somebody is fast */
1896         found = find_domain(pdev);
1897         if (found != NULL) {
1898                 spin_unlock_irqrestore(&device_domain_lock, flags);
1899                 if (found != domain) {
1900                         domain_exit(domain);
1901                         domain = found;
1902                 }
1903                 free_devinfo_mem(info);
1904                 return domain;
1905         }
1906         list_add(&info->link, &domain->devices);
1907         list_add(&info->global, &device_domain_list);
1908         pdev->dev.archdata.iommu = info;
1909         spin_unlock_irqrestore(&device_domain_lock, flags);
1910         return domain;
1911 error:
1912         /* recheck it here, maybe others set it */
1913         return find_domain(pdev);
1914 }
1915
1916 static int iommu_identity_mapping;
1917
1918 static int iommu_domain_identity_map(struct dmar_domain *domain,
1919                                      unsigned long long start,
1920                                      unsigned long long end)
1921 {
1922         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1923         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1924
1925         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1926                           dma_to_mm_pfn(last_vpfn))) {
1927                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1928                 return -ENOMEM;
1929         }
1930
1931         pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1932                  start, end, domain->id);
1933         /*
1934          * RMRR range might have overlap with physical memory range,
1935          * clear it first
1936          */
1937         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1938
1939         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1940                                   last_vpfn - first_vpfn + 1,
1941                                   DMA_PTE_READ|DMA_PTE_WRITE);
1942 }
1943
1944 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1945                                       unsigned long long start,
1946                                       unsigned long long end)
1947 {
1948         struct dmar_domain *domain;
1949         int ret;
1950
1951         printk(KERN_INFO
1952                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1953                pci_name(pdev), start, end);
1954
1955         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1956         if (!domain)
1957                 return -ENOMEM;
1958
1959         ret = iommu_domain_identity_map(domain, start, end);
1960         if (ret)
1961                 goto error;
1962
1963         /* context entry init */
1964         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1965         if (ret)
1966                 goto error;
1967
1968         return 0;
1969
1970  error:
1971         domain_exit(domain);
1972         return ret;
1973 }
1974
1975 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1976         struct pci_dev *pdev)
1977 {
1978         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1979                 return 0;
1980         return iommu_prepare_identity_map(pdev, rmrr->base_address,
1981                 rmrr->end_address + 1);
1982 }
1983
1984 #ifdef CONFIG_DMAR_FLOPPY_WA
1985 static inline void iommu_prepare_isa(void)
1986 {
1987         struct pci_dev *pdev;
1988         int ret;
1989
1990         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1991         if (!pdev)
1992                 return;
1993
1994         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1995         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1996
1997         if (ret)
1998                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
1999                        "floppy might not work\n");
2000
2001 }
2002 #else
2003 static inline void iommu_prepare_isa(void)
2004 {
2005         return;
2006 }
2007 #endif /* !CONFIG_DMAR_FLPY_WA */
2008
2009 /* Initialize each context entry as pass through.*/
2010 static int __init init_context_pass_through(void)
2011 {
2012         struct pci_dev *pdev = NULL;
2013         struct dmar_domain *domain;
2014         int ret;
2015
2016         for_each_pci_dev(pdev) {
2017                 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2018                 ret = domain_context_mapping(domain, pdev,
2019                                              CONTEXT_TT_PASS_THROUGH);
2020                 if (ret)
2021                         return ret;
2022         }
2023         return 0;
2024 }
2025
2026 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2027
2028 static int __init si_domain_work_fn(unsigned long start_pfn,
2029                                     unsigned long end_pfn, void *datax)
2030 {
2031         int *ret = datax;
2032
2033         *ret = iommu_domain_identity_map(si_domain,
2034                                          (uint64_t)start_pfn << PAGE_SHIFT,
2035                                          (uint64_t)end_pfn << PAGE_SHIFT);
2036         return *ret;
2037
2038 }
2039
2040 static int si_domain_init(void)
2041 {
2042         struct dmar_drhd_unit *drhd;
2043         struct intel_iommu *iommu;
2044         int nid, ret = 0;
2045
2046         si_domain = alloc_domain();
2047         if (!si_domain)
2048                 return -EFAULT;
2049
2050         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2051
2052         for_each_active_iommu(iommu, drhd) {
2053                 ret = iommu_attach_domain(si_domain, iommu);
2054                 if (ret) {
2055                         domain_exit(si_domain);
2056                         return -EFAULT;
2057                 }
2058         }
2059
2060         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2061                 domain_exit(si_domain);
2062                 return -EFAULT;
2063         }
2064
2065         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2066
2067         for_each_online_node(nid) {
2068                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2069                 if (ret)
2070                         return ret;
2071         }
2072
2073         return 0;
2074 }
2075
2076 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2077                                           struct pci_dev *pdev);
2078 static int identity_mapping(struct pci_dev *pdev)
2079 {
2080         struct device_domain_info *info;
2081
2082         if (likely(!iommu_identity_mapping))
2083                 return 0;
2084
2085
2086         list_for_each_entry(info, &si_domain->devices, link)
2087                 if (info->dev == pdev)
2088                         return 1;
2089         return 0;
2090 }
2091
2092 static int domain_add_dev_info(struct dmar_domain *domain,
2093                                   struct pci_dev *pdev)
2094 {
2095         struct device_domain_info *info;
2096         unsigned long flags;
2097
2098         info = alloc_devinfo_mem();
2099         if (!info)
2100                 return -ENOMEM;
2101
2102         info->segment = pci_domain_nr(pdev->bus);
2103         info->bus = pdev->bus->number;
2104         info->devfn = pdev->devfn;
2105         info->dev = pdev;
2106         info->domain = domain;
2107
2108         spin_lock_irqsave(&device_domain_lock, flags);
2109         list_add(&info->link, &domain->devices);
2110         list_add(&info->global, &device_domain_list);
2111         pdev->dev.archdata.iommu = info;
2112         spin_unlock_irqrestore(&device_domain_lock, flags);
2113
2114         return 0;
2115 }
2116
2117 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2118 {
2119         if (iommu_identity_mapping == 2)
2120                 return IS_GFX_DEVICE(pdev);
2121
2122         /*
2123          * We want to start off with all devices in the 1:1 domain, and
2124          * take them out later if we find they can't access all of memory.
2125          *
2126          * However, we can't do this for PCI devices behind bridges,
2127          * because all PCI devices behind the same bridge will end up
2128          * with the same source-id on their transactions.
2129          *
2130          * Practically speaking, we can't change things around for these
2131          * devices at run-time, because we can't be sure there'll be no
2132          * DMA transactions in flight for any of their siblings.
2133          * 
2134          * So PCI devices (unless they're on the root bus) as well as
2135          * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2136          * the 1:1 domain, just in _case_ one of their siblings turns out
2137          * not to be able to map all of memory.
2138          */
2139         if (!pdev->is_pcie) {
2140                 if (!pci_is_root_bus(pdev->bus))
2141                         return 0;
2142                 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2143                         return 0;
2144         } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2145                 return 0;
2146
2147         /* 
2148          * At boot time, we don't yet know if devices will be 64-bit capable.
2149          * Assume that they will -- if they turn out not to be, then we can 
2150          * take them out of the 1:1 domain later.
2151          */
2152         if (!startup)
2153                 return pdev->dma_mask > DMA_BIT_MASK(32);
2154
2155         return 1;
2156 }
2157
2158 static int iommu_prepare_static_identity_mapping(void)
2159 {
2160         struct pci_dev *pdev = NULL;
2161         int ret;
2162
2163         ret = si_domain_init();
2164         if (ret)
2165                 return -EFAULT;
2166
2167         for_each_pci_dev(pdev) {
2168                 if (iommu_should_identity_map(pdev, 1)) {
2169                         printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2170                                pci_name(pdev));
2171
2172                         ret = domain_context_mapping(si_domain, pdev,
2173                                                      CONTEXT_TT_MULTI_LEVEL);
2174                         if (ret)
2175                                 return ret;
2176                         ret = domain_add_dev_info(si_domain, pdev);
2177                         if (ret)
2178                                 return ret;
2179                 }
2180         }
2181
2182         return 0;
2183 }
2184
2185 int __init init_dmars(void)
2186 {
2187         struct dmar_drhd_unit *drhd;
2188         struct dmar_rmrr_unit *rmrr;
2189         struct pci_dev *pdev;
2190         struct intel_iommu *iommu;
2191         int i, ret;
2192         int pass_through = 1;
2193
2194         /*
2195          * In case pass through can not be enabled, iommu tries to use identity
2196          * mapping.
2197          */
2198         if (iommu_pass_through)
2199                 iommu_identity_mapping = 1;
2200
2201         /*
2202          * for each drhd
2203          *    allocate root
2204          *    initialize and program root entry to not present
2205          * endfor
2206          */
2207         for_each_drhd_unit(drhd) {
2208                 g_num_of_iommus++;
2209                 /*
2210                  * lock not needed as this is only incremented in the single
2211                  * threaded kernel __init code path all other access are read
2212                  * only
2213                  */
2214         }
2215
2216         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2217                         GFP_KERNEL);
2218         if (!g_iommus) {
2219                 printk(KERN_ERR "Allocating global iommu array failed\n");
2220                 ret = -ENOMEM;
2221                 goto error;
2222         }
2223
2224         deferred_flush = kzalloc(g_num_of_iommus *
2225                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2226         if (!deferred_flush) {
2227                 ret = -ENOMEM;
2228                 goto error;
2229         }
2230
2231         for_each_drhd_unit(drhd) {
2232                 if (drhd->ignored)
2233                         continue;
2234
2235                 iommu = drhd->iommu;
2236                 g_iommus[iommu->seq_id] = iommu;
2237
2238                 ret = iommu_init_domains(iommu);
2239                 if (ret)
2240                         goto error;
2241
2242                 /*
2243                  * TBD:
2244                  * we could share the same root & context tables
2245                  * amoung all IOMMU's. Need to Split it later.
2246                  */
2247                 ret = iommu_alloc_root_entry(iommu);
2248                 if (ret) {
2249                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2250                         goto error;
2251                 }
2252                 if (!ecap_pass_through(iommu->ecap))
2253                         pass_through = 0;
2254         }
2255         if (iommu_pass_through)
2256                 if (!pass_through) {
2257                         printk(KERN_INFO
2258                                "Pass Through is not supported by hardware.\n");
2259                         iommu_pass_through = 0;
2260                 }
2261
2262         /*
2263          * Start from the sane iommu hardware state.
2264          */
2265         for_each_drhd_unit(drhd) {
2266                 if (drhd->ignored)
2267                         continue;
2268
2269                 iommu = drhd->iommu;
2270
2271                 /*
2272                  * If the queued invalidation is already initialized by us
2273                  * (for example, while enabling interrupt-remapping) then
2274                  * we got the things already rolling from a sane state.
2275                  */
2276                 if (iommu->qi)
2277                         continue;
2278
2279                 /*
2280                  * Clear any previous faults.
2281                  */
2282                 dmar_fault(-1, iommu);
2283                 /*
2284                  * Disable queued invalidation if supported and already enabled
2285                  * before OS handover.
2286                  */
2287                 dmar_disable_qi(iommu);
2288         }
2289
2290         for_each_drhd_unit(drhd) {
2291                 if (drhd->ignored)
2292                         continue;
2293
2294                 iommu = drhd->iommu;
2295
2296                 if (dmar_enable_qi(iommu)) {
2297                         /*
2298                          * Queued Invalidate not enabled, use Register Based
2299                          * Invalidate
2300                          */
2301                         iommu->flush.flush_context = __iommu_flush_context;
2302                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2303                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2304                                "invalidation\n",
2305                                (unsigned long long)drhd->reg_base_addr);
2306                 } else {
2307                         iommu->flush.flush_context = qi_flush_context;
2308                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2309                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2310                                "invalidation\n",
2311                                (unsigned long long)drhd->reg_base_addr);
2312                 }
2313         }
2314
2315         /*
2316          * If pass through is set and enabled, context entries of all pci
2317          * devices are intialized by pass through translation type.
2318          */
2319         if (iommu_pass_through) {
2320                 ret = init_context_pass_through();
2321                 if (ret) {
2322                         printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2323                         iommu_pass_through = 0;
2324                 }
2325         }
2326
2327         /*
2328          * If pass through is not set or not enabled, setup context entries for
2329          * identity mappings for rmrr, gfx, and isa and may fall back to static
2330          * identity mapping if iommu_identity_mapping is set.
2331          */
2332         if (!iommu_pass_through) {
2333 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2334                 if (!iommu_identity_mapping)
2335                         iommu_identity_mapping = 2;
2336 #endif
2337                 if (iommu_identity_mapping)
2338                         iommu_prepare_static_identity_mapping();
2339                 /*
2340                  * For each rmrr
2341                  *   for each dev attached to rmrr
2342                  *   do
2343                  *     locate drhd for dev, alloc domain for dev
2344                  *     allocate free domain
2345                  *     allocate page table entries for rmrr
2346                  *     if context not allocated for bus
2347                  *           allocate and init context
2348                  *           set present in root table for this bus
2349                  *     init context with domain, translation etc
2350                  *    endfor
2351                  * endfor
2352                  */
2353                 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2354                 for_each_rmrr_units(rmrr) {
2355                         for (i = 0; i < rmrr->devices_cnt; i++) {
2356                                 pdev = rmrr->devices[i];
2357                                 /*
2358                                  * some BIOS lists non-exist devices in DMAR
2359                                  * table.
2360                                  */
2361                                 if (!pdev)
2362                                         continue;
2363                                 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2364                                 if (ret)
2365                                         printk(KERN_ERR
2366                                  "IOMMU: mapping reserved region failed\n");
2367                         }
2368                 }
2369
2370                 iommu_prepare_isa();
2371         }
2372
2373         /*
2374          * for each drhd
2375          *   enable fault log
2376          *   global invalidate context cache
2377          *   global invalidate iotlb
2378          *   enable translation
2379          */
2380         for_each_drhd_unit(drhd) {
2381                 if (drhd->ignored)
2382                         continue;
2383                 iommu = drhd->iommu;
2384
2385                 iommu_flush_write_buffer(iommu);
2386
2387                 ret = dmar_set_interrupt(iommu);
2388                 if (ret)
2389                         goto error;
2390
2391                 iommu_set_root_entry(iommu);
2392
2393                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2394                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2395                 iommu_disable_protect_mem_regions(iommu);
2396
2397                 ret = iommu_enable_translation(iommu);
2398                 if (ret)
2399                         goto error;
2400         }
2401
2402         return 0;
2403 error:
2404         for_each_drhd_unit(drhd) {
2405                 if (drhd->ignored)
2406                         continue;
2407                 iommu = drhd->iommu;
2408                 free_iommu(iommu);
2409         }
2410         kfree(g_iommus);
2411         return ret;
2412 }
2413
2414 /* Returns a number of VTD pages, but aligned to MM page size */
2415 static inline unsigned long aligned_nrpages(unsigned long host_addr,
2416                                             size_t size)
2417 {
2418         host_addr &= ~PAGE_MASK;
2419         return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
2420 }
2421
2422 /* This takes a number of _MM_ pages, not VTD pages */
2423 static struct iova *intel_alloc_iova(struct device *dev,
2424                                      struct dmar_domain *domain,
2425                                      unsigned long nrpages, uint64_t dma_mask)
2426 {
2427         struct pci_dev *pdev = to_pci_dev(dev);
2428         struct iova *iova = NULL;
2429
2430         /* Restrict dma_mask to the width that the iommu can handle */
2431         dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2432
2433         if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2434                 /*
2435                  * First try to allocate an io virtual address in
2436                  * DMA_BIT_MASK(32) and if that fails then try allocating
2437                  * from higher range
2438                  */
2439                 iova = alloc_iova(&domain->iovad, nrpages,
2440                                   IOVA_PFN(DMA_BIT_MASK(32)), 1);
2441                 if (iova)
2442                         return iova;
2443         }
2444         iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2445         if (unlikely(!iova)) {
2446                 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2447                        nrpages, pci_name(pdev));
2448                 return NULL;
2449         }
2450
2451         return iova;
2452 }
2453
2454 static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2455 {
2456         struct dmar_domain *domain;
2457         int ret;
2458
2459         domain = get_domain_for_dev(pdev,
2460                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2461         if (!domain) {
2462                 printk(KERN_ERR
2463                         "Allocating domain for %s failed", pci_name(pdev));
2464                 return NULL;
2465         }
2466
2467         /* make sure context mapping is ok */
2468         if (unlikely(!domain_context_mapped(pdev))) {
2469                 ret = domain_context_mapping(domain, pdev,
2470                                              CONTEXT_TT_MULTI_LEVEL);
2471                 if (ret) {
2472                         printk(KERN_ERR
2473                                 "Domain context map for %s failed",
2474                                 pci_name(pdev));
2475                         return NULL;
2476                 }
2477         }
2478
2479         return domain;
2480 }
2481
2482 static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2483 {
2484         struct device_domain_info *info;
2485
2486         /* No lock here, assumes no domain exit in normal case */
2487         info = dev->dev.archdata.iommu;
2488         if (likely(info))
2489                 return info->domain;
2490
2491         return __get_valid_domain_for_dev(dev);
2492 }
2493
2494 static int iommu_dummy(struct pci_dev *pdev)
2495 {
2496         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2497 }
2498
2499 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2500 static int iommu_no_mapping(struct device *dev)
2501 {
2502         struct pci_dev *pdev;
2503         int found;
2504
2505         if (unlikely(dev->bus != &pci_bus_type))
2506                 return 1;
2507
2508         pdev = to_pci_dev(dev);
2509         if (iommu_dummy(pdev))
2510                 return 1;
2511
2512         if (!iommu_identity_mapping)
2513                 return 0;
2514
2515         found = identity_mapping(pdev);
2516         if (found) {
2517                 if (iommu_should_identity_map(pdev, 0))
2518                         return 1;
2519                 else {
2520                         /*
2521                          * 32 bit DMA is removed from si_domain and fall back
2522                          * to non-identity mapping.
2523                          */
2524                         domain_remove_one_dev_info(si_domain, pdev);
2525                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2526                                pci_name(pdev));
2527                         return 0;
2528                 }
2529         } else {
2530                 /*
2531                  * In case of a detached 64 bit DMA device from vm, the device
2532                  * is put into si_domain for identity mapping.
2533                  */
2534                 if (iommu_should_identity_map(pdev, 0)) {
2535                         int ret;
2536                         ret = domain_add_dev_info(si_domain, pdev);
2537                         if (ret)
2538                                 return 0;
2539                         ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2540                         if (!ret) {
2541                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2542                                        pci_name(pdev));
2543                                 return 1;
2544                         }
2545                 }
2546         }
2547
2548         return 0;
2549 }
2550
2551 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2552                                      size_t size, int dir, u64 dma_mask)
2553 {
2554         struct pci_dev *pdev = to_pci_dev(hwdev);
2555         struct dmar_domain *domain;
2556         phys_addr_t start_paddr;
2557         struct iova *iova;
2558         int prot = 0;
2559         int ret;
2560         struct intel_iommu *iommu;
2561
2562         BUG_ON(dir == DMA_NONE);
2563
2564         if (iommu_no_mapping(hwdev))
2565                 return paddr;
2566
2567         domain = get_valid_domain_for_dev(pdev);
2568         if (!domain)
2569                 return 0;
2570
2571         iommu = domain_get_iommu(domain);
2572         size = aligned_nrpages(paddr, size);
2573
2574         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2575                                 pdev->dma_mask);
2576         if (!iova)
2577                 goto error;
2578
2579         /*
2580          * Check if DMAR supports zero-length reads on write only
2581          * mappings..
2582          */
2583         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2584                         !cap_zlr(iommu->cap))
2585                 prot |= DMA_PTE_READ;
2586         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2587                 prot |= DMA_PTE_WRITE;
2588         /*
2589          * paddr - (paddr + size) might be partial page, we should map the whole
2590          * page.  Note: if two part of one page are separately mapped, we
2591          * might have two guest_addr mapping to the same host paddr, but this
2592          * is not a big problem
2593          */
2594         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2595                                  paddr >> VTD_PAGE_SHIFT, size, prot);
2596         if (ret)
2597                 goto error;
2598
2599         /* it's a non-present to present mapping. Only flush if caching mode */
2600         if (cap_caching_mode(iommu->cap))
2601                 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2602         else
2603                 iommu_flush_write_buffer(iommu);
2604
2605         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2606         start_paddr += paddr & ~PAGE_MASK;
2607         return start_paddr;
2608
2609 error:
2610         if (iova)
2611                 __free_iova(&domain->iovad, iova);
2612         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2613                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2614         return 0;
2615 }
2616
2617 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2618                                  unsigned long offset, size_t size,
2619                                  enum dma_data_direction dir,
2620                                  struct dma_attrs *attrs)
2621 {
2622         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2623                                   dir, to_pci_dev(dev)->dma_mask);
2624 }
2625
2626 static void flush_unmaps(void)
2627 {
2628         int i, j;
2629
2630         timer_on = 0;
2631
2632         /* just flush them all */
2633         for (i = 0; i < g_num_of_iommus; i++) {
2634                 struct intel_iommu *iommu = g_iommus[i];
2635                 if (!iommu)
2636                         continue;
2637
2638                 if (!deferred_flush[i].next)
2639                         continue;
2640
2641                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2642                                          DMA_TLB_GLOBAL_FLUSH);
2643                 for (j = 0; j < deferred_flush[i].next; j++) {
2644                         unsigned long mask;
2645                         struct iova *iova = deferred_flush[i].iova[j];
2646
2647                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2648                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2649                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2650                                         iova->pfn_lo << PAGE_SHIFT, mask);
2651                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2652                 }
2653                 deferred_flush[i].next = 0;
2654         }
2655
2656         list_size = 0;
2657 }
2658
2659 static void flush_unmaps_timeout(unsigned long data)
2660 {
2661         unsigned long flags;
2662
2663         spin_lock_irqsave(&async_umap_flush_lock, flags);
2664         flush_unmaps();
2665         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2666 }
2667
2668 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2669 {
2670         unsigned long flags;
2671         int next, iommu_id;
2672         struct intel_iommu *iommu;
2673
2674         spin_lock_irqsave(&async_umap_flush_lock, flags);
2675         if (list_size == HIGH_WATER_MARK)
2676                 flush_unmaps();
2677
2678         iommu = domain_get_iommu(dom);
2679         iommu_id = iommu->seq_id;
2680
2681         next = deferred_flush[iommu_id].next;
2682         deferred_flush[iommu_id].domain[next] = dom;
2683         deferred_flush[iommu_id].iova[next] = iova;
2684         deferred_flush[iommu_id].next++;
2685
2686         if (!timer_on) {
2687                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2688                 timer_on = 1;
2689         }
2690         list_size++;
2691         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2692 }
2693
2694 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2695                              size_t size, enum dma_data_direction dir,
2696                              struct dma_attrs *attrs)
2697 {
2698         struct pci_dev *pdev = to_pci_dev(dev);
2699         struct dmar_domain *domain;
2700         unsigned long start_pfn, last_pfn;
2701         struct iova *iova;
2702         struct intel_iommu *iommu;
2703
2704         if (iommu_no_mapping(dev))
2705                 return;
2706
2707         domain = find_domain(pdev);
2708         BUG_ON(!domain);
2709
2710         iommu = domain_get_iommu(domain);
2711
2712         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2713         if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2714                       (unsigned long long)dev_addr))
2715                 return;
2716
2717         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2718         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2719
2720         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2721                  pci_name(pdev), start_pfn, last_pfn);
2722
2723         /*  clear the whole page */
2724         dma_pte_clear_range(domain, start_pfn, last_pfn);
2725
2726         /* free page tables */
2727         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2728
2729         if (intel_iommu_strict) {
2730                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2731                                       last_pfn - start_pfn + 1);
2732                 /* free iova */
2733                 __free_iova(&domain->iovad, iova);
2734         } else {
2735                 add_unmap(domain, iova);
2736                 /*
2737                  * queue up the release of the unmap to save the 1/6th of the
2738                  * cpu used up by the iotlb flush operation...
2739                  */
2740         }
2741 }
2742
2743 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2744                                   dma_addr_t *dma_handle, gfp_t flags)
2745 {
2746         void *vaddr;
2747         int order;
2748
2749         size = PAGE_ALIGN(size);
2750         order = get_order(size);
2751         flags &= ~(GFP_DMA | GFP_DMA32);
2752
2753         vaddr = (void *)__get_free_pages(flags, order);
2754         if (!vaddr)
2755                 return NULL;
2756         memset(vaddr, 0, size);
2757
2758         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2759                                          DMA_BIDIRECTIONAL,
2760                                          hwdev->coherent_dma_mask);
2761         if (*dma_handle)
2762                 return vaddr;
2763         free_pages((unsigned long)vaddr, order);
2764         return NULL;
2765 }
2766
2767 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2768                                 dma_addr_t dma_handle)
2769 {
2770         int order;
2771
2772         size = PAGE_ALIGN(size);
2773         order = get_order(size);
2774
2775         intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
2776         free_pages((unsigned long)vaddr, order);
2777 }
2778
2779 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2780                            int nelems, enum dma_data_direction dir,
2781                            struct dma_attrs *attrs)
2782 {
2783         struct pci_dev *pdev = to_pci_dev(hwdev);
2784         struct dmar_domain *domain;
2785         unsigned long start_pfn, last_pfn;
2786         struct iova *iova;
2787         struct intel_iommu *iommu;
2788
2789         if (iommu_no_mapping(hwdev))
2790                 return;
2791
2792         domain = find_domain(pdev);
2793         BUG_ON(!domain);
2794
2795         iommu = domain_get_iommu(domain);
2796
2797         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2798         if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2799                       (unsigned long long)sglist[0].dma_address))
2800                 return;
2801
2802         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2803         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2804
2805         /*  clear the whole page */
2806         dma_pte_clear_range(domain, start_pfn, last_pfn);
2807
2808         /* free page tables */
2809         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2810
2811         if (intel_iommu_strict) {
2812                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2813                                       last_pfn - start_pfn + 1);
2814                 /* free iova */
2815                 __free_iova(&domain->iovad, iova);
2816         } else {
2817                 add_unmap(domain, iova);
2818                 /*
2819                  * queue up the release of the unmap to save the 1/6th of the
2820                  * cpu used up by the iotlb flush operation...
2821                  */
2822         }
2823 }
2824
2825 static int intel_nontranslate_map_sg(struct device *hddev,
2826         struct scatterlist *sglist, int nelems, int dir)
2827 {
2828         int i;
2829         struct scatterlist *sg;
2830
2831         for_each_sg(sglist, sg, nelems, i) {
2832                 BUG_ON(!sg_page(sg));
2833                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2834                 sg->dma_length = sg->length;
2835         }
2836         return nelems;
2837 }
2838
2839 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2840                         enum dma_data_direction dir, struct dma_attrs *attrs)
2841 {
2842         int i;
2843         struct pci_dev *pdev = to_pci_dev(hwdev);
2844         struct dmar_domain *domain;
2845         size_t size = 0;
2846         int prot = 0;
2847         size_t offset_pfn = 0;
2848         struct iova *iova = NULL;
2849         int ret;
2850         struct scatterlist *sg;
2851         unsigned long start_vpfn;
2852         struct intel_iommu *iommu;
2853
2854         BUG_ON(dir == DMA_NONE);
2855         if (iommu_no_mapping(hwdev))
2856                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2857
2858         domain = get_valid_domain_for_dev(pdev);
2859         if (!domain)
2860                 return 0;
2861
2862         iommu = domain_get_iommu(domain);
2863
2864         for_each_sg(sglist, sg, nelems, i)
2865                 size += aligned_nrpages(sg->offset, sg->length);
2866
2867         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2868                                 pdev->dma_mask);
2869         if (!iova) {
2870                 sglist->dma_length = 0;
2871                 return 0;
2872         }
2873
2874         /*
2875          * Check if DMAR supports zero-length reads on write only
2876          * mappings..
2877          */
2878         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2879                         !cap_zlr(iommu->cap))
2880                 prot |= DMA_PTE_READ;
2881         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2882                 prot |= DMA_PTE_WRITE;
2883
2884         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2885
2886         ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot);
2887         if (unlikely(ret)) {
2888                 /*  clear the page */
2889                 dma_pte_clear_range(domain, start_vpfn,
2890                                     start_vpfn + size - 1);
2891                 /* free page tables */
2892                 dma_pte_free_pagetable(domain, start_vpfn,
2893                                        start_vpfn + size - 1);
2894                 /* free iova */
2895                 __free_iova(&domain->iovad, iova);
2896                 return 0;
2897         }
2898
2899         /* it's a non-present to present mapping. Only flush if caching mode */
2900         if (cap_caching_mode(iommu->cap))
2901                 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2902         else
2903                 iommu_flush_write_buffer(iommu);
2904
2905         return nelems;
2906 }
2907
2908 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2909 {
2910         return !dma_addr;
2911 }
2912
2913 struct dma_map_ops intel_dma_ops = {
2914         .alloc_coherent = intel_alloc_coherent,
2915         .free_coherent = intel_free_coherent,
2916         .map_sg = intel_map_sg,
2917         .unmap_sg = intel_unmap_sg,
2918         .map_page = intel_map_page,
2919         .unmap_page = intel_unmap_page,
2920         .mapping_error = intel_mapping_error,
2921 };
2922
2923 static inline int iommu_domain_cache_init(void)
2924 {
2925         int ret = 0;
2926
2927         iommu_domain_cache = kmem_cache_create("iommu_domain",
2928                                          sizeof(struct dmar_domain),
2929                                          0,
2930                                          SLAB_HWCACHE_ALIGN,
2931
2932                                          NULL);
2933         if (!iommu_domain_cache) {
2934                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2935                 ret = -ENOMEM;
2936         }
2937
2938         return ret;
2939 }
2940
2941 static inline int iommu_devinfo_cache_init(void)
2942 {
2943         int ret = 0;
2944
2945         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2946                                          sizeof(struct device_domain_info),
2947                                          0,
2948                                          SLAB_HWCACHE_ALIGN,
2949                                          NULL);
2950         if (!iommu_devinfo_cache) {
2951                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2952                 ret = -ENOMEM;
2953         }
2954
2955         return ret;
2956 }
2957
2958 static inline int iommu_iova_cache_init(void)
2959 {
2960         int ret = 0;
2961
2962         iommu_iova_cache = kmem_cache_create("iommu_iova",
2963                                          sizeof(struct iova),
2964                                          0,
2965                                          SLAB_HWCACHE_ALIGN,
2966                                          NULL);
2967         if (!iommu_iova_cache) {
2968                 printk(KERN_ERR "Couldn't create iova cache\n");
2969                 ret = -ENOMEM;
2970         }
2971
2972         return ret;
2973 }
2974
2975 static int __init iommu_init_mempool(void)
2976 {
2977         int ret;
2978         ret = iommu_iova_cache_init();
2979         if (ret)
2980                 return ret;
2981
2982         ret = iommu_domain_cache_init();
2983         if (ret)
2984                 goto domain_error;
2985
2986         ret = iommu_devinfo_cache_init();
2987         if (!ret)
2988                 return ret;
2989
2990         kmem_cache_destroy(iommu_domain_cache);
2991 domain_error:
2992         kmem_cache_destroy(iommu_iova_cache);
2993
2994         return -ENOMEM;
2995 }
2996
2997 static void __init iommu_exit_mempool(void)
2998 {
2999         kmem_cache_destroy(iommu_devinfo_cache);
3000         kmem_cache_destroy(iommu_domain_cache);
3001         kmem_cache_destroy(iommu_iova_cache);
3002
3003 }
3004
3005 static void __init init_no_remapping_devices(void)
3006 {
3007         struct dmar_drhd_unit *drhd;
3008
3009         for_each_drhd_unit(drhd) {
3010                 if (!drhd->include_all) {
3011                         int i;
3012                         for (i = 0; i < drhd->devices_cnt; i++)
3013                                 if (drhd->devices[i] != NULL)
3014                                         break;
3015                         /* ignore DMAR unit if no pci devices exist */
3016                         if (i == drhd->devices_cnt)
3017                                 drhd->ignored = 1;
3018                 }
3019         }
3020
3021         if (dmar_map_gfx)
3022                 return;
3023
3024         for_each_drhd_unit(drhd) {
3025                 int i;
3026                 if (drhd->ignored || drhd->include_all)
3027                         continue;
3028
3029                 for (i = 0; i < drhd->devices_cnt; i++)
3030                         if (drhd->devices[i] &&
3031                                 !IS_GFX_DEVICE(drhd->devices[i]))
3032                                 break;
3033
3034                 if (i < drhd->devices_cnt)
3035                         continue;
3036
3037                 /* bypass IOMMU if it is just for gfx devices */
3038                 drhd->ignored = 1;
3039                 for (i = 0; i < drhd->devices_cnt; i++) {
3040                         if (!drhd->devices[i])
3041                                 continue;
3042                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3043                 }
3044         }
3045 }
3046
3047 #ifdef CONFIG_SUSPEND
3048 static int init_iommu_hw(void)
3049 {
3050         struct dmar_drhd_unit *drhd;
3051         struct intel_iommu *iommu = NULL;
3052
3053         for_each_active_iommu(iommu, drhd)
3054                 if (iommu->qi)
3055                         dmar_reenable_qi(iommu);
3056
3057         for_each_active_iommu(iommu, drhd) {
3058                 iommu_flush_write_buffer(iommu);
3059
3060                 iommu_set_root_entry(iommu);
3061
3062                 iommu->flush.flush_context(iommu, 0, 0, 0,
3063                                            DMA_CCMD_GLOBAL_INVL);
3064                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3065                                          DMA_TLB_GLOBAL_FLUSH);
3066                 iommu_disable_protect_mem_regions(iommu);
3067                 iommu_enable_translation(iommu);
3068         }
3069
3070         return 0;
3071 }
3072
3073 static void iommu_flush_all(void)
3074 {
3075         struct dmar_drhd_unit *drhd;
3076         struct intel_iommu *iommu;
3077
3078         for_each_active_iommu(iommu, drhd) {
3079                 iommu->flush.flush_context(iommu, 0, 0, 0,
3080                                            DMA_CCMD_GLOBAL_INVL);
3081                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3082                                          DMA_TLB_GLOBAL_FLUSH);
3083         }
3084 }
3085
3086 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3087 {
3088         struct dmar_drhd_unit *drhd;
3089         struct intel_iommu *iommu = NULL;
3090         unsigned long flag;
3091
3092         for_each_active_iommu(iommu, drhd) {
3093                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3094                                                  GFP_ATOMIC);
3095                 if (!iommu->iommu_state)
3096                         goto nomem;
3097         }
3098
3099         iommu_flush_all();
3100
3101         for_each_active_iommu(iommu, drhd) {
3102                 iommu_disable_translation(iommu);
3103
3104                 spin_lock_irqsave(&iommu->register_lock, flag);
3105
3106                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3107                         readl(iommu->reg + DMAR_FECTL_REG);
3108                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3109                         readl(iommu->reg + DMAR_FEDATA_REG);
3110                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3111                         readl(iommu->reg + DMAR_FEADDR_REG);
3112                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3113                         readl(iommu->reg + DMAR_FEUADDR_REG);
3114
3115                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3116         }
3117         return 0;
3118
3119 nomem:
3120         for_each_active_iommu(iommu, drhd)
3121                 kfree(iommu->iommu_state);
3122
3123         return -ENOMEM;
3124 }
3125
3126 static int iommu_resume(struct sys_device *dev)
3127 {
3128         struct dmar_drhd_unit *drhd;
3129         struct intel_iommu *iommu = NULL;
3130         unsigned long flag;
3131
3132         if (init_iommu_hw()) {
3133                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3134                 return -EIO;
3135         }
3136
3137         for_each_active_iommu(iommu, drhd) {
3138
3139                 spin_lock_irqsave(&iommu->register_lock, flag);
3140
3141                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3142                         iommu->reg + DMAR_FECTL_REG);
3143                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3144                         iommu->reg + DMAR_FEDATA_REG);
3145                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3146                         iommu->reg + DMAR_FEADDR_REG);
3147                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3148                         iommu->reg + DMAR_FEUADDR_REG);
3149
3150                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3151         }
3152
3153         for_each_active_iommu(iommu, drhd)
3154                 kfree(iommu->iommu_state);
3155
3156         return 0;
3157 }
3158
3159 static struct sysdev_class iommu_sysclass = {
3160         .name           = "iommu",
3161         .resume         = iommu_resume,
3162         .suspend        = iommu_suspend,
3163 };
3164
3165 static struct sys_device device_iommu = {
3166         .cls    = &iommu_sysclass,
3167 };
3168
3169 static int __init init_iommu_sysfs(void)
3170 {
3171         int error;
3172
3173         error = sysdev_class_register(&iommu_sysclass);
3174         if (error)
3175                 return error;
3176
3177         error = sysdev_register(&device_iommu);
3178         if (error)
3179                 sysdev_class_unregister(&iommu_sysclass);
3180
3181         return error;
3182 }
3183
3184 #else
3185 static int __init init_iommu_sysfs(void)
3186 {
3187         return 0;
3188 }
3189 #endif  /* CONFIG_PM */
3190
3191 int __init intel_iommu_init(void)
3192 {
3193         int ret = 0;
3194
3195         if (dmar_table_init())
3196                 return  -ENODEV;
3197
3198         if (dmar_dev_scope_init())
3199                 return  -ENODEV;
3200
3201         /*
3202          * Check the need for DMA-remapping initialization now.
3203          * Above initialization will also be used by Interrupt-remapping.
3204          */
3205         if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3206                 return -ENODEV;
3207
3208         iommu_init_mempool();
3209         dmar_init_reserved_ranges();
3210
3211         init_no_remapping_devices();
3212
3213         ret = init_dmars();
3214         if (ret) {
3215                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3216                 put_iova_domain(&reserved_iova_list);
3217                 iommu_exit_mempool();
3218                 return ret;
3219         }
3220         printk(KERN_INFO
3221         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3222
3223         init_timer(&unmap_timer);
3224         force_iommu = 1;
3225
3226         if (!iommu_pass_through) {
3227                 printk(KERN_INFO
3228                        "Multi-level page-table translation for DMAR.\n");
3229                 dma_ops = &intel_dma_ops;
3230         } else
3231                 printk(KERN_INFO
3232                        "DMAR: Pass through translation for DMAR.\n");
3233
3234         init_iommu_sysfs();
3235
3236         register_iommu(&intel_iommu_ops);
3237
3238         return 0;
3239 }
3240
3241 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3242                                            struct pci_dev *pdev)
3243 {
3244         struct pci_dev *tmp, *parent;
3245
3246         if (!iommu || !pdev)
3247                 return;
3248
3249         /* dependent device detach */
3250         tmp = pci_find_upstream_pcie_bridge(pdev);
3251         /* Secondary interface's bus number and devfn 0 */
3252         if (tmp) {
3253                 parent = pdev->bus->self;
3254                 while (parent != tmp) {
3255                         iommu_detach_dev(iommu, parent->bus->number,
3256                                          parent->devfn);
3257                         parent = parent->bus->self;
3258                 }
3259                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3260                         iommu_detach_dev(iommu,
3261                                 tmp->subordinate->number, 0);
3262                 else /* this is a legacy PCI bridge */
3263                         iommu_detach_dev(iommu, tmp->bus->number,
3264                                          tmp->devfn);
3265         }
3266 }
3267
3268 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3269                                           struct pci_dev *pdev)
3270 {
3271         struct device_domain_info *info;
3272         struct intel_iommu *iommu;
3273         unsigned long flags;
3274         int found = 0;
3275         struct list_head *entry, *tmp;
3276
3277         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3278                                 pdev->devfn);
3279         if (!iommu)
3280                 return;
3281
3282         spin_lock_irqsave(&device_domain_lock, flags);
3283         list_for_each_safe(entry, tmp, &domain->devices) {
3284                 info = list_entry(entry, struct device_domain_info, link);
3285                 /* No need to compare PCI domain; it has to be the same */
3286                 if (info->bus == pdev->bus->number &&
3287                     info->devfn == pdev->devfn) {
3288                         list_del(&info->link);
3289                         list_del(&info->global);
3290                         if (info->dev)
3291                                 info->dev->dev.archdata.iommu = NULL;
3292                         spin_unlock_irqrestore(&device_domain_lock, flags);
3293
3294                         iommu_disable_dev_iotlb(info);
3295                         iommu_detach_dev(iommu, info->bus, info->devfn);
3296                         iommu_detach_dependent_devices(iommu, pdev);
3297                         free_devinfo_mem(info);
3298
3299                         spin_lock_irqsave(&device_domain_lock, flags);
3300
3301                         if (found)
3302                                 break;
3303                         else
3304                                 continue;
3305                 }
3306
3307                 /* if there is no other devices under the same iommu
3308                  * owned by this domain, clear this iommu in iommu_bmp
3309                  * update iommu count and coherency
3310                  */
3311                 if (iommu == device_to_iommu(info->segment, info->bus,
3312                                             info->devfn))
3313                         found = 1;
3314         }
3315
3316         if (found == 0) {
3317                 unsigned long tmp_flags;
3318                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3319                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3320                 domain->iommu_count--;
3321                 domain_update_iommu_cap(domain);
3322                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3323         }
3324
3325         spin_unlock_irqrestore(&device_domain_lock, flags);
3326 }
3327
3328 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3329 {
3330         struct device_domain_info *info;
3331         struct intel_iommu *iommu;
3332         unsigned long flags1, flags2;
3333
3334         spin_lock_irqsave(&device_domain_lock, flags1);
3335         while (!list_empty(&domain->devices)) {
3336                 info = list_entry(domain->devices.next,
3337                         struct device_domain_info, link);
3338                 list_del(&info->link);
3339                 list_del(&info->global);
3340                 if (info->dev)
3341                         info->dev->dev.archdata.iommu = NULL;
3342
3343                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3344
3345                 iommu_disable_dev_iotlb(info);
3346                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3347                 iommu_detach_dev(iommu, info->bus, info->devfn);
3348                 iommu_detach_dependent_devices(iommu, info->dev);
3349
3350                 /* clear this iommu in iommu_bmp, update iommu count
3351                  * and capabilities
3352                  */
3353                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3354                 if (test_and_clear_bit(iommu->seq_id,
3355                                        &domain->iommu_bmp)) {
3356                         domain->iommu_count--;
3357                         domain_update_iommu_cap(domain);
3358                 }
3359                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3360
3361                 free_devinfo_mem(info);
3362                 spin_lock_irqsave(&device_domain_lock, flags1);
3363         }
3364         spin_unlock_irqrestore(&device_domain_lock, flags1);
3365 }
3366
3367 /* domain id for virtual machine, it won't be set in context */
3368 static unsigned long vm_domid;
3369
3370 static int vm_domain_min_agaw(struct dmar_domain *domain)
3371 {
3372         int i;
3373         int min_agaw = domain->agaw;
3374
3375         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3376         for (; i < g_num_of_iommus; ) {
3377                 if (min_agaw > g_iommus[i]->agaw)
3378                         min_agaw = g_iommus[i]->agaw;
3379
3380                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3381         }
3382
3383         return min_agaw;
3384 }
3385
3386 static struct dmar_domain *iommu_alloc_vm_domain(void)
3387 {
3388         struct dmar_domain *domain;
3389
3390         domain = alloc_domain_mem();
3391         if (!domain)
3392                 return NULL;
3393
3394         domain->id = vm_domid++;
3395         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3396         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3397
3398         return domain;
3399 }
3400
3401 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3402 {
3403         int adjust_width;
3404
3405         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3406         spin_lock_init(&domain->iommu_lock);
3407
3408         domain_reserve_special_ranges(domain);
3409
3410         /* calculate AGAW */
3411         domain->gaw = guest_width;
3412         adjust_width = guestwidth_to_adjustwidth(guest_width);
3413         domain->agaw = width_to_agaw(adjust_width);
3414
3415         INIT_LIST_HEAD(&domain->devices);
3416
3417         domain->iommu_count = 0;
3418         domain->iommu_coherency = 0;
3419         domain->max_addr = 0;
3420
3421         /* always allocate the top pgd */
3422         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3423         if (!domain->pgd)
3424                 return -ENOMEM;
3425         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3426         return 0;
3427 }
3428
3429 static void iommu_free_vm_domain(struct dmar_domain *domain)
3430 {
3431         unsigned long flags;
3432         struct dmar_drhd_unit *drhd;
3433         struct intel_iommu *iommu;
3434         unsigned long i;
3435         unsigned long ndomains;
3436
3437         for_each_drhd_unit(drhd) {
3438                 if (drhd->ignored)
3439                         continue;
3440                 iommu = drhd->iommu;
3441
3442                 ndomains = cap_ndoms(iommu->cap);
3443                 i = find_first_bit(iommu->domain_ids, ndomains);
3444                 for (; i < ndomains; ) {
3445                         if (iommu->domains[i] == domain) {
3446                                 spin_lock_irqsave(&iommu->lock, flags);
3447                                 clear_bit(i, iommu->domain_ids);
3448                                 iommu->domains[i] = NULL;
3449                                 spin_unlock_irqrestore(&iommu->lock, flags);
3450                                 break;
3451                         }
3452                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3453                 }
3454         }
3455 }
3456
3457 static void vm_domain_exit(struct dmar_domain *domain)
3458 {
3459         /* Domain 0 is reserved, so dont process it */
3460         if (!domain)
3461                 return;
3462
3463         vm_domain_remove_all_dev_info(domain);
3464         /* destroy iovas */
3465         put_iova_domain(&domain->iovad);
3466
3467         /* clear ptes */
3468         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3469
3470         /* free page tables */
3471         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3472
3473         iommu_free_vm_domain(domain);
3474         free_domain_mem(domain);
3475 }
3476
3477 static int intel_iommu_domain_init(struct iommu_domain *domain)
3478 {
3479         struct dmar_domain *dmar_domain;
3480
3481         dmar_domain = iommu_alloc_vm_domain();
3482         if (!dmar_domain) {
3483                 printk(KERN_ERR
3484                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3485                 return -ENOMEM;
3486         }
3487         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3488                 printk(KERN_ERR
3489                         "intel_iommu_domain_init() failed\n");
3490                 vm_domain_exit(dmar_domain);
3491                 return -ENOMEM;
3492         }
3493         domain->priv = dmar_domain;
3494
3495         return 0;
3496 }
3497
3498 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3499 {
3500         struct dmar_domain *dmar_domain = domain->priv;
3501
3502         domain->priv = NULL;
3503         vm_domain_exit(dmar_domain);
3504 }
3505
3506 static int intel_iommu_attach_device(struct iommu_domain *domain,
3507                                      struct device *dev)
3508 {
3509         struct dmar_domain *dmar_domain = domain->priv;
3510         struct pci_dev *pdev = to_pci_dev(dev);
3511         struct intel_iommu *iommu;
3512         int addr_width;
3513         u64 end;
3514         int ret;
3515
3516         /* normally pdev is not mapped */
3517         if (unlikely(domain_context_mapped(pdev))) {
3518                 struct dmar_domain *old_domain;
3519
3520                 old_domain = find_domain(pdev);
3521                 if (old_domain) {
3522                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3523                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3524                                 domain_remove_one_dev_info(old_domain, pdev);
3525                         else
3526                                 domain_remove_dev_info(old_domain);
3527                 }
3528         }
3529
3530         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3531                                 pdev->devfn);
3532         if (!iommu)
3533                 return -ENODEV;
3534
3535         /* check if this iommu agaw is sufficient for max mapped address */
3536         addr_width = agaw_to_width(iommu->agaw);
3537         end = DOMAIN_MAX_ADDR(addr_width);
3538         end = end & VTD_PAGE_MASK;
3539         if (end < dmar_domain->max_addr) {
3540                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3541                        "sufficient for the mapped address (%llx)\n",
3542                        __func__, iommu->agaw, dmar_domain->max_addr);
3543                 return -EFAULT;
3544         }
3545
3546         ret = domain_add_dev_info(dmar_domain, pdev);
3547         if (ret)
3548                 return ret;
3549
3550         ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3551         return ret;
3552 }
3553
3554 static void intel_iommu_detach_device(struct iommu_domain *domain,
3555                                       struct device *dev)
3556 {
3557         struct dmar_domain *dmar_domain = domain->priv;
3558         struct pci_dev *pdev = to_pci_dev(dev);
3559
3560         domain_remove_one_dev_info(dmar_domain, pdev);
3561 }
3562
3563 static int intel_iommu_map_range(struct iommu_domain *domain,
3564                                  unsigned long iova, phys_addr_t hpa,
3565                                  size_t size, int iommu_prot)
3566 {
3567         struct dmar_domain *dmar_domain = domain->priv;
3568         u64 max_addr;
3569         int addr_width;
3570         int prot = 0;
3571         int ret;
3572
3573         if (iommu_prot & IOMMU_READ)
3574                 prot |= DMA_PTE_READ;
3575         if (iommu_prot & IOMMU_WRITE)
3576                 prot |= DMA_PTE_WRITE;
3577         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3578                 prot |= DMA_PTE_SNP;
3579
3580         max_addr = iova + size;
3581         if (dmar_domain->max_addr < max_addr) {
3582                 int min_agaw;
3583                 u64 end;
3584
3585                 /* check if minimum agaw is sufficient for mapped address */
3586                 min_agaw = vm_domain_min_agaw(dmar_domain);
3587                 addr_width = agaw_to_width(min_agaw);
3588                 end = DOMAIN_MAX_ADDR(addr_width);
3589                 end = end & VTD_PAGE_MASK;
3590                 if (end < max_addr) {
3591                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3592                                "sufficient for the mapped address (%llx)\n",
3593                                __func__, min_agaw, max_addr);
3594                         return -EFAULT;
3595                 }
3596                 dmar_domain->max_addr = max_addr;
3597         }
3598         /* Round up size to next multiple of PAGE_SIZE, if it and
3599            the low bits of hpa would take us onto the next page */
3600         size = aligned_nrpages(hpa, size);
3601         ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3602                                  hpa >> VTD_PAGE_SHIFT, size, prot);
3603         return ret;
3604 }
3605
3606 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3607                                     unsigned long iova, size_t size)
3608 {
3609         struct dmar_domain *dmar_domain = domain->priv;
3610
3611         dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3612                             (iova + size - 1) >> VTD_PAGE_SHIFT);
3613
3614         if (dmar_domain->max_addr == iova + size)
3615                 dmar_domain->max_addr = iova;
3616 }
3617
3618 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3619                                             unsigned long iova)
3620 {
3621         struct dmar_domain *dmar_domain = domain->priv;
3622         struct dma_pte *pte;
3623         u64 phys = 0;
3624
3625         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3626         if (pte)
3627                 phys = dma_pte_addr(pte);
3628
3629         return phys;
3630 }
3631
3632 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3633                                       unsigned long cap)
3634 {
3635         struct dmar_domain *dmar_domain = domain->priv;
3636
3637         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3638                 return dmar_domain->iommu_snooping;
3639
3640         return 0;
3641 }
3642
3643 static struct iommu_ops intel_iommu_ops = {
3644         .domain_init    = intel_iommu_domain_init,
3645         .domain_destroy = intel_iommu_domain_destroy,
3646         .attach_dev     = intel_iommu_attach_device,
3647         .detach_dev     = intel_iommu_detach_device,
3648         .map            = intel_iommu_map_range,
3649         .unmap          = intel_iommu_unmap_range,
3650         .iova_to_phys   = intel_iommu_iova_to_phys,
3651         .domain_has_cap = intel_iommu_domain_has_cap,
3652 };
3653
3654 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3655 {
3656         /*
3657          * Mobile 4 Series Chipset neglects to set RWBF capability,
3658          * but needs it:
3659          */
3660         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3661         rwbf_quirk = 1;
3662 }
3663
3664 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);