intel-iommu: Use iommu_should_identity_map() at startup time too.
[linux-2.6.git] / drivers / pci / intel-iommu.c
1 /*
2  * Copyright (c) 2006, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15  * Place - Suite 330, Boston, MA 02111-1307 USA.
16  *
17  * Copyright (C) 2006-2008 Intel Corporation
18  * Author: Ashok Raj <ashok.raj@intel.com>
19  * Author: Shaohua Li <shaohua.li@intel.com>
20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21  * Author: Fenghua Yu <fenghua.yu@intel.com>
22  */
23
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
42 #include "pci.h"
43
44 #define ROOT_SIZE               VTD_PAGE_SIZE
45 #define CONTEXT_SIZE            VTD_PAGE_SIZE
46
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50 #define IOAPIC_RANGE_START      (0xfee00000)
51 #define IOAPIC_RANGE_END        (0xfeefffff)
52 #define IOVA_START_ADDR         (0x1000)
53
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
56 #define MAX_AGAW_WIDTH 64
57
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
59 #define DOMAIN_MAX_PFN(gaw)  ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
60
61 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
62 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
63 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
64
65
66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67    are never going to work. */
68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
69 {
70         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
71 }
72
73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
74 {
75         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
76 }
77 static inline unsigned long page_to_dma_pfn(struct page *pg)
78 {
79         return mm_to_dma_pfn(page_to_pfn(pg));
80 }
81 static inline unsigned long virt_to_dma_pfn(void *p)
82 {
83         return page_to_dma_pfn(virt_to_page(p));
84 }
85
86 /* global iommu list, set NULL for ignored DMAR units */
87 static struct intel_iommu **g_iommus;
88
89 static int rwbf_quirk;
90
91 /*
92  * 0: Present
93  * 1-11: Reserved
94  * 12-63: Context Ptr (12 - (haw-1))
95  * 64-127: Reserved
96  */
97 struct root_entry {
98         u64     val;
99         u64     rsvd1;
100 };
101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102 static inline bool root_present(struct root_entry *root)
103 {
104         return (root->val & 1);
105 }
106 static inline void set_root_present(struct root_entry *root)
107 {
108         root->val |= 1;
109 }
110 static inline void set_root_value(struct root_entry *root, unsigned long value)
111 {
112         root->val |= value & VTD_PAGE_MASK;
113 }
114
115 static inline struct context_entry *
116 get_context_addr_from_root(struct root_entry *root)
117 {
118         return (struct context_entry *)
119                 (root_present(root)?phys_to_virt(
120                 root->val & VTD_PAGE_MASK) :
121                 NULL);
122 }
123
124 /*
125  * low 64 bits:
126  * 0: present
127  * 1: fault processing disable
128  * 2-3: translation type
129  * 12-63: address space root
130  * high 64 bits:
131  * 0-2: address width
132  * 3-6: aval
133  * 8-23: domain id
134  */
135 struct context_entry {
136         u64 lo;
137         u64 hi;
138 };
139
140 static inline bool context_present(struct context_entry *context)
141 {
142         return (context->lo & 1);
143 }
144 static inline void context_set_present(struct context_entry *context)
145 {
146         context->lo |= 1;
147 }
148
149 static inline void context_set_fault_enable(struct context_entry *context)
150 {
151         context->lo &= (((u64)-1) << 2) | 1;
152 }
153
154 static inline void context_set_translation_type(struct context_entry *context,
155                                                 unsigned long value)
156 {
157         context->lo &= (((u64)-1) << 4) | 3;
158         context->lo |= (value & 3) << 2;
159 }
160
161 static inline void context_set_address_root(struct context_entry *context,
162                                             unsigned long value)
163 {
164         context->lo |= value & VTD_PAGE_MASK;
165 }
166
167 static inline void context_set_address_width(struct context_entry *context,
168                                              unsigned long value)
169 {
170         context->hi |= value & 7;
171 }
172
173 static inline void context_set_domain_id(struct context_entry *context,
174                                          unsigned long value)
175 {
176         context->hi |= (value & ((1 << 16) - 1)) << 8;
177 }
178
179 static inline void context_clear_entry(struct context_entry *context)
180 {
181         context->lo = 0;
182         context->hi = 0;
183 }
184
185 /*
186  * 0: readable
187  * 1: writable
188  * 2-6: reserved
189  * 7: super page
190  * 8-10: available
191  * 11: snoop behavior
192  * 12-63: Host physcial address
193  */
194 struct dma_pte {
195         u64 val;
196 };
197
198 static inline void dma_clear_pte(struct dma_pte *pte)
199 {
200         pte->val = 0;
201 }
202
203 static inline void dma_set_pte_readable(struct dma_pte *pte)
204 {
205         pte->val |= DMA_PTE_READ;
206 }
207
208 static inline void dma_set_pte_writable(struct dma_pte *pte)
209 {
210         pte->val |= DMA_PTE_WRITE;
211 }
212
213 static inline void dma_set_pte_snp(struct dma_pte *pte)
214 {
215         pte->val |= DMA_PTE_SNP;
216 }
217
218 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
219 {
220         pte->val = (pte->val & ~3) | (prot & 3);
221 }
222
223 static inline u64 dma_pte_addr(struct dma_pte *pte)
224 {
225 #ifdef CONFIG_64BIT
226         return pte->val & VTD_PAGE_MASK;
227 #else
228         /* Must have a full atomic 64-bit read */
229         return  __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
230 #endif
231 }
232
233 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
234 {
235         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
236 }
237
238 static inline bool dma_pte_present(struct dma_pte *pte)
239 {
240         return (pte->val & 3) != 0;
241 }
242
243 static inline int first_pte_in_page(struct dma_pte *pte)
244 {
245         return !((unsigned long)pte & ~VTD_PAGE_MASK);
246 }
247
248 /*
249  * This domain is a statically identity mapping domain.
250  *      1. This domain creats a static 1:1 mapping to all usable memory.
251  *      2. It maps to each iommu if successful.
252  *      3. Each iommu mapps to this domain if successful.
253  */
254 struct dmar_domain *si_domain;
255
256 /* devices under the same p2p bridge are owned in one domain */
257 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
258
259 /* domain represents a virtual machine, more than one devices
260  * across iommus may be owned in one domain, e.g. kvm guest.
261  */
262 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
263
264 /* si_domain contains mulitple devices */
265 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
266
267 struct dmar_domain {
268         int     id;                     /* domain id */
269         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
270
271         struct list_head devices;       /* all devices' list */
272         struct iova_domain iovad;       /* iova's that belong to this domain */
273
274         struct dma_pte  *pgd;           /* virtual address */
275         int             gaw;            /* max guest address width */
276
277         /* adjusted guest address width, 0 is level 2 30-bit */
278         int             agaw;
279
280         int             flags;          /* flags to find out type of domain */
281
282         int             iommu_coherency;/* indicate coherency of iommu access */
283         int             iommu_snooping; /* indicate snooping control feature*/
284         int             iommu_count;    /* reference count of iommu */
285         spinlock_t      iommu_lock;     /* protect iommu set in domain */
286         u64             max_addr;       /* maximum mapped address */
287 };
288
289 /* PCI domain-device relationship */
290 struct device_domain_info {
291         struct list_head link;  /* link to domain siblings */
292         struct list_head global; /* link to global list */
293         int segment;            /* PCI domain */
294         u8 bus;                 /* PCI bus number */
295         u8 devfn;               /* PCI devfn number */
296         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
297         struct intel_iommu *iommu; /* IOMMU used by this device */
298         struct dmar_domain *domain; /* pointer to domain */
299 };
300
301 static void flush_unmaps_timeout(unsigned long data);
302
303 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
304
305 #define HIGH_WATER_MARK 250
306 struct deferred_flush_tables {
307         int next;
308         struct iova *iova[HIGH_WATER_MARK];
309         struct dmar_domain *domain[HIGH_WATER_MARK];
310 };
311
312 static struct deferred_flush_tables *deferred_flush;
313
314 /* bitmap for indexing intel_iommus */
315 static int g_num_of_iommus;
316
317 static DEFINE_SPINLOCK(async_umap_flush_lock);
318 static LIST_HEAD(unmaps_to_do);
319
320 static int timer_on;
321 static long list_size;
322
323 static void domain_remove_dev_info(struct dmar_domain *domain);
324
325 #ifdef CONFIG_DMAR_DEFAULT_ON
326 int dmar_disabled = 0;
327 #else
328 int dmar_disabled = 1;
329 #endif /*CONFIG_DMAR_DEFAULT_ON*/
330
331 static int __initdata dmar_map_gfx = 1;
332 static int dmar_forcedac;
333 static int intel_iommu_strict;
334
335 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
336 static DEFINE_SPINLOCK(device_domain_lock);
337 static LIST_HEAD(device_domain_list);
338
339 static struct iommu_ops intel_iommu_ops;
340
341 static int __init intel_iommu_setup(char *str)
342 {
343         if (!str)
344                 return -EINVAL;
345         while (*str) {
346                 if (!strncmp(str, "on", 2)) {
347                         dmar_disabled = 0;
348                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
349                 } else if (!strncmp(str, "off", 3)) {
350                         dmar_disabled = 1;
351                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
352                 } else if (!strncmp(str, "igfx_off", 8)) {
353                         dmar_map_gfx = 0;
354                         printk(KERN_INFO
355                                 "Intel-IOMMU: disable GFX device mapping\n");
356                 } else if (!strncmp(str, "forcedac", 8)) {
357                         printk(KERN_INFO
358                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
359                         dmar_forcedac = 1;
360                 } else if (!strncmp(str, "strict", 6)) {
361                         printk(KERN_INFO
362                                 "Intel-IOMMU: disable batched IOTLB flush\n");
363                         intel_iommu_strict = 1;
364                 }
365
366                 str += strcspn(str, ",");
367                 while (*str == ',')
368                         str++;
369         }
370         return 0;
371 }
372 __setup("intel_iommu=", intel_iommu_setup);
373
374 static struct kmem_cache *iommu_domain_cache;
375 static struct kmem_cache *iommu_devinfo_cache;
376 static struct kmem_cache *iommu_iova_cache;
377
378 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
379 {
380         unsigned int flags;
381         void *vaddr;
382
383         /* trying to avoid low memory issues */
384         flags = current->flags & PF_MEMALLOC;
385         current->flags |= PF_MEMALLOC;
386         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
387         current->flags &= (~PF_MEMALLOC | flags);
388         return vaddr;
389 }
390
391
392 static inline void *alloc_pgtable_page(void)
393 {
394         unsigned int flags;
395         void *vaddr;
396
397         /* trying to avoid low memory issues */
398         flags = current->flags & PF_MEMALLOC;
399         current->flags |= PF_MEMALLOC;
400         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
401         current->flags &= (~PF_MEMALLOC | flags);
402         return vaddr;
403 }
404
405 static inline void free_pgtable_page(void *vaddr)
406 {
407         free_page((unsigned long)vaddr);
408 }
409
410 static inline void *alloc_domain_mem(void)
411 {
412         return iommu_kmem_cache_alloc(iommu_domain_cache);
413 }
414
415 static void free_domain_mem(void *vaddr)
416 {
417         kmem_cache_free(iommu_domain_cache, vaddr);
418 }
419
420 static inline void * alloc_devinfo_mem(void)
421 {
422         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
423 }
424
425 static inline void free_devinfo_mem(void *vaddr)
426 {
427         kmem_cache_free(iommu_devinfo_cache, vaddr);
428 }
429
430 struct iova *alloc_iova_mem(void)
431 {
432         return iommu_kmem_cache_alloc(iommu_iova_cache);
433 }
434
435 void free_iova_mem(struct iova *iova)
436 {
437         kmem_cache_free(iommu_iova_cache, iova);
438 }
439
440
441 static inline int width_to_agaw(int width);
442
443 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
444 {
445         unsigned long sagaw;
446         int agaw = -1;
447
448         sagaw = cap_sagaw(iommu->cap);
449         for (agaw = width_to_agaw(max_gaw);
450              agaw >= 0; agaw--) {
451                 if (test_bit(agaw, &sagaw))
452                         break;
453         }
454
455         return agaw;
456 }
457
458 /*
459  * Calculate max SAGAW for each iommu.
460  */
461 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
462 {
463         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
464 }
465
466 /*
467  * calculate agaw for each iommu.
468  * "SAGAW" may be different across iommus, use a default agaw, and
469  * get a supported less agaw for iommus that don't support the default agaw.
470  */
471 int iommu_calculate_agaw(struct intel_iommu *iommu)
472 {
473         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
474 }
475
476 /* This functionin only returns single iommu in a domain */
477 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
478 {
479         int iommu_id;
480
481         /* si_domain and vm domain should not get here. */
482         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
483         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
484
485         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
486         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
487                 return NULL;
488
489         return g_iommus[iommu_id];
490 }
491
492 static void domain_update_iommu_coherency(struct dmar_domain *domain)
493 {
494         int i;
495
496         domain->iommu_coherency = 1;
497
498         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
499         for (; i < g_num_of_iommus; ) {
500                 if (!ecap_coherent(g_iommus[i]->ecap)) {
501                         domain->iommu_coherency = 0;
502                         break;
503                 }
504                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
505         }
506 }
507
508 static void domain_update_iommu_snooping(struct dmar_domain *domain)
509 {
510         int i;
511
512         domain->iommu_snooping = 1;
513
514         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
515         for (; i < g_num_of_iommus; ) {
516                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
517                         domain->iommu_snooping = 0;
518                         break;
519                 }
520                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
521         }
522 }
523
524 /* Some capabilities may be different across iommus */
525 static void domain_update_iommu_cap(struct dmar_domain *domain)
526 {
527         domain_update_iommu_coherency(domain);
528         domain_update_iommu_snooping(domain);
529 }
530
531 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
532 {
533         struct dmar_drhd_unit *drhd = NULL;
534         int i;
535
536         for_each_drhd_unit(drhd) {
537                 if (drhd->ignored)
538                         continue;
539                 if (segment != drhd->segment)
540                         continue;
541
542                 for (i = 0; i < drhd->devices_cnt; i++) {
543                         if (drhd->devices[i] &&
544                             drhd->devices[i]->bus->number == bus &&
545                             drhd->devices[i]->devfn == devfn)
546                                 return drhd->iommu;
547                         if (drhd->devices[i] &&
548                             drhd->devices[i]->subordinate &&
549                             drhd->devices[i]->subordinate->number <= bus &&
550                             drhd->devices[i]->subordinate->subordinate >= bus)
551                                 return drhd->iommu;
552                 }
553
554                 if (drhd->include_all)
555                         return drhd->iommu;
556         }
557
558         return NULL;
559 }
560
561 static void domain_flush_cache(struct dmar_domain *domain,
562                                void *addr, int size)
563 {
564         if (!domain->iommu_coherency)
565                 clflush_cache_range(addr, size);
566 }
567
568 /* Gets context entry for a given bus and devfn */
569 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
570                 u8 bus, u8 devfn)
571 {
572         struct root_entry *root;
573         struct context_entry *context;
574         unsigned long phy_addr;
575         unsigned long flags;
576
577         spin_lock_irqsave(&iommu->lock, flags);
578         root = &iommu->root_entry[bus];
579         context = get_context_addr_from_root(root);
580         if (!context) {
581                 context = (struct context_entry *)alloc_pgtable_page();
582                 if (!context) {
583                         spin_unlock_irqrestore(&iommu->lock, flags);
584                         return NULL;
585                 }
586                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
587                 phy_addr = virt_to_phys((void *)context);
588                 set_root_value(root, phy_addr);
589                 set_root_present(root);
590                 __iommu_flush_cache(iommu, root, sizeof(*root));
591         }
592         spin_unlock_irqrestore(&iommu->lock, flags);
593         return &context[devfn];
594 }
595
596 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
597 {
598         struct root_entry *root;
599         struct context_entry *context;
600         int ret;
601         unsigned long flags;
602
603         spin_lock_irqsave(&iommu->lock, flags);
604         root = &iommu->root_entry[bus];
605         context = get_context_addr_from_root(root);
606         if (!context) {
607                 ret = 0;
608                 goto out;
609         }
610         ret = context_present(&context[devfn]);
611 out:
612         spin_unlock_irqrestore(&iommu->lock, flags);
613         return ret;
614 }
615
616 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
617 {
618         struct root_entry *root;
619         struct context_entry *context;
620         unsigned long flags;
621
622         spin_lock_irqsave(&iommu->lock, flags);
623         root = &iommu->root_entry[bus];
624         context = get_context_addr_from_root(root);
625         if (context) {
626                 context_clear_entry(&context[devfn]);
627                 __iommu_flush_cache(iommu, &context[devfn], \
628                         sizeof(*context));
629         }
630         spin_unlock_irqrestore(&iommu->lock, flags);
631 }
632
633 static void free_context_table(struct intel_iommu *iommu)
634 {
635         struct root_entry *root;
636         int i;
637         unsigned long flags;
638         struct context_entry *context;
639
640         spin_lock_irqsave(&iommu->lock, flags);
641         if (!iommu->root_entry) {
642                 goto out;
643         }
644         for (i = 0; i < ROOT_ENTRY_NR; i++) {
645                 root = &iommu->root_entry[i];
646                 context = get_context_addr_from_root(root);
647                 if (context)
648                         free_pgtable_page(context);
649         }
650         free_pgtable_page(iommu->root_entry);
651         iommu->root_entry = NULL;
652 out:
653         spin_unlock_irqrestore(&iommu->lock, flags);
654 }
655
656 /* page table handling */
657 #define LEVEL_STRIDE            (9)
658 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
659
660 static inline int agaw_to_level(int agaw)
661 {
662         return agaw + 2;
663 }
664
665 static inline int agaw_to_width(int agaw)
666 {
667         return 30 + agaw * LEVEL_STRIDE;
668
669 }
670
671 static inline int width_to_agaw(int width)
672 {
673         return (width - 30) / LEVEL_STRIDE;
674 }
675
676 static inline unsigned int level_to_offset_bits(int level)
677 {
678         return (level - 1) * LEVEL_STRIDE;
679 }
680
681 static inline int pfn_level_offset(unsigned long pfn, int level)
682 {
683         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
684 }
685
686 static inline unsigned long level_mask(int level)
687 {
688         return -1UL << level_to_offset_bits(level);
689 }
690
691 static inline unsigned long level_size(int level)
692 {
693         return 1UL << level_to_offset_bits(level);
694 }
695
696 static inline unsigned long align_to_level(unsigned long pfn, int level)
697 {
698         return (pfn + level_size(level) - 1) & level_mask(level);
699 }
700
701 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
702                                       unsigned long pfn)
703 {
704         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
705         struct dma_pte *parent, *pte = NULL;
706         int level = agaw_to_level(domain->agaw);
707         int offset;
708
709         BUG_ON(!domain->pgd);
710         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
711         parent = domain->pgd;
712
713         while (level > 0) {
714                 void *tmp_page;
715
716                 offset = pfn_level_offset(pfn, level);
717                 pte = &parent[offset];
718                 if (level == 1)
719                         break;
720
721                 if (!dma_pte_present(pte)) {
722                         uint64_t pteval;
723
724                         tmp_page = alloc_pgtable_page();
725
726                         if (!tmp_page)
727                                 return NULL;
728
729                         domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
730                         pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
731                         if (cmpxchg64(&pte->val, 0ULL, pteval)) {
732                                 /* Someone else set it while we were thinking; use theirs. */
733                                 free_pgtable_page(tmp_page);
734                         } else {
735                                 dma_pte_addr(pte);
736                                 domain_flush_cache(domain, pte, sizeof(*pte));
737                         }
738                 }
739                 parent = phys_to_virt(dma_pte_addr(pte));
740                 level--;
741         }
742
743         return pte;
744 }
745
746 /* return address's pte at specific level */
747 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
748                                          unsigned long pfn,
749                                          int level)
750 {
751         struct dma_pte *parent, *pte = NULL;
752         int total = agaw_to_level(domain->agaw);
753         int offset;
754
755         parent = domain->pgd;
756         while (level <= total) {
757                 offset = pfn_level_offset(pfn, total);
758                 pte = &parent[offset];
759                 if (level == total)
760                         return pte;
761
762                 if (!dma_pte_present(pte))
763                         break;
764                 parent = phys_to_virt(dma_pte_addr(pte));
765                 total--;
766         }
767         return NULL;
768 }
769
770 /* clear last level pte, a tlb flush should be followed */
771 static void dma_pte_clear_range(struct dmar_domain *domain,
772                                 unsigned long start_pfn,
773                                 unsigned long last_pfn)
774 {
775         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
776         struct dma_pte *first_pte, *pte;
777
778         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
779         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
780
781         /* we don't need lock here; nobody else touches the iova range */
782         while (start_pfn <= last_pfn) {
783                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
784                 if (!pte) {
785                         start_pfn = align_to_level(start_pfn + 1, 2);
786                         continue;
787                 }
788                 do { 
789                         dma_clear_pte(pte);
790                         start_pfn++;
791                         pte++;
792                 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
793
794                 domain_flush_cache(domain, first_pte,
795                                    (void *)pte - (void *)first_pte);
796         }
797 }
798
799 /* free page table pages. last level pte should already be cleared */
800 static void dma_pte_free_pagetable(struct dmar_domain *domain,
801                                    unsigned long start_pfn,
802                                    unsigned long last_pfn)
803 {
804         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
805         struct dma_pte *first_pte, *pte;
806         int total = agaw_to_level(domain->agaw);
807         int level;
808         unsigned long tmp;
809
810         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
811         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
812
813         /* We don't need lock here; nobody else touches the iova range */
814         level = 2;
815         while (level <= total) {
816                 tmp = align_to_level(start_pfn, level);
817
818                 /* If we can't even clear one PTE at this level, we're done */
819                 if (tmp + level_size(level) - 1 > last_pfn)
820                         return;
821
822                 while (tmp + level_size(level) - 1 <= last_pfn) {
823                         first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
824                         if (!pte) {
825                                 tmp = align_to_level(tmp + 1, level + 1);
826                                 continue;
827                         }
828                         do {
829                                 if (dma_pte_present(pte)) {
830                                         free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
831                                         dma_clear_pte(pte);
832                                 }
833                                 pte++;
834                                 tmp += level_size(level);
835                         } while (!first_pte_in_page(pte) &&
836                                  tmp + level_size(level) - 1 <= last_pfn);
837
838                         domain_flush_cache(domain, first_pte,
839                                            (void *)pte - (void *)first_pte);
840                         
841                 }
842                 level++;
843         }
844         /* free pgd */
845         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
846                 free_pgtable_page(domain->pgd);
847                 domain->pgd = NULL;
848         }
849 }
850
851 /* iommu handling */
852 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
853 {
854         struct root_entry *root;
855         unsigned long flags;
856
857         root = (struct root_entry *)alloc_pgtable_page();
858         if (!root)
859                 return -ENOMEM;
860
861         __iommu_flush_cache(iommu, root, ROOT_SIZE);
862
863         spin_lock_irqsave(&iommu->lock, flags);
864         iommu->root_entry = root;
865         spin_unlock_irqrestore(&iommu->lock, flags);
866
867         return 0;
868 }
869
870 static void iommu_set_root_entry(struct intel_iommu *iommu)
871 {
872         void *addr;
873         u32 sts;
874         unsigned long flag;
875
876         addr = iommu->root_entry;
877
878         spin_lock_irqsave(&iommu->register_lock, flag);
879         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
880
881         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
882
883         /* Make sure hardware complete it */
884         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
885                       readl, (sts & DMA_GSTS_RTPS), sts);
886
887         spin_unlock_irqrestore(&iommu->register_lock, flag);
888 }
889
890 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
891 {
892         u32 val;
893         unsigned long flag;
894
895         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
896                 return;
897
898         spin_lock_irqsave(&iommu->register_lock, flag);
899         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
900
901         /* Make sure hardware complete it */
902         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
903                       readl, (!(val & DMA_GSTS_WBFS)), val);
904
905         spin_unlock_irqrestore(&iommu->register_lock, flag);
906 }
907
908 /* return value determine if we need a write buffer flush */
909 static void __iommu_flush_context(struct intel_iommu *iommu,
910                                   u16 did, u16 source_id, u8 function_mask,
911                                   u64 type)
912 {
913         u64 val = 0;
914         unsigned long flag;
915
916         switch (type) {
917         case DMA_CCMD_GLOBAL_INVL:
918                 val = DMA_CCMD_GLOBAL_INVL;
919                 break;
920         case DMA_CCMD_DOMAIN_INVL:
921                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
922                 break;
923         case DMA_CCMD_DEVICE_INVL:
924                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
925                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
926                 break;
927         default:
928                 BUG();
929         }
930         val |= DMA_CCMD_ICC;
931
932         spin_lock_irqsave(&iommu->register_lock, flag);
933         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
934
935         /* Make sure hardware complete it */
936         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
937                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
938
939         spin_unlock_irqrestore(&iommu->register_lock, flag);
940 }
941
942 /* return value determine if we need a write buffer flush */
943 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
944                                 u64 addr, unsigned int size_order, u64 type)
945 {
946         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
947         u64 val = 0, val_iva = 0;
948         unsigned long flag;
949
950         switch (type) {
951         case DMA_TLB_GLOBAL_FLUSH:
952                 /* global flush doesn't need set IVA_REG */
953                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
954                 break;
955         case DMA_TLB_DSI_FLUSH:
956                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
957                 break;
958         case DMA_TLB_PSI_FLUSH:
959                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
960                 /* Note: always flush non-leaf currently */
961                 val_iva = size_order | addr;
962                 break;
963         default:
964                 BUG();
965         }
966         /* Note: set drain read/write */
967 #if 0
968         /*
969          * This is probably to be super secure.. Looks like we can
970          * ignore it without any impact.
971          */
972         if (cap_read_drain(iommu->cap))
973                 val |= DMA_TLB_READ_DRAIN;
974 #endif
975         if (cap_write_drain(iommu->cap))
976                 val |= DMA_TLB_WRITE_DRAIN;
977
978         spin_lock_irqsave(&iommu->register_lock, flag);
979         /* Note: Only uses first TLB reg currently */
980         if (val_iva)
981                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
982         dmar_writeq(iommu->reg + tlb_offset + 8, val);
983
984         /* Make sure hardware complete it */
985         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
986                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
987
988         spin_unlock_irqrestore(&iommu->register_lock, flag);
989
990         /* check IOTLB invalidation granularity */
991         if (DMA_TLB_IAIG(val) == 0)
992                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
993         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
994                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
995                         (unsigned long long)DMA_TLB_IIRG(type),
996                         (unsigned long long)DMA_TLB_IAIG(val));
997 }
998
999 static struct device_domain_info *iommu_support_dev_iotlb(
1000         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1001 {
1002         int found = 0;
1003         unsigned long flags;
1004         struct device_domain_info *info;
1005         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1006
1007         if (!ecap_dev_iotlb_support(iommu->ecap))
1008                 return NULL;
1009
1010         if (!iommu->qi)
1011                 return NULL;
1012
1013         spin_lock_irqsave(&device_domain_lock, flags);
1014         list_for_each_entry(info, &domain->devices, link)
1015                 if (info->bus == bus && info->devfn == devfn) {
1016                         found = 1;
1017                         break;
1018                 }
1019         spin_unlock_irqrestore(&device_domain_lock, flags);
1020
1021         if (!found || !info->dev)
1022                 return NULL;
1023
1024         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1025                 return NULL;
1026
1027         if (!dmar_find_matched_atsr_unit(info->dev))
1028                 return NULL;
1029
1030         info->iommu = iommu;
1031
1032         return info;
1033 }
1034
1035 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1036 {
1037         if (!info)
1038                 return;
1039
1040         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1041 }
1042
1043 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1044 {
1045         if (!info->dev || !pci_ats_enabled(info->dev))
1046                 return;
1047
1048         pci_disable_ats(info->dev);
1049 }
1050
1051 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1052                                   u64 addr, unsigned mask)
1053 {
1054         u16 sid, qdep;
1055         unsigned long flags;
1056         struct device_domain_info *info;
1057
1058         spin_lock_irqsave(&device_domain_lock, flags);
1059         list_for_each_entry(info, &domain->devices, link) {
1060                 if (!info->dev || !pci_ats_enabled(info->dev))
1061                         continue;
1062
1063                 sid = info->bus << 8 | info->devfn;
1064                 qdep = pci_ats_queue_depth(info->dev);
1065                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1066         }
1067         spin_unlock_irqrestore(&device_domain_lock, flags);
1068 }
1069
1070 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1071                                   unsigned long pfn, unsigned int pages)
1072 {
1073         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1074         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1075
1076         BUG_ON(pages == 0);
1077
1078         /*
1079          * Fallback to domain selective flush if no PSI support or the size is
1080          * too big.
1081          * PSI requires page size to be 2 ^ x, and the base address is naturally
1082          * aligned to the size
1083          */
1084         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1085                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1086                                                 DMA_TLB_DSI_FLUSH);
1087         else
1088                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1089                                                 DMA_TLB_PSI_FLUSH);
1090
1091         /*
1092          * In caching mode, domain ID 0 is reserved for non-present to present
1093          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1094          */
1095         if (!cap_caching_mode(iommu->cap) || did)
1096                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1097 }
1098
1099 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1100 {
1101         u32 pmen;
1102         unsigned long flags;
1103
1104         spin_lock_irqsave(&iommu->register_lock, flags);
1105         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1106         pmen &= ~DMA_PMEN_EPM;
1107         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1108
1109         /* wait for the protected region status bit to clear */
1110         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1111                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1112
1113         spin_unlock_irqrestore(&iommu->register_lock, flags);
1114 }
1115
1116 static int iommu_enable_translation(struct intel_iommu *iommu)
1117 {
1118         u32 sts;
1119         unsigned long flags;
1120
1121         spin_lock_irqsave(&iommu->register_lock, flags);
1122         iommu->gcmd |= DMA_GCMD_TE;
1123         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1124
1125         /* Make sure hardware complete it */
1126         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1127                       readl, (sts & DMA_GSTS_TES), sts);
1128
1129         spin_unlock_irqrestore(&iommu->register_lock, flags);
1130         return 0;
1131 }
1132
1133 static int iommu_disable_translation(struct intel_iommu *iommu)
1134 {
1135         u32 sts;
1136         unsigned long flag;
1137
1138         spin_lock_irqsave(&iommu->register_lock, flag);
1139         iommu->gcmd &= ~DMA_GCMD_TE;
1140         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1141
1142         /* Make sure hardware complete it */
1143         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1144                       readl, (!(sts & DMA_GSTS_TES)), sts);
1145
1146         spin_unlock_irqrestore(&iommu->register_lock, flag);
1147         return 0;
1148 }
1149
1150
1151 static int iommu_init_domains(struct intel_iommu *iommu)
1152 {
1153         unsigned long ndomains;
1154         unsigned long nlongs;
1155
1156         ndomains = cap_ndoms(iommu->cap);
1157         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1158         nlongs = BITS_TO_LONGS(ndomains);
1159
1160         /* TBD: there might be 64K domains,
1161          * consider other allocation for future chip
1162          */
1163         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1164         if (!iommu->domain_ids) {
1165                 printk(KERN_ERR "Allocating domain id array failed\n");
1166                 return -ENOMEM;
1167         }
1168         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1169                         GFP_KERNEL);
1170         if (!iommu->domains) {
1171                 printk(KERN_ERR "Allocating domain array failed\n");
1172                 kfree(iommu->domain_ids);
1173                 return -ENOMEM;
1174         }
1175
1176         spin_lock_init(&iommu->lock);
1177
1178         /*
1179          * if Caching mode is set, then invalid translations are tagged
1180          * with domainid 0. Hence we need to pre-allocate it.
1181          */
1182         if (cap_caching_mode(iommu->cap))
1183                 set_bit(0, iommu->domain_ids);
1184         return 0;
1185 }
1186
1187
1188 static void domain_exit(struct dmar_domain *domain);
1189 static void vm_domain_exit(struct dmar_domain *domain);
1190
1191 void free_dmar_iommu(struct intel_iommu *iommu)
1192 {
1193         struct dmar_domain *domain;
1194         int i;
1195         unsigned long flags;
1196
1197         i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1198         for (; i < cap_ndoms(iommu->cap); ) {
1199                 domain = iommu->domains[i];
1200                 clear_bit(i, iommu->domain_ids);
1201
1202                 spin_lock_irqsave(&domain->iommu_lock, flags);
1203                 if (--domain->iommu_count == 0) {
1204                         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1205                                 vm_domain_exit(domain);
1206                         else
1207                                 domain_exit(domain);
1208                 }
1209                 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1210
1211                 i = find_next_bit(iommu->domain_ids,
1212                         cap_ndoms(iommu->cap), i+1);
1213         }
1214
1215         if (iommu->gcmd & DMA_GCMD_TE)
1216                 iommu_disable_translation(iommu);
1217
1218         if (iommu->irq) {
1219                 set_irq_data(iommu->irq, NULL);
1220                 /* This will mask the irq */
1221                 free_irq(iommu->irq, iommu);
1222                 destroy_irq(iommu->irq);
1223         }
1224
1225         kfree(iommu->domains);
1226         kfree(iommu->domain_ids);
1227
1228         g_iommus[iommu->seq_id] = NULL;
1229
1230         /* if all iommus are freed, free g_iommus */
1231         for (i = 0; i < g_num_of_iommus; i++) {
1232                 if (g_iommus[i])
1233                         break;
1234         }
1235
1236         if (i == g_num_of_iommus)
1237                 kfree(g_iommus);
1238
1239         /* free context mapping */
1240         free_context_table(iommu);
1241 }
1242
1243 static struct dmar_domain *alloc_domain(void)
1244 {
1245         struct dmar_domain *domain;
1246
1247         domain = alloc_domain_mem();
1248         if (!domain)
1249                 return NULL;
1250
1251         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1252         domain->flags = 0;
1253
1254         return domain;
1255 }
1256
1257 static int iommu_attach_domain(struct dmar_domain *domain,
1258                                struct intel_iommu *iommu)
1259 {
1260         int num;
1261         unsigned long ndomains;
1262         unsigned long flags;
1263
1264         ndomains = cap_ndoms(iommu->cap);
1265
1266         spin_lock_irqsave(&iommu->lock, flags);
1267
1268         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1269         if (num >= ndomains) {
1270                 spin_unlock_irqrestore(&iommu->lock, flags);
1271                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1272                 return -ENOMEM;
1273         }
1274
1275         domain->id = num;
1276         set_bit(num, iommu->domain_ids);
1277         set_bit(iommu->seq_id, &domain->iommu_bmp);
1278         iommu->domains[num] = domain;
1279         spin_unlock_irqrestore(&iommu->lock, flags);
1280
1281         return 0;
1282 }
1283
1284 static void iommu_detach_domain(struct dmar_domain *domain,
1285                                 struct intel_iommu *iommu)
1286 {
1287         unsigned long flags;
1288         int num, ndomains;
1289         int found = 0;
1290
1291         spin_lock_irqsave(&iommu->lock, flags);
1292         ndomains = cap_ndoms(iommu->cap);
1293         num = find_first_bit(iommu->domain_ids, ndomains);
1294         for (; num < ndomains; ) {
1295                 if (iommu->domains[num] == domain) {
1296                         found = 1;
1297                         break;
1298                 }
1299                 num = find_next_bit(iommu->domain_ids,
1300                                     cap_ndoms(iommu->cap), num+1);
1301         }
1302
1303         if (found) {
1304                 clear_bit(num, iommu->domain_ids);
1305                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1306                 iommu->domains[num] = NULL;
1307         }
1308         spin_unlock_irqrestore(&iommu->lock, flags);
1309 }
1310
1311 static struct iova_domain reserved_iova_list;
1312 static struct lock_class_key reserved_alloc_key;
1313 static struct lock_class_key reserved_rbtree_key;
1314
1315 static void dmar_init_reserved_ranges(void)
1316 {
1317         struct pci_dev *pdev = NULL;
1318         struct iova *iova;
1319         int i;
1320
1321         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1322
1323         lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1324                 &reserved_alloc_key);
1325         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1326                 &reserved_rbtree_key);
1327
1328         /* IOAPIC ranges shouldn't be accessed by DMA */
1329         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1330                 IOVA_PFN(IOAPIC_RANGE_END));
1331         if (!iova)
1332                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1333
1334         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1335         for_each_pci_dev(pdev) {
1336                 struct resource *r;
1337
1338                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1339                         r = &pdev->resource[i];
1340                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1341                                 continue;
1342                         iova = reserve_iova(&reserved_iova_list,
1343                                             IOVA_PFN(r->start),
1344                                             IOVA_PFN(r->end));
1345                         if (!iova)
1346                                 printk(KERN_ERR "Reserve iova failed\n");
1347                 }
1348         }
1349
1350 }
1351
1352 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1353 {
1354         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1355 }
1356
1357 static inline int guestwidth_to_adjustwidth(int gaw)
1358 {
1359         int agaw;
1360         int r = (gaw - 12) % 9;
1361
1362         if (r == 0)
1363                 agaw = gaw;
1364         else
1365                 agaw = gaw + 9 - r;
1366         if (agaw > 64)
1367                 agaw = 64;
1368         return agaw;
1369 }
1370
1371 static int domain_init(struct dmar_domain *domain, int guest_width)
1372 {
1373         struct intel_iommu *iommu;
1374         int adjust_width, agaw;
1375         unsigned long sagaw;
1376
1377         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1378         spin_lock_init(&domain->iommu_lock);
1379
1380         domain_reserve_special_ranges(domain);
1381
1382         /* calculate AGAW */
1383         iommu = domain_get_iommu(domain);
1384         if (guest_width > cap_mgaw(iommu->cap))
1385                 guest_width = cap_mgaw(iommu->cap);
1386         domain->gaw = guest_width;
1387         adjust_width = guestwidth_to_adjustwidth(guest_width);
1388         agaw = width_to_agaw(adjust_width);
1389         sagaw = cap_sagaw(iommu->cap);
1390         if (!test_bit(agaw, &sagaw)) {
1391                 /* hardware doesn't support it, choose a bigger one */
1392                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1393                 agaw = find_next_bit(&sagaw, 5, agaw);
1394                 if (agaw >= 5)
1395                         return -ENODEV;
1396         }
1397         domain->agaw = agaw;
1398         INIT_LIST_HEAD(&domain->devices);
1399
1400         if (ecap_coherent(iommu->ecap))
1401                 domain->iommu_coherency = 1;
1402         else
1403                 domain->iommu_coherency = 0;
1404
1405         if (ecap_sc_support(iommu->ecap))
1406                 domain->iommu_snooping = 1;
1407         else
1408                 domain->iommu_snooping = 0;
1409
1410         domain->iommu_count = 1;
1411
1412         /* always allocate the top pgd */
1413         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1414         if (!domain->pgd)
1415                 return -ENOMEM;
1416         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1417         return 0;
1418 }
1419
1420 static void domain_exit(struct dmar_domain *domain)
1421 {
1422         struct dmar_drhd_unit *drhd;
1423         struct intel_iommu *iommu;
1424
1425         /* Domain 0 is reserved, so dont process it */
1426         if (!domain)
1427                 return;
1428
1429         domain_remove_dev_info(domain);
1430         /* destroy iovas */
1431         put_iova_domain(&domain->iovad);
1432
1433         /* clear ptes */
1434         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1435
1436         /* free page tables */
1437         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1438
1439         for_each_active_iommu(iommu, drhd)
1440                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1441                         iommu_detach_domain(domain, iommu);
1442
1443         free_domain_mem(domain);
1444 }
1445
1446 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1447                                  u8 bus, u8 devfn, int translation)
1448 {
1449         struct context_entry *context;
1450         unsigned long flags;
1451         struct intel_iommu *iommu;
1452         struct dma_pte *pgd;
1453         unsigned long num;
1454         unsigned long ndomains;
1455         int id;
1456         int agaw;
1457         struct device_domain_info *info = NULL;
1458
1459         pr_debug("Set context mapping for %02x:%02x.%d\n",
1460                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1461
1462         BUG_ON(!domain->pgd);
1463         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1464                translation != CONTEXT_TT_MULTI_LEVEL);
1465
1466         iommu = device_to_iommu(segment, bus, devfn);
1467         if (!iommu)
1468                 return -ENODEV;
1469
1470         context = device_to_context_entry(iommu, bus, devfn);
1471         if (!context)
1472                 return -ENOMEM;
1473         spin_lock_irqsave(&iommu->lock, flags);
1474         if (context_present(context)) {
1475                 spin_unlock_irqrestore(&iommu->lock, flags);
1476                 return 0;
1477         }
1478
1479         id = domain->id;
1480         pgd = domain->pgd;
1481
1482         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1483             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1484                 int found = 0;
1485
1486                 /* find an available domain id for this device in iommu */
1487                 ndomains = cap_ndoms(iommu->cap);
1488                 num = find_first_bit(iommu->domain_ids, ndomains);
1489                 for (; num < ndomains; ) {
1490                         if (iommu->domains[num] == domain) {
1491                                 id = num;
1492                                 found = 1;
1493                                 break;
1494                         }
1495                         num = find_next_bit(iommu->domain_ids,
1496                                             cap_ndoms(iommu->cap), num+1);
1497                 }
1498
1499                 if (found == 0) {
1500                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1501                         if (num >= ndomains) {
1502                                 spin_unlock_irqrestore(&iommu->lock, flags);
1503                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1504                                 return -EFAULT;
1505                         }
1506
1507                         set_bit(num, iommu->domain_ids);
1508                         set_bit(iommu->seq_id, &domain->iommu_bmp);
1509                         iommu->domains[num] = domain;
1510                         id = num;
1511                 }
1512
1513                 /* Skip top levels of page tables for
1514                  * iommu which has less agaw than default.
1515                  */
1516                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1517                         pgd = phys_to_virt(dma_pte_addr(pgd));
1518                         if (!dma_pte_present(pgd)) {
1519                                 spin_unlock_irqrestore(&iommu->lock, flags);
1520                                 return -ENOMEM;
1521                         }
1522                 }
1523         }
1524
1525         context_set_domain_id(context, id);
1526
1527         if (translation != CONTEXT_TT_PASS_THROUGH) {
1528                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1529                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1530                                      CONTEXT_TT_MULTI_LEVEL;
1531         }
1532         /*
1533          * In pass through mode, AW must be programmed to indicate the largest
1534          * AGAW value supported by hardware. And ASR is ignored by hardware.
1535          */
1536         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1537                 context_set_address_width(context, iommu->msagaw);
1538         else {
1539                 context_set_address_root(context, virt_to_phys(pgd));
1540                 context_set_address_width(context, iommu->agaw);
1541         }
1542
1543         context_set_translation_type(context, translation);
1544         context_set_fault_enable(context);
1545         context_set_present(context);
1546         domain_flush_cache(domain, context, sizeof(*context));
1547
1548         /*
1549          * It's a non-present to present mapping. If hardware doesn't cache
1550          * non-present entry we only need to flush the write-buffer. If the
1551          * _does_ cache non-present entries, then it does so in the special
1552          * domain #0, which we have to flush:
1553          */
1554         if (cap_caching_mode(iommu->cap)) {
1555                 iommu->flush.flush_context(iommu, 0,
1556                                            (((u16)bus) << 8) | devfn,
1557                                            DMA_CCMD_MASK_NOBIT,
1558                                            DMA_CCMD_DEVICE_INVL);
1559                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1560         } else {
1561                 iommu_flush_write_buffer(iommu);
1562         }
1563         iommu_enable_dev_iotlb(info);
1564         spin_unlock_irqrestore(&iommu->lock, flags);
1565
1566         spin_lock_irqsave(&domain->iommu_lock, flags);
1567         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1568                 domain->iommu_count++;
1569                 domain_update_iommu_cap(domain);
1570         }
1571         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1572         return 0;
1573 }
1574
1575 static int
1576 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1577                         int translation)
1578 {
1579         int ret;
1580         struct pci_dev *tmp, *parent;
1581
1582         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1583                                          pdev->bus->number, pdev->devfn,
1584                                          translation);
1585         if (ret)
1586                 return ret;
1587
1588         /* dependent device mapping */
1589         tmp = pci_find_upstream_pcie_bridge(pdev);
1590         if (!tmp)
1591                 return 0;
1592         /* Secondary interface's bus number and devfn 0 */
1593         parent = pdev->bus->self;
1594         while (parent != tmp) {
1595                 ret = domain_context_mapping_one(domain,
1596                                                  pci_domain_nr(parent->bus),
1597                                                  parent->bus->number,
1598                                                  parent->devfn, translation);
1599                 if (ret)
1600                         return ret;
1601                 parent = parent->bus->self;
1602         }
1603         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1604                 return domain_context_mapping_one(domain,
1605                                         pci_domain_nr(tmp->subordinate),
1606                                         tmp->subordinate->number, 0,
1607                                         translation);
1608         else /* this is a legacy PCI bridge */
1609                 return domain_context_mapping_one(domain,
1610                                                   pci_domain_nr(tmp->bus),
1611                                                   tmp->bus->number,
1612                                                   tmp->devfn,
1613                                                   translation);
1614 }
1615
1616 static int domain_context_mapped(struct pci_dev *pdev)
1617 {
1618         int ret;
1619         struct pci_dev *tmp, *parent;
1620         struct intel_iommu *iommu;
1621
1622         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1623                                 pdev->devfn);
1624         if (!iommu)
1625                 return -ENODEV;
1626
1627         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1628         if (!ret)
1629                 return ret;
1630         /* dependent device mapping */
1631         tmp = pci_find_upstream_pcie_bridge(pdev);
1632         if (!tmp)
1633                 return ret;
1634         /* Secondary interface's bus number and devfn 0 */
1635         parent = pdev->bus->self;
1636         while (parent != tmp) {
1637                 ret = device_context_mapped(iommu, parent->bus->number,
1638                                             parent->devfn);
1639                 if (!ret)
1640                         return ret;
1641                 parent = parent->bus->self;
1642         }
1643         if (tmp->is_pcie)
1644                 return device_context_mapped(iommu, tmp->subordinate->number,
1645                                              0);
1646         else
1647                 return device_context_mapped(iommu, tmp->bus->number,
1648                                              tmp->devfn);
1649 }
1650
1651 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1652                             struct scatterlist *sg, unsigned long phys_pfn,
1653                             unsigned long nr_pages, int prot)
1654 {
1655         struct dma_pte *first_pte = NULL, *pte = NULL;
1656         phys_addr_t uninitialized_var(pteval);
1657         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1658         unsigned long sg_res;
1659
1660         BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1661
1662         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1663                 return -EINVAL;
1664
1665         prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1666
1667         if (sg)
1668                 sg_res = 0;
1669         else {
1670                 sg_res = nr_pages + 1;
1671                 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1672         }
1673
1674         while (nr_pages--) {
1675                 uint64_t tmp;
1676
1677                 if (!sg_res) {
1678                         sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT;
1679                         sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1680                         sg->dma_length = sg->length;
1681                         pteval = page_to_phys(sg_page(sg)) | prot;
1682                 }
1683                 if (!pte) {
1684                         first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1685                         if (!pte)
1686                                 return -ENOMEM;
1687                 }
1688                 /* We don't need lock here, nobody else
1689                  * touches the iova range
1690                  */
1691                 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1692                 if (tmp) {
1693                         static int dumps = 5;
1694                         printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1695                                iov_pfn, tmp, (unsigned long long)pteval);
1696                         if (dumps) {
1697                                 dumps--;
1698                                 debug_dma_dump_mappings(NULL);
1699                         }
1700                         WARN_ON(1);
1701                 }
1702                 pte++;
1703                 if (!nr_pages || first_pte_in_page(pte)) {
1704                         domain_flush_cache(domain, first_pte,
1705                                            (void *)pte - (void *)first_pte);
1706                         pte = NULL;
1707                 }
1708                 iov_pfn++;
1709                 pteval += VTD_PAGE_SIZE;
1710                 sg_res--;
1711                 if (!sg_res)
1712                         sg = sg_next(sg);
1713         }
1714         return 0;
1715 }
1716
1717 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1718                                     struct scatterlist *sg, unsigned long nr_pages,
1719                                     int prot)
1720 {
1721         return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1722 }
1723
1724 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1725                                      unsigned long phys_pfn, unsigned long nr_pages,
1726                                      int prot)
1727 {
1728         return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1729 }
1730
1731 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1732 {
1733         if (!iommu)
1734                 return;
1735
1736         clear_context_table(iommu, bus, devfn);
1737         iommu->flush.flush_context(iommu, 0, 0, 0,
1738                                            DMA_CCMD_GLOBAL_INVL);
1739         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1740 }
1741
1742 static void domain_remove_dev_info(struct dmar_domain *domain)
1743 {
1744         struct device_domain_info *info;
1745         unsigned long flags;
1746         struct intel_iommu *iommu;
1747
1748         spin_lock_irqsave(&device_domain_lock, flags);
1749         while (!list_empty(&domain->devices)) {
1750                 info = list_entry(domain->devices.next,
1751                         struct device_domain_info, link);
1752                 list_del(&info->link);
1753                 list_del(&info->global);
1754                 if (info->dev)
1755                         info->dev->dev.archdata.iommu = NULL;
1756                 spin_unlock_irqrestore(&device_domain_lock, flags);
1757
1758                 iommu_disable_dev_iotlb(info);
1759                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1760                 iommu_detach_dev(iommu, info->bus, info->devfn);
1761                 free_devinfo_mem(info);
1762
1763                 spin_lock_irqsave(&device_domain_lock, flags);
1764         }
1765         spin_unlock_irqrestore(&device_domain_lock, flags);
1766 }
1767
1768 /*
1769  * find_domain
1770  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1771  */
1772 static struct dmar_domain *
1773 find_domain(struct pci_dev *pdev)
1774 {
1775         struct device_domain_info *info;
1776
1777         /* No lock here, assumes no domain exit in normal case */
1778         info = pdev->dev.archdata.iommu;
1779         if (info)
1780                 return info->domain;
1781         return NULL;
1782 }
1783
1784 /* domain is initialized */
1785 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1786 {
1787         struct dmar_domain *domain, *found = NULL;
1788         struct intel_iommu *iommu;
1789         struct dmar_drhd_unit *drhd;
1790         struct device_domain_info *info, *tmp;
1791         struct pci_dev *dev_tmp;
1792         unsigned long flags;
1793         int bus = 0, devfn = 0;
1794         int segment;
1795         int ret;
1796
1797         domain = find_domain(pdev);
1798         if (domain)
1799                 return domain;
1800
1801         segment = pci_domain_nr(pdev->bus);
1802
1803         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1804         if (dev_tmp) {
1805                 if (dev_tmp->is_pcie) {
1806                         bus = dev_tmp->subordinate->number;
1807                         devfn = 0;
1808                 } else {
1809                         bus = dev_tmp->bus->number;
1810                         devfn = dev_tmp->devfn;
1811                 }
1812                 spin_lock_irqsave(&device_domain_lock, flags);
1813                 list_for_each_entry(info, &device_domain_list, global) {
1814                         if (info->segment == segment &&
1815                             info->bus == bus && info->devfn == devfn) {
1816                                 found = info->domain;
1817                                 break;
1818                         }
1819                 }
1820                 spin_unlock_irqrestore(&device_domain_lock, flags);
1821                 /* pcie-pci bridge already has a domain, uses it */
1822                 if (found) {
1823                         domain = found;
1824                         goto found_domain;
1825                 }
1826         }
1827
1828         domain = alloc_domain();
1829         if (!domain)
1830                 goto error;
1831
1832         /* Allocate new domain for the device */
1833         drhd = dmar_find_matched_drhd_unit(pdev);
1834         if (!drhd) {
1835                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1836                         pci_name(pdev));
1837                 return NULL;
1838         }
1839         iommu = drhd->iommu;
1840
1841         ret = iommu_attach_domain(domain, iommu);
1842         if (ret) {
1843                 domain_exit(domain);
1844                 goto error;
1845         }
1846
1847         if (domain_init(domain, gaw)) {
1848                 domain_exit(domain);
1849                 goto error;
1850         }
1851
1852         /* register pcie-to-pci device */
1853         if (dev_tmp) {
1854                 info = alloc_devinfo_mem();
1855                 if (!info) {
1856                         domain_exit(domain);
1857                         goto error;
1858                 }
1859                 info->segment = segment;
1860                 info->bus = bus;
1861                 info->devfn = devfn;
1862                 info->dev = NULL;
1863                 info->domain = domain;
1864                 /* This domain is shared by devices under p2p bridge */
1865                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1866
1867                 /* pcie-to-pci bridge already has a domain, uses it */
1868                 found = NULL;
1869                 spin_lock_irqsave(&device_domain_lock, flags);
1870                 list_for_each_entry(tmp, &device_domain_list, global) {
1871                         if (tmp->segment == segment &&
1872                             tmp->bus == bus && tmp->devfn == devfn) {
1873                                 found = tmp->domain;
1874                                 break;
1875                         }
1876                 }
1877                 if (found) {
1878                         free_devinfo_mem(info);
1879                         domain_exit(domain);
1880                         domain = found;
1881                 } else {
1882                         list_add(&info->link, &domain->devices);
1883                         list_add(&info->global, &device_domain_list);
1884                 }
1885                 spin_unlock_irqrestore(&device_domain_lock, flags);
1886         }
1887
1888 found_domain:
1889         info = alloc_devinfo_mem();
1890         if (!info)
1891                 goto error;
1892         info->segment = segment;
1893         info->bus = pdev->bus->number;
1894         info->devfn = pdev->devfn;
1895         info->dev = pdev;
1896         info->domain = domain;
1897         spin_lock_irqsave(&device_domain_lock, flags);
1898         /* somebody is fast */
1899         found = find_domain(pdev);
1900         if (found != NULL) {
1901                 spin_unlock_irqrestore(&device_domain_lock, flags);
1902                 if (found != domain) {
1903                         domain_exit(domain);
1904                         domain = found;
1905                 }
1906                 free_devinfo_mem(info);
1907                 return domain;
1908         }
1909         list_add(&info->link, &domain->devices);
1910         list_add(&info->global, &device_domain_list);
1911         pdev->dev.archdata.iommu = info;
1912         spin_unlock_irqrestore(&device_domain_lock, flags);
1913         return domain;
1914 error:
1915         /* recheck it here, maybe others set it */
1916         return find_domain(pdev);
1917 }
1918
1919 static int iommu_identity_mapping;
1920
1921 static int iommu_domain_identity_map(struct dmar_domain *domain,
1922                                      unsigned long long start,
1923                                      unsigned long long end)
1924 {
1925         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1926         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1927
1928         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1929                           dma_to_mm_pfn(last_vpfn))) {
1930                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1931                 return -ENOMEM;
1932         }
1933
1934         pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1935                  start, end, domain->id);
1936         /*
1937          * RMRR range might have overlap with physical memory range,
1938          * clear it first
1939          */
1940         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1941
1942         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1943                                   last_vpfn - first_vpfn + 1,
1944                                   DMA_PTE_READ|DMA_PTE_WRITE);
1945 }
1946
1947 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1948                                       unsigned long long start,
1949                                       unsigned long long end)
1950 {
1951         struct dmar_domain *domain;
1952         int ret;
1953
1954         printk(KERN_INFO
1955                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1956                pci_name(pdev), start, end);
1957
1958         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1959         if (!domain)
1960                 return -ENOMEM;
1961
1962         ret = iommu_domain_identity_map(domain, start, end);
1963         if (ret)
1964                 goto error;
1965
1966         /* context entry init */
1967         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1968         if (ret)
1969                 goto error;
1970
1971         return 0;
1972
1973  error:
1974         domain_exit(domain);
1975         return ret;
1976 }
1977
1978 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1979         struct pci_dev *pdev)
1980 {
1981         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1982                 return 0;
1983         return iommu_prepare_identity_map(pdev, rmrr->base_address,
1984                 rmrr->end_address + 1);
1985 }
1986
1987 #ifdef CONFIG_DMAR_FLOPPY_WA
1988 static inline void iommu_prepare_isa(void)
1989 {
1990         struct pci_dev *pdev;
1991         int ret;
1992
1993         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1994         if (!pdev)
1995                 return;
1996
1997         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1998         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1999
2000         if (ret)
2001                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2002                        "floppy might not work\n");
2003
2004 }
2005 #else
2006 static inline void iommu_prepare_isa(void)
2007 {
2008         return;
2009 }
2010 #endif /* !CONFIG_DMAR_FLPY_WA */
2011
2012 /* Initialize each context entry as pass through.*/
2013 static int __init init_context_pass_through(void)
2014 {
2015         struct pci_dev *pdev = NULL;
2016         struct dmar_domain *domain;
2017         int ret;
2018
2019         for_each_pci_dev(pdev) {
2020                 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2021                 ret = domain_context_mapping(domain, pdev,
2022                                              CONTEXT_TT_PASS_THROUGH);
2023                 if (ret)
2024                         return ret;
2025         }
2026         return 0;
2027 }
2028
2029 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2030
2031 static int __init si_domain_work_fn(unsigned long start_pfn,
2032                                     unsigned long end_pfn, void *datax)
2033 {
2034         int *ret = datax;
2035
2036         *ret = iommu_domain_identity_map(si_domain,
2037                                          (uint64_t)start_pfn << PAGE_SHIFT,
2038                                          (uint64_t)end_pfn << PAGE_SHIFT);
2039         return *ret;
2040
2041 }
2042
2043 static int si_domain_init(void)
2044 {
2045         struct dmar_drhd_unit *drhd;
2046         struct intel_iommu *iommu;
2047         int nid, ret = 0;
2048
2049         si_domain = alloc_domain();
2050         if (!si_domain)
2051                 return -EFAULT;
2052
2053         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2054
2055         for_each_active_iommu(iommu, drhd) {
2056                 ret = iommu_attach_domain(si_domain, iommu);
2057                 if (ret) {
2058                         domain_exit(si_domain);
2059                         return -EFAULT;
2060                 }
2061         }
2062
2063         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2064                 domain_exit(si_domain);
2065                 return -EFAULT;
2066         }
2067
2068         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2069
2070         for_each_online_node(nid) {
2071                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2072                 if (ret)
2073                         return ret;
2074         }
2075
2076         return 0;
2077 }
2078
2079 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2080                                           struct pci_dev *pdev);
2081 static int identity_mapping(struct pci_dev *pdev)
2082 {
2083         struct device_domain_info *info;
2084
2085         if (likely(!iommu_identity_mapping))
2086                 return 0;
2087
2088
2089         list_for_each_entry(info, &si_domain->devices, link)
2090                 if (info->dev == pdev)
2091                         return 1;
2092         return 0;
2093 }
2094
2095 static int domain_add_dev_info(struct dmar_domain *domain,
2096                                   struct pci_dev *pdev)
2097 {
2098         struct device_domain_info *info;
2099         unsigned long flags;
2100
2101         info = alloc_devinfo_mem();
2102         if (!info)
2103                 return -ENOMEM;
2104
2105         info->segment = pci_domain_nr(pdev->bus);
2106         info->bus = pdev->bus->number;
2107         info->devfn = pdev->devfn;
2108         info->dev = pdev;
2109         info->domain = domain;
2110
2111         spin_lock_irqsave(&device_domain_lock, flags);
2112         list_add(&info->link, &domain->devices);
2113         list_add(&info->global, &device_domain_list);
2114         pdev->dev.archdata.iommu = info;
2115         spin_unlock_irqrestore(&device_domain_lock, flags);
2116
2117         return 0;
2118 }
2119
2120 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2121 {
2122         if (iommu_identity_mapping == 2)
2123                 return IS_GFX_DEVICE(pdev);
2124
2125         if (!startup)
2126                 return pdev->dma_mask > DMA_BIT_MASK(32);
2127
2128         return 1;
2129 }
2130
2131 static int iommu_prepare_static_identity_mapping(void)
2132 {
2133         struct pci_dev *pdev = NULL;
2134         int ret;
2135
2136         ret = si_domain_init();
2137         if (ret)
2138                 return -EFAULT;
2139
2140         for_each_pci_dev(pdev) {
2141                 if (iommu_should_identity_map(pdev, 1)) {
2142                         printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2143                                pci_name(pdev));
2144
2145                         ret = domain_context_mapping(si_domain, pdev,
2146                                                      CONTEXT_TT_MULTI_LEVEL);
2147                         if (ret)
2148                                 return ret;
2149                         ret = domain_add_dev_info(si_domain, pdev);
2150                         if (ret)
2151                                 return ret;
2152                 }
2153         }
2154
2155         return 0;
2156 }
2157
2158 int __init init_dmars(void)
2159 {
2160         struct dmar_drhd_unit *drhd;
2161         struct dmar_rmrr_unit *rmrr;
2162         struct pci_dev *pdev;
2163         struct intel_iommu *iommu;
2164         int i, ret;
2165         int pass_through = 1;
2166
2167         /*
2168          * In case pass through can not be enabled, iommu tries to use identity
2169          * mapping.
2170          */
2171         if (iommu_pass_through)
2172                 iommu_identity_mapping = 1;
2173
2174         /*
2175          * for each drhd
2176          *    allocate root
2177          *    initialize and program root entry to not present
2178          * endfor
2179          */
2180         for_each_drhd_unit(drhd) {
2181                 g_num_of_iommus++;
2182                 /*
2183                  * lock not needed as this is only incremented in the single
2184                  * threaded kernel __init code path all other access are read
2185                  * only
2186                  */
2187         }
2188
2189         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2190                         GFP_KERNEL);
2191         if (!g_iommus) {
2192                 printk(KERN_ERR "Allocating global iommu array failed\n");
2193                 ret = -ENOMEM;
2194                 goto error;
2195         }
2196
2197         deferred_flush = kzalloc(g_num_of_iommus *
2198                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2199         if (!deferred_flush) {
2200                 kfree(g_iommus);
2201                 ret = -ENOMEM;
2202                 goto error;
2203         }
2204
2205         for_each_drhd_unit(drhd) {
2206                 if (drhd->ignored)
2207                         continue;
2208
2209                 iommu = drhd->iommu;
2210                 g_iommus[iommu->seq_id] = iommu;
2211
2212                 ret = iommu_init_domains(iommu);
2213                 if (ret)
2214                         goto error;
2215
2216                 /*
2217                  * TBD:
2218                  * we could share the same root & context tables
2219                  * amoung all IOMMU's. Need to Split it later.
2220                  */
2221                 ret = iommu_alloc_root_entry(iommu);
2222                 if (ret) {
2223                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2224                         goto error;
2225                 }
2226                 if (!ecap_pass_through(iommu->ecap))
2227                         pass_through = 0;
2228         }
2229         if (iommu_pass_through)
2230                 if (!pass_through) {
2231                         printk(KERN_INFO
2232                                "Pass Through is not supported by hardware.\n");
2233                         iommu_pass_through = 0;
2234                 }
2235
2236         /*
2237          * Start from the sane iommu hardware state.
2238          */
2239         for_each_drhd_unit(drhd) {
2240                 if (drhd->ignored)
2241                         continue;
2242
2243                 iommu = drhd->iommu;
2244
2245                 /*
2246                  * If the queued invalidation is already initialized by us
2247                  * (for example, while enabling interrupt-remapping) then
2248                  * we got the things already rolling from a sane state.
2249                  */
2250                 if (iommu->qi)
2251                         continue;
2252
2253                 /*
2254                  * Clear any previous faults.
2255                  */
2256                 dmar_fault(-1, iommu);
2257                 /*
2258                  * Disable queued invalidation if supported and already enabled
2259                  * before OS handover.
2260                  */
2261                 dmar_disable_qi(iommu);
2262         }
2263
2264         for_each_drhd_unit(drhd) {
2265                 if (drhd->ignored)
2266                         continue;
2267
2268                 iommu = drhd->iommu;
2269
2270                 if (dmar_enable_qi(iommu)) {
2271                         /*
2272                          * Queued Invalidate not enabled, use Register Based
2273                          * Invalidate
2274                          */
2275                         iommu->flush.flush_context = __iommu_flush_context;
2276                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2277                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2278                                "invalidation\n",
2279                                (unsigned long long)drhd->reg_base_addr);
2280                 } else {
2281                         iommu->flush.flush_context = qi_flush_context;
2282                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2283                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2284                                "invalidation\n",
2285                                (unsigned long long)drhd->reg_base_addr);
2286                 }
2287         }
2288
2289         /*
2290          * If pass through is set and enabled, context entries of all pci
2291          * devices are intialized by pass through translation type.
2292          */
2293         if (iommu_pass_through) {
2294                 ret = init_context_pass_through();
2295                 if (ret) {
2296                         printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2297                         iommu_pass_through = 0;
2298                 }
2299         }
2300
2301         /*
2302          * If pass through is not set or not enabled, setup context entries for
2303          * identity mappings for rmrr, gfx, and isa and may fall back to static
2304          * identity mapping if iommu_identity_mapping is set.
2305          */
2306         if (!iommu_pass_through) {
2307 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2308                 if (!iommu_identity_mapping)
2309                         iommu_identity_mapping = 2;
2310 #endif
2311                 if (iommu_identity_mapping)
2312                         iommu_prepare_static_identity_mapping();
2313                 /*
2314                  * For each rmrr
2315                  *   for each dev attached to rmrr
2316                  *   do
2317                  *     locate drhd for dev, alloc domain for dev
2318                  *     allocate free domain
2319                  *     allocate page table entries for rmrr
2320                  *     if context not allocated for bus
2321                  *           allocate and init context
2322                  *           set present in root table for this bus
2323                  *     init context with domain, translation etc
2324                  *    endfor
2325                  * endfor
2326                  */
2327                 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2328                 for_each_rmrr_units(rmrr) {
2329                         for (i = 0; i < rmrr->devices_cnt; i++) {
2330                                 pdev = rmrr->devices[i];
2331                                 /*
2332                                  * some BIOS lists non-exist devices in DMAR
2333                                  * table.
2334                                  */
2335                                 if (!pdev)
2336                                         continue;
2337                                 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2338                                 if (ret)
2339                                         printk(KERN_ERR
2340                                  "IOMMU: mapping reserved region failed\n");
2341                         }
2342                 }
2343
2344                 iommu_prepare_isa();
2345         }
2346
2347         /*
2348          * for each drhd
2349          *   enable fault log
2350          *   global invalidate context cache
2351          *   global invalidate iotlb
2352          *   enable translation
2353          */
2354         for_each_drhd_unit(drhd) {
2355                 if (drhd->ignored)
2356                         continue;
2357                 iommu = drhd->iommu;
2358
2359                 iommu_flush_write_buffer(iommu);
2360
2361                 ret = dmar_set_interrupt(iommu);
2362                 if (ret)
2363                         goto error;
2364
2365                 iommu_set_root_entry(iommu);
2366
2367                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2368                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2369                 iommu_disable_protect_mem_regions(iommu);
2370
2371                 ret = iommu_enable_translation(iommu);
2372                 if (ret)
2373                         goto error;
2374         }
2375
2376         return 0;
2377 error:
2378         for_each_drhd_unit(drhd) {
2379                 if (drhd->ignored)
2380                         continue;
2381                 iommu = drhd->iommu;
2382                 free_iommu(iommu);
2383         }
2384         kfree(g_iommus);
2385         return ret;
2386 }
2387
2388 /* Returns a number of VTD pages, but aligned to MM page size */
2389 static inline unsigned long aligned_nrpages(unsigned long host_addr,
2390                                             size_t size)
2391 {
2392         host_addr &= ~PAGE_MASK;
2393         return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
2394 }
2395
2396 /* This takes a number of _MM_ pages, not VTD pages */
2397 static struct iova *intel_alloc_iova(struct device *dev,
2398                                      struct dmar_domain *domain,
2399                                      unsigned long nrpages, uint64_t dma_mask)
2400 {
2401         struct pci_dev *pdev = to_pci_dev(dev);
2402         struct iova *iova = NULL;
2403
2404         /* Restrict dma_mask to the width that the iommu can handle */
2405         dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2406
2407         if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2408                 /*
2409                  * First try to allocate an io virtual address in
2410                  * DMA_BIT_MASK(32) and if that fails then try allocating
2411                  * from higher range
2412                  */
2413                 iova = alloc_iova(&domain->iovad, nrpages,
2414                                   IOVA_PFN(DMA_BIT_MASK(32)), 1);
2415                 if (iova)
2416                         return iova;
2417         }
2418         iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2419         if (unlikely(!iova)) {
2420                 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2421                        nrpages, pci_name(pdev));
2422                 return NULL;
2423         }
2424
2425         return iova;
2426 }
2427
2428 static struct dmar_domain *
2429 get_valid_domain_for_dev(struct pci_dev *pdev)
2430 {
2431         struct dmar_domain *domain;
2432         int ret;
2433
2434         domain = get_domain_for_dev(pdev,
2435                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2436         if (!domain) {
2437                 printk(KERN_ERR
2438                         "Allocating domain for %s failed", pci_name(pdev));
2439                 return NULL;
2440         }
2441
2442         /* make sure context mapping is ok */
2443         if (unlikely(!domain_context_mapped(pdev))) {
2444                 ret = domain_context_mapping(domain, pdev,
2445                                              CONTEXT_TT_MULTI_LEVEL);
2446                 if (ret) {
2447                         printk(KERN_ERR
2448                                 "Domain context map for %s failed",
2449                                 pci_name(pdev));
2450                         return NULL;
2451                 }
2452         }
2453
2454         return domain;
2455 }
2456
2457 static int iommu_dummy(struct pci_dev *pdev)
2458 {
2459         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2460 }
2461
2462 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2463 static int iommu_no_mapping(struct device *dev)
2464 {
2465         struct pci_dev *pdev;
2466         int found;
2467
2468         if (unlikely(dev->bus != &pci_bus_type))
2469                 return 1;
2470
2471         pdev = to_pci_dev(dev);
2472         if (iommu_dummy(pdev))
2473                 return 1;
2474
2475         if (!iommu_identity_mapping)
2476                 return 0;
2477
2478         found = identity_mapping(pdev);
2479         if (found) {
2480                 if (iommu_should_identity_map(pdev, 0))
2481                         return 1;
2482                 else {
2483                         /*
2484                          * 32 bit DMA is removed from si_domain and fall back
2485                          * to non-identity mapping.
2486                          */
2487                         domain_remove_one_dev_info(si_domain, pdev);
2488                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2489                                pci_name(pdev));
2490                         return 0;
2491                 }
2492         } else {
2493                 /*
2494                  * In case of a detached 64 bit DMA device from vm, the device
2495                  * is put into si_domain for identity mapping.
2496                  */
2497                 if (iommu_should_identity_map(pdev, 0)) {
2498                         int ret;
2499                         ret = domain_add_dev_info(si_domain, pdev);
2500                         if (ret)
2501                                 return 0;
2502                         ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2503                         if (!ret) {
2504                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2505                                        pci_name(pdev));
2506                                 return 1;
2507                         }
2508                 }
2509         }
2510
2511         return 0;
2512 }
2513
2514 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2515                                      size_t size, int dir, u64 dma_mask)
2516 {
2517         struct pci_dev *pdev = to_pci_dev(hwdev);
2518         struct dmar_domain *domain;
2519         phys_addr_t start_paddr;
2520         struct iova *iova;
2521         int prot = 0;
2522         int ret;
2523         struct intel_iommu *iommu;
2524
2525         BUG_ON(dir == DMA_NONE);
2526
2527         if (iommu_no_mapping(hwdev))
2528                 return paddr;
2529
2530         domain = get_valid_domain_for_dev(pdev);
2531         if (!domain)
2532                 return 0;
2533
2534         iommu = domain_get_iommu(domain);
2535         size = aligned_nrpages(paddr, size);
2536
2537         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2538                                 pdev->dma_mask);
2539         if (!iova)
2540                 goto error;
2541
2542         /*
2543          * Check if DMAR supports zero-length reads on write only
2544          * mappings..
2545          */
2546         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2547                         !cap_zlr(iommu->cap))
2548                 prot |= DMA_PTE_READ;
2549         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2550                 prot |= DMA_PTE_WRITE;
2551         /*
2552          * paddr - (paddr + size) might be partial page, we should map the whole
2553          * page.  Note: if two part of one page are separately mapped, we
2554          * might have two guest_addr mapping to the same host paddr, but this
2555          * is not a big problem
2556          */
2557         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2558                                  paddr >> VTD_PAGE_SHIFT, size, prot);
2559         if (ret)
2560                 goto error;
2561
2562         /* it's a non-present to present mapping. Only flush if caching mode */
2563         if (cap_caching_mode(iommu->cap))
2564                 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2565         else
2566                 iommu_flush_write_buffer(iommu);
2567
2568         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2569         start_paddr += paddr & ~PAGE_MASK;
2570         return start_paddr;
2571
2572 error:
2573         if (iova)
2574                 __free_iova(&domain->iovad, iova);
2575         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2576                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2577         return 0;
2578 }
2579
2580 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2581                                  unsigned long offset, size_t size,
2582                                  enum dma_data_direction dir,
2583                                  struct dma_attrs *attrs)
2584 {
2585         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2586                                   dir, to_pci_dev(dev)->dma_mask);
2587 }
2588
2589 static void flush_unmaps(void)
2590 {
2591         int i, j;
2592
2593         timer_on = 0;
2594
2595         /* just flush them all */
2596         for (i = 0; i < g_num_of_iommus; i++) {
2597                 struct intel_iommu *iommu = g_iommus[i];
2598                 if (!iommu)
2599                         continue;
2600
2601                 if (!deferred_flush[i].next)
2602                         continue;
2603
2604                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2605                                          DMA_TLB_GLOBAL_FLUSH);
2606                 for (j = 0; j < deferred_flush[i].next; j++) {
2607                         unsigned long mask;
2608                         struct iova *iova = deferred_flush[i].iova[j];
2609
2610                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2611                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2612                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2613                                         iova->pfn_lo << PAGE_SHIFT, mask);
2614                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2615                 }
2616                 deferred_flush[i].next = 0;
2617         }
2618
2619         list_size = 0;
2620 }
2621
2622 static void flush_unmaps_timeout(unsigned long data)
2623 {
2624         unsigned long flags;
2625
2626         spin_lock_irqsave(&async_umap_flush_lock, flags);
2627         flush_unmaps();
2628         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2629 }
2630
2631 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2632 {
2633         unsigned long flags;
2634         int next, iommu_id;
2635         struct intel_iommu *iommu;
2636
2637         spin_lock_irqsave(&async_umap_flush_lock, flags);
2638         if (list_size == HIGH_WATER_MARK)
2639                 flush_unmaps();
2640
2641         iommu = domain_get_iommu(dom);
2642         iommu_id = iommu->seq_id;
2643
2644         next = deferred_flush[iommu_id].next;
2645         deferred_flush[iommu_id].domain[next] = dom;
2646         deferred_flush[iommu_id].iova[next] = iova;
2647         deferred_flush[iommu_id].next++;
2648
2649         if (!timer_on) {
2650                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2651                 timer_on = 1;
2652         }
2653         list_size++;
2654         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2655 }
2656
2657 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2658                              size_t size, enum dma_data_direction dir,
2659                              struct dma_attrs *attrs)
2660 {
2661         struct pci_dev *pdev = to_pci_dev(dev);
2662         struct dmar_domain *domain;
2663         unsigned long start_pfn, last_pfn;
2664         struct iova *iova;
2665         struct intel_iommu *iommu;
2666
2667         if (iommu_no_mapping(dev))
2668                 return;
2669
2670         domain = find_domain(pdev);
2671         BUG_ON(!domain);
2672
2673         iommu = domain_get_iommu(domain);
2674
2675         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2676         if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2677                       (unsigned long long)dev_addr))
2678                 return;
2679
2680         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2681         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2682
2683         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2684                  pci_name(pdev), start_pfn, last_pfn);
2685
2686         /*  clear the whole page */
2687         dma_pte_clear_range(domain, start_pfn, last_pfn);
2688
2689         /* free page tables */
2690         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2691
2692         if (intel_iommu_strict) {
2693                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2694                                       last_pfn - start_pfn + 1);
2695                 /* free iova */
2696                 __free_iova(&domain->iovad, iova);
2697         } else {
2698                 add_unmap(domain, iova);
2699                 /*
2700                  * queue up the release of the unmap to save the 1/6th of the
2701                  * cpu used up by the iotlb flush operation...
2702                  */
2703         }
2704 }
2705
2706 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2707                                int dir)
2708 {
2709         intel_unmap_page(dev, dev_addr, size, dir, NULL);
2710 }
2711
2712 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2713                                   dma_addr_t *dma_handle, gfp_t flags)
2714 {
2715         void *vaddr;
2716         int order;
2717
2718         size = PAGE_ALIGN(size);
2719         order = get_order(size);
2720         flags &= ~(GFP_DMA | GFP_DMA32);
2721
2722         vaddr = (void *)__get_free_pages(flags, order);
2723         if (!vaddr)
2724                 return NULL;
2725         memset(vaddr, 0, size);
2726
2727         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2728                                          DMA_BIDIRECTIONAL,
2729                                          hwdev->coherent_dma_mask);
2730         if (*dma_handle)
2731                 return vaddr;
2732         free_pages((unsigned long)vaddr, order);
2733         return NULL;
2734 }
2735
2736 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2737                                 dma_addr_t dma_handle)
2738 {
2739         int order;
2740
2741         size = PAGE_ALIGN(size);
2742         order = get_order(size);
2743
2744         intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2745         free_pages((unsigned long)vaddr, order);
2746 }
2747
2748 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2749                            int nelems, enum dma_data_direction dir,
2750                            struct dma_attrs *attrs)
2751 {
2752         struct pci_dev *pdev = to_pci_dev(hwdev);
2753         struct dmar_domain *domain;
2754         unsigned long start_pfn, last_pfn;
2755         struct iova *iova;
2756         struct intel_iommu *iommu;
2757
2758         if (iommu_no_mapping(hwdev))
2759                 return;
2760
2761         domain = find_domain(pdev);
2762         BUG_ON(!domain);
2763
2764         iommu = domain_get_iommu(domain);
2765
2766         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2767         if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2768                       (unsigned long long)sglist[0].dma_address))
2769                 return;
2770
2771         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2772         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2773
2774         /*  clear the whole page */
2775         dma_pte_clear_range(domain, start_pfn, last_pfn);
2776
2777         /* free page tables */
2778         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2779
2780         iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2781                               (last_pfn - start_pfn + 1));
2782
2783         /* free iova */
2784         __free_iova(&domain->iovad, iova);
2785 }
2786
2787 static int intel_nontranslate_map_sg(struct device *hddev,
2788         struct scatterlist *sglist, int nelems, int dir)
2789 {
2790         int i;
2791         struct scatterlist *sg;
2792
2793         for_each_sg(sglist, sg, nelems, i) {
2794                 BUG_ON(!sg_page(sg));
2795                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2796                 sg->dma_length = sg->length;
2797         }
2798         return nelems;
2799 }
2800
2801 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2802                         enum dma_data_direction dir, struct dma_attrs *attrs)
2803 {
2804         int i;
2805         struct pci_dev *pdev = to_pci_dev(hwdev);
2806         struct dmar_domain *domain;
2807         size_t size = 0;
2808         int prot = 0;
2809         size_t offset_pfn = 0;
2810         struct iova *iova = NULL;
2811         int ret;
2812         struct scatterlist *sg;
2813         unsigned long start_vpfn;
2814         struct intel_iommu *iommu;
2815
2816         BUG_ON(dir == DMA_NONE);
2817         if (iommu_no_mapping(hwdev))
2818                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2819
2820         domain = get_valid_domain_for_dev(pdev);
2821         if (!domain)
2822                 return 0;
2823
2824         iommu = domain_get_iommu(domain);
2825
2826         for_each_sg(sglist, sg, nelems, i)
2827                 size += aligned_nrpages(sg->offset, sg->length);
2828
2829         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2830                                 pdev->dma_mask);
2831         if (!iova) {
2832                 sglist->dma_length = 0;
2833                 return 0;
2834         }
2835
2836         /*
2837          * Check if DMAR supports zero-length reads on write only
2838          * mappings..
2839          */
2840         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2841                         !cap_zlr(iommu->cap))
2842                 prot |= DMA_PTE_READ;
2843         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2844                 prot |= DMA_PTE_WRITE;
2845
2846         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2847
2848         ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot);
2849         if (unlikely(ret)) {
2850                 /*  clear the page */
2851                 dma_pte_clear_range(domain, start_vpfn,
2852                                     start_vpfn + size - 1);
2853                 /* free page tables */
2854                 dma_pte_free_pagetable(domain, start_vpfn,
2855                                        start_vpfn + size - 1);
2856                 /* free iova */
2857                 __free_iova(&domain->iovad, iova);
2858                 return 0;
2859         }
2860
2861         /* it's a non-present to present mapping. Only flush if caching mode */
2862         if (cap_caching_mode(iommu->cap))
2863                 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2864         else
2865                 iommu_flush_write_buffer(iommu);
2866
2867         return nelems;
2868 }
2869
2870 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2871 {
2872         return !dma_addr;
2873 }
2874
2875 struct dma_map_ops intel_dma_ops = {
2876         .alloc_coherent = intel_alloc_coherent,
2877         .free_coherent = intel_free_coherent,
2878         .map_sg = intel_map_sg,
2879         .unmap_sg = intel_unmap_sg,
2880         .map_page = intel_map_page,
2881         .unmap_page = intel_unmap_page,
2882         .mapping_error = intel_mapping_error,
2883 };
2884
2885 static inline int iommu_domain_cache_init(void)
2886 {
2887         int ret = 0;
2888
2889         iommu_domain_cache = kmem_cache_create("iommu_domain",
2890                                          sizeof(struct dmar_domain),
2891                                          0,
2892                                          SLAB_HWCACHE_ALIGN,
2893
2894                                          NULL);
2895         if (!iommu_domain_cache) {
2896                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2897                 ret = -ENOMEM;
2898         }
2899
2900         return ret;
2901 }
2902
2903 static inline int iommu_devinfo_cache_init(void)
2904 {
2905         int ret = 0;
2906
2907         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2908                                          sizeof(struct device_domain_info),
2909                                          0,
2910                                          SLAB_HWCACHE_ALIGN,
2911                                          NULL);
2912         if (!iommu_devinfo_cache) {
2913                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2914                 ret = -ENOMEM;
2915         }
2916
2917         return ret;
2918 }
2919
2920 static inline int iommu_iova_cache_init(void)
2921 {
2922         int ret = 0;
2923
2924         iommu_iova_cache = kmem_cache_create("iommu_iova",
2925                                          sizeof(struct iova),
2926                                          0,
2927                                          SLAB_HWCACHE_ALIGN,
2928                                          NULL);
2929         if (!iommu_iova_cache) {
2930                 printk(KERN_ERR "Couldn't create iova cache\n");
2931                 ret = -ENOMEM;
2932         }
2933
2934         return ret;
2935 }
2936
2937 static int __init iommu_init_mempool(void)
2938 {
2939         int ret;
2940         ret = iommu_iova_cache_init();
2941         if (ret)
2942                 return ret;
2943
2944         ret = iommu_domain_cache_init();
2945         if (ret)
2946                 goto domain_error;
2947
2948         ret = iommu_devinfo_cache_init();
2949         if (!ret)
2950                 return ret;
2951
2952         kmem_cache_destroy(iommu_domain_cache);
2953 domain_error:
2954         kmem_cache_destroy(iommu_iova_cache);
2955
2956         return -ENOMEM;
2957 }
2958
2959 static void __init iommu_exit_mempool(void)
2960 {
2961         kmem_cache_destroy(iommu_devinfo_cache);
2962         kmem_cache_destroy(iommu_domain_cache);
2963         kmem_cache_destroy(iommu_iova_cache);
2964
2965 }
2966
2967 static void __init init_no_remapping_devices(void)
2968 {
2969         struct dmar_drhd_unit *drhd;
2970
2971         for_each_drhd_unit(drhd) {
2972                 if (!drhd->include_all) {
2973                         int i;
2974                         for (i = 0; i < drhd->devices_cnt; i++)
2975                                 if (drhd->devices[i] != NULL)
2976                                         break;
2977                         /* ignore DMAR unit if no pci devices exist */
2978                         if (i == drhd->devices_cnt)
2979                                 drhd->ignored = 1;
2980                 }
2981         }
2982
2983         if (dmar_map_gfx)
2984                 return;
2985
2986         for_each_drhd_unit(drhd) {
2987                 int i;
2988                 if (drhd->ignored || drhd->include_all)
2989                         continue;
2990
2991                 for (i = 0; i < drhd->devices_cnt; i++)
2992                         if (drhd->devices[i] &&
2993                                 !IS_GFX_DEVICE(drhd->devices[i]))
2994                                 break;
2995
2996                 if (i < drhd->devices_cnt)
2997                         continue;
2998
2999                 /* bypass IOMMU if it is just for gfx devices */
3000                 drhd->ignored = 1;
3001                 for (i = 0; i < drhd->devices_cnt; i++) {
3002                         if (!drhd->devices[i])
3003                                 continue;
3004                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3005                 }
3006         }
3007 }
3008
3009 #ifdef CONFIG_SUSPEND
3010 static int init_iommu_hw(void)
3011 {
3012         struct dmar_drhd_unit *drhd;
3013         struct intel_iommu *iommu = NULL;
3014
3015         for_each_active_iommu(iommu, drhd)
3016                 if (iommu->qi)
3017                         dmar_reenable_qi(iommu);
3018
3019         for_each_active_iommu(iommu, drhd) {
3020                 iommu_flush_write_buffer(iommu);
3021
3022                 iommu_set_root_entry(iommu);
3023
3024                 iommu->flush.flush_context(iommu, 0, 0, 0,
3025                                            DMA_CCMD_GLOBAL_INVL);
3026                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3027                                          DMA_TLB_GLOBAL_FLUSH);
3028                 iommu_disable_protect_mem_regions(iommu);
3029                 iommu_enable_translation(iommu);
3030         }
3031
3032         return 0;
3033 }
3034
3035 static void iommu_flush_all(void)
3036 {
3037         struct dmar_drhd_unit *drhd;
3038         struct intel_iommu *iommu;
3039
3040         for_each_active_iommu(iommu, drhd) {
3041                 iommu->flush.flush_context(iommu, 0, 0, 0,
3042                                            DMA_CCMD_GLOBAL_INVL);
3043                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3044                                          DMA_TLB_GLOBAL_FLUSH);
3045         }
3046 }
3047
3048 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3049 {
3050         struct dmar_drhd_unit *drhd;
3051         struct intel_iommu *iommu = NULL;
3052         unsigned long flag;
3053
3054         for_each_active_iommu(iommu, drhd) {
3055                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3056                                                  GFP_ATOMIC);
3057                 if (!iommu->iommu_state)
3058                         goto nomem;
3059         }
3060
3061         iommu_flush_all();
3062
3063         for_each_active_iommu(iommu, drhd) {
3064                 iommu_disable_translation(iommu);
3065
3066                 spin_lock_irqsave(&iommu->register_lock, flag);
3067
3068                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3069                         readl(iommu->reg + DMAR_FECTL_REG);
3070                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3071                         readl(iommu->reg + DMAR_FEDATA_REG);
3072                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3073                         readl(iommu->reg + DMAR_FEADDR_REG);
3074                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3075                         readl(iommu->reg + DMAR_FEUADDR_REG);
3076
3077                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3078         }
3079         return 0;
3080
3081 nomem:
3082         for_each_active_iommu(iommu, drhd)
3083                 kfree(iommu->iommu_state);
3084
3085         return -ENOMEM;
3086 }
3087
3088 static int iommu_resume(struct sys_device *dev)
3089 {
3090         struct dmar_drhd_unit *drhd;
3091         struct intel_iommu *iommu = NULL;
3092         unsigned long flag;
3093
3094         if (init_iommu_hw()) {
3095                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3096                 return -EIO;
3097         }
3098
3099         for_each_active_iommu(iommu, drhd) {
3100
3101                 spin_lock_irqsave(&iommu->register_lock, flag);
3102
3103                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3104                         iommu->reg + DMAR_FECTL_REG);
3105                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3106                         iommu->reg + DMAR_FEDATA_REG);
3107                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3108                         iommu->reg + DMAR_FEADDR_REG);
3109                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3110                         iommu->reg + DMAR_FEUADDR_REG);
3111
3112                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3113         }
3114
3115         for_each_active_iommu(iommu, drhd)
3116                 kfree(iommu->iommu_state);
3117
3118         return 0;
3119 }
3120
3121 static struct sysdev_class iommu_sysclass = {
3122         .name           = "iommu",
3123         .resume         = iommu_resume,
3124         .suspend        = iommu_suspend,
3125 };
3126
3127 static struct sys_device device_iommu = {
3128         .cls    = &iommu_sysclass,
3129 };
3130
3131 static int __init init_iommu_sysfs(void)
3132 {
3133         int error;
3134
3135         error = sysdev_class_register(&iommu_sysclass);
3136         if (error)
3137                 return error;
3138
3139         error = sysdev_register(&device_iommu);
3140         if (error)
3141                 sysdev_class_unregister(&iommu_sysclass);
3142
3143         return error;
3144 }
3145
3146 #else
3147 static int __init init_iommu_sysfs(void)
3148 {
3149         return 0;
3150 }
3151 #endif  /* CONFIG_PM */
3152
3153 int __init intel_iommu_init(void)
3154 {
3155         int ret = 0;
3156
3157         if (dmar_table_init())
3158                 return  -ENODEV;
3159
3160         if (dmar_dev_scope_init())
3161                 return  -ENODEV;
3162
3163         /*
3164          * Check the need for DMA-remapping initialization now.
3165          * Above initialization will also be used by Interrupt-remapping.
3166          */
3167         if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3168                 return -ENODEV;
3169
3170         iommu_init_mempool();
3171         dmar_init_reserved_ranges();
3172
3173         init_no_remapping_devices();
3174
3175         ret = init_dmars();
3176         if (ret) {
3177                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3178                 put_iova_domain(&reserved_iova_list);
3179                 iommu_exit_mempool();
3180                 return ret;
3181         }
3182         printk(KERN_INFO
3183         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3184
3185         init_timer(&unmap_timer);
3186         force_iommu = 1;
3187
3188         if (!iommu_pass_through) {
3189                 printk(KERN_INFO
3190                        "Multi-level page-table translation for DMAR.\n");
3191                 dma_ops = &intel_dma_ops;
3192         } else
3193                 printk(KERN_INFO
3194                        "DMAR: Pass through translation for DMAR.\n");
3195
3196         init_iommu_sysfs();
3197
3198         register_iommu(&intel_iommu_ops);
3199
3200         return 0;
3201 }
3202
3203 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3204                                            struct pci_dev *pdev)
3205 {
3206         struct pci_dev *tmp, *parent;
3207
3208         if (!iommu || !pdev)
3209                 return;
3210
3211         /* dependent device detach */
3212         tmp = pci_find_upstream_pcie_bridge(pdev);
3213         /* Secondary interface's bus number and devfn 0 */
3214         if (tmp) {
3215                 parent = pdev->bus->self;
3216                 while (parent != tmp) {
3217                         iommu_detach_dev(iommu, parent->bus->number,
3218                                          parent->devfn);
3219                         parent = parent->bus->self;
3220                 }
3221                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3222                         iommu_detach_dev(iommu,
3223                                 tmp->subordinate->number, 0);
3224                 else /* this is a legacy PCI bridge */
3225                         iommu_detach_dev(iommu, tmp->bus->number,
3226                                          tmp->devfn);
3227         }
3228 }
3229
3230 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3231                                           struct pci_dev *pdev)
3232 {
3233         struct device_domain_info *info;
3234         struct intel_iommu *iommu;
3235         unsigned long flags;
3236         int found = 0;
3237         struct list_head *entry, *tmp;
3238
3239         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3240                                 pdev->devfn);
3241         if (!iommu)
3242                 return;
3243
3244         spin_lock_irqsave(&device_domain_lock, flags);
3245         list_for_each_safe(entry, tmp, &domain->devices) {
3246                 info = list_entry(entry, struct device_domain_info, link);
3247                 /* No need to compare PCI domain; it has to be the same */
3248                 if (info->bus == pdev->bus->number &&
3249                     info->devfn == pdev->devfn) {
3250                         list_del(&info->link);
3251                         list_del(&info->global);
3252                         if (info->dev)
3253                                 info->dev->dev.archdata.iommu = NULL;
3254                         spin_unlock_irqrestore(&device_domain_lock, flags);
3255
3256                         iommu_disable_dev_iotlb(info);
3257                         iommu_detach_dev(iommu, info->bus, info->devfn);
3258                         iommu_detach_dependent_devices(iommu, pdev);
3259                         free_devinfo_mem(info);
3260
3261                         spin_lock_irqsave(&device_domain_lock, flags);
3262
3263                         if (found)
3264                                 break;
3265                         else
3266                                 continue;
3267                 }
3268
3269                 /* if there is no other devices under the same iommu
3270                  * owned by this domain, clear this iommu in iommu_bmp
3271                  * update iommu count and coherency
3272                  */
3273                 if (iommu == device_to_iommu(info->segment, info->bus,
3274                                             info->devfn))
3275                         found = 1;
3276         }
3277
3278         if (found == 0) {
3279                 unsigned long tmp_flags;
3280                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3281                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3282                 domain->iommu_count--;
3283                 domain_update_iommu_cap(domain);
3284                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3285         }
3286
3287         spin_unlock_irqrestore(&device_domain_lock, flags);
3288 }
3289
3290 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3291 {
3292         struct device_domain_info *info;
3293         struct intel_iommu *iommu;
3294         unsigned long flags1, flags2;
3295
3296         spin_lock_irqsave(&device_domain_lock, flags1);
3297         while (!list_empty(&domain->devices)) {
3298                 info = list_entry(domain->devices.next,
3299                         struct device_domain_info, link);
3300                 list_del(&info->link);
3301                 list_del(&info->global);
3302                 if (info->dev)
3303                         info->dev->dev.archdata.iommu = NULL;
3304
3305                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3306
3307                 iommu_disable_dev_iotlb(info);
3308                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3309                 iommu_detach_dev(iommu, info->bus, info->devfn);
3310                 iommu_detach_dependent_devices(iommu, info->dev);
3311
3312                 /* clear this iommu in iommu_bmp, update iommu count
3313                  * and capabilities
3314                  */
3315                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3316                 if (test_and_clear_bit(iommu->seq_id,
3317                                        &domain->iommu_bmp)) {
3318                         domain->iommu_count--;
3319                         domain_update_iommu_cap(domain);
3320                 }
3321                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3322
3323                 free_devinfo_mem(info);
3324                 spin_lock_irqsave(&device_domain_lock, flags1);
3325         }
3326         spin_unlock_irqrestore(&device_domain_lock, flags1);
3327 }
3328
3329 /* domain id for virtual machine, it won't be set in context */
3330 static unsigned long vm_domid;
3331
3332 static int vm_domain_min_agaw(struct dmar_domain *domain)
3333 {
3334         int i;
3335         int min_agaw = domain->agaw;
3336
3337         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3338         for (; i < g_num_of_iommus; ) {
3339                 if (min_agaw > g_iommus[i]->agaw)
3340                         min_agaw = g_iommus[i]->agaw;
3341
3342                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3343         }
3344
3345         return min_agaw;
3346 }
3347
3348 static struct dmar_domain *iommu_alloc_vm_domain(void)
3349 {
3350         struct dmar_domain *domain;
3351
3352         domain = alloc_domain_mem();
3353         if (!domain)
3354                 return NULL;
3355
3356         domain->id = vm_domid++;
3357         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3358         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3359
3360         return domain;
3361 }
3362
3363 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3364 {
3365         int adjust_width;
3366
3367         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3368         spin_lock_init(&domain->iommu_lock);
3369
3370         domain_reserve_special_ranges(domain);
3371
3372         /* calculate AGAW */
3373         domain->gaw = guest_width;
3374         adjust_width = guestwidth_to_adjustwidth(guest_width);
3375         domain->agaw = width_to_agaw(adjust_width);
3376
3377         INIT_LIST_HEAD(&domain->devices);
3378
3379         domain->iommu_count = 0;
3380         domain->iommu_coherency = 0;
3381         domain->max_addr = 0;
3382
3383         /* always allocate the top pgd */
3384         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3385         if (!domain->pgd)
3386                 return -ENOMEM;
3387         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3388         return 0;
3389 }
3390
3391 static void iommu_free_vm_domain(struct dmar_domain *domain)
3392 {
3393         unsigned long flags;
3394         struct dmar_drhd_unit *drhd;
3395         struct intel_iommu *iommu;
3396         unsigned long i;
3397         unsigned long ndomains;
3398
3399         for_each_drhd_unit(drhd) {
3400                 if (drhd->ignored)
3401                         continue;
3402                 iommu = drhd->iommu;
3403
3404                 ndomains = cap_ndoms(iommu->cap);
3405                 i = find_first_bit(iommu->domain_ids, ndomains);
3406                 for (; i < ndomains; ) {
3407                         if (iommu->domains[i] == domain) {
3408                                 spin_lock_irqsave(&iommu->lock, flags);
3409                                 clear_bit(i, iommu->domain_ids);
3410                                 iommu->domains[i] = NULL;
3411                                 spin_unlock_irqrestore(&iommu->lock, flags);
3412                                 break;
3413                         }
3414                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3415                 }
3416         }
3417 }
3418
3419 static void vm_domain_exit(struct dmar_domain *domain)
3420 {
3421         /* Domain 0 is reserved, so dont process it */
3422         if (!domain)
3423                 return;
3424
3425         vm_domain_remove_all_dev_info(domain);
3426         /* destroy iovas */
3427         put_iova_domain(&domain->iovad);
3428
3429         /* clear ptes */
3430         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3431
3432         /* free page tables */
3433         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3434
3435         iommu_free_vm_domain(domain);
3436         free_domain_mem(domain);
3437 }
3438
3439 static int intel_iommu_domain_init(struct iommu_domain *domain)
3440 {
3441         struct dmar_domain *dmar_domain;
3442
3443         dmar_domain = iommu_alloc_vm_domain();
3444         if (!dmar_domain) {
3445                 printk(KERN_ERR
3446                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3447                 return -ENOMEM;
3448         }
3449         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3450                 printk(KERN_ERR
3451                         "intel_iommu_domain_init() failed\n");
3452                 vm_domain_exit(dmar_domain);
3453                 return -ENOMEM;
3454         }
3455         domain->priv = dmar_domain;
3456
3457         return 0;
3458 }
3459
3460 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3461 {
3462         struct dmar_domain *dmar_domain = domain->priv;
3463
3464         domain->priv = NULL;
3465         vm_domain_exit(dmar_domain);
3466 }
3467
3468 static int intel_iommu_attach_device(struct iommu_domain *domain,
3469                                      struct device *dev)
3470 {
3471         struct dmar_domain *dmar_domain = domain->priv;
3472         struct pci_dev *pdev = to_pci_dev(dev);
3473         struct intel_iommu *iommu;
3474         int addr_width;
3475         u64 end;
3476         int ret;
3477
3478         /* normally pdev is not mapped */
3479         if (unlikely(domain_context_mapped(pdev))) {
3480                 struct dmar_domain *old_domain;
3481
3482                 old_domain = find_domain(pdev);
3483                 if (old_domain) {
3484                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3485                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3486                                 domain_remove_one_dev_info(old_domain, pdev);
3487                         else
3488                                 domain_remove_dev_info(old_domain);
3489                 }
3490         }
3491
3492         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3493                                 pdev->devfn);
3494         if (!iommu)
3495                 return -ENODEV;
3496
3497         /* check if this iommu agaw is sufficient for max mapped address */
3498         addr_width = agaw_to_width(iommu->agaw);
3499         end = DOMAIN_MAX_ADDR(addr_width);
3500         end = end & VTD_PAGE_MASK;
3501         if (end < dmar_domain->max_addr) {
3502                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3503                        "sufficient for the mapped address (%llx)\n",
3504                        __func__, iommu->agaw, dmar_domain->max_addr);
3505                 return -EFAULT;
3506         }
3507
3508         ret = domain_add_dev_info(dmar_domain, pdev);
3509         if (ret)
3510                 return ret;
3511
3512         ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3513         return ret;
3514 }
3515
3516 static void intel_iommu_detach_device(struct iommu_domain *domain,
3517                                       struct device *dev)
3518 {
3519         struct dmar_domain *dmar_domain = domain->priv;
3520         struct pci_dev *pdev = to_pci_dev(dev);
3521
3522         domain_remove_one_dev_info(dmar_domain, pdev);
3523 }
3524
3525 static int intel_iommu_map_range(struct iommu_domain *domain,
3526                                  unsigned long iova, phys_addr_t hpa,
3527                                  size_t size, int iommu_prot)
3528 {
3529         struct dmar_domain *dmar_domain = domain->priv;
3530         u64 max_addr;
3531         int addr_width;
3532         int prot = 0;
3533         int ret;
3534
3535         if (iommu_prot & IOMMU_READ)
3536                 prot |= DMA_PTE_READ;
3537         if (iommu_prot & IOMMU_WRITE)
3538                 prot |= DMA_PTE_WRITE;
3539         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3540                 prot |= DMA_PTE_SNP;
3541
3542         max_addr = iova + size;
3543         if (dmar_domain->max_addr < max_addr) {
3544                 int min_agaw;
3545                 u64 end;
3546
3547                 /* check if minimum agaw is sufficient for mapped address */
3548                 min_agaw = vm_domain_min_agaw(dmar_domain);
3549                 addr_width = agaw_to_width(min_agaw);
3550                 end = DOMAIN_MAX_ADDR(addr_width);
3551                 end = end & VTD_PAGE_MASK;
3552                 if (end < max_addr) {
3553                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3554                                "sufficient for the mapped address (%llx)\n",
3555                                __func__, min_agaw, max_addr);
3556                         return -EFAULT;
3557                 }
3558                 dmar_domain->max_addr = max_addr;
3559         }
3560         /* Round up size to next multiple of PAGE_SIZE, if it and
3561            the low bits of hpa would take us onto the next page */
3562         size = aligned_nrpages(hpa, size);
3563         ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3564                                  hpa >> VTD_PAGE_SHIFT, size, prot);
3565         return ret;
3566 }
3567
3568 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3569                                     unsigned long iova, size_t size)
3570 {
3571         struct dmar_domain *dmar_domain = domain->priv;
3572
3573         dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3574                             (iova + size - 1) >> VTD_PAGE_SHIFT);
3575
3576         if (dmar_domain->max_addr == iova + size)
3577                 dmar_domain->max_addr = iova;
3578 }
3579
3580 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3581                                             unsigned long iova)
3582 {
3583         struct dmar_domain *dmar_domain = domain->priv;
3584         struct dma_pte *pte;
3585         u64 phys = 0;
3586
3587         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3588         if (pte)
3589                 phys = dma_pte_addr(pte);
3590
3591         return phys;
3592 }
3593
3594 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3595                                       unsigned long cap)
3596 {
3597         struct dmar_domain *dmar_domain = domain->priv;
3598
3599         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3600                 return dmar_domain->iommu_snooping;
3601
3602         return 0;
3603 }
3604
3605 static struct iommu_ops intel_iommu_ops = {
3606         .domain_init    = intel_iommu_domain_init,
3607         .domain_destroy = intel_iommu_domain_destroy,
3608         .attach_dev     = intel_iommu_attach_device,
3609         .detach_dev     = intel_iommu_detach_device,
3610         .map            = intel_iommu_map_range,
3611         .unmap          = intel_iommu_unmap_range,
3612         .iova_to_phys   = intel_iommu_iova_to_phys,
3613         .domain_has_cap = intel_iommu_domain_has_cap,
3614 };
3615
3616 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3617 {
3618         /*
3619          * Mobile 4 Series Chipset neglects to set RWBF capability,
3620          * but needs it:
3621          */
3622         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3623         rwbf_quirk = 1;
3624 }
3625
3626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);