intel-iommu: Cope with yet another BIOS screwup causing crashes
[linux-2.6.git] / drivers / pci / intel-iommu.c
1 /*
2  * Copyright (c) 2006, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15  * Place - Suite 330, Boston, MA 02111-1307 USA.
16  *
17  * Copyright (C) 2006-2008 Intel Corporation
18  * Author: Ashok Raj <ashok.raj@intel.com>
19  * Author: Shaohua Li <shaohua.li@intel.com>
20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21  * Author: Fenghua Yu <fenghua.yu@intel.com>
22  */
23
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
42 #include "pci.h"
43
44 #define ROOT_SIZE               VTD_PAGE_SIZE
45 #define CONTEXT_SIZE            VTD_PAGE_SIZE
46
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50 #define IOAPIC_RANGE_START      (0xfee00000)
51 #define IOAPIC_RANGE_END        (0xfeefffff)
52 #define IOVA_START_ADDR         (0x1000)
53
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
56 #define MAX_AGAW_WIDTH 64
57
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
59 #define DOMAIN_MAX_PFN(gaw)  ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
60
61 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
62 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
63 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
64
65
66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
67    are never going to work. */
68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
69 {
70         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
71 }
72
73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
74 {
75         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
76 }
77 static inline unsigned long page_to_dma_pfn(struct page *pg)
78 {
79         return mm_to_dma_pfn(page_to_pfn(pg));
80 }
81 static inline unsigned long virt_to_dma_pfn(void *p)
82 {
83         return page_to_dma_pfn(virt_to_page(p));
84 }
85
86 /* global iommu list, set NULL for ignored DMAR units */
87 static struct intel_iommu **g_iommus;
88
89 static int rwbf_quirk;
90
91 /*
92  * 0: Present
93  * 1-11: Reserved
94  * 12-63: Context Ptr (12 - (haw-1))
95  * 64-127: Reserved
96  */
97 struct root_entry {
98         u64     val;
99         u64     rsvd1;
100 };
101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
102 static inline bool root_present(struct root_entry *root)
103 {
104         return (root->val & 1);
105 }
106 static inline void set_root_present(struct root_entry *root)
107 {
108         root->val |= 1;
109 }
110 static inline void set_root_value(struct root_entry *root, unsigned long value)
111 {
112         root->val |= value & VTD_PAGE_MASK;
113 }
114
115 static inline struct context_entry *
116 get_context_addr_from_root(struct root_entry *root)
117 {
118         return (struct context_entry *)
119                 (root_present(root)?phys_to_virt(
120                 root->val & VTD_PAGE_MASK) :
121                 NULL);
122 }
123
124 /*
125  * low 64 bits:
126  * 0: present
127  * 1: fault processing disable
128  * 2-3: translation type
129  * 12-63: address space root
130  * high 64 bits:
131  * 0-2: address width
132  * 3-6: aval
133  * 8-23: domain id
134  */
135 struct context_entry {
136         u64 lo;
137         u64 hi;
138 };
139
140 static inline bool context_present(struct context_entry *context)
141 {
142         return (context->lo & 1);
143 }
144 static inline void context_set_present(struct context_entry *context)
145 {
146         context->lo |= 1;
147 }
148
149 static inline void context_set_fault_enable(struct context_entry *context)
150 {
151         context->lo &= (((u64)-1) << 2) | 1;
152 }
153
154 static inline void context_set_translation_type(struct context_entry *context,
155                                                 unsigned long value)
156 {
157         context->lo &= (((u64)-1) << 4) | 3;
158         context->lo |= (value & 3) << 2;
159 }
160
161 static inline void context_set_address_root(struct context_entry *context,
162                                             unsigned long value)
163 {
164         context->lo |= value & VTD_PAGE_MASK;
165 }
166
167 static inline void context_set_address_width(struct context_entry *context,
168                                              unsigned long value)
169 {
170         context->hi |= value & 7;
171 }
172
173 static inline void context_set_domain_id(struct context_entry *context,
174                                          unsigned long value)
175 {
176         context->hi |= (value & ((1 << 16) - 1)) << 8;
177 }
178
179 static inline void context_clear_entry(struct context_entry *context)
180 {
181         context->lo = 0;
182         context->hi = 0;
183 }
184
185 /*
186  * 0: readable
187  * 1: writable
188  * 2-6: reserved
189  * 7: super page
190  * 8-10: available
191  * 11: snoop behavior
192  * 12-63: Host physcial address
193  */
194 struct dma_pte {
195         u64 val;
196 };
197
198 static inline void dma_clear_pte(struct dma_pte *pte)
199 {
200         pte->val = 0;
201 }
202
203 static inline void dma_set_pte_readable(struct dma_pte *pte)
204 {
205         pte->val |= DMA_PTE_READ;
206 }
207
208 static inline void dma_set_pte_writable(struct dma_pte *pte)
209 {
210         pte->val |= DMA_PTE_WRITE;
211 }
212
213 static inline void dma_set_pte_snp(struct dma_pte *pte)
214 {
215         pte->val |= DMA_PTE_SNP;
216 }
217
218 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
219 {
220         pte->val = (pte->val & ~3) | (prot & 3);
221 }
222
223 static inline u64 dma_pte_addr(struct dma_pte *pte)
224 {
225 #ifdef CONFIG_64BIT
226         return pte->val & VTD_PAGE_MASK;
227 #else
228         /* Must have a full atomic 64-bit read */
229         return  __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
230 #endif
231 }
232
233 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
234 {
235         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
236 }
237
238 static inline bool dma_pte_present(struct dma_pte *pte)
239 {
240         return (pte->val & 3) != 0;
241 }
242
243 static inline int first_pte_in_page(struct dma_pte *pte)
244 {
245         return !((unsigned long)pte & ~VTD_PAGE_MASK);
246 }
247
248 /*
249  * This domain is a statically identity mapping domain.
250  *      1. This domain creats a static 1:1 mapping to all usable memory.
251  *      2. It maps to each iommu if successful.
252  *      3. Each iommu mapps to this domain if successful.
253  */
254 static struct dmar_domain *si_domain;
255 static int hw_pass_through = 1;
256
257 /* devices under the same p2p bridge are owned in one domain */
258 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
259
260 /* domain represents a virtual machine, more than one devices
261  * across iommus may be owned in one domain, e.g. kvm guest.
262  */
263 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
264
265 /* si_domain contains mulitple devices */
266 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
267
268 struct dmar_domain {
269         int     id;                     /* domain id */
270         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
271
272         struct list_head devices;       /* all devices' list */
273         struct iova_domain iovad;       /* iova's that belong to this domain */
274
275         struct dma_pte  *pgd;           /* virtual address */
276         int             gaw;            /* max guest address width */
277
278         /* adjusted guest address width, 0 is level 2 30-bit */
279         int             agaw;
280
281         int             flags;          /* flags to find out type of domain */
282
283         int             iommu_coherency;/* indicate coherency of iommu access */
284         int             iommu_snooping; /* indicate snooping control feature*/
285         int             iommu_count;    /* reference count of iommu */
286         spinlock_t      iommu_lock;     /* protect iommu set in domain */
287         u64             max_addr;       /* maximum mapped address */
288 };
289
290 /* PCI domain-device relationship */
291 struct device_domain_info {
292         struct list_head link;  /* link to domain siblings */
293         struct list_head global; /* link to global list */
294         int segment;            /* PCI domain */
295         u8 bus;                 /* PCI bus number */
296         u8 devfn;               /* PCI devfn number */
297         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
298         struct intel_iommu *iommu; /* IOMMU used by this device */
299         struct dmar_domain *domain; /* pointer to domain */
300 };
301
302 static void flush_unmaps_timeout(unsigned long data);
303
304 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
305
306 #define HIGH_WATER_MARK 250
307 struct deferred_flush_tables {
308         int next;
309         struct iova *iova[HIGH_WATER_MARK];
310         struct dmar_domain *domain[HIGH_WATER_MARK];
311 };
312
313 static struct deferred_flush_tables *deferred_flush;
314
315 /* bitmap for indexing intel_iommus */
316 static int g_num_of_iommus;
317
318 static DEFINE_SPINLOCK(async_umap_flush_lock);
319 static LIST_HEAD(unmaps_to_do);
320
321 static int timer_on;
322 static long list_size;
323
324 static void domain_remove_dev_info(struct dmar_domain *domain);
325
326 #ifdef CONFIG_DMAR_DEFAULT_ON
327 int dmar_disabled = 0;
328 #else
329 int dmar_disabled = 1;
330 #endif /*CONFIG_DMAR_DEFAULT_ON*/
331
332 static int __initdata dmar_map_gfx = 1;
333 static int dmar_forcedac;
334 static int intel_iommu_strict;
335
336 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
337 static DEFINE_SPINLOCK(device_domain_lock);
338 static LIST_HEAD(device_domain_list);
339
340 static struct iommu_ops intel_iommu_ops;
341
342 static int __init intel_iommu_setup(char *str)
343 {
344         if (!str)
345                 return -EINVAL;
346         while (*str) {
347                 if (!strncmp(str, "on", 2)) {
348                         dmar_disabled = 0;
349                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
350                 } else if (!strncmp(str, "off", 3)) {
351                         dmar_disabled = 1;
352                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
353                 } else if (!strncmp(str, "igfx_off", 8)) {
354                         dmar_map_gfx = 0;
355                         printk(KERN_INFO
356                                 "Intel-IOMMU: disable GFX device mapping\n");
357                 } else if (!strncmp(str, "forcedac", 8)) {
358                         printk(KERN_INFO
359                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
360                         dmar_forcedac = 1;
361                 } else if (!strncmp(str, "strict", 6)) {
362                         printk(KERN_INFO
363                                 "Intel-IOMMU: disable batched IOTLB flush\n");
364                         intel_iommu_strict = 1;
365                 }
366
367                 str += strcspn(str, ",");
368                 while (*str == ',')
369                         str++;
370         }
371         return 0;
372 }
373 __setup("intel_iommu=", intel_iommu_setup);
374
375 static struct kmem_cache *iommu_domain_cache;
376 static struct kmem_cache *iommu_devinfo_cache;
377 static struct kmem_cache *iommu_iova_cache;
378
379 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
380 {
381         unsigned int flags;
382         void *vaddr;
383
384         /* trying to avoid low memory issues */
385         flags = current->flags & PF_MEMALLOC;
386         current->flags |= PF_MEMALLOC;
387         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
388         current->flags &= (~PF_MEMALLOC | flags);
389         return vaddr;
390 }
391
392
393 static inline void *alloc_pgtable_page(void)
394 {
395         unsigned int flags;
396         void *vaddr;
397
398         /* trying to avoid low memory issues */
399         flags = current->flags & PF_MEMALLOC;
400         current->flags |= PF_MEMALLOC;
401         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
402         current->flags &= (~PF_MEMALLOC | flags);
403         return vaddr;
404 }
405
406 static inline void free_pgtable_page(void *vaddr)
407 {
408         free_page((unsigned long)vaddr);
409 }
410
411 static inline void *alloc_domain_mem(void)
412 {
413         return iommu_kmem_cache_alloc(iommu_domain_cache);
414 }
415
416 static void free_domain_mem(void *vaddr)
417 {
418         kmem_cache_free(iommu_domain_cache, vaddr);
419 }
420
421 static inline void * alloc_devinfo_mem(void)
422 {
423         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
424 }
425
426 static inline void free_devinfo_mem(void *vaddr)
427 {
428         kmem_cache_free(iommu_devinfo_cache, vaddr);
429 }
430
431 struct iova *alloc_iova_mem(void)
432 {
433         return iommu_kmem_cache_alloc(iommu_iova_cache);
434 }
435
436 void free_iova_mem(struct iova *iova)
437 {
438         kmem_cache_free(iommu_iova_cache, iova);
439 }
440
441
442 static inline int width_to_agaw(int width);
443
444 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
445 {
446         unsigned long sagaw;
447         int agaw = -1;
448
449         sagaw = cap_sagaw(iommu->cap);
450         for (agaw = width_to_agaw(max_gaw);
451              agaw >= 0; agaw--) {
452                 if (test_bit(agaw, &sagaw))
453                         break;
454         }
455
456         return agaw;
457 }
458
459 /*
460  * Calculate max SAGAW for each iommu.
461  */
462 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
463 {
464         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
465 }
466
467 /*
468  * calculate agaw for each iommu.
469  * "SAGAW" may be different across iommus, use a default agaw, and
470  * get a supported less agaw for iommus that don't support the default agaw.
471  */
472 int iommu_calculate_agaw(struct intel_iommu *iommu)
473 {
474         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
475 }
476
477 /* This functionin only returns single iommu in a domain */
478 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
479 {
480         int iommu_id;
481
482         /* si_domain and vm domain should not get here. */
483         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
484         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
485
486         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
487         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
488                 return NULL;
489
490         return g_iommus[iommu_id];
491 }
492
493 static void domain_update_iommu_coherency(struct dmar_domain *domain)
494 {
495         int i;
496
497         domain->iommu_coherency = 1;
498
499         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
500         for (; i < g_num_of_iommus; ) {
501                 if (!ecap_coherent(g_iommus[i]->ecap)) {
502                         domain->iommu_coherency = 0;
503                         break;
504                 }
505                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
506         }
507 }
508
509 static void domain_update_iommu_snooping(struct dmar_domain *domain)
510 {
511         int i;
512
513         domain->iommu_snooping = 1;
514
515         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
516         for (; i < g_num_of_iommus; ) {
517                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
518                         domain->iommu_snooping = 0;
519                         break;
520                 }
521                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
522         }
523 }
524
525 /* Some capabilities may be different across iommus */
526 static void domain_update_iommu_cap(struct dmar_domain *domain)
527 {
528         domain_update_iommu_coherency(domain);
529         domain_update_iommu_snooping(domain);
530 }
531
532 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
533 {
534         struct dmar_drhd_unit *drhd = NULL;
535         int i;
536
537         for_each_drhd_unit(drhd) {
538                 if (drhd->ignored)
539                         continue;
540                 if (segment != drhd->segment)
541                         continue;
542
543                 for (i = 0; i < drhd->devices_cnt; i++) {
544                         if (drhd->devices[i] &&
545                             drhd->devices[i]->bus->number == bus &&
546                             drhd->devices[i]->devfn == devfn)
547                                 return drhd->iommu;
548                         if (drhd->devices[i] &&
549                             drhd->devices[i]->subordinate &&
550                             drhd->devices[i]->subordinate->number <= bus &&
551                             drhd->devices[i]->subordinate->subordinate >= bus)
552                                 return drhd->iommu;
553                 }
554
555                 if (drhd->include_all)
556                         return drhd->iommu;
557         }
558
559         return NULL;
560 }
561
562 static void domain_flush_cache(struct dmar_domain *domain,
563                                void *addr, int size)
564 {
565         if (!domain->iommu_coherency)
566                 clflush_cache_range(addr, size);
567 }
568
569 /* Gets context entry for a given bus and devfn */
570 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
571                 u8 bus, u8 devfn)
572 {
573         struct root_entry *root;
574         struct context_entry *context;
575         unsigned long phy_addr;
576         unsigned long flags;
577
578         spin_lock_irqsave(&iommu->lock, flags);
579         root = &iommu->root_entry[bus];
580         context = get_context_addr_from_root(root);
581         if (!context) {
582                 context = (struct context_entry *)alloc_pgtable_page();
583                 if (!context) {
584                         spin_unlock_irqrestore(&iommu->lock, flags);
585                         return NULL;
586                 }
587                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
588                 phy_addr = virt_to_phys((void *)context);
589                 set_root_value(root, phy_addr);
590                 set_root_present(root);
591                 __iommu_flush_cache(iommu, root, sizeof(*root));
592         }
593         spin_unlock_irqrestore(&iommu->lock, flags);
594         return &context[devfn];
595 }
596
597 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
598 {
599         struct root_entry *root;
600         struct context_entry *context;
601         int ret;
602         unsigned long flags;
603
604         spin_lock_irqsave(&iommu->lock, flags);
605         root = &iommu->root_entry[bus];
606         context = get_context_addr_from_root(root);
607         if (!context) {
608                 ret = 0;
609                 goto out;
610         }
611         ret = context_present(&context[devfn]);
612 out:
613         spin_unlock_irqrestore(&iommu->lock, flags);
614         return ret;
615 }
616
617 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
618 {
619         struct root_entry *root;
620         struct context_entry *context;
621         unsigned long flags;
622
623         spin_lock_irqsave(&iommu->lock, flags);
624         root = &iommu->root_entry[bus];
625         context = get_context_addr_from_root(root);
626         if (context) {
627                 context_clear_entry(&context[devfn]);
628                 __iommu_flush_cache(iommu, &context[devfn], \
629                         sizeof(*context));
630         }
631         spin_unlock_irqrestore(&iommu->lock, flags);
632 }
633
634 static void free_context_table(struct intel_iommu *iommu)
635 {
636         struct root_entry *root;
637         int i;
638         unsigned long flags;
639         struct context_entry *context;
640
641         spin_lock_irqsave(&iommu->lock, flags);
642         if (!iommu->root_entry) {
643                 goto out;
644         }
645         for (i = 0; i < ROOT_ENTRY_NR; i++) {
646                 root = &iommu->root_entry[i];
647                 context = get_context_addr_from_root(root);
648                 if (context)
649                         free_pgtable_page(context);
650         }
651         free_pgtable_page(iommu->root_entry);
652         iommu->root_entry = NULL;
653 out:
654         spin_unlock_irqrestore(&iommu->lock, flags);
655 }
656
657 /* page table handling */
658 #define LEVEL_STRIDE            (9)
659 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
660
661 static inline int agaw_to_level(int agaw)
662 {
663         return agaw + 2;
664 }
665
666 static inline int agaw_to_width(int agaw)
667 {
668         return 30 + agaw * LEVEL_STRIDE;
669
670 }
671
672 static inline int width_to_agaw(int width)
673 {
674         return (width - 30) / LEVEL_STRIDE;
675 }
676
677 static inline unsigned int level_to_offset_bits(int level)
678 {
679         return (level - 1) * LEVEL_STRIDE;
680 }
681
682 static inline int pfn_level_offset(unsigned long pfn, int level)
683 {
684         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
685 }
686
687 static inline unsigned long level_mask(int level)
688 {
689         return -1UL << level_to_offset_bits(level);
690 }
691
692 static inline unsigned long level_size(int level)
693 {
694         return 1UL << level_to_offset_bits(level);
695 }
696
697 static inline unsigned long align_to_level(unsigned long pfn, int level)
698 {
699         return (pfn + level_size(level) - 1) & level_mask(level);
700 }
701
702 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
703                                       unsigned long pfn)
704 {
705         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
706         struct dma_pte *parent, *pte = NULL;
707         int level = agaw_to_level(domain->agaw);
708         int offset;
709
710         BUG_ON(!domain->pgd);
711         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
712         parent = domain->pgd;
713
714         while (level > 0) {
715                 void *tmp_page;
716
717                 offset = pfn_level_offset(pfn, level);
718                 pte = &parent[offset];
719                 if (level == 1)
720                         break;
721
722                 if (!dma_pte_present(pte)) {
723                         uint64_t pteval;
724
725                         tmp_page = alloc_pgtable_page();
726
727                         if (!tmp_page)
728                                 return NULL;
729
730                         domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
731                         pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
732                         if (cmpxchg64(&pte->val, 0ULL, pteval)) {
733                                 /* Someone else set it while we were thinking; use theirs. */
734                                 free_pgtable_page(tmp_page);
735                         } else {
736                                 dma_pte_addr(pte);
737                                 domain_flush_cache(domain, pte, sizeof(*pte));
738                         }
739                 }
740                 parent = phys_to_virt(dma_pte_addr(pte));
741                 level--;
742         }
743
744         return pte;
745 }
746
747 /* return address's pte at specific level */
748 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
749                                          unsigned long pfn,
750                                          int level)
751 {
752         struct dma_pte *parent, *pte = NULL;
753         int total = agaw_to_level(domain->agaw);
754         int offset;
755
756         parent = domain->pgd;
757         while (level <= total) {
758                 offset = pfn_level_offset(pfn, total);
759                 pte = &parent[offset];
760                 if (level == total)
761                         return pte;
762
763                 if (!dma_pte_present(pte))
764                         break;
765                 parent = phys_to_virt(dma_pte_addr(pte));
766                 total--;
767         }
768         return NULL;
769 }
770
771 /* clear last level pte, a tlb flush should be followed */
772 static void dma_pte_clear_range(struct dmar_domain *domain,
773                                 unsigned long start_pfn,
774                                 unsigned long last_pfn)
775 {
776         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
777         struct dma_pte *first_pte, *pte;
778
779         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
780         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
781
782         /* we don't need lock here; nobody else touches the iova range */
783         while (start_pfn <= last_pfn) {
784                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
785                 if (!pte) {
786                         start_pfn = align_to_level(start_pfn + 1, 2);
787                         continue;
788                 }
789                 do { 
790                         dma_clear_pte(pte);
791                         start_pfn++;
792                         pte++;
793                 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
794
795                 domain_flush_cache(domain, first_pte,
796                                    (void *)pte - (void *)first_pte);
797         }
798 }
799
800 /* free page table pages. last level pte should already be cleared */
801 static void dma_pte_free_pagetable(struct dmar_domain *domain,
802                                    unsigned long start_pfn,
803                                    unsigned long last_pfn)
804 {
805         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
806         struct dma_pte *first_pte, *pte;
807         int total = agaw_to_level(domain->agaw);
808         int level;
809         unsigned long tmp;
810
811         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
812         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
813
814         /* We don't need lock here; nobody else touches the iova range */
815         level = 2;
816         while (level <= total) {
817                 tmp = align_to_level(start_pfn, level);
818
819                 /* If we can't even clear one PTE at this level, we're done */
820                 if (tmp + level_size(level) - 1 > last_pfn)
821                         return;
822
823                 while (tmp + level_size(level) - 1 <= last_pfn) {
824                         first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
825                         if (!pte) {
826                                 tmp = align_to_level(tmp + 1, level + 1);
827                                 continue;
828                         }
829                         do {
830                                 if (dma_pte_present(pte)) {
831                                         free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
832                                         dma_clear_pte(pte);
833                                 }
834                                 pte++;
835                                 tmp += level_size(level);
836                         } while (!first_pte_in_page(pte) &&
837                                  tmp + level_size(level) - 1 <= last_pfn);
838
839                         domain_flush_cache(domain, first_pte,
840                                            (void *)pte - (void *)first_pte);
841                         
842                 }
843                 level++;
844         }
845         /* free pgd */
846         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
847                 free_pgtable_page(domain->pgd);
848                 domain->pgd = NULL;
849         }
850 }
851
852 /* iommu handling */
853 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
854 {
855         struct root_entry *root;
856         unsigned long flags;
857
858         root = (struct root_entry *)alloc_pgtable_page();
859         if (!root)
860                 return -ENOMEM;
861
862         __iommu_flush_cache(iommu, root, ROOT_SIZE);
863
864         spin_lock_irqsave(&iommu->lock, flags);
865         iommu->root_entry = root;
866         spin_unlock_irqrestore(&iommu->lock, flags);
867
868         return 0;
869 }
870
871 static void iommu_set_root_entry(struct intel_iommu *iommu)
872 {
873         void *addr;
874         u32 sts;
875         unsigned long flag;
876
877         addr = iommu->root_entry;
878
879         spin_lock_irqsave(&iommu->register_lock, flag);
880         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
881
882         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
883
884         /* Make sure hardware complete it */
885         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
886                       readl, (sts & DMA_GSTS_RTPS), sts);
887
888         spin_unlock_irqrestore(&iommu->register_lock, flag);
889 }
890
891 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
892 {
893         u32 val;
894         unsigned long flag;
895
896         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
897                 return;
898
899         spin_lock_irqsave(&iommu->register_lock, flag);
900         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
901
902         /* Make sure hardware complete it */
903         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
904                       readl, (!(val & DMA_GSTS_WBFS)), val);
905
906         spin_unlock_irqrestore(&iommu->register_lock, flag);
907 }
908
909 /* return value determine if we need a write buffer flush */
910 static void __iommu_flush_context(struct intel_iommu *iommu,
911                                   u16 did, u16 source_id, u8 function_mask,
912                                   u64 type)
913 {
914         u64 val = 0;
915         unsigned long flag;
916
917         switch (type) {
918         case DMA_CCMD_GLOBAL_INVL:
919                 val = DMA_CCMD_GLOBAL_INVL;
920                 break;
921         case DMA_CCMD_DOMAIN_INVL:
922                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
923                 break;
924         case DMA_CCMD_DEVICE_INVL:
925                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
926                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
927                 break;
928         default:
929                 BUG();
930         }
931         val |= DMA_CCMD_ICC;
932
933         spin_lock_irqsave(&iommu->register_lock, flag);
934         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
935
936         /* Make sure hardware complete it */
937         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
938                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
939
940         spin_unlock_irqrestore(&iommu->register_lock, flag);
941 }
942
943 /* return value determine if we need a write buffer flush */
944 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
945                                 u64 addr, unsigned int size_order, u64 type)
946 {
947         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
948         u64 val = 0, val_iva = 0;
949         unsigned long flag;
950
951         switch (type) {
952         case DMA_TLB_GLOBAL_FLUSH:
953                 /* global flush doesn't need set IVA_REG */
954                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
955                 break;
956         case DMA_TLB_DSI_FLUSH:
957                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
958                 break;
959         case DMA_TLB_PSI_FLUSH:
960                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
961                 /* Note: always flush non-leaf currently */
962                 val_iva = size_order | addr;
963                 break;
964         default:
965                 BUG();
966         }
967         /* Note: set drain read/write */
968 #if 0
969         /*
970          * This is probably to be super secure.. Looks like we can
971          * ignore it without any impact.
972          */
973         if (cap_read_drain(iommu->cap))
974                 val |= DMA_TLB_READ_DRAIN;
975 #endif
976         if (cap_write_drain(iommu->cap))
977                 val |= DMA_TLB_WRITE_DRAIN;
978
979         spin_lock_irqsave(&iommu->register_lock, flag);
980         /* Note: Only uses first TLB reg currently */
981         if (val_iva)
982                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
983         dmar_writeq(iommu->reg + tlb_offset + 8, val);
984
985         /* Make sure hardware complete it */
986         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
987                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
988
989         spin_unlock_irqrestore(&iommu->register_lock, flag);
990
991         /* check IOTLB invalidation granularity */
992         if (DMA_TLB_IAIG(val) == 0)
993                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
994         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
995                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
996                         (unsigned long long)DMA_TLB_IIRG(type),
997                         (unsigned long long)DMA_TLB_IAIG(val));
998 }
999
1000 static struct device_domain_info *iommu_support_dev_iotlb(
1001         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1002 {
1003         int found = 0;
1004         unsigned long flags;
1005         struct device_domain_info *info;
1006         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1007
1008         if (!ecap_dev_iotlb_support(iommu->ecap))
1009                 return NULL;
1010
1011         if (!iommu->qi)
1012                 return NULL;
1013
1014         spin_lock_irqsave(&device_domain_lock, flags);
1015         list_for_each_entry(info, &domain->devices, link)
1016                 if (info->bus == bus && info->devfn == devfn) {
1017                         found = 1;
1018                         break;
1019                 }
1020         spin_unlock_irqrestore(&device_domain_lock, flags);
1021
1022         if (!found || !info->dev)
1023                 return NULL;
1024
1025         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1026                 return NULL;
1027
1028         if (!dmar_find_matched_atsr_unit(info->dev))
1029                 return NULL;
1030
1031         info->iommu = iommu;
1032
1033         return info;
1034 }
1035
1036 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1037 {
1038         if (!info)
1039                 return;
1040
1041         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1042 }
1043
1044 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1045 {
1046         if (!info->dev || !pci_ats_enabled(info->dev))
1047                 return;
1048
1049         pci_disable_ats(info->dev);
1050 }
1051
1052 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1053                                   u64 addr, unsigned mask)
1054 {
1055         u16 sid, qdep;
1056         unsigned long flags;
1057         struct device_domain_info *info;
1058
1059         spin_lock_irqsave(&device_domain_lock, flags);
1060         list_for_each_entry(info, &domain->devices, link) {
1061                 if (!info->dev || !pci_ats_enabled(info->dev))
1062                         continue;
1063
1064                 sid = info->bus << 8 | info->devfn;
1065                 qdep = pci_ats_queue_depth(info->dev);
1066                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1067         }
1068         spin_unlock_irqrestore(&device_domain_lock, flags);
1069 }
1070
1071 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1072                                   unsigned long pfn, unsigned int pages)
1073 {
1074         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1075         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1076
1077         BUG_ON(pages == 0);
1078
1079         /*
1080          * Fallback to domain selective flush if no PSI support or the size is
1081          * too big.
1082          * PSI requires page size to be 2 ^ x, and the base address is naturally
1083          * aligned to the size
1084          */
1085         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1086                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1087                                                 DMA_TLB_DSI_FLUSH);
1088         else
1089                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1090                                                 DMA_TLB_PSI_FLUSH);
1091
1092         /*
1093          * In caching mode, domain ID 0 is reserved for non-present to present
1094          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1095          */
1096         if (!cap_caching_mode(iommu->cap) || did)
1097                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1098 }
1099
1100 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1101 {
1102         u32 pmen;
1103         unsigned long flags;
1104
1105         spin_lock_irqsave(&iommu->register_lock, flags);
1106         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1107         pmen &= ~DMA_PMEN_EPM;
1108         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1109
1110         /* wait for the protected region status bit to clear */
1111         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1112                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1113
1114         spin_unlock_irqrestore(&iommu->register_lock, flags);
1115 }
1116
1117 static int iommu_enable_translation(struct intel_iommu *iommu)
1118 {
1119         u32 sts;
1120         unsigned long flags;
1121
1122         spin_lock_irqsave(&iommu->register_lock, flags);
1123         iommu->gcmd |= DMA_GCMD_TE;
1124         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1125
1126         /* Make sure hardware complete it */
1127         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1128                       readl, (sts & DMA_GSTS_TES), sts);
1129
1130         spin_unlock_irqrestore(&iommu->register_lock, flags);
1131         return 0;
1132 }
1133
1134 static int iommu_disable_translation(struct intel_iommu *iommu)
1135 {
1136         u32 sts;
1137         unsigned long flag;
1138
1139         spin_lock_irqsave(&iommu->register_lock, flag);
1140         iommu->gcmd &= ~DMA_GCMD_TE;
1141         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1142
1143         /* Make sure hardware complete it */
1144         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1145                       readl, (!(sts & DMA_GSTS_TES)), sts);
1146
1147         spin_unlock_irqrestore(&iommu->register_lock, flag);
1148         return 0;
1149 }
1150
1151
1152 static int iommu_init_domains(struct intel_iommu *iommu)
1153 {
1154         unsigned long ndomains;
1155         unsigned long nlongs;
1156
1157         ndomains = cap_ndoms(iommu->cap);
1158         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1159         nlongs = BITS_TO_LONGS(ndomains);
1160
1161         spin_lock_init(&iommu->lock);
1162
1163         /* TBD: there might be 64K domains,
1164          * consider other allocation for future chip
1165          */
1166         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1167         if (!iommu->domain_ids) {
1168                 printk(KERN_ERR "Allocating domain id array failed\n");
1169                 return -ENOMEM;
1170         }
1171         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1172                         GFP_KERNEL);
1173         if (!iommu->domains) {
1174                 printk(KERN_ERR "Allocating domain array failed\n");
1175                 return -ENOMEM;
1176         }
1177
1178         /*
1179          * if Caching mode is set, then invalid translations are tagged
1180          * with domainid 0. Hence we need to pre-allocate it.
1181          */
1182         if (cap_caching_mode(iommu->cap))
1183                 set_bit(0, iommu->domain_ids);
1184         return 0;
1185 }
1186
1187
1188 static void domain_exit(struct dmar_domain *domain);
1189 static void vm_domain_exit(struct dmar_domain *domain);
1190
1191 void free_dmar_iommu(struct intel_iommu *iommu)
1192 {
1193         struct dmar_domain *domain;
1194         int i;
1195         unsigned long flags;
1196
1197         if ((iommu->domains) && (iommu->domain_ids)) {
1198                 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1199                 for (; i < cap_ndoms(iommu->cap); ) {
1200                         domain = iommu->domains[i];
1201                         clear_bit(i, iommu->domain_ids);
1202
1203                         spin_lock_irqsave(&domain->iommu_lock, flags);
1204                         if (--domain->iommu_count == 0) {
1205                                 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1206                                         vm_domain_exit(domain);
1207                                 else
1208                                         domain_exit(domain);
1209                         }
1210                         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1211
1212                         i = find_next_bit(iommu->domain_ids,
1213                                 cap_ndoms(iommu->cap), i+1);
1214                 }
1215         }
1216
1217         if (iommu->gcmd & DMA_GCMD_TE)
1218                 iommu_disable_translation(iommu);
1219
1220         if (iommu->irq) {
1221                 set_irq_data(iommu->irq, NULL);
1222                 /* This will mask the irq */
1223                 free_irq(iommu->irq, iommu);
1224                 destroy_irq(iommu->irq);
1225         }
1226
1227         kfree(iommu->domains);
1228         kfree(iommu->domain_ids);
1229
1230         g_iommus[iommu->seq_id] = NULL;
1231
1232         /* if all iommus are freed, free g_iommus */
1233         for (i = 0; i < g_num_of_iommus; i++) {
1234                 if (g_iommus[i])
1235                         break;
1236         }
1237
1238         if (i == g_num_of_iommus)
1239                 kfree(g_iommus);
1240
1241         /* free context mapping */
1242         free_context_table(iommu);
1243 }
1244
1245 static struct dmar_domain *alloc_domain(void)
1246 {
1247         struct dmar_domain *domain;
1248
1249         domain = alloc_domain_mem();
1250         if (!domain)
1251                 return NULL;
1252
1253         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1254         domain->flags = 0;
1255
1256         return domain;
1257 }
1258
1259 static int iommu_attach_domain(struct dmar_domain *domain,
1260                                struct intel_iommu *iommu)
1261 {
1262         int num;
1263         unsigned long ndomains;
1264         unsigned long flags;
1265
1266         ndomains = cap_ndoms(iommu->cap);
1267
1268         spin_lock_irqsave(&iommu->lock, flags);
1269
1270         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1271         if (num >= ndomains) {
1272                 spin_unlock_irqrestore(&iommu->lock, flags);
1273                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1274                 return -ENOMEM;
1275         }
1276
1277         domain->id = num;
1278         set_bit(num, iommu->domain_ids);
1279         set_bit(iommu->seq_id, &domain->iommu_bmp);
1280         iommu->domains[num] = domain;
1281         spin_unlock_irqrestore(&iommu->lock, flags);
1282
1283         return 0;
1284 }
1285
1286 static void iommu_detach_domain(struct dmar_domain *domain,
1287                                 struct intel_iommu *iommu)
1288 {
1289         unsigned long flags;
1290         int num, ndomains;
1291         int found = 0;
1292
1293         spin_lock_irqsave(&iommu->lock, flags);
1294         ndomains = cap_ndoms(iommu->cap);
1295         num = find_first_bit(iommu->domain_ids, ndomains);
1296         for (; num < ndomains; ) {
1297                 if (iommu->domains[num] == domain) {
1298                         found = 1;
1299                         break;
1300                 }
1301                 num = find_next_bit(iommu->domain_ids,
1302                                     cap_ndoms(iommu->cap), num+1);
1303         }
1304
1305         if (found) {
1306                 clear_bit(num, iommu->domain_ids);
1307                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1308                 iommu->domains[num] = NULL;
1309         }
1310         spin_unlock_irqrestore(&iommu->lock, flags);
1311 }
1312
1313 static struct iova_domain reserved_iova_list;
1314 static struct lock_class_key reserved_rbtree_key;
1315
1316 static void dmar_init_reserved_ranges(void)
1317 {
1318         struct pci_dev *pdev = NULL;
1319         struct iova *iova;
1320         int i;
1321
1322         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1323
1324         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1325                 &reserved_rbtree_key);
1326
1327         /* IOAPIC ranges shouldn't be accessed by DMA */
1328         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1329                 IOVA_PFN(IOAPIC_RANGE_END));
1330         if (!iova)
1331                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1332
1333         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1334         for_each_pci_dev(pdev) {
1335                 struct resource *r;
1336
1337                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1338                         r = &pdev->resource[i];
1339                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1340                                 continue;
1341                         iova = reserve_iova(&reserved_iova_list,
1342                                             IOVA_PFN(r->start),
1343                                             IOVA_PFN(r->end));
1344                         if (!iova)
1345                                 printk(KERN_ERR "Reserve iova failed\n");
1346                 }
1347         }
1348
1349 }
1350
1351 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1352 {
1353         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1354 }
1355
1356 static inline int guestwidth_to_adjustwidth(int gaw)
1357 {
1358         int agaw;
1359         int r = (gaw - 12) % 9;
1360
1361         if (r == 0)
1362                 agaw = gaw;
1363         else
1364                 agaw = gaw + 9 - r;
1365         if (agaw > 64)
1366                 agaw = 64;
1367         return agaw;
1368 }
1369
1370 static int domain_init(struct dmar_domain *domain, int guest_width)
1371 {
1372         struct intel_iommu *iommu;
1373         int adjust_width, agaw;
1374         unsigned long sagaw;
1375
1376         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1377         spin_lock_init(&domain->iommu_lock);
1378
1379         domain_reserve_special_ranges(domain);
1380
1381         /* calculate AGAW */
1382         iommu = domain_get_iommu(domain);
1383         if (guest_width > cap_mgaw(iommu->cap))
1384                 guest_width = cap_mgaw(iommu->cap);
1385         domain->gaw = guest_width;
1386         adjust_width = guestwidth_to_adjustwidth(guest_width);
1387         agaw = width_to_agaw(adjust_width);
1388         sagaw = cap_sagaw(iommu->cap);
1389         if (!test_bit(agaw, &sagaw)) {
1390                 /* hardware doesn't support it, choose a bigger one */
1391                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1392                 agaw = find_next_bit(&sagaw, 5, agaw);
1393                 if (agaw >= 5)
1394                         return -ENODEV;
1395         }
1396         domain->agaw = agaw;
1397         INIT_LIST_HEAD(&domain->devices);
1398
1399         if (ecap_coherent(iommu->ecap))
1400                 domain->iommu_coherency = 1;
1401         else
1402                 domain->iommu_coherency = 0;
1403
1404         if (ecap_sc_support(iommu->ecap))
1405                 domain->iommu_snooping = 1;
1406         else
1407                 domain->iommu_snooping = 0;
1408
1409         domain->iommu_count = 1;
1410
1411         /* always allocate the top pgd */
1412         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1413         if (!domain->pgd)
1414                 return -ENOMEM;
1415         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1416         return 0;
1417 }
1418
1419 static void domain_exit(struct dmar_domain *domain)
1420 {
1421         struct dmar_drhd_unit *drhd;
1422         struct intel_iommu *iommu;
1423
1424         /* Domain 0 is reserved, so dont process it */
1425         if (!domain)
1426                 return;
1427
1428         domain_remove_dev_info(domain);
1429         /* destroy iovas */
1430         put_iova_domain(&domain->iovad);
1431
1432         /* clear ptes */
1433         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1434
1435         /* free page tables */
1436         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1437
1438         for_each_active_iommu(iommu, drhd)
1439                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1440                         iommu_detach_domain(domain, iommu);
1441
1442         free_domain_mem(domain);
1443 }
1444
1445 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1446                                  u8 bus, u8 devfn, int translation)
1447 {
1448         struct context_entry *context;
1449         unsigned long flags;
1450         struct intel_iommu *iommu;
1451         struct dma_pte *pgd;
1452         unsigned long num;
1453         unsigned long ndomains;
1454         int id;
1455         int agaw;
1456         struct device_domain_info *info = NULL;
1457
1458         pr_debug("Set context mapping for %02x:%02x.%d\n",
1459                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1460
1461         BUG_ON(!domain->pgd);
1462         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1463                translation != CONTEXT_TT_MULTI_LEVEL);
1464
1465         iommu = device_to_iommu(segment, bus, devfn);
1466         if (!iommu)
1467                 return -ENODEV;
1468
1469         context = device_to_context_entry(iommu, bus, devfn);
1470         if (!context)
1471                 return -ENOMEM;
1472         spin_lock_irqsave(&iommu->lock, flags);
1473         if (context_present(context)) {
1474                 spin_unlock_irqrestore(&iommu->lock, flags);
1475                 return 0;
1476         }
1477
1478         id = domain->id;
1479         pgd = domain->pgd;
1480
1481         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1482             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1483                 int found = 0;
1484
1485                 /* find an available domain id for this device in iommu */
1486                 ndomains = cap_ndoms(iommu->cap);
1487                 num = find_first_bit(iommu->domain_ids, ndomains);
1488                 for (; num < ndomains; ) {
1489                         if (iommu->domains[num] == domain) {
1490                                 id = num;
1491                                 found = 1;
1492                                 break;
1493                         }
1494                         num = find_next_bit(iommu->domain_ids,
1495                                             cap_ndoms(iommu->cap), num+1);
1496                 }
1497
1498                 if (found == 0) {
1499                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1500                         if (num >= ndomains) {
1501                                 spin_unlock_irqrestore(&iommu->lock, flags);
1502                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1503                                 return -EFAULT;
1504                         }
1505
1506                         set_bit(num, iommu->domain_ids);
1507                         iommu->domains[num] = domain;
1508                         id = num;
1509                 }
1510
1511                 /* Skip top levels of page tables for
1512                  * iommu which has less agaw than default.
1513                  */
1514                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1515                         pgd = phys_to_virt(dma_pte_addr(pgd));
1516                         if (!dma_pte_present(pgd)) {
1517                                 spin_unlock_irqrestore(&iommu->lock, flags);
1518                                 return -ENOMEM;
1519                         }
1520                 }
1521         }
1522
1523         context_set_domain_id(context, id);
1524
1525         if (translation != CONTEXT_TT_PASS_THROUGH) {
1526                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1527                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1528                                      CONTEXT_TT_MULTI_LEVEL;
1529         }
1530         /*
1531          * In pass through mode, AW must be programmed to indicate the largest
1532          * AGAW value supported by hardware. And ASR is ignored by hardware.
1533          */
1534         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1535                 context_set_address_width(context, iommu->msagaw);
1536         else {
1537                 context_set_address_root(context, virt_to_phys(pgd));
1538                 context_set_address_width(context, iommu->agaw);
1539         }
1540
1541         context_set_translation_type(context, translation);
1542         context_set_fault_enable(context);
1543         context_set_present(context);
1544         domain_flush_cache(domain, context, sizeof(*context));
1545
1546         /*
1547          * It's a non-present to present mapping. If hardware doesn't cache
1548          * non-present entry we only need to flush the write-buffer. If the
1549          * _does_ cache non-present entries, then it does so in the special
1550          * domain #0, which we have to flush:
1551          */
1552         if (cap_caching_mode(iommu->cap)) {
1553                 iommu->flush.flush_context(iommu, 0,
1554                                            (((u16)bus) << 8) | devfn,
1555                                            DMA_CCMD_MASK_NOBIT,
1556                                            DMA_CCMD_DEVICE_INVL);
1557                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1558         } else {
1559                 iommu_flush_write_buffer(iommu);
1560         }
1561         iommu_enable_dev_iotlb(info);
1562         spin_unlock_irqrestore(&iommu->lock, flags);
1563
1564         spin_lock_irqsave(&domain->iommu_lock, flags);
1565         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1566                 domain->iommu_count++;
1567                 domain_update_iommu_cap(domain);
1568         }
1569         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1570         return 0;
1571 }
1572
1573 static int
1574 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1575                         int translation)
1576 {
1577         int ret;
1578         struct pci_dev *tmp, *parent;
1579
1580         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1581                                          pdev->bus->number, pdev->devfn,
1582                                          translation);
1583         if (ret)
1584                 return ret;
1585
1586         /* dependent device mapping */
1587         tmp = pci_find_upstream_pcie_bridge(pdev);
1588         if (!tmp)
1589                 return 0;
1590         /* Secondary interface's bus number and devfn 0 */
1591         parent = pdev->bus->self;
1592         while (parent != tmp) {
1593                 ret = domain_context_mapping_one(domain,
1594                                                  pci_domain_nr(parent->bus),
1595                                                  parent->bus->number,
1596                                                  parent->devfn, translation);
1597                 if (ret)
1598                         return ret;
1599                 parent = parent->bus->self;
1600         }
1601         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1602                 return domain_context_mapping_one(domain,
1603                                         pci_domain_nr(tmp->subordinate),
1604                                         tmp->subordinate->number, 0,
1605                                         translation);
1606         else /* this is a legacy PCI bridge */
1607                 return domain_context_mapping_one(domain,
1608                                                   pci_domain_nr(tmp->bus),
1609                                                   tmp->bus->number,
1610                                                   tmp->devfn,
1611                                                   translation);
1612 }
1613
1614 static int domain_context_mapped(struct pci_dev *pdev)
1615 {
1616         int ret;
1617         struct pci_dev *tmp, *parent;
1618         struct intel_iommu *iommu;
1619
1620         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1621                                 pdev->devfn);
1622         if (!iommu)
1623                 return -ENODEV;
1624
1625         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1626         if (!ret)
1627                 return ret;
1628         /* dependent device mapping */
1629         tmp = pci_find_upstream_pcie_bridge(pdev);
1630         if (!tmp)
1631                 return ret;
1632         /* Secondary interface's bus number and devfn 0 */
1633         parent = pdev->bus->self;
1634         while (parent != tmp) {
1635                 ret = device_context_mapped(iommu, parent->bus->number,
1636                                             parent->devfn);
1637                 if (!ret)
1638                         return ret;
1639                 parent = parent->bus->self;
1640         }
1641         if (tmp->is_pcie)
1642                 return device_context_mapped(iommu, tmp->subordinate->number,
1643                                              0);
1644         else
1645                 return device_context_mapped(iommu, tmp->bus->number,
1646                                              tmp->devfn);
1647 }
1648
1649 /* Returns a number of VTD pages, but aligned to MM page size */
1650 static inline unsigned long aligned_nrpages(unsigned long host_addr,
1651                                             size_t size)
1652 {
1653         host_addr &= ~PAGE_MASK;
1654         return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1655 }
1656
1657 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1658                             struct scatterlist *sg, unsigned long phys_pfn,
1659                             unsigned long nr_pages, int prot)
1660 {
1661         struct dma_pte *first_pte = NULL, *pte = NULL;
1662         phys_addr_t uninitialized_var(pteval);
1663         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1664         unsigned long sg_res;
1665
1666         BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1667
1668         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1669                 return -EINVAL;
1670
1671         prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1672
1673         if (sg)
1674                 sg_res = 0;
1675         else {
1676                 sg_res = nr_pages + 1;
1677                 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1678         }
1679
1680         while (nr_pages--) {
1681                 uint64_t tmp;
1682
1683                 if (!sg_res) {
1684                         sg_res = aligned_nrpages(sg->offset, sg->length);
1685                         sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1686                         sg->dma_length = sg->length;
1687                         pteval = page_to_phys(sg_page(sg)) | prot;
1688                 }
1689                 if (!pte) {
1690                         first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1691                         if (!pte)
1692                                 return -ENOMEM;
1693                 }
1694                 /* We don't need lock here, nobody else
1695                  * touches the iova range
1696                  */
1697                 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1698                 if (tmp) {
1699                         static int dumps = 5;
1700                         printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1701                                iov_pfn, tmp, (unsigned long long)pteval);
1702                         if (dumps) {
1703                                 dumps--;
1704                                 debug_dma_dump_mappings(NULL);
1705                         }
1706                         WARN_ON(1);
1707                 }
1708                 pte++;
1709                 if (!nr_pages || first_pte_in_page(pte)) {
1710                         domain_flush_cache(domain, first_pte,
1711                                            (void *)pte - (void *)first_pte);
1712                         pte = NULL;
1713                 }
1714                 iov_pfn++;
1715                 pteval += VTD_PAGE_SIZE;
1716                 sg_res--;
1717                 if (!sg_res)
1718                         sg = sg_next(sg);
1719         }
1720         return 0;
1721 }
1722
1723 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1724                                     struct scatterlist *sg, unsigned long nr_pages,
1725                                     int prot)
1726 {
1727         return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1728 }
1729
1730 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1731                                      unsigned long phys_pfn, unsigned long nr_pages,
1732                                      int prot)
1733 {
1734         return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1735 }
1736
1737 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1738 {
1739         if (!iommu)
1740                 return;
1741
1742         clear_context_table(iommu, bus, devfn);
1743         iommu->flush.flush_context(iommu, 0, 0, 0,
1744                                            DMA_CCMD_GLOBAL_INVL);
1745         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1746 }
1747
1748 static void domain_remove_dev_info(struct dmar_domain *domain)
1749 {
1750         struct device_domain_info *info;
1751         unsigned long flags;
1752         struct intel_iommu *iommu;
1753
1754         spin_lock_irqsave(&device_domain_lock, flags);
1755         while (!list_empty(&domain->devices)) {
1756                 info = list_entry(domain->devices.next,
1757                         struct device_domain_info, link);
1758                 list_del(&info->link);
1759                 list_del(&info->global);
1760                 if (info->dev)
1761                         info->dev->dev.archdata.iommu = NULL;
1762                 spin_unlock_irqrestore(&device_domain_lock, flags);
1763
1764                 iommu_disable_dev_iotlb(info);
1765                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1766                 iommu_detach_dev(iommu, info->bus, info->devfn);
1767                 free_devinfo_mem(info);
1768
1769                 spin_lock_irqsave(&device_domain_lock, flags);
1770         }
1771         spin_unlock_irqrestore(&device_domain_lock, flags);
1772 }
1773
1774 /*
1775  * find_domain
1776  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1777  */
1778 static struct dmar_domain *
1779 find_domain(struct pci_dev *pdev)
1780 {
1781         struct device_domain_info *info;
1782
1783         /* No lock here, assumes no domain exit in normal case */
1784         info = pdev->dev.archdata.iommu;
1785         if (info)
1786                 return info->domain;
1787         return NULL;
1788 }
1789
1790 /* domain is initialized */
1791 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1792 {
1793         struct dmar_domain *domain, *found = NULL;
1794         struct intel_iommu *iommu;
1795         struct dmar_drhd_unit *drhd;
1796         struct device_domain_info *info, *tmp;
1797         struct pci_dev *dev_tmp;
1798         unsigned long flags;
1799         int bus = 0, devfn = 0;
1800         int segment;
1801         int ret;
1802
1803         domain = find_domain(pdev);
1804         if (domain)
1805                 return domain;
1806
1807         segment = pci_domain_nr(pdev->bus);
1808
1809         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1810         if (dev_tmp) {
1811                 if (dev_tmp->is_pcie) {
1812                         bus = dev_tmp->subordinate->number;
1813                         devfn = 0;
1814                 } else {
1815                         bus = dev_tmp->bus->number;
1816                         devfn = dev_tmp->devfn;
1817                 }
1818                 spin_lock_irqsave(&device_domain_lock, flags);
1819                 list_for_each_entry(info, &device_domain_list, global) {
1820                         if (info->segment == segment &&
1821                             info->bus == bus && info->devfn == devfn) {
1822                                 found = info->domain;
1823                                 break;
1824                         }
1825                 }
1826                 spin_unlock_irqrestore(&device_domain_lock, flags);
1827                 /* pcie-pci bridge already has a domain, uses it */
1828                 if (found) {
1829                         domain = found;
1830                         goto found_domain;
1831                 }
1832         }
1833
1834         domain = alloc_domain();
1835         if (!domain)
1836                 goto error;
1837
1838         /* Allocate new domain for the device */
1839         drhd = dmar_find_matched_drhd_unit(pdev);
1840         if (!drhd) {
1841                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1842                         pci_name(pdev));
1843                 return NULL;
1844         }
1845         iommu = drhd->iommu;
1846
1847         ret = iommu_attach_domain(domain, iommu);
1848         if (ret) {
1849                 domain_exit(domain);
1850                 goto error;
1851         }
1852
1853         if (domain_init(domain, gaw)) {
1854                 domain_exit(domain);
1855                 goto error;
1856         }
1857
1858         /* register pcie-to-pci device */
1859         if (dev_tmp) {
1860                 info = alloc_devinfo_mem();
1861                 if (!info) {
1862                         domain_exit(domain);
1863                         goto error;
1864                 }
1865                 info->segment = segment;
1866                 info->bus = bus;
1867                 info->devfn = devfn;
1868                 info->dev = NULL;
1869                 info->domain = domain;
1870                 /* This domain is shared by devices under p2p bridge */
1871                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1872
1873                 /* pcie-to-pci bridge already has a domain, uses it */
1874                 found = NULL;
1875                 spin_lock_irqsave(&device_domain_lock, flags);
1876                 list_for_each_entry(tmp, &device_domain_list, global) {
1877                         if (tmp->segment == segment &&
1878                             tmp->bus == bus && tmp->devfn == devfn) {
1879                                 found = tmp->domain;
1880                                 break;
1881                         }
1882                 }
1883                 if (found) {
1884                         free_devinfo_mem(info);
1885                         domain_exit(domain);
1886                         domain = found;
1887                 } else {
1888                         list_add(&info->link, &domain->devices);
1889                         list_add(&info->global, &device_domain_list);
1890                 }
1891                 spin_unlock_irqrestore(&device_domain_lock, flags);
1892         }
1893
1894 found_domain:
1895         info = alloc_devinfo_mem();
1896         if (!info)
1897                 goto error;
1898         info->segment = segment;
1899         info->bus = pdev->bus->number;
1900         info->devfn = pdev->devfn;
1901         info->dev = pdev;
1902         info->domain = domain;
1903         spin_lock_irqsave(&device_domain_lock, flags);
1904         /* somebody is fast */
1905         found = find_domain(pdev);
1906         if (found != NULL) {
1907                 spin_unlock_irqrestore(&device_domain_lock, flags);
1908                 if (found != domain) {
1909                         domain_exit(domain);
1910                         domain = found;
1911                 }
1912                 free_devinfo_mem(info);
1913                 return domain;
1914         }
1915         list_add(&info->link, &domain->devices);
1916         list_add(&info->global, &device_domain_list);
1917         pdev->dev.archdata.iommu = info;
1918         spin_unlock_irqrestore(&device_domain_lock, flags);
1919         return domain;
1920 error:
1921         /* recheck it here, maybe others set it */
1922         return find_domain(pdev);
1923 }
1924
1925 static int iommu_identity_mapping;
1926
1927 static int iommu_domain_identity_map(struct dmar_domain *domain,
1928                                      unsigned long long start,
1929                                      unsigned long long end)
1930 {
1931         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1932         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1933
1934         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1935                           dma_to_mm_pfn(last_vpfn))) {
1936                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1937                 return -ENOMEM;
1938         }
1939
1940         pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1941                  start, end, domain->id);
1942         /*
1943          * RMRR range might have overlap with physical memory range,
1944          * clear it first
1945          */
1946         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1947
1948         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1949                                   last_vpfn - first_vpfn + 1,
1950                                   DMA_PTE_READ|DMA_PTE_WRITE);
1951 }
1952
1953 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1954                                       unsigned long long start,
1955                                       unsigned long long end)
1956 {
1957         struct dmar_domain *domain;
1958         int ret;
1959
1960         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1961         if (!domain)
1962                 return -ENOMEM;
1963
1964         /* For _hardware_ passthrough, don't bother. But for software
1965            passthrough, we do it anyway -- it may indicate a memory
1966            range which is reserved in E820, so which didn't get set
1967            up to start with in si_domain */
1968         if (domain == si_domain && hw_pass_through) {
1969                 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
1970                        pci_name(pdev), start, end);
1971                 return 0;
1972         }
1973
1974         printk(KERN_INFO
1975                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1976                pci_name(pdev), start, end);
1977         
1978         if (end >> agaw_to_width(domain->agaw)) {
1979                 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
1980                      "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
1981                      agaw_to_width(domain->agaw),
1982                      dmi_get_system_info(DMI_BIOS_VENDOR),
1983                      dmi_get_system_info(DMI_BIOS_VERSION),
1984                      dmi_get_system_info(DMI_PRODUCT_VERSION));
1985                 ret = -EIO;
1986                 goto error;
1987         }
1988
1989         ret = iommu_domain_identity_map(domain, start, end);
1990         if (ret)
1991                 goto error;
1992
1993         /* context entry init */
1994         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1995         if (ret)
1996                 goto error;
1997
1998         return 0;
1999
2000  error:
2001         domain_exit(domain);
2002         return ret;
2003 }
2004
2005 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2006         struct pci_dev *pdev)
2007 {
2008         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2009                 return 0;
2010         return iommu_prepare_identity_map(pdev, rmrr->base_address,
2011                 rmrr->end_address + 1);
2012 }
2013
2014 #ifdef CONFIG_DMAR_FLOPPY_WA
2015 static inline void iommu_prepare_isa(void)
2016 {
2017         struct pci_dev *pdev;
2018         int ret;
2019
2020         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2021         if (!pdev)
2022                 return;
2023
2024         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2025         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2026
2027         if (ret)
2028                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2029                        "floppy might not work\n");
2030
2031 }
2032 #else
2033 static inline void iommu_prepare_isa(void)
2034 {
2035         return;
2036 }
2037 #endif /* !CONFIG_DMAR_FLPY_WA */
2038
2039 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2040
2041 static int __init si_domain_work_fn(unsigned long start_pfn,
2042                                     unsigned long end_pfn, void *datax)
2043 {
2044         int *ret = datax;
2045
2046         *ret = iommu_domain_identity_map(si_domain,
2047                                          (uint64_t)start_pfn << PAGE_SHIFT,
2048                                          (uint64_t)end_pfn << PAGE_SHIFT);
2049         return *ret;
2050
2051 }
2052
2053 static int __init si_domain_init(int hw)
2054 {
2055         struct dmar_drhd_unit *drhd;
2056         struct intel_iommu *iommu;
2057         int nid, ret = 0;
2058
2059         si_domain = alloc_domain();
2060         if (!si_domain)
2061                 return -EFAULT;
2062
2063         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2064
2065         for_each_active_iommu(iommu, drhd) {
2066                 ret = iommu_attach_domain(si_domain, iommu);
2067                 if (ret) {
2068                         domain_exit(si_domain);
2069                         return -EFAULT;
2070                 }
2071         }
2072
2073         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2074                 domain_exit(si_domain);
2075                 return -EFAULT;
2076         }
2077
2078         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2079
2080         if (hw)
2081                 return 0;
2082
2083         for_each_online_node(nid) {
2084                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2085                 if (ret)
2086                         return ret;
2087         }
2088
2089         return 0;
2090 }
2091
2092 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2093                                           struct pci_dev *pdev);
2094 static int identity_mapping(struct pci_dev *pdev)
2095 {
2096         struct device_domain_info *info;
2097
2098         if (likely(!iommu_identity_mapping))
2099                 return 0;
2100
2101
2102         list_for_each_entry(info, &si_domain->devices, link)
2103                 if (info->dev == pdev)
2104                         return 1;
2105         return 0;
2106 }
2107
2108 static int domain_add_dev_info(struct dmar_domain *domain,
2109                                struct pci_dev *pdev,
2110                                int translation)
2111 {
2112         struct device_domain_info *info;
2113         unsigned long flags;
2114         int ret;
2115
2116         info = alloc_devinfo_mem();
2117         if (!info)
2118                 return -ENOMEM;
2119
2120         ret = domain_context_mapping(domain, pdev, translation);
2121         if (ret) {
2122                 free_devinfo_mem(info);
2123                 return ret;
2124         }
2125
2126         info->segment = pci_domain_nr(pdev->bus);
2127         info->bus = pdev->bus->number;
2128         info->devfn = pdev->devfn;
2129         info->dev = pdev;
2130         info->domain = domain;
2131
2132         spin_lock_irqsave(&device_domain_lock, flags);
2133         list_add(&info->link, &domain->devices);
2134         list_add(&info->global, &device_domain_list);
2135         pdev->dev.archdata.iommu = info;
2136         spin_unlock_irqrestore(&device_domain_lock, flags);
2137
2138         return 0;
2139 }
2140
2141 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2142 {
2143         if (iommu_identity_mapping == 2)
2144                 return IS_GFX_DEVICE(pdev);
2145
2146         /*
2147          * We want to start off with all devices in the 1:1 domain, and
2148          * take them out later if we find they can't access all of memory.
2149          *
2150          * However, we can't do this for PCI devices behind bridges,
2151          * because all PCI devices behind the same bridge will end up
2152          * with the same source-id on their transactions.
2153          *
2154          * Practically speaking, we can't change things around for these
2155          * devices at run-time, because we can't be sure there'll be no
2156          * DMA transactions in flight for any of their siblings.
2157          * 
2158          * So PCI devices (unless they're on the root bus) as well as
2159          * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2160          * the 1:1 domain, just in _case_ one of their siblings turns out
2161          * not to be able to map all of memory.
2162          */
2163         if (!pdev->is_pcie) {
2164                 if (!pci_is_root_bus(pdev->bus))
2165                         return 0;
2166                 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2167                         return 0;
2168         } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2169                 return 0;
2170
2171         /* 
2172          * At boot time, we don't yet know if devices will be 64-bit capable.
2173          * Assume that they will -- if they turn out not to be, then we can 
2174          * take them out of the 1:1 domain later.
2175          */
2176         if (!startup)
2177                 return pdev->dma_mask > DMA_BIT_MASK(32);
2178
2179         return 1;
2180 }
2181
2182 static int __init iommu_prepare_static_identity_mapping(int hw)
2183 {
2184         struct pci_dev *pdev = NULL;
2185         int ret;
2186
2187         ret = si_domain_init(hw);
2188         if (ret)
2189                 return -EFAULT;
2190
2191         for_each_pci_dev(pdev) {
2192                 if (iommu_should_identity_map(pdev, 1)) {
2193                         printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2194                                hw ? "hardware" : "software", pci_name(pdev));
2195
2196                         ret = domain_add_dev_info(si_domain, pdev,
2197                                                      hw ? CONTEXT_TT_PASS_THROUGH :
2198                                                      CONTEXT_TT_MULTI_LEVEL);
2199                         if (ret)
2200                                 return ret;
2201                 }
2202         }
2203
2204         return 0;
2205 }
2206
2207 int __init init_dmars(void)
2208 {
2209         struct dmar_drhd_unit *drhd;
2210         struct dmar_rmrr_unit *rmrr;
2211         struct pci_dev *pdev;
2212         struct intel_iommu *iommu;
2213         int i, ret;
2214
2215         /*
2216          * for each drhd
2217          *    allocate root
2218          *    initialize and program root entry to not present
2219          * endfor
2220          */
2221         for_each_drhd_unit(drhd) {
2222                 g_num_of_iommus++;
2223                 /*
2224                  * lock not needed as this is only incremented in the single
2225                  * threaded kernel __init code path all other access are read
2226                  * only
2227                  */
2228         }
2229
2230         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2231                         GFP_KERNEL);
2232         if (!g_iommus) {
2233                 printk(KERN_ERR "Allocating global iommu array failed\n");
2234                 ret = -ENOMEM;
2235                 goto error;
2236         }
2237
2238         deferred_flush = kzalloc(g_num_of_iommus *
2239                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2240         if (!deferred_flush) {
2241                 ret = -ENOMEM;
2242                 goto error;
2243         }
2244
2245         for_each_drhd_unit(drhd) {
2246                 if (drhd->ignored)
2247                         continue;
2248
2249                 iommu = drhd->iommu;
2250                 g_iommus[iommu->seq_id] = iommu;
2251
2252                 ret = iommu_init_domains(iommu);
2253                 if (ret)
2254                         goto error;
2255
2256                 /*
2257                  * TBD:
2258                  * we could share the same root & context tables
2259                  * amoung all IOMMU's. Need to Split it later.
2260                  */
2261                 ret = iommu_alloc_root_entry(iommu);
2262                 if (ret) {
2263                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2264                         goto error;
2265                 }
2266                 if (!ecap_pass_through(iommu->ecap))
2267                         hw_pass_through = 0;
2268         }
2269
2270         /*
2271          * Start from the sane iommu hardware state.
2272          */
2273         for_each_drhd_unit(drhd) {
2274                 if (drhd->ignored)
2275                         continue;
2276
2277                 iommu = drhd->iommu;
2278
2279                 /*
2280                  * If the queued invalidation is already initialized by us
2281                  * (for example, while enabling interrupt-remapping) then
2282                  * we got the things already rolling from a sane state.
2283                  */
2284                 if (iommu->qi)
2285                         continue;
2286
2287                 /*
2288                  * Clear any previous faults.
2289                  */
2290                 dmar_fault(-1, iommu);
2291                 /*
2292                  * Disable queued invalidation if supported and already enabled
2293                  * before OS handover.
2294                  */
2295                 dmar_disable_qi(iommu);
2296         }
2297
2298         for_each_drhd_unit(drhd) {
2299                 if (drhd->ignored)
2300                         continue;
2301
2302                 iommu = drhd->iommu;
2303
2304                 if (dmar_enable_qi(iommu)) {
2305                         /*
2306                          * Queued Invalidate not enabled, use Register Based
2307                          * Invalidate
2308                          */
2309                         iommu->flush.flush_context = __iommu_flush_context;
2310                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2311                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2312                                "invalidation\n",
2313                                (unsigned long long)drhd->reg_base_addr);
2314                 } else {
2315                         iommu->flush.flush_context = qi_flush_context;
2316                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2317                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2318                                "invalidation\n",
2319                                (unsigned long long)drhd->reg_base_addr);
2320                 }
2321         }
2322
2323         if (iommu_pass_through)
2324                 iommu_identity_mapping = 1;
2325 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2326         else
2327                 iommu_identity_mapping = 2;
2328 #endif
2329         /*
2330          * If pass through is not set or not enabled, setup context entries for
2331          * identity mappings for rmrr, gfx, and isa and may fall back to static
2332          * identity mapping if iommu_identity_mapping is set.
2333          */
2334         if (iommu_identity_mapping) {
2335                 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
2336                 if (ret) {
2337                         printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2338                         goto error;
2339                 }
2340         }
2341         /*
2342          * For each rmrr
2343          *   for each dev attached to rmrr
2344          *   do
2345          *     locate drhd for dev, alloc domain for dev
2346          *     allocate free domain
2347          *     allocate page table entries for rmrr
2348          *     if context not allocated for bus
2349          *           allocate and init context
2350          *           set present in root table for this bus
2351          *     init context with domain, translation etc
2352          *    endfor
2353          * endfor
2354          */
2355         printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2356         for_each_rmrr_units(rmrr) {
2357                 for (i = 0; i < rmrr->devices_cnt; i++) {
2358                         pdev = rmrr->devices[i];
2359                         /*
2360                          * some BIOS lists non-exist devices in DMAR
2361                          * table.
2362                          */
2363                         if (!pdev)
2364                                 continue;
2365                         ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2366                         if (ret)
2367                                 printk(KERN_ERR
2368                                        "IOMMU: mapping reserved region failed\n");
2369                 }
2370         }
2371
2372         iommu_prepare_isa();
2373
2374         /*
2375          * for each drhd
2376          *   enable fault log
2377          *   global invalidate context cache
2378          *   global invalidate iotlb
2379          *   enable translation
2380          */
2381         for_each_drhd_unit(drhd) {
2382                 if (drhd->ignored)
2383                         continue;
2384                 iommu = drhd->iommu;
2385
2386                 iommu_flush_write_buffer(iommu);
2387
2388                 ret = dmar_set_interrupt(iommu);
2389                 if (ret)
2390                         goto error;
2391
2392                 iommu_set_root_entry(iommu);
2393
2394                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2395                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2396                 iommu_disable_protect_mem_regions(iommu);
2397
2398                 ret = iommu_enable_translation(iommu);
2399                 if (ret)
2400                         goto error;
2401         }
2402
2403         return 0;
2404 error:
2405         for_each_drhd_unit(drhd) {
2406                 if (drhd->ignored)
2407                         continue;
2408                 iommu = drhd->iommu;
2409                 free_iommu(iommu);
2410         }
2411         kfree(g_iommus);
2412         return ret;
2413 }
2414
2415 /* This takes a number of _MM_ pages, not VTD pages */
2416 static struct iova *intel_alloc_iova(struct device *dev,
2417                                      struct dmar_domain *domain,
2418                                      unsigned long nrpages, uint64_t dma_mask)
2419 {
2420         struct pci_dev *pdev = to_pci_dev(dev);
2421         struct iova *iova = NULL;
2422
2423         /* Restrict dma_mask to the width that the iommu can handle */
2424         dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2425
2426         if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2427                 /*
2428                  * First try to allocate an io virtual address in
2429                  * DMA_BIT_MASK(32) and if that fails then try allocating
2430                  * from higher range
2431                  */
2432                 iova = alloc_iova(&domain->iovad, nrpages,
2433                                   IOVA_PFN(DMA_BIT_MASK(32)), 1);
2434                 if (iova)
2435                         return iova;
2436         }
2437         iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2438         if (unlikely(!iova)) {
2439                 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2440                        nrpages, pci_name(pdev));
2441                 return NULL;
2442         }
2443
2444         return iova;
2445 }
2446
2447 static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2448 {
2449         struct dmar_domain *domain;
2450         int ret;
2451
2452         domain = get_domain_for_dev(pdev,
2453                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2454         if (!domain) {
2455                 printk(KERN_ERR
2456                         "Allocating domain for %s failed", pci_name(pdev));
2457                 return NULL;
2458         }
2459
2460         /* make sure context mapping is ok */
2461         if (unlikely(!domain_context_mapped(pdev))) {
2462                 ret = domain_context_mapping(domain, pdev,
2463                                              CONTEXT_TT_MULTI_LEVEL);
2464                 if (ret) {
2465                         printk(KERN_ERR
2466                                 "Domain context map for %s failed",
2467                                 pci_name(pdev));
2468                         return NULL;
2469                 }
2470         }
2471
2472         return domain;
2473 }
2474
2475 static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2476 {
2477         struct device_domain_info *info;
2478
2479         /* No lock here, assumes no domain exit in normal case */
2480         info = dev->dev.archdata.iommu;
2481         if (likely(info))
2482                 return info->domain;
2483
2484         return __get_valid_domain_for_dev(dev);
2485 }
2486
2487 static int iommu_dummy(struct pci_dev *pdev)
2488 {
2489         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2490 }
2491
2492 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2493 static int iommu_no_mapping(struct device *dev)
2494 {
2495         struct pci_dev *pdev;
2496         int found;
2497
2498         if (unlikely(dev->bus != &pci_bus_type))
2499                 return 1;
2500
2501         pdev = to_pci_dev(dev);
2502         if (iommu_dummy(pdev))
2503                 return 1;
2504
2505         if (!iommu_identity_mapping)
2506                 return 0;
2507
2508         found = identity_mapping(pdev);
2509         if (found) {
2510                 if (iommu_should_identity_map(pdev, 0))
2511                         return 1;
2512                 else {
2513                         /*
2514                          * 32 bit DMA is removed from si_domain and fall back
2515                          * to non-identity mapping.
2516                          */
2517                         domain_remove_one_dev_info(si_domain, pdev);
2518                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2519                                pci_name(pdev));
2520                         return 0;
2521                 }
2522         } else {
2523                 /*
2524                  * In case of a detached 64 bit DMA device from vm, the device
2525                  * is put into si_domain for identity mapping.
2526                  */
2527                 if (iommu_should_identity_map(pdev, 0)) {
2528                         int ret;
2529                         ret = domain_add_dev_info(si_domain, pdev,
2530                                                   hw_pass_through ?
2531                                                   CONTEXT_TT_PASS_THROUGH :
2532                                                   CONTEXT_TT_MULTI_LEVEL);
2533                         if (!ret) {
2534                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2535                                        pci_name(pdev));
2536                                 return 1;
2537                         }
2538                 }
2539         }
2540
2541         return 0;
2542 }
2543
2544 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2545                                      size_t size, int dir, u64 dma_mask)
2546 {
2547         struct pci_dev *pdev = to_pci_dev(hwdev);
2548         struct dmar_domain *domain;
2549         phys_addr_t start_paddr;
2550         struct iova *iova;
2551         int prot = 0;
2552         int ret;
2553         struct intel_iommu *iommu;
2554         unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2555
2556         BUG_ON(dir == DMA_NONE);
2557
2558         if (iommu_no_mapping(hwdev))
2559                 return paddr;
2560
2561         domain = get_valid_domain_for_dev(pdev);
2562         if (!domain)
2563                 return 0;
2564
2565         iommu = domain_get_iommu(domain);
2566         size = aligned_nrpages(paddr, size);
2567
2568         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2569                                 pdev->dma_mask);
2570         if (!iova)
2571                 goto error;
2572
2573         /*
2574          * Check if DMAR supports zero-length reads on write only
2575          * mappings..
2576          */
2577         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2578                         !cap_zlr(iommu->cap))
2579                 prot |= DMA_PTE_READ;
2580         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2581                 prot |= DMA_PTE_WRITE;
2582         /*
2583          * paddr - (paddr + size) might be partial page, we should map the whole
2584          * page.  Note: if two part of one page are separately mapped, we
2585          * might have two guest_addr mapping to the same host paddr, but this
2586          * is not a big problem
2587          */
2588         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2589                                  mm_to_dma_pfn(paddr_pfn), size, prot);
2590         if (ret)
2591                 goto error;
2592
2593         /* it's a non-present to present mapping. Only flush if caching mode */
2594         if (cap_caching_mode(iommu->cap))
2595                 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2596         else
2597                 iommu_flush_write_buffer(iommu);
2598
2599         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2600         start_paddr += paddr & ~PAGE_MASK;
2601         return start_paddr;
2602
2603 error:
2604         if (iova)
2605                 __free_iova(&domain->iovad, iova);
2606         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2607                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2608         return 0;
2609 }
2610
2611 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2612                                  unsigned long offset, size_t size,
2613                                  enum dma_data_direction dir,
2614                                  struct dma_attrs *attrs)
2615 {
2616         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2617                                   dir, to_pci_dev(dev)->dma_mask);
2618 }
2619
2620 static void flush_unmaps(void)
2621 {
2622         int i, j;
2623
2624         timer_on = 0;
2625
2626         /* just flush them all */
2627         for (i = 0; i < g_num_of_iommus; i++) {
2628                 struct intel_iommu *iommu = g_iommus[i];
2629                 if (!iommu)
2630                         continue;
2631
2632                 if (!deferred_flush[i].next)
2633                         continue;
2634
2635                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2636                                          DMA_TLB_GLOBAL_FLUSH);
2637                 for (j = 0; j < deferred_flush[i].next; j++) {
2638                         unsigned long mask;
2639                         struct iova *iova = deferred_flush[i].iova[j];
2640
2641                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2642                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2643                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2644                                         iova->pfn_lo << PAGE_SHIFT, mask);
2645                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2646                 }
2647                 deferred_flush[i].next = 0;
2648         }
2649
2650         list_size = 0;
2651 }
2652
2653 static void flush_unmaps_timeout(unsigned long data)
2654 {
2655         unsigned long flags;
2656
2657         spin_lock_irqsave(&async_umap_flush_lock, flags);
2658         flush_unmaps();
2659         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2660 }
2661
2662 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2663 {
2664         unsigned long flags;
2665         int next, iommu_id;
2666         struct intel_iommu *iommu;
2667
2668         spin_lock_irqsave(&async_umap_flush_lock, flags);
2669         if (list_size == HIGH_WATER_MARK)
2670                 flush_unmaps();
2671
2672         iommu = domain_get_iommu(dom);
2673         iommu_id = iommu->seq_id;
2674
2675         next = deferred_flush[iommu_id].next;
2676         deferred_flush[iommu_id].domain[next] = dom;
2677         deferred_flush[iommu_id].iova[next] = iova;
2678         deferred_flush[iommu_id].next++;
2679
2680         if (!timer_on) {
2681                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2682                 timer_on = 1;
2683         }
2684         list_size++;
2685         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2686 }
2687
2688 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2689                              size_t size, enum dma_data_direction dir,
2690                              struct dma_attrs *attrs)
2691 {
2692         struct pci_dev *pdev = to_pci_dev(dev);
2693         struct dmar_domain *domain;
2694         unsigned long start_pfn, last_pfn;
2695         struct iova *iova;
2696         struct intel_iommu *iommu;
2697
2698         if (iommu_no_mapping(dev))
2699                 return;
2700
2701         domain = find_domain(pdev);
2702         BUG_ON(!domain);
2703
2704         iommu = domain_get_iommu(domain);
2705
2706         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2707         if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2708                       (unsigned long long)dev_addr))
2709                 return;
2710
2711         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2712         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2713
2714         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2715                  pci_name(pdev), start_pfn, last_pfn);
2716
2717         /*  clear the whole page */
2718         dma_pte_clear_range(domain, start_pfn, last_pfn);
2719
2720         /* free page tables */
2721         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2722
2723         if (intel_iommu_strict) {
2724                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2725                                       last_pfn - start_pfn + 1);
2726                 /* free iova */
2727                 __free_iova(&domain->iovad, iova);
2728         } else {
2729                 add_unmap(domain, iova);
2730                 /*
2731                  * queue up the release of the unmap to save the 1/6th of the
2732                  * cpu used up by the iotlb flush operation...
2733                  */
2734         }
2735 }
2736
2737 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2738                                   dma_addr_t *dma_handle, gfp_t flags)
2739 {
2740         void *vaddr;
2741         int order;
2742
2743         size = PAGE_ALIGN(size);
2744         order = get_order(size);
2745         flags &= ~(GFP_DMA | GFP_DMA32);
2746
2747         vaddr = (void *)__get_free_pages(flags, order);
2748         if (!vaddr)
2749                 return NULL;
2750         memset(vaddr, 0, size);
2751
2752         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2753                                          DMA_BIDIRECTIONAL,
2754                                          hwdev->coherent_dma_mask);
2755         if (*dma_handle)
2756                 return vaddr;
2757         free_pages((unsigned long)vaddr, order);
2758         return NULL;
2759 }
2760
2761 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2762                                 dma_addr_t dma_handle)
2763 {
2764         int order;
2765
2766         size = PAGE_ALIGN(size);
2767         order = get_order(size);
2768
2769         intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
2770         free_pages((unsigned long)vaddr, order);
2771 }
2772
2773 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2774                            int nelems, enum dma_data_direction dir,
2775                            struct dma_attrs *attrs)
2776 {
2777         struct pci_dev *pdev = to_pci_dev(hwdev);
2778         struct dmar_domain *domain;
2779         unsigned long start_pfn, last_pfn;
2780         struct iova *iova;
2781         struct intel_iommu *iommu;
2782
2783         if (iommu_no_mapping(hwdev))
2784                 return;
2785
2786         domain = find_domain(pdev);
2787         BUG_ON(!domain);
2788
2789         iommu = domain_get_iommu(domain);
2790
2791         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2792         if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2793                       (unsigned long long)sglist[0].dma_address))
2794                 return;
2795
2796         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2797         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2798
2799         /*  clear the whole page */
2800         dma_pte_clear_range(domain, start_pfn, last_pfn);
2801
2802         /* free page tables */
2803         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2804
2805         if (intel_iommu_strict) {
2806                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2807                                       last_pfn - start_pfn + 1);
2808                 /* free iova */
2809                 __free_iova(&domain->iovad, iova);
2810         } else {
2811                 add_unmap(domain, iova);
2812                 /*
2813                  * queue up the release of the unmap to save the 1/6th of the
2814                  * cpu used up by the iotlb flush operation...
2815                  */
2816         }
2817 }
2818
2819 static int intel_nontranslate_map_sg(struct device *hddev,
2820         struct scatterlist *sglist, int nelems, int dir)
2821 {
2822         int i;
2823         struct scatterlist *sg;
2824
2825         for_each_sg(sglist, sg, nelems, i) {
2826                 BUG_ON(!sg_page(sg));
2827                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2828                 sg->dma_length = sg->length;
2829         }
2830         return nelems;
2831 }
2832
2833 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2834                         enum dma_data_direction dir, struct dma_attrs *attrs)
2835 {
2836         int i;
2837         struct pci_dev *pdev = to_pci_dev(hwdev);
2838         struct dmar_domain *domain;
2839         size_t size = 0;
2840         int prot = 0;
2841         size_t offset_pfn = 0;
2842         struct iova *iova = NULL;
2843         int ret;
2844         struct scatterlist *sg;
2845         unsigned long start_vpfn;
2846         struct intel_iommu *iommu;
2847
2848         BUG_ON(dir == DMA_NONE);
2849         if (iommu_no_mapping(hwdev))
2850                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2851
2852         domain = get_valid_domain_for_dev(pdev);
2853         if (!domain)
2854                 return 0;
2855
2856         iommu = domain_get_iommu(domain);
2857
2858         for_each_sg(sglist, sg, nelems, i)
2859                 size += aligned_nrpages(sg->offset, sg->length);
2860
2861         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2862                                 pdev->dma_mask);
2863         if (!iova) {
2864                 sglist->dma_length = 0;
2865                 return 0;
2866         }
2867
2868         /*
2869          * Check if DMAR supports zero-length reads on write only
2870          * mappings..
2871          */
2872         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2873                         !cap_zlr(iommu->cap))
2874                 prot |= DMA_PTE_READ;
2875         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2876                 prot |= DMA_PTE_WRITE;
2877
2878         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2879
2880         ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
2881         if (unlikely(ret)) {
2882                 /*  clear the page */
2883                 dma_pte_clear_range(domain, start_vpfn,
2884                                     start_vpfn + size - 1);
2885                 /* free page tables */
2886                 dma_pte_free_pagetable(domain, start_vpfn,
2887                                        start_vpfn + size - 1);
2888                 /* free iova */
2889                 __free_iova(&domain->iovad, iova);
2890                 return 0;
2891         }
2892
2893         /* it's a non-present to present mapping. Only flush if caching mode */
2894         if (cap_caching_mode(iommu->cap))
2895                 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2896         else
2897                 iommu_flush_write_buffer(iommu);
2898
2899         return nelems;
2900 }
2901
2902 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2903 {
2904         return !dma_addr;
2905 }
2906
2907 struct dma_map_ops intel_dma_ops = {
2908         .alloc_coherent = intel_alloc_coherent,
2909         .free_coherent = intel_free_coherent,
2910         .map_sg = intel_map_sg,
2911         .unmap_sg = intel_unmap_sg,
2912         .map_page = intel_map_page,
2913         .unmap_page = intel_unmap_page,
2914         .mapping_error = intel_mapping_error,
2915 };
2916
2917 static inline int iommu_domain_cache_init(void)
2918 {
2919         int ret = 0;
2920
2921         iommu_domain_cache = kmem_cache_create("iommu_domain",
2922                                          sizeof(struct dmar_domain),
2923                                          0,
2924                                          SLAB_HWCACHE_ALIGN,
2925
2926                                          NULL);
2927         if (!iommu_domain_cache) {
2928                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2929                 ret = -ENOMEM;
2930         }
2931
2932         return ret;
2933 }
2934
2935 static inline int iommu_devinfo_cache_init(void)
2936 {
2937         int ret = 0;
2938
2939         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2940                                          sizeof(struct device_domain_info),
2941                                          0,
2942                                          SLAB_HWCACHE_ALIGN,
2943                                          NULL);
2944         if (!iommu_devinfo_cache) {
2945                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2946                 ret = -ENOMEM;
2947         }
2948
2949         return ret;
2950 }
2951
2952 static inline int iommu_iova_cache_init(void)
2953 {
2954         int ret = 0;
2955
2956         iommu_iova_cache = kmem_cache_create("iommu_iova",
2957                                          sizeof(struct iova),
2958                                          0,
2959                                          SLAB_HWCACHE_ALIGN,
2960                                          NULL);
2961         if (!iommu_iova_cache) {
2962                 printk(KERN_ERR "Couldn't create iova cache\n");
2963                 ret = -ENOMEM;
2964         }
2965
2966         return ret;
2967 }
2968
2969 static int __init iommu_init_mempool(void)
2970 {
2971         int ret;
2972         ret = iommu_iova_cache_init();
2973         if (ret)
2974                 return ret;
2975
2976         ret = iommu_domain_cache_init();
2977         if (ret)
2978                 goto domain_error;
2979
2980         ret = iommu_devinfo_cache_init();
2981         if (!ret)
2982                 return ret;
2983
2984         kmem_cache_destroy(iommu_domain_cache);
2985 domain_error:
2986         kmem_cache_destroy(iommu_iova_cache);
2987
2988         return -ENOMEM;
2989 }
2990
2991 static void __init iommu_exit_mempool(void)
2992 {
2993         kmem_cache_destroy(iommu_devinfo_cache);
2994         kmem_cache_destroy(iommu_domain_cache);
2995         kmem_cache_destroy(iommu_iova_cache);
2996
2997 }
2998
2999 static void __init init_no_remapping_devices(void)
3000 {
3001         struct dmar_drhd_unit *drhd;
3002
3003         for_each_drhd_unit(drhd) {
3004                 if (!drhd->include_all) {
3005                         int i;
3006                         for (i = 0; i < drhd->devices_cnt; i++)
3007                                 if (drhd->devices[i] != NULL)
3008                                         break;
3009                         /* ignore DMAR unit if no pci devices exist */
3010                         if (i == drhd->devices_cnt)
3011                                 drhd->ignored = 1;
3012                 }
3013         }
3014
3015         if (dmar_map_gfx)
3016                 return;
3017
3018         for_each_drhd_unit(drhd) {
3019                 int i;
3020                 if (drhd->ignored || drhd->include_all)
3021                         continue;
3022
3023                 for (i = 0; i < drhd->devices_cnt; i++)
3024                         if (drhd->devices[i] &&
3025                                 !IS_GFX_DEVICE(drhd->devices[i]))
3026                                 break;
3027
3028                 if (i < drhd->devices_cnt)
3029                         continue;
3030
3031                 /* bypass IOMMU if it is just for gfx devices */
3032                 drhd->ignored = 1;
3033                 for (i = 0; i < drhd->devices_cnt; i++) {
3034                         if (!drhd->devices[i])
3035                                 continue;
3036                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3037                 }
3038         }
3039 }
3040
3041 #ifdef CONFIG_SUSPEND
3042 static int init_iommu_hw(void)
3043 {
3044         struct dmar_drhd_unit *drhd;
3045         struct intel_iommu *iommu = NULL;
3046
3047         for_each_active_iommu(iommu, drhd)
3048                 if (iommu->qi)
3049                         dmar_reenable_qi(iommu);
3050
3051         for_each_active_iommu(iommu, drhd) {
3052                 iommu_flush_write_buffer(iommu);
3053
3054                 iommu_set_root_entry(iommu);
3055
3056                 iommu->flush.flush_context(iommu, 0, 0, 0,
3057                                            DMA_CCMD_GLOBAL_INVL);
3058                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3059                                          DMA_TLB_GLOBAL_FLUSH);
3060                 iommu_disable_protect_mem_regions(iommu);
3061                 iommu_enable_translation(iommu);
3062         }
3063
3064         return 0;
3065 }
3066
3067 static void iommu_flush_all(void)
3068 {
3069         struct dmar_drhd_unit *drhd;
3070         struct intel_iommu *iommu;
3071
3072         for_each_active_iommu(iommu, drhd) {
3073                 iommu->flush.flush_context(iommu, 0, 0, 0,
3074                                            DMA_CCMD_GLOBAL_INVL);
3075                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3076                                          DMA_TLB_GLOBAL_FLUSH);
3077         }
3078 }
3079
3080 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3081 {
3082         struct dmar_drhd_unit *drhd;
3083         struct intel_iommu *iommu = NULL;
3084         unsigned long flag;
3085
3086         for_each_active_iommu(iommu, drhd) {
3087                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3088                                                  GFP_ATOMIC);
3089                 if (!iommu->iommu_state)
3090                         goto nomem;
3091         }
3092
3093         iommu_flush_all();
3094
3095         for_each_active_iommu(iommu, drhd) {
3096                 iommu_disable_translation(iommu);
3097
3098                 spin_lock_irqsave(&iommu->register_lock, flag);
3099
3100                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3101                         readl(iommu->reg + DMAR_FECTL_REG);
3102                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3103                         readl(iommu->reg + DMAR_FEDATA_REG);
3104                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3105                         readl(iommu->reg + DMAR_FEADDR_REG);
3106                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3107                         readl(iommu->reg + DMAR_FEUADDR_REG);
3108
3109                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3110         }
3111         return 0;
3112
3113 nomem:
3114         for_each_active_iommu(iommu, drhd)
3115                 kfree(iommu->iommu_state);
3116
3117         return -ENOMEM;
3118 }
3119
3120 static int iommu_resume(struct sys_device *dev)
3121 {
3122         struct dmar_drhd_unit *drhd;
3123         struct intel_iommu *iommu = NULL;
3124         unsigned long flag;
3125
3126         if (init_iommu_hw()) {
3127                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3128                 return -EIO;
3129         }
3130
3131         for_each_active_iommu(iommu, drhd) {
3132
3133                 spin_lock_irqsave(&iommu->register_lock, flag);
3134
3135                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3136                         iommu->reg + DMAR_FECTL_REG);
3137                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3138                         iommu->reg + DMAR_FEDATA_REG);
3139                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3140                         iommu->reg + DMAR_FEADDR_REG);
3141                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3142                         iommu->reg + DMAR_FEUADDR_REG);
3143
3144                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3145         }
3146
3147         for_each_active_iommu(iommu, drhd)
3148                 kfree(iommu->iommu_state);
3149
3150         return 0;
3151 }
3152
3153 static struct sysdev_class iommu_sysclass = {
3154         .name           = "iommu",
3155         .resume         = iommu_resume,
3156         .suspend        = iommu_suspend,
3157 };
3158
3159 static struct sys_device device_iommu = {
3160         .cls    = &iommu_sysclass,
3161 };
3162
3163 static int __init init_iommu_sysfs(void)
3164 {
3165         int error;
3166
3167         error = sysdev_class_register(&iommu_sysclass);
3168         if (error)
3169                 return error;
3170
3171         error = sysdev_register(&device_iommu);
3172         if (error)
3173                 sysdev_class_unregister(&iommu_sysclass);
3174
3175         return error;
3176 }
3177
3178 #else
3179 static int __init init_iommu_sysfs(void)
3180 {
3181         return 0;
3182 }
3183 #endif  /* CONFIG_PM */
3184
3185 int __init intel_iommu_init(void)
3186 {
3187         int ret = 0;
3188
3189         if (dmar_table_init())
3190                 return  -ENODEV;
3191
3192         if (dmar_dev_scope_init())
3193                 return  -ENODEV;
3194
3195         /*
3196          * Check the need for DMA-remapping initialization now.
3197          * Above initialization will also be used by Interrupt-remapping.
3198          */
3199         if (no_iommu || swiotlb || dmar_disabled)
3200                 return -ENODEV;
3201
3202         iommu_init_mempool();
3203         dmar_init_reserved_ranges();
3204
3205         init_no_remapping_devices();
3206
3207         ret = init_dmars();
3208         if (ret) {
3209                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3210                 put_iova_domain(&reserved_iova_list);
3211                 iommu_exit_mempool();
3212                 return ret;
3213         }
3214         printk(KERN_INFO
3215         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3216
3217         init_timer(&unmap_timer);
3218         force_iommu = 1;
3219         dma_ops = &intel_dma_ops;
3220
3221         init_iommu_sysfs();
3222
3223         register_iommu(&intel_iommu_ops);
3224
3225         return 0;
3226 }
3227
3228 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3229                                            struct pci_dev *pdev)
3230 {
3231         struct pci_dev *tmp, *parent;
3232
3233         if (!iommu || !pdev)
3234                 return;
3235
3236         /* dependent device detach */
3237         tmp = pci_find_upstream_pcie_bridge(pdev);
3238         /* Secondary interface's bus number and devfn 0 */
3239         if (tmp) {
3240                 parent = pdev->bus->self;
3241                 while (parent != tmp) {
3242                         iommu_detach_dev(iommu, parent->bus->number,
3243                                          parent->devfn);
3244                         parent = parent->bus->self;
3245                 }
3246                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3247                         iommu_detach_dev(iommu,
3248                                 tmp->subordinate->number, 0);
3249                 else /* this is a legacy PCI bridge */
3250                         iommu_detach_dev(iommu, tmp->bus->number,
3251                                          tmp->devfn);
3252         }
3253 }
3254
3255 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3256                                           struct pci_dev *pdev)
3257 {
3258         struct device_domain_info *info;
3259         struct intel_iommu *iommu;
3260         unsigned long flags;
3261         int found = 0;
3262         struct list_head *entry, *tmp;
3263
3264         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3265                                 pdev->devfn);
3266         if (!iommu)
3267                 return;
3268
3269         spin_lock_irqsave(&device_domain_lock, flags);
3270         list_for_each_safe(entry, tmp, &domain->devices) {
3271                 info = list_entry(entry, struct device_domain_info, link);
3272                 /* No need to compare PCI domain; it has to be the same */
3273                 if (info->bus == pdev->bus->number &&
3274                     info->devfn == pdev->devfn) {
3275                         list_del(&info->link);
3276                         list_del(&info->global);
3277                         if (info->dev)
3278                                 info->dev->dev.archdata.iommu = NULL;
3279                         spin_unlock_irqrestore(&device_domain_lock, flags);
3280
3281                         iommu_disable_dev_iotlb(info);
3282                         iommu_detach_dev(iommu, info->bus, info->devfn);
3283                         iommu_detach_dependent_devices(iommu, pdev);
3284                         free_devinfo_mem(info);
3285
3286                         spin_lock_irqsave(&device_domain_lock, flags);
3287
3288                         if (found)
3289                                 break;
3290                         else
3291                                 continue;
3292                 }
3293
3294                 /* if there is no other devices under the same iommu
3295                  * owned by this domain, clear this iommu in iommu_bmp
3296                  * update iommu count and coherency
3297                  */
3298                 if (iommu == device_to_iommu(info->segment, info->bus,
3299                                             info->devfn))
3300                         found = 1;
3301         }
3302
3303         if (found == 0) {
3304                 unsigned long tmp_flags;
3305                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3306                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3307                 domain->iommu_count--;
3308                 domain_update_iommu_cap(domain);
3309                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3310         }
3311
3312         spin_unlock_irqrestore(&device_domain_lock, flags);
3313 }
3314
3315 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3316 {
3317         struct device_domain_info *info;
3318         struct intel_iommu *iommu;
3319         unsigned long flags1, flags2;
3320
3321         spin_lock_irqsave(&device_domain_lock, flags1);
3322         while (!list_empty(&domain->devices)) {
3323                 info = list_entry(domain->devices.next,
3324                         struct device_domain_info, link);
3325                 list_del(&info->link);
3326                 list_del(&info->global);
3327                 if (info->dev)
3328                         info->dev->dev.archdata.iommu = NULL;
3329
3330                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3331
3332                 iommu_disable_dev_iotlb(info);
3333                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3334                 iommu_detach_dev(iommu, info->bus, info->devfn);
3335                 iommu_detach_dependent_devices(iommu, info->dev);
3336
3337                 /* clear this iommu in iommu_bmp, update iommu count
3338                  * and capabilities
3339                  */
3340                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3341                 if (test_and_clear_bit(iommu->seq_id,
3342                                        &domain->iommu_bmp)) {
3343                         domain->iommu_count--;
3344                         domain_update_iommu_cap(domain);
3345                 }
3346                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3347
3348                 free_devinfo_mem(info);
3349                 spin_lock_irqsave(&device_domain_lock, flags1);
3350         }
3351         spin_unlock_irqrestore(&device_domain_lock, flags1);
3352 }
3353
3354 /* domain id for virtual machine, it won't be set in context */
3355 static unsigned long vm_domid;
3356
3357 static int vm_domain_min_agaw(struct dmar_domain *domain)
3358 {
3359         int i;
3360         int min_agaw = domain->agaw;
3361
3362         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3363         for (; i < g_num_of_iommus; ) {
3364                 if (min_agaw > g_iommus[i]->agaw)
3365                         min_agaw = g_iommus[i]->agaw;
3366
3367                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3368         }
3369
3370         return min_agaw;
3371 }
3372
3373 static struct dmar_domain *iommu_alloc_vm_domain(void)
3374 {
3375         struct dmar_domain *domain;
3376
3377         domain = alloc_domain_mem();
3378         if (!domain)
3379                 return NULL;
3380
3381         domain->id = vm_domid++;
3382         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3383         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3384
3385         return domain;
3386 }
3387
3388 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3389 {
3390         int adjust_width;
3391
3392         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3393         spin_lock_init(&domain->iommu_lock);
3394
3395         domain_reserve_special_ranges(domain);
3396
3397         /* calculate AGAW */
3398         domain->gaw = guest_width;
3399         adjust_width = guestwidth_to_adjustwidth(guest_width);
3400         domain->agaw = width_to_agaw(adjust_width);
3401
3402         INIT_LIST_HEAD(&domain->devices);
3403
3404         domain->iommu_count = 0;
3405         domain->iommu_coherency = 0;
3406         domain->iommu_snooping = 0;
3407         domain->max_addr = 0;
3408
3409         /* always allocate the top pgd */
3410         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3411         if (!domain->pgd)
3412                 return -ENOMEM;
3413         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3414         return 0;
3415 }
3416
3417 static void iommu_free_vm_domain(struct dmar_domain *domain)
3418 {
3419         unsigned long flags;
3420         struct dmar_drhd_unit *drhd;
3421         struct intel_iommu *iommu;
3422         unsigned long i;
3423         unsigned long ndomains;
3424
3425         for_each_drhd_unit(drhd) {
3426                 if (drhd->ignored)
3427                         continue;
3428                 iommu = drhd->iommu;
3429
3430                 ndomains = cap_ndoms(iommu->cap);
3431                 i = find_first_bit(iommu->domain_ids, ndomains);
3432                 for (; i < ndomains; ) {
3433                         if (iommu->domains[i] == domain) {
3434                                 spin_lock_irqsave(&iommu->lock, flags);
3435                                 clear_bit(i, iommu->domain_ids);
3436                                 iommu->domains[i] = NULL;
3437                                 spin_unlock_irqrestore(&iommu->lock, flags);
3438                                 break;
3439                         }
3440                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3441                 }
3442         }
3443 }
3444
3445 static void vm_domain_exit(struct dmar_domain *domain)
3446 {
3447         /* Domain 0 is reserved, so dont process it */
3448         if (!domain)
3449                 return;
3450
3451         vm_domain_remove_all_dev_info(domain);
3452         /* destroy iovas */
3453         put_iova_domain(&domain->iovad);
3454
3455         /* clear ptes */
3456         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3457
3458         /* free page tables */
3459         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3460
3461         iommu_free_vm_domain(domain);
3462         free_domain_mem(domain);
3463 }
3464
3465 static int intel_iommu_domain_init(struct iommu_domain *domain)
3466 {
3467         struct dmar_domain *dmar_domain;
3468
3469         dmar_domain = iommu_alloc_vm_domain();
3470         if (!dmar_domain) {
3471                 printk(KERN_ERR
3472                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3473                 return -ENOMEM;
3474         }
3475         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3476                 printk(KERN_ERR
3477                         "intel_iommu_domain_init() failed\n");
3478                 vm_domain_exit(dmar_domain);
3479                 return -ENOMEM;
3480         }
3481         domain->priv = dmar_domain;
3482
3483         return 0;
3484 }
3485
3486 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3487 {
3488         struct dmar_domain *dmar_domain = domain->priv;
3489
3490         domain->priv = NULL;
3491         vm_domain_exit(dmar_domain);
3492 }
3493
3494 static int intel_iommu_attach_device(struct iommu_domain *domain,
3495                                      struct device *dev)
3496 {
3497         struct dmar_domain *dmar_domain = domain->priv;
3498         struct pci_dev *pdev = to_pci_dev(dev);
3499         struct intel_iommu *iommu;
3500         int addr_width;
3501         u64 end;
3502
3503         /* normally pdev is not mapped */
3504         if (unlikely(domain_context_mapped(pdev))) {
3505                 struct dmar_domain *old_domain;
3506
3507                 old_domain = find_domain(pdev);
3508                 if (old_domain) {
3509                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3510                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3511                                 domain_remove_one_dev_info(old_domain, pdev);
3512                         else
3513                                 domain_remove_dev_info(old_domain);
3514                 }
3515         }
3516
3517         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3518                                 pdev->devfn);
3519         if (!iommu)
3520                 return -ENODEV;
3521
3522         /* check if this iommu agaw is sufficient for max mapped address */
3523         addr_width = agaw_to_width(iommu->agaw);
3524         end = DOMAIN_MAX_ADDR(addr_width);
3525         end = end & VTD_PAGE_MASK;
3526         if (end < dmar_domain->max_addr) {
3527                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3528                        "sufficient for the mapped address (%llx)\n",
3529                        __func__, iommu->agaw, dmar_domain->max_addr);
3530                 return -EFAULT;
3531         }
3532
3533         return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3534 }
3535
3536 static void intel_iommu_detach_device(struct iommu_domain *domain,
3537                                       struct device *dev)
3538 {
3539         struct dmar_domain *dmar_domain = domain->priv;
3540         struct pci_dev *pdev = to_pci_dev(dev);
3541
3542         domain_remove_one_dev_info(dmar_domain, pdev);
3543 }
3544
3545 static int intel_iommu_map_range(struct iommu_domain *domain,
3546                                  unsigned long iova, phys_addr_t hpa,
3547                                  size_t size, int iommu_prot)
3548 {
3549         struct dmar_domain *dmar_domain = domain->priv;
3550         u64 max_addr;
3551         int addr_width;
3552         int prot = 0;
3553         int ret;
3554
3555         if (iommu_prot & IOMMU_READ)
3556                 prot |= DMA_PTE_READ;
3557         if (iommu_prot & IOMMU_WRITE)
3558                 prot |= DMA_PTE_WRITE;
3559         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3560                 prot |= DMA_PTE_SNP;
3561
3562         max_addr = iova + size;
3563         if (dmar_domain->max_addr < max_addr) {
3564                 int min_agaw;
3565                 u64 end;
3566
3567                 /* check if minimum agaw is sufficient for mapped address */
3568                 min_agaw = vm_domain_min_agaw(dmar_domain);
3569                 addr_width = agaw_to_width(min_agaw);
3570                 end = DOMAIN_MAX_ADDR(addr_width);
3571                 end = end & VTD_PAGE_MASK;
3572                 if (end < max_addr) {
3573                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3574                                "sufficient for the mapped address (%llx)\n",
3575                                __func__, min_agaw, max_addr);
3576                         return -EFAULT;
3577                 }
3578                 dmar_domain->max_addr = max_addr;
3579         }
3580         /* Round up size to next multiple of PAGE_SIZE, if it and
3581            the low bits of hpa would take us onto the next page */
3582         size = aligned_nrpages(hpa, size);
3583         ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3584                                  hpa >> VTD_PAGE_SHIFT, size, prot);
3585         return ret;
3586 }
3587
3588 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3589                                     unsigned long iova, size_t size)
3590 {
3591         struct dmar_domain *dmar_domain = domain->priv;
3592
3593         if (!size)
3594                 return;
3595
3596         dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3597                             (iova + size - 1) >> VTD_PAGE_SHIFT);
3598
3599         if (dmar_domain->max_addr == iova + size)
3600                 dmar_domain->max_addr = iova;
3601 }
3602
3603 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3604                                             unsigned long iova)
3605 {
3606         struct dmar_domain *dmar_domain = domain->priv;
3607         struct dma_pte *pte;
3608         u64 phys = 0;
3609
3610         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3611         if (pte)
3612                 phys = dma_pte_addr(pte);
3613
3614         return phys;
3615 }
3616
3617 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3618                                       unsigned long cap)
3619 {
3620         struct dmar_domain *dmar_domain = domain->priv;
3621
3622         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3623                 return dmar_domain->iommu_snooping;
3624
3625         return 0;
3626 }
3627
3628 static struct iommu_ops intel_iommu_ops = {
3629         .domain_init    = intel_iommu_domain_init,
3630         .domain_destroy = intel_iommu_domain_destroy,
3631         .attach_dev     = intel_iommu_attach_device,
3632         .detach_dev     = intel_iommu_detach_device,
3633         .map            = intel_iommu_map_range,
3634         .unmap          = intel_iommu_unmap_range,
3635         .iova_to_phys   = intel_iommu_iova_to_phys,
3636         .domain_has_cap = intel_iommu_domain_has_cap,
3637 };
3638
3639 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3640 {
3641         /*
3642          * Mobile 4 Series Chipset neglects to set RWBF capability,
3643          * but needs it:
3644          */
3645         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3646         rwbf_quirk = 1;
3647 }
3648
3649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);