intel-iommu: Clean up address handling in domain_page_mapping()
[linux-2.6.git] / drivers / pci / intel-iommu.c
1 /*
2  * Copyright (c) 2006, Intel Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License along with
14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15  * Place - Suite 330, Boston, MA 02111-1307 USA.
16  *
17  * Copyright (C) 2006-2008 Intel Corporation
18  * Author: Ashok Raj <ashok.raj@intel.com>
19  * Author: Shaohua Li <shaohua.li@intel.com>
20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21  * Author: Fenghua Yu <fenghua.yu@intel.com>
22  */
23
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
42 #include "pci.h"
43
44 #define ROOT_SIZE               VTD_PAGE_SIZE
45 #define CONTEXT_SIZE            VTD_PAGE_SIZE
46
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
49
50 #define IOAPIC_RANGE_START      (0xfee00000)
51 #define IOAPIC_RANGE_END        (0xfeefffff)
52 #define IOVA_START_ADDR         (0x1000)
53
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
55
56 #define MAX_AGAW_WIDTH 64
57
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
59 #define DOMAIN_MAX_PFN(gaw)  ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
60
61 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
62 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
63 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
64
65 #ifndef PHYSICAL_PAGE_MASK
66 #define PHYSICAL_PAGE_MASK PAGE_MASK
67 #endif
68
69 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
70    are never going to work. */
71 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
72 {
73         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
74 }
75
76 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
77 {
78         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
79 }
80 static inline unsigned long page_to_dma_pfn(struct page *pg)
81 {
82         return mm_to_dma_pfn(page_to_pfn(pg));
83 }
84 static inline unsigned long virt_to_dma_pfn(void *p)
85 {
86         return page_to_dma_pfn(virt_to_page(p));
87 }
88
89 /* global iommu list, set NULL for ignored DMAR units */
90 static struct intel_iommu **g_iommus;
91
92 static int rwbf_quirk;
93
94 /*
95  * 0: Present
96  * 1-11: Reserved
97  * 12-63: Context Ptr (12 - (haw-1))
98  * 64-127: Reserved
99  */
100 struct root_entry {
101         u64     val;
102         u64     rsvd1;
103 };
104 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
105 static inline bool root_present(struct root_entry *root)
106 {
107         return (root->val & 1);
108 }
109 static inline void set_root_present(struct root_entry *root)
110 {
111         root->val |= 1;
112 }
113 static inline void set_root_value(struct root_entry *root, unsigned long value)
114 {
115         root->val |= value & VTD_PAGE_MASK;
116 }
117
118 static inline struct context_entry *
119 get_context_addr_from_root(struct root_entry *root)
120 {
121         return (struct context_entry *)
122                 (root_present(root)?phys_to_virt(
123                 root->val & VTD_PAGE_MASK) :
124                 NULL);
125 }
126
127 /*
128  * low 64 bits:
129  * 0: present
130  * 1: fault processing disable
131  * 2-3: translation type
132  * 12-63: address space root
133  * high 64 bits:
134  * 0-2: address width
135  * 3-6: aval
136  * 8-23: domain id
137  */
138 struct context_entry {
139         u64 lo;
140         u64 hi;
141 };
142
143 static inline bool context_present(struct context_entry *context)
144 {
145         return (context->lo & 1);
146 }
147 static inline void context_set_present(struct context_entry *context)
148 {
149         context->lo |= 1;
150 }
151
152 static inline void context_set_fault_enable(struct context_entry *context)
153 {
154         context->lo &= (((u64)-1) << 2) | 1;
155 }
156
157 static inline void context_set_translation_type(struct context_entry *context,
158                                                 unsigned long value)
159 {
160         context->lo &= (((u64)-1) << 4) | 3;
161         context->lo |= (value & 3) << 2;
162 }
163
164 static inline void context_set_address_root(struct context_entry *context,
165                                             unsigned long value)
166 {
167         context->lo |= value & VTD_PAGE_MASK;
168 }
169
170 static inline void context_set_address_width(struct context_entry *context,
171                                              unsigned long value)
172 {
173         context->hi |= value & 7;
174 }
175
176 static inline void context_set_domain_id(struct context_entry *context,
177                                          unsigned long value)
178 {
179         context->hi |= (value & ((1 << 16) - 1)) << 8;
180 }
181
182 static inline void context_clear_entry(struct context_entry *context)
183 {
184         context->lo = 0;
185         context->hi = 0;
186 }
187
188 /*
189  * 0: readable
190  * 1: writable
191  * 2-6: reserved
192  * 7: super page
193  * 8-10: available
194  * 11: snoop behavior
195  * 12-63: Host physcial address
196  */
197 struct dma_pte {
198         u64 val;
199 };
200
201 static inline void dma_clear_pte(struct dma_pte *pte)
202 {
203         pte->val = 0;
204 }
205
206 static inline void dma_set_pte_readable(struct dma_pte *pte)
207 {
208         pte->val |= DMA_PTE_READ;
209 }
210
211 static inline void dma_set_pte_writable(struct dma_pte *pte)
212 {
213         pte->val |= DMA_PTE_WRITE;
214 }
215
216 static inline void dma_set_pte_snp(struct dma_pte *pte)
217 {
218         pte->val |= DMA_PTE_SNP;
219 }
220
221 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
222 {
223         pte->val = (pte->val & ~3) | (prot & 3);
224 }
225
226 static inline u64 dma_pte_addr(struct dma_pte *pte)
227 {
228         return (pte->val & VTD_PAGE_MASK);
229 }
230
231 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
232 {
233         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
234 }
235
236 static inline bool dma_pte_present(struct dma_pte *pte)
237 {
238         return (pte->val & 3) != 0;
239 }
240
241 /*
242  * This domain is a statically identity mapping domain.
243  *      1. This domain creats a static 1:1 mapping to all usable memory.
244  *      2. It maps to each iommu if successful.
245  *      3. Each iommu mapps to this domain if successful.
246  */
247 struct dmar_domain *si_domain;
248
249 /* devices under the same p2p bridge are owned in one domain */
250 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
251
252 /* domain represents a virtual machine, more than one devices
253  * across iommus may be owned in one domain, e.g. kvm guest.
254  */
255 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
256
257 /* si_domain contains mulitple devices */
258 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
259
260 struct dmar_domain {
261         int     id;                     /* domain id */
262         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
263
264         struct list_head devices;       /* all devices' list */
265         struct iova_domain iovad;       /* iova's that belong to this domain */
266
267         struct dma_pte  *pgd;           /* virtual address */
268         spinlock_t      mapping_lock;   /* page table lock */
269         int             gaw;            /* max guest address width */
270
271         /* adjusted guest address width, 0 is level 2 30-bit */
272         int             agaw;
273
274         int             flags;          /* flags to find out type of domain */
275
276         int             iommu_coherency;/* indicate coherency of iommu access */
277         int             iommu_snooping; /* indicate snooping control feature*/
278         int             iommu_count;    /* reference count of iommu */
279         spinlock_t      iommu_lock;     /* protect iommu set in domain */
280         u64             max_addr;       /* maximum mapped address */
281 };
282
283 /* PCI domain-device relationship */
284 struct device_domain_info {
285         struct list_head link;  /* link to domain siblings */
286         struct list_head global; /* link to global list */
287         int segment;            /* PCI domain */
288         u8 bus;                 /* PCI bus number */
289         u8 devfn;               /* PCI devfn number */
290         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
291         struct intel_iommu *iommu; /* IOMMU used by this device */
292         struct dmar_domain *domain; /* pointer to domain */
293 };
294
295 static void flush_unmaps_timeout(unsigned long data);
296
297 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
298
299 #define HIGH_WATER_MARK 250
300 struct deferred_flush_tables {
301         int next;
302         struct iova *iova[HIGH_WATER_MARK];
303         struct dmar_domain *domain[HIGH_WATER_MARK];
304 };
305
306 static struct deferred_flush_tables *deferred_flush;
307
308 /* bitmap for indexing intel_iommus */
309 static int g_num_of_iommus;
310
311 static DEFINE_SPINLOCK(async_umap_flush_lock);
312 static LIST_HEAD(unmaps_to_do);
313
314 static int timer_on;
315 static long list_size;
316
317 static void domain_remove_dev_info(struct dmar_domain *domain);
318
319 #ifdef CONFIG_DMAR_DEFAULT_ON
320 int dmar_disabled = 0;
321 #else
322 int dmar_disabled = 1;
323 #endif /*CONFIG_DMAR_DEFAULT_ON*/
324
325 static int __initdata dmar_map_gfx = 1;
326 static int dmar_forcedac;
327 static int intel_iommu_strict;
328
329 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
330 static DEFINE_SPINLOCK(device_domain_lock);
331 static LIST_HEAD(device_domain_list);
332
333 static struct iommu_ops intel_iommu_ops;
334
335 static int __init intel_iommu_setup(char *str)
336 {
337         if (!str)
338                 return -EINVAL;
339         while (*str) {
340                 if (!strncmp(str, "on", 2)) {
341                         dmar_disabled = 0;
342                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
343                 } else if (!strncmp(str, "off", 3)) {
344                         dmar_disabled = 1;
345                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
346                 } else if (!strncmp(str, "igfx_off", 8)) {
347                         dmar_map_gfx = 0;
348                         printk(KERN_INFO
349                                 "Intel-IOMMU: disable GFX device mapping\n");
350                 } else if (!strncmp(str, "forcedac", 8)) {
351                         printk(KERN_INFO
352                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
353                         dmar_forcedac = 1;
354                 } else if (!strncmp(str, "strict", 6)) {
355                         printk(KERN_INFO
356                                 "Intel-IOMMU: disable batched IOTLB flush\n");
357                         intel_iommu_strict = 1;
358                 }
359
360                 str += strcspn(str, ",");
361                 while (*str == ',')
362                         str++;
363         }
364         return 0;
365 }
366 __setup("intel_iommu=", intel_iommu_setup);
367
368 static struct kmem_cache *iommu_domain_cache;
369 static struct kmem_cache *iommu_devinfo_cache;
370 static struct kmem_cache *iommu_iova_cache;
371
372 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
373 {
374         unsigned int flags;
375         void *vaddr;
376
377         /* trying to avoid low memory issues */
378         flags = current->flags & PF_MEMALLOC;
379         current->flags |= PF_MEMALLOC;
380         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
381         current->flags &= (~PF_MEMALLOC | flags);
382         return vaddr;
383 }
384
385
386 static inline void *alloc_pgtable_page(void)
387 {
388         unsigned int flags;
389         void *vaddr;
390
391         /* trying to avoid low memory issues */
392         flags = current->flags & PF_MEMALLOC;
393         current->flags |= PF_MEMALLOC;
394         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
395         current->flags &= (~PF_MEMALLOC | flags);
396         return vaddr;
397 }
398
399 static inline void free_pgtable_page(void *vaddr)
400 {
401         free_page((unsigned long)vaddr);
402 }
403
404 static inline void *alloc_domain_mem(void)
405 {
406         return iommu_kmem_cache_alloc(iommu_domain_cache);
407 }
408
409 static void free_domain_mem(void *vaddr)
410 {
411         kmem_cache_free(iommu_domain_cache, vaddr);
412 }
413
414 static inline void * alloc_devinfo_mem(void)
415 {
416         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
417 }
418
419 static inline void free_devinfo_mem(void *vaddr)
420 {
421         kmem_cache_free(iommu_devinfo_cache, vaddr);
422 }
423
424 struct iova *alloc_iova_mem(void)
425 {
426         return iommu_kmem_cache_alloc(iommu_iova_cache);
427 }
428
429 void free_iova_mem(struct iova *iova)
430 {
431         kmem_cache_free(iommu_iova_cache, iova);
432 }
433
434
435 static inline int width_to_agaw(int width);
436
437 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
438 {
439         unsigned long sagaw;
440         int agaw = -1;
441
442         sagaw = cap_sagaw(iommu->cap);
443         for (agaw = width_to_agaw(max_gaw);
444              agaw >= 0; agaw--) {
445                 if (test_bit(agaw, &sagaw))
446                         break;
447         }
448
449         return agaw;
450 }
451
452 /*
453  * Calculate max SAGAW for each iommu.
454  */
455 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
456 {
457         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
458 }
459
460 /*
461  * calculate agaw for each iommu.
462  * "SAGAW" may be different across iommus, use a default agaw, and
463  * get a supported less agaw for iommus that don't support the default agaw.
464  */
465 int iommu_calculate_agaw(struct intel_iommu *iommu)
466 {
467         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
468 }
469
470 /* This functionin only returns single iommu in a domain */
471 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
472 {
473         int iommu_id;
474
475         /* si_domain and vm domain should not get here. */
476         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
477         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
478
479         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
480         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
481                 return NULL;
482
483         return g_iommus[iommu_id];
484 }
485
486 static void domain_update_iommu_coherency(struct dmar_domain *domain)
487 {
488         int i;
489
490         domain->iommu_coherency = 1;
491
492         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
493         for (; i < g_num_of_iommus; ) {
494                 if (!ecap_coherent(g_iommus[i]->ecap)) {
495                         domain->iommu_coherency = 0;
496                         break;
497                 }
498                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
499         }
500 }
501
502 static void domain_update_iommu_snooping(struct dmar_domain *domain)
503 {
504         int i;
505
506         domain->iommu_snooping = 1;
507
508         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
509         for (; i < g_num_of_iommus; ) {
510                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
511                         domain->iommu_snooping = 0;
512                         break;
513                 }
514                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
515         }
516 }
517
518 /* Some capabilities may be different across iommus */
519 static void domain_update_iommu_cap(struct dmar_domain *domain)
520 {
521         domain_update_iommu_coherency(domain);
522         domain_update_iommu_snooping(domain);
523 }
524
525 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
526 {
527         struct dmar_drhd_unit *drhd = NULL;
528         int i;
529
530         for_each_drhd_unit(drhd) {
531                 if (drhd->ignored)
532                         continue;
533                 if (segment != drhd->segment)
534                         continue;
535
536                 for (i = 0; i < drhd->devices_cnt; i++) {
537                         if (drhd->devices[i] &&
538                             drhd->devices[i]->bus->number == bus &&
539                             drhd->devices[i]->devfn == devfn)
540                                 return drhd->iommu;
541                         if (drhd->devices[i] &&
542                             drhd->devices[i]->subordinate &&
543                             drhd->devices[i]->subordinate->number <= bus &&
544                             drhd->devices[i]->subordinate->subordinate >= bus)
545                                 return drhd->iommu;
546                 }
547
548                 if (drhd->include_all)
549                         return drhd->iommu;
550         }
551
552         return NULL;
553 }
554
555 static void domain_flush_cache(struct dmar_domain *domain,
556                                void *addr, int size)
557 {
558         if (!domain->iommu_coherency)
559                 clflush_cache_range(addr, size);
560 }
561
562 /* Gets context entry for a given bus and devfn */
563 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
564                 u8 bus, u8 devfn)
565 {
566         struct root_entry *root;
567         struct context_entry *context;
568         unsigned long phy_addr;
569         unsigned long flags;
570
571         spin_lock_irqsave(&iommu->lock, flags);
572         root = &iommu->root_entry[bus];
573         context = get_context_addr_from_root(root);
574         if (!context) {
575                 context = (struct context_entry *)alloc_pgtable_page();
576                 if (!context) {
577                         spin_unlock_irqrestore(&iommu->lock, flags);
578                         return NULL;
579                 }
580                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
581                 phy_addr = virt_to_phys((void *)context);
582                 set_root_value(root, phy_addr);
583                 set_root_present(root);
584                 __iommu_flush_cache(iommu, root, sizeof(*root));
585         }
586         spin_unlock_irqrestore(&iommu->lock, flags);
587         return &context[devfn];
588 }
589
590 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
591 {
592         struct root_entry *root;
593         struct context_entry *context;
594         int ret;
595         unsigned long flags;
596
597         spin_lock_irqsave(&iommu->lock, flags);
598         root = &iommu->root_entry[bus];
599         context = get_context_addr_from_root(root);
600         if (!context) {
601                 ret = 0;
602                 goto out;
603         }
604         ret = context_present(&context[devfn]);
605 out:
606         spin_unlock_irqrestore(&iommu->lock, flags);
607         return ret;
608 }
609
610 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
611 {
612         struct root_entry *root;
613         struct context_entry *context;
614         unsigned long flags;
615
616         spin_lock_irqsave(&iommu->lock, flags);
617         root = &iommu->root_entry[bus];
618         context = get_context_addr_from_root(root);
619         if (context) {
620                 context_clear_entry(&context[devfn]);
621                 __iommu_flush_cache(iommu, &context[devfn], \
622                         sizeof(*context));
623         }
624         spin_unlock_irqrestore(&iommu->lock, flags);
625 }
626
627 static void free_context_table(struct intel_iommu *iommu)
628 {
629         struct root_entry *root;
630         int i;
631         unsigned long flags;
632         struct context_entry *context;
633
634         spin_lock_irqsave(&iommu->lock, flags);
635         if (!iommu->root_entry) {
636                 goto out;
637         }
638         for (i = 0; i < ROOT_ENTRY_NR; i++) {
639                 root = &iommu->root_entry[i];
640                 context = get_context_addr_from_root(root);
641                 if (context)
642                         free_pgtable_page(context);
643         }
644         free_pgtable_page(iommu->root_entry);
645         iommu->root_entry = NULL;
646 out:
647         spin_unlock_irqrestore(&iommu->lock, flags);
648 }
649
650 /* page table handling */
651 #define LEVEL_STRIDE            (9)
652 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
653
654 static inline int agaw_to_level(int agaw)
655 {
656         return agaw + 2;
657 }
658
659 static inline int agaw_to_width(int agaw)
660 {
661         return 30 + agaw * LEVEL_STRIDE;
662
663 }
664
665 static inline int width_to_agaw(int width)
666 {
667         return (width - 30) / LEVEL_STRIDE;
668 }
669
670 static inline unsigned int level_to_offset_bits(int level)
671 {
672         return (level - 1) * LEVEL_STRIDE;
673 }
674
675 static inline int pfn_level_offset(unsigned long pfn, int level)
676 {
677         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
678 }
679
680 static inline unsigned long level_mask(int level)
681 {
682         return -1UL << level_to_offset_bits(level);
683 }
684
685 static inline unsigned long level_size(int level)
686 {
687         return 1UL << level_to_offset_bits(level);
688 }
689
690 static inline unsigned long align_to_level(unsigned long pfn, int level)
691 {
692         return (pfn + level_size(level) - 1) & level_mask(level);
693 }
694
695 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
696                                       unsigned long pfn)
697 {
698         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
699         struct dma_pte *parent, *pte = NULL;
700         int level = agaw_to_level(domain->agaw);
701         int offset;
702         unsigned long flags;
703
704         BUG_ON(!domain->pgd);
705         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
706         parent = domain->pgd;
707
708         spin_lock_irqsave(&domain->mapping_lock, flags);
709         while (level > 0) {
710                 void *tmp_page;
711
712                 offset = pfn_level_offset(pfn, level);
713                 pte = &parent[offset];
714                 if (level == 1)
715                         break;
716
717                 if (!dma_pte_present(pte)) {
718                         tmp_page = alloc_pgtable_page();
719
720                         if (!tmp_page) {
721                                 spin_unlock_irqrestore(&domain->mapping_lock,
722                                         flags);
723                                 return NULL;
724                         }
725                         domain_flush_cache(domain, tmp_page, PAGE_SIZE);
726                         dma_set_pte_pfn(pte, virt_to_dma_pfn(tmp_page));
727                         /*
728                          * high level table always sets r/w, last level page
729                          * table control read/write
730                          */
731                         dma_set_pte_readable(pte);
732                         dma_set_pte_writable(pte);
733                         domain_flush_cache(domain, pte, sizeof(*pte));
734                 }
735                 parent = phys_to_virt(dma_pte_addr(pte));
736                 level--;
737         }
738
739         spin_unlock_irqrestore(&domain->mapping_lock, flags);
740         return pte;
741 }
742
743 /* return address's pte at specific level */
744 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
745                                          unsigned long pfn,
746                                          int level)
747 {
748         struct dma_pte *parent, *pte = NULL;
749         int total = agaw_to_level(domain->agaw);
750         int offset;
751
752         parent = domain->pgd;
753         while (level <= total) {
754                 offset = pfn_level_offset(pfn, total);
755                 pte = &parent[offset];
756                 if (level == total)
757                         return pte;
758
759                 if (!dma_pte_present(pte))
760                         break;
761                 parent = phys_to_virt(dma_pte_addr(pte));
762                 total--;
763         }
764         return NULL;
765 }
766
767 /* clear one page's page table */
768 static void dma_pte_clear_one(struct dmar_domain *domain, unsigned long pfn)
769 {
770         struct dma_pte *pte = NULL;
771
772         /* get last level pte */
773         pte = dma_pfn_level_pte(domain, pfn, 1);
774
775         if (pte) {
776                 dma_clear_pte(pte);
777                 domain_flush_cache(domain, pte, sizeof(*pte));
778         }
779 }
780
781 /* clear last level pte, a tlb flush should be followed */
782 static void dma_pte_clear_range(struct dmar_domain *domain,
783                                 unsigned long start_pfn,
784                                 unsigned long last_pfn)
785 {
786         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
787
788         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
789         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
790
791         /* we don't need lock here; nobody else touches the iova range */
792         while (start_pfn <= last_pfn) {
793                 dma_pte_clear_one(domain, start_pfn);
794                 start_pfn++;
795         }
796 }
797
798 /* free page table pages. last level pte should already be cleared */
799 static void dma_pte_free_pagetable(struct dmar_domain *domain,
800                                    unsigned long start_pfn,
801                                    unsigned long last_pfn)
802 {
803         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
804         struct dma_pte *pte;
805         int total = agaw_to_level(domain->agaw);
806         int level;
807         unsigned long tmp;
808
809         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
810         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
811
812         /* we don't need lock here, nobody else touches the iova range */
813         level = 2;
814         while (level <= total) {
815                 tmp = align_to_level(start_pfn, level);
816
817                 /* Only clear this pte/pmd if we're asked to clear its
818                    _whole_ range */
819                 if (tmp + level_size(level) - 1 > last_pfn)
820                         return;
821
822                 while (tmp <= last_pfn) {
823                         pte = dma_pfn_level_pte(domain, tmp, level);
824                         if (pte) {
825                                 free_pgtable_page(
826                                         phys_to_virt(dma_pte_addr(pte)));
827                                 dma_clear_pte(pte);
828                                 domain_flush_cache(domain, pte, sizeof(*pte));
829                         }
830                         tmp += level_size(level);
831                 }
832                 level++;
833         }
834         /* free pgd */
835         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
836                 free_pgtable_page(domain->pgd);
837                 domain->pgd = NULL;
838         }
839 }
840
841 /* iommu handling */
842 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
843 {
844         struct root_entry *root;
845         unsigned long flags;
846
847         root = (struct root_entry *)alloc_pgtable_page();
848         if (!root)
849                 return -ENOMEM;
850
851         __iommu_flush_cache(iommu, root, ROOT_SIZE);
852
853         spin_lock_irqsave(&iommu->lock, flags);
854         iommu->root_entry = root;
855         spin_unlock_irqrestore(&iommu->lock, flags);
856
857         return 0;
858 }
859
860 static void iommu_set_root_entry(struct intel_iommu *iommu)
861 {
862         void *addr;
863         u32 sts;
864         unsigned long flag;
865
866         addr = iommu->root_entry;
867
868         spin_lock_irqsave(&iommu->register_lock, flag);
869         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
870
871         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
872
873         /* Make sure hardware complete it */
874         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
875                       readl, (sts & DMA_GSTS_RTPS), sts);
876
877         spin_unlock_irqrestore(&iommu->register_lock, flag);
878 }
879
880 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
881 {
882         u32 val;
883         unsigned long flag;
884
885         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
886                 return;
887
888         spin_lock_irqsave(&iommu->register_lock, flag);
889         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
890
891         /* Make sure hardware complete it */
892         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
893                       readl, (!(val & DMA_GSTS_WBFS)), val);
894
895         spin_unlock_irqrestore(&iommu->register_lock, flag);
896 }
897
898 /* return value determine if we need a write buffer flush */
899 static void __iommu_flush_context(struct intel_iommu *iommu,
900                                   u16 did, u16 source_id, u8 function_mask,
901                                   u64 type)
902 {
903         u64 val = 0;
904         unsigned long flag;
905
906         switch (type) {
907         case DMA_CCMD_GLOBAL_INVL:
908                 val = DMA_CCMD_GLOBAL_INVL;
909                 break;
910         case DMA_CCMD_DOMAIN_INVL:
911                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
912                 break;
913         case DMA_CCMD_DEVICE_INVL:
914                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
915                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
916                 break;
917         default:
918                 BUG();
919         }
920         val |= DMA_CCMD_ICC;
921
922         spin_lock_irqsave(&iommu->register_lock, flag);
923         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
924
925         /* Make sure hardware complete it */
926         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
927                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
928
929         spin_unlock_irqrestore(&iommu->register_lock, flag);
930 }
931
932 /* return value determine if we need a write buffer flush */
933 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
934                                 u64 addr, unsigned int size_order, u64 type)
935 {
936         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
937         u64 val = 0, val_iva = 0;
938         unsigned long flag;
939
940         switch (type) {
941         case DMA_TLB_GLOBAL_FLUSH:
942                 /* global flush doesn't need set IVA_REG */
943                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
944                 break;
945         case DMA_TLB_DSI_FLUSH:
946                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
947                 break;
948         case DMA_TLB_PSI_FLUSH:
949                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
950                 /* Note: always flush non-leaf currently */
951                 val_iva = size_order | addr;
952                 break;
953         default:
954                 BUG();
955         }
956         /* Note: set drain read/write */
957 #if 0
958         /*
959          * This is probably to be super secure.. Looks like we can
960          * ignore it without any impact.
961          */
962         if (cap_read_drain(iommu->cap))
963                 val |= DMA_TLB_READ_DRAIN;
964 #endif
965         if (cap_write_drain(iommu->cap))
966                 val |= DMA_TLB_WRITE_DRAIN;
967
968         spin_lock_irqsave(&iommu->register_lock, flag);
969         /* Note: Only uses first TLB reg currently */
970         if (val_iva)
971                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
972         dmar_writeq(iommu->reg + tlb_offset + 8, val);
973
974         /* Make sure hardware complete it */
975         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
976                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
977
978         spin_unlock_irqrestore(&iommu->register_lock, flag);
979
980         /* check IOTLB invalidation granularity */
981         if (DMA_TLB_IAIG(val) == 0)
982                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
983         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
984                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
985                         (unsigned long long)DMA_TLB_IIRG(type),
986                         (unsigned long long)DMA_TLB_IAIG(val));
987 }
988
989 static struct device_domain_info *iommu_support_dev_iotlb(
990         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
991 {
992         int found = 0;
993         unsigned long flags;
994         struct device_domain_info *info;
995         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
996
997         if (!ecap_dev_iotlb_support(iommu->ecap))
998                 return NULL;
999
1000         if (!iommu->qi)
1001                 return NULL;
1002
1003         spin_lock_irqsave(&device_domain_lock, flags);
1004         list_for_each_entry(info, &domain->devices, link)
1005                 if (info->bus == bus && info->devfn == devfn) {
1006                         found = 1;
1007                         break;
1008                 }
1009         spin_unlock_irqrestore(&device_domain_lock, flags);
1010
1011         if (!found || !info->dev)
1012                 return NULL;
1013
1014         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1015                 return NULL;
1016
1017         if (!dmar_find_matched_atsr_unit(info->dev))
1018                 return NULL;
1019
1020         info->iommu = iommu;
1021
1022         return info;
1023 }
1024
1025 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1026 {
1027         if (!info)
1028                 return;
1029
1030         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1031 }
1032
1033 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1034 {
1035         if (!info->dev || !pci_ats_enabled(info->dev))
1036                 return;
1037
1038         pci_disable_ats(info->dev);
1039 }
1040
1041 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1042                                   u64 addr, unsigned mask)
1043 {
1044         u16 sid, qdep;
1045         unsigned long flags;
1046         struct device_domain_info *info;
1047
1048         spin_lock_irqsave(&device_domain_lock, flags);
1049         list_for_each_entry(info, &domain->devices, link) {
1050                 if (!info->dev || !pci_ats_enabled(info->dev))
1051                         continue;
1052
1053                 sid = info->bus << 8 | info->devfn;
1054                 qdep = pci_ats_queue_depth(info->dev);
1055                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1056         }
1057         spin_unlock_irqrestore(&device_domain_lock, flags);
1058 }
1059
1060 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1061                                   u64 addr, unsigned int pages)
1062 {
1063         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1064
1065         BUG_ON(addr & (~VTD_PAGE_MASK));
1066         BUG_ON(pages == 0);
1067
1068         /*
1069          * Fallback to domain selective flush if no PSI support or the size is
1070          * too big.
1071          * PSI requires page size to be 2 ^ x, and the base address is naturally
1072          * aligned to the size
1073          */
1074         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1075                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1076                                                 DMA_TLB_DSI_FLUSH);
1077         else
1078                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1079                                                 DMA_TLB_PSI_FLUSH);
1080
1081         /*
1082          * In caching mode, domain ID 0 is reserved for non-present to present
1083          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1084          */
1085         if (!cap_caching_mode(iommu->cap) || did)
1086                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1087 }
1088
1089 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1090 {
1091         u32 pmen;
1092         unsigned long flags;
1093
1094         spin_lock_irqsave(&iommu->register_lock, flags);
1095         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1096         pmen &= ~DMA_PMEN_EPM;
1097         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1098
1099         /* wait for the protected region status bit to clear */
1100         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1101                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1102
1103         spin_unlock_irqrestore(&iommu->register_lock, flags);
1104 }
1105
1106 static int iommu_enable_translation(struct intel_iommu *iommu)
1107 {
1108         u32 sts;
1109         unsigned long flags;
1110
1111         spin_lock_irqsave(&iommu->register_lock, flags);
1112         iommu->gcmd |= DMA_GCMD_TE;
1113         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1114
1115         /* Make sure hardware complete it */
1116         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1117                       readl, (sts & DMA_GSTS_TES), sts);
1118
1119         spin_unlock_irqrestore(&iommu->register_lock, flags);
1120         return 0;
1121 }
1122
1123 static int iommu_disable_translation(struct intel_iommu *iommu)
1124 {
1125         u32 sts;
1126         unsigned long flag;
1127
1128         spin_lock_irqsave(&iommu->register_lock, flag);
1129         iommu->gcmd &= ~DMA_GCMD_TE;
1130         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1131
1132         /* Make sure hardware complete it */
1133         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1134                       readl, (!(sts & DMA_GSTS_TES)), sts);
1135
1136         spin_unlock_irqrestore(&iommu->register_lock, flag);
1137         return 0;
1138 }
1139
1140
1141 static int iommu_init_domains(struct intel_iommu *iommu)
1142 {
1143         unsigned long ndomains;
1144         unsigned long nlongs;
1145
1146         ndomains = cap_ndoms(iommu->cap);
1147         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1148         nlongs = BITS_TO_LONGS(ndomains);
1149
1150         /* TBD: there might be 64K domains,
1151          * consider other allocation for future chip
1152          */
1153         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1154         if (!iommu->domain_ids) {
1155                 printk(KERN_ERR "Allocating domain id array failed\n");
1156                 return -ENOMEM;
1157         }
1158         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1159                         GFP_KERNEL);
1160         if (!iommu->domains) {
1161                 printk(KERN_ERR "Allocating domain array failed\n");
1162                 kfree(iommu->domain_ids);
1163                 return -ENOMEM;
1164         }
1165
1166         spin_lock_init(&iommu->lock);
1167
1168         /*
1169          * if Caching mode is set, then invalid translations are tagged
1170          * with domainid 0. Hence we need to pre-allocate it.
1171          */
1172         if (cap_caching_mode(iommu->cap))
1173                 set_bit(0, iommu->domain_ids);
1174         return 0;
1175 }
1176
1177
1178 static void domain_exit(struct dmar_domain *domain);
1179 static void vm_domain_exit(struct dmar_domain *domain);
1180
1181 void free_dmar_iommu(struct intel_iommu *iommu)
1182 {
1183         struct dmar_domain *domain;
1184         int i;
1185         unsigned long flags;
1186
1187         i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1188         for (; i < cap_ndoms(iommu->cap); ) {
1189                 domain = iommu->domains[i];
1190                 clear_bit(i, iommu->domain_ids);
1191
1192                 spin_lock_irqsave(&domain->iommu_lock, flags);
1193                 if (--domain->iommu_count == 0) {
1194                         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1195                                 vm_domain_exit(domain);
1196                         else
1197                                 domain_exit(domain);
1198                 }
1199                 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1200
1201                 i = find_next_bit(iommu->domain_ids,
1202                         cap_ndoms(iommu->cap), i+1);
1203         }
1204
1205         if (iommu->gcmd & DMA_GCMD_TE)
1206                 iommu_disable_translation(iommu);
1207
1208         if (iommu->irq) {
1209                 set_irq_data(iommu->irq, NULL);
1210                 /* This will mask the irq */
1211                 free_irq(iommu->irq, iommu);
1212                 destroy_irq(iommu->irq);
1213         }
1214
1215         kfree(iommu->domains);
1216         kfree(iommu->domain_ids);
1217
1218         g_iommus[iommu->seq_id] = NULL;
1219
1220         /* if all iommus are freed, free g_iommus */
1221         for (i = 0; i < g_num_of_iommus; i++) {
1222                 if (g_iommus[i])
1223                         break;
1224         }
1225
1226         if (i == g_num_of_iommus)
1227                 kfree(g_iommus);
1228
1229         /* free context mapping */
1230         free_context_table(iommu);
1231 }
1232
1233 static struct dmar_domain *alloc_domain(void)
1234 {
1235         struct dmar_domain *domain;
1236
1237         domain = alloc_domain_mem();
1238         if (!domain)
1239                 return NULL;
1240
1241         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1242         domain->flags = 0;
1243
1244         return domain;
1245 }
1246
1247 static int iommu_attach_domain(struct dmar_domain *domain,
1248                                struct intel_iommu *iommu)
1249 {
1250         int num;
1251         unsigned long ndomains;
1252         unsigned long flags;
1253
1254         ndomains = cap_ndoms(iommu->cap);
1255
1256         spin_lock_irqsave(&iommu->lock, flags);
1257
1258         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1259         if (num >= ndomains) {
1260                 spin_unlock_irqrestore(&iommu->lock, flags);
1261                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1262                 return -ENOMEM;
1263         }
1264
1265         domain->id = num;
1266         set_bit(num, iommu->domain_ids);
1267         set_bit(iommu->seq_id, &domain->iommu_bmp);
1268         iommu->domains[num] = domain;
1269         spin_unlock_irqrestore(&iommu->lock, flags);
1270
1271         return 0;
1272 }
1273
1274 static void iommu_detach_domain(struct dmar_domain *domain,
1275                                 struct intel_iommu *iommu)
1276 {
1277         unsigned long flags;
1278         int num, ndomains;
1279         int found = 0;
1280
1281         spin_lock_irqsave(&iommu->lock, flags);
1282         ndomains = cap_ndoms(iommu->cap);
1283         num = find_first_bit(iommu->domain_ids, ndomains);
1284         for (; num < ndomains; ) {
1285                 if (iommu->domains[num] == domain) {
1286                         found = 1;
1287                         break;
1288                 }
1289                 num = find_next_bit(iommu->domain_ids,
1290                                     cap_ndoms(iommu->cap), num+1);
1291         }
1292
1293         if (found) {
1294                 clear_bit(num, iommu->domain_ids);
1295                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1296                 iommu->domains[num] = NULL;
1297         }
1298         spin_unlock_irqrestore(&iommu->lock, flags);
1299 }
1300
1301 static struct iova_domain reserved_iova_list;
1302 static struct lock_class_key reserved_alloc_key;
1303 static struct lock_class_key reserved_rbtree_key;
1304
1305 static void dmar_init_reserved_ranges(void)
1306 {
1307         struct pci_dev *pdev = NULL;
1308         struct iova *iova;
1309         int i;
1310         u64 addr, size;
1311
1312         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1313
1314         lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1315                 &reserved_alloc_key);
1316         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1317                 &reserved_rbtree_key);
1318
1319         /* IOAPIC ranges shouldn't be accessed by DMA */
1320         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1321                 IOVA_PFN(IOAPIC_RANGE_END));
1322         if (!iova)
1323                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1324
1325         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1326         for_each_pci_dev(pdev) {
1327                 struct resource *r;
1328
1329                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1330                         r = &pdev->resource[i];
1331                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1332                                 continue;
1333                         addr = r->start;
1334                         addr &= PHYSICAL_PAGE_MASK;
1335                         size = r->end - addr;
1336                         size = PAGE_ALIGN(size);
1337                         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr),
1338                                 IOVA_PFN(size + addr) - 1);
1339                         if (!iova)
1340                                 printk(KERN_ERR "Reserve iova failed\n");
1341                 }
1342         }
1343
1344 }
1345
1346 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1347 {
1348         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1349 }
1350
1351 static inline int guestwidth_to_adjustwidth(int gaw)
1352 {
1353         int agaw;
1354         int r = (gaw - 12) % 9;
1355
1356         if (r == 0)
1357                 agaw = gaw;
1358         else
1359                 agaw = gaw + 9 - r;
1360         if (agaw > 64)
1361                 agaw = 64;
1362         return agaw;
1363 }
1364
1365 static int domain_init(struct dmar_domain *domain, int guest_width)
1366 {
1367         struct intel_iommu *iommu;
1368         int adjust_width, agaw;
1369         unsigned long sagaw;
1370
1371         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1372         spin_lock_init(&domain->mapping_lock);
1373         spin_lock_init(&domain->iommu_lock);
1374
1375         domain_reserve_special_ranges(domain);
1376
1377         /* calculate AGAW */
1378         iommu = domain_get_iommu(domain);
1379         if (guest_width > cap_mgaw(iommu->cap))
1380                 guest_width = cap_mgaw(iommu->cap);
1381         domain->gaw = guest_width;
1382         adjust_width = guestwidth_to_adjustwidth(guest_width);
1383         agaw = width_to_agaw(adjust_width);
1384         sagaw = cap_sagaw(iommu->cap);
1385         if (!test_bit(agaw, &sagaw)) {
1386                 /* hardware doesn't support it, choose a bigger one */
1387                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1388                 agaw = find_next_bit(&sagaw, 5, agaw);
1389                 if (agaw >= 5)
1390                         return -ENODEV;
1391         }
1392         domain->agaw = agaw;
1393         INIT_LIST_HEAD(&domain->devices);
1394
1395         if (ecap_coherent(iommu->ecap))
1396                 domain->iommu_coherency = 1;
1397         else
1398                 domain->iommu_coherency = 0;
1399
1400         if (ecap_sc_support(iommu->ecap))
1401                 domain->iommu_snooping = 1;
1402         else
1403                 domain->iommu_snooping = 0;
1404
1405         domain->iommu_count = 1;
1406
1407         /* always allocate the top pgd */
1408         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1409         if (!domain->pgd)
1410                 return -ENOMEM;
1411         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1412         return 0;
1413 }
1414
1415 static void domain_exit(struct dmar_domain *domain)
1416 {
1417         struct dmar_drhd_unit *drhd;
1418         struct intel_iommu *iommu;
1419
1420         /* Domain 0 is reserved, so dont process it */
1421         if (!domain)
1422                 return;
1423
1424         domain_remove_dev_info(domain);
1425         /* destroy iovas */
1426         put_iova_domain(&domain->iovad);
1427
1428         /* clear ptes */
1429         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1430
1431         /* free page tables */
1432         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1433
1434         for_each_active_iommu(iommu, drhd)
1435                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1436                         iommu_detach_domain(domain, iommu);
1437
1438         free_domain_mem(domain);
1439 }
1440
1441 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1442                                  u8 bus, u8 devfn, int translation)
1443 {
1444         struct context_entry *context;
1445         unsigned long flags;
1446         struct intel_iommu *iommu;
1447         struct dma_pte *pgd;
1448         unsigned long num;
1449         unsigned long ndomains;
1450         int id;
1451         int agaw;
1452         struct device_domain_info *info = NULL;
1453
1454         pr_debug("Set context mapping for %02x:%02x.%d\n",
1455                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1456
1457         BUG_ON(!domain->pgd);
1458         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1459                translation != CONTEXT_TT_MULTI_LEVEL);
1460
1461         iommu = device_to_iommu(segment, bus, devfn);
1462         if (!iommu)
1463                 return -ENODEV;
1464
1465         context = device_to_context_entry(iommu, bus, devfn);
1466         if (!context)
1467                 return -ENOMEM;
1468         spin_lock_irqsave(&iommu->lock, flags);
1469         if (context_present(context)) {
1470                 spin_unlock_irqrestore(&iommu->lock, flags);
1471                 return 0;
1472         }
1473
1474         id = domain->id;
1475         pgd = domain->pgd;
1476
1477         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1478             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1479                 int found = 0;
1480
1481                 /* find an available domain id for this device in iommu */
1482                 ndomains = cap_ndoms(iommu->cap);
1483                 num = find_first_bit(iommu->domain_ids, ndomains);
1484                 for (; num < ndomains; ) {
1485                         if (iommu->domains[num] == domain) {
1486                                 id = num;
1487                                 found = 1;
1488                                 break;
1489                         }
1490                         num = find_next_bit(iommu->domain_ids,
1491                                             cap_ndoms(iommu->cap), num+1);
1492                 }
1493
1494                 if (found == 0) {
1495                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1496                         if (num >= ndomains) {
1497                                 spin_unlock_irqrestore(&iommu->lock, flags);
1498                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1499                                 return -EFAULT;
1500                         }
1501
1502                         set_bit(num, iommu->domain_ids);
1503                         set_bit(iommu->seq_id, &domain->iommu_bmp);
1504                         iommu->domains[num] = domain;
1505                         id = num;
1506                 }
1507
1508                 /* Skip top levels of page tables for
1509                  * iommu which has less agaw than default.
1510                  */
1511                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1512                         pgd = phys_to_virt(dma_pte_addr(pgd));
1513                         if (!dma_pte_present(pgd)) {
1514                                 spin_unlock_irqrestore(&iommu->lock, flags);
1515                                 return -ENOMEM;
1516                         }
1517                 }
1518         }
1519
1520         context_set_domain_id(context, id);
1521
1522         if (translation != CONTEXT_TT_PASS_THROUGH) {
1523                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1524                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1525                                      CONTEXT_TT_MULTI_LEVEL;
1526         }
1527         /*
1528          * In pass through mode, AW must be programmed to indicate the largest
1529          * AGAW value supported by hardware. And ASR is ignored by hardware.
1530          */
1531         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1532                 context_set_address_width(context, iommu->msagaw);
1533         else {
1534                 context_set_address_root(context, virt_to_phys(pgd));
1535                 context_set_address_width(context, iommu->agaw);
1536         }
1537
1538         context_set_translation_type(context, translation);
1539         context_set_fault_enable(context);
1540         context_set_present(context);
1541         domain_flush_cache(domain, context, sizeof(*context));
1542
1543         /*
1544          * It's a non-present to present mapping. If hardware doesn't cache
1545          * non-present entry we only need to flush the write-buffer. If the
1546          * _does_ cache non-present entries, then it does so in the special
1547          * domain #0, which we have to flush:
1548          */
1549         if (cap_caching_mode(iommu->cap)) {
1550                 iommu->flush.flush_context(iommu, 0,
1551                                            (((u16)bus) << 8) | devfn,
1552                                            DMA_CCMD_MASK_NOBIT,
1553                                            DMA_CCMD_DEVICE_INVL);
1554                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1555         } else {
1556                 iommu_flush_write_buffer(iommu);
1557         }
1558         iommu_enable_dev_iotlb(info);
1559         spin_unlock_irqrestore(&iommu->lock, flags);
1560
1561         spin_lock_irqsave(&domain->iommu_lock, flags);
1562         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1563                 domain->iommu_count++;
1564                 domain_update_iommu_cap(domain);
1565         }
1566         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1567         return 0;
1568 }
1569
1570 static int
1571 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1572                         int translation)
1573 {
1574         int ret;
1575         struct pci_dev *tmp, *parent;
1576
1577         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1578                                          pdev->bus->number, pdev->devfn,
1579                                          translation);
1580         if (ret)
1581                 return ret;
1582
1583         /* dependent device mapping */
1584         tmp = pci_find_upstream_pcie_bridge(pdev);
1585         if (!tmp)
1586                 return 0;
1587         /* Secondary interface's bus number and devfn 0 */
1588         parent = pdev->bus->self;
1589         while (parent != tmp) {
1590                 ret = domain_context_mapping_one(domain,
1591                                                  pci_domain_nr(parent->bus),
1592                                                  parent->bus->number,
1593                                                  parent->devfn, translation);
1594                 if (ret)
1595                         return ret;
1596                 parent = parent->bus->self;
1597         }
1598         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1599                 return domain_context_mapping_one(domain,
1600                                         pci_domain_nr(tmp->subordinate),
1601                                         tmp->subordinate->number, 0,
1602                                         translation);
1603         else /* this is a legacy PCI bridge */
1604                 return domain_context_mapping_one(domain,
1605                                                   pci_domain_nr(tmp->bus),
1606                                                   tmp->bus->number,
1607                                                   tmp->devfn,
1608                                                   translation);
1609 }
1610
1611 static int domain_context_mapped(struct pci_dev *pdev)
1612 {
1613         int ret;
1614         struct pci_dev *tmp, *parent;
1615         struct intel_iommu *iommu;
1616
1617         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1618                                 pdev->devfn);
1619         if (!iommu)
1620                 return -ENODEV;
1621
1622         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1623         if (!ret)
1624                 return ret;
1625         /* dependent device mapping */
1626         tmp = pci_find_upstream_pcie_bridge(pdev);
1627         if (!tmp)
1628                 return ret;
1629         /* Secondary interface's bus number and devfn 0 */
1630         parent = pdev->bus->self;
1631         while (parent != tmp) {
1632                 ret = device_context_mapped(iommu, parent->bus->number,
1633                                             parent->devfn);
1634                 if (!ret)
1635                         return ret;
1636                 parent = parent->bus->self;
1637         }
1638         if (tmp->is_pcie)
1639                 return device_context_mapped(iommu, tmp->subordinate->number,
1640                                              0);
1641         else
1642                 return device_context_mapped(iommu, tmp->bus->number,
1643                                              tmp->devfn);
1644 }
1645
1646 static int
1647 domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
1648                         u64 hpa, size_t size, int prot)
1649 {
1650         unsigned long start_pfn = hpa >> VTD_PAGE_SHIFT;
1651         unsigned long last_pfn = (hpa + size - 1) >> VTD_PAGE_SHIFT;
1652         struct dma_pte *pte;
1653         int index = 0;
1654         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1655
1656         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
1657
1658         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1659                 return -EINVAL;
1660
1661         while (start_pfn <= last_pfn) {
1662                 pte = pfn_to_dma_pte(domain, (iova >> VTD_PAGE_SHIFT) + index);
1663                 if (!pte)
1664                         return -ENOMEM;
1665                 /* We don't need lock here, nobody else
1666                  * touches the iova range
1667                  */
1668                 BUG_ON(dma_pte_addr(pte));
1669                 dma_set_pte_pfn(pte, start_pfn);
1670                 dma_set_pte_prot(pte, prot);
1671                 if (prot & DMA_PTE_SNP)
1672                         dma_set_pte_snp(pte);
1673                 domain_flush_cache(domain, pte, sizeof(*pte));
1674                 start_pfn++;
1675                 index++;
1676         }
1677         return 0;
1678 }
1679
1680 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1681 {
1682         if (!iommu)
1683                 return;
1684
1685         clear_context_table(iommu, bus, devfn);
1686         iommu->flush.flush_context(iommu, 0, 0, 0,
1687                                            DMA_CCMD_GLOBAL_INVL);
1688         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1689 }
1690
1691 static void domain_remove_dev_info(struct dmar_domain *domain)
1692 {
1693         struct device_domain_info *info;
1694         unsigned long flags;
1695         struct intel_iommu *iommu;
1696
1697         spin_lock_irqsave(&device_domain_lock, flags);
1698         while (!list_empty(&domain->devices)) {
1699                 info = list_entry(domain->devices.next,
1700                         struct device_domain_info, link);
1701                 list_del(&info->link);
1702                 list_del(&info->global);
1703                 if (info->dev)
1704                         info->dev->dev.archdata.iommu = NULL;
1705                 spin_unlock_irqrestore(&device_domain_lock, flags);
1706
1707                 iommu_disable_dev_iotlb(info);
1708                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1709                 iommu_detach_dev(iommu, info->bus, info->devfn);
1710                 free_devinfo_mem(info);
1711
1712                 spin_lock_irqsave(&device_domain_lock, flags);
1713         }
1714         spin_unlock_irqrestore(&device_domain_lock, flags);
1715 }
1716
1717 /*
1718  * find_domain
1719  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1720  */
1721 static struct dmar_domain *
1722 find_domain(struct pci_dev *pdev)
1723 {
1724         struct device_domain_info *info;
1725
1726         /* No lock here, assumes no domain exit in normal case */
1727         info = pdev->dev.archdata.iommu;
1728         if (info)
1729                 return info->domain;
1730         return NULL;
1731 }
1732
1733 /* domain is initialized */
1734 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1735 {
1736         struct dmar_domain *domain, *found = NULL;
1737         struct intel_iommu *iommu;
1738         struct dmar_drhd_unit *drhd;
1739         struct device_domain_info *info, *tmp;
1740         struct pci_dev *dev_tmp;
1741         unsigned long flags;
1742         int bus = 0, devfn = 0;
1743         int segment;
1744         int ret;
1745
1746         domain = find_domain(pdev);
1747         if (domain)
1748                 return domain;
1749
1750         segment = pci_domain_nr(pdev->bus);
1751
1752         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1753         if (dev_tmp) {
1754                 if (dev_tmp->is_pcie) {
1755                         bus = dev_tmp->subordinate->number;
1756                         devfn = 0;
1757                 } else {
1758                         bus = dev_tmp->bus->number;
1759                         devfn = dev_tmp->devfn;
1760                 }
1761                 spin_lock_irqsave(&device_domain_lock, flags);
1762                 list_for_each_entry(info, &device_domain_list, global) {
1763                         if (info->segment == segment &&
1764                             info->bus == bus && info->devfn == devfn) {
1765                                 found = info->domain;
1766                                 break;
1767                         }
1768                 }
1769                 spin_unlock_irqrestore(&device_domain_lock, flags);
1770                 /* pcie-pci bridge already has a domain, uses it */
1771                 if (found) {
1772                         domain = found;
1773                         goto found_domain;
1774                 }
1775         }
1776
1777         domain = alloc_domain();
1778         if (!domain)
1779                 goto error;
1780
1781         /* Allocate new domain for the device */
1782         drhd = dmar_find_matched_drhd_unit(pdev);
1783         if (!drhd) {
1784                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1785                         pci_name(pdev));
1786                 return NULL;
1787         }
1788         iommu = drhd->iommu;
1789
1790         ret = iommu_attach_domain(domain, iommu);
1791         if (ret) {
1792                 domain_exit(domain);
1793                 goto error;
1794         }
1795
1796         if (domain_init(domain, gaw)) {
1797                 domain_exit(domain);
1798                 goto error;
1799         }
1800
1801         /* register pcie-to-pci device */
1802         if (dev_tmp) {
1803                 info = alloc_devinfo_mem();
1804                 if (!info) {
1805                         domain_exit(domain);
1806                         goto error;
1807                 }
1808                 info->segment = segment;
1809                 info->bus = bus;
1810                 info->devfn = devfn;
1811                 info->dev = NULL;
1812                 info->domain = domain;
1813                 /* This domain is shared by devices under p2p bridge */
1814                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1815
1816                 /* pcie-to-pci bridge already has a domain, uses it */
1817                 found = NULL;
1818                 spin_lock_irqsave(&device_domain_lock, flags);
1819                 list_for_each_entry(tmp, &device_domain_list, global) {
1820                         if (tmp->segment == segment &&
1821                             tmp->bus == bus && tmp->devfn == devfn) {
1822                                 found = tmp->domain;
1823                                 break;
1824                         }
1825                 }
1826                 if (found) {
1827                         free_devinfo_mem(info);
1828                         domain_exit(domain);
1829                         domain = found;
1830                 } else {
1831                         list_add(&info->link, &domain->devices);
1832                         list_add(&info->global, &device_domain_list);
1833                 }
1834                 spin_unlock_irqrestore(&device_domain_lock, flags);
1835         }
1836
1837 found_domain:
1838         info = alloc_devinfo_mem();
1839         if (!info)
1840                 goto error;
1841         info->segment = segment;
1842         info->bus = pdev->bus->number;
1843         info->devfn = pdev->devfn;
1844         info->dev = pdev;
1845         info->domain = domain;
1846         spin_lock_irqsave(&device_domain_lock, flags);
1847         /* somebody is fast */
1848         found = find_domain(pdev);
1849         if (found != NULL) {
1850                 spin_unlock_irqrestore(&device_domain_lock, flags);
1851                 if (found != domain) {
1852                         domain_exit(domain);
1853                         domain = found;
1854                 }
1855                 free_devinfo_mem(info);
1856                 return domain;
1857         }
1858         list_add(&info->link, &domain->devices);
1859         list_add(&info->global, &device_domain_list);
1860         pdev->dev.archdata.iommu = info;
1861         spin_unlock_irqrestore(&device_domain_lock, flags);
1862         return domain;
1863 error:
1864         /* recheck it here, maybe others set it */
1865         return find_domain(pdev);
1866 }
1867
1868 static int iommu_identity_mapping;
1869
1870 static int iommu_domain_identity_map(struct dmar_domain *domain,
1871                                      unsigned long long start,
1872                                      unsigned long long end)
1873 {
1874         unsigned long size;
1875         unsigned long long base;
1876
1877         /* The address might not be aligned */
1878         base = start & PAGE_MASK;
1879         size = end - base;
1880         size = PAGE_ALIGN(size);
1881         if (!reserve_iova(&domain->iovad, IOVA_PFN(base),
1882                         IOVA_PFN(base + size) - 1)) {
1883                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1884                 return -ENOMEM;
1885         }
1886
1887         pr_debug("Mapping reserved region %lx@%llx for domain %d\n",
1888                  size, base, domain->id);
1889         /*
1890          * RMRR range might have overlap with physical memory range,
1891          * clear it first
1892          */
1893         dma_pte_clear_range(domain, base >> VTD_PAGE_SHIFT,
1894                             (base + size - 1) >> VTD_PAGE_SHIFT);
1895
1896         return domain_page_mapping(domain, base, base, size,
1897                                    DMA_PTE_READ|DMA_PTE_WRITE);
1898 }
1899
1900 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1901                                       unsigned long long start,
1902                                       unsigned long long end)
1903 {
1904         struct dmar_domain *domain;
1905         int ret;
1906
1907         printk(KERN_INFO
1908                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1909                pci_name(pdev), start, end);
1910
1911         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1912         if (!domain)
1913                 return -ENOMEM;
1914
1915         ret = iommu_domain_identity_map(domain, start, end);
1916         if (ret)
1917                 goto error;
1918
1919         /* context entry init */
1920         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1921         if (ret)
1922                 goto error;
1923
1924         return 0;
1925
1926  error:
1927         domain_exit(domain);
1928         return ret;
1929 }
1930
1931 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1932         struct pci_dev *pdev)
1933 {
1934         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1935                 return 0;
1936         return iommu_prepare_identity_map(pdev, rmrr->base_address,
1937                 rmrr->end_address + 1);
1938 }
1939
1940 #ifdef CONFIG_DMAR_FLOPPY_WA
1941 static inline void iommu_prepare_isa(void)
1942 {
1943         struct pci_dev *pdev;
1944         int ret;
1945
1946         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1947         if (!pdev)
1948                 return;
1949
1950         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1951         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1952
1953         if (ret)
1954                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
1955                        "floppy might not work\n");
1956
1957 }
1958 #else
1959 static inline void iommu_prepare_isa(void)
1960 {
1961         return;
1962 }
1963 #endif /* !CONFIG_DMAR_FLPY_WA */
1964
1965 /* Initialize each context entry as pass through.*/
1966 static int __init init_context_pass_through(void)
1967 {
1968         struct pci_dev *pdev = NULL;
1969         struct dmar_domain *domain;
1970         int ret;
1971
1972         for_each_pci_dev(pdev) {
1973                 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1974                 ret = domain_context_mapping(domain, pdev,
1975                                              CONTEXT_TT_PASS_THROUGH);
1976                 if (ret)
1977                         return ret;
1978         }
1979         return 0;
1980 }
1981
1982 static int md_domain_init(struct dmar_domain *domain, int guest_width);
1983
1984 static int __init si_domain_work_fn(unsigned long start_pfn,
1985                                     unsigned long end_pfn, void *datax)
1986 {
1987         int *ret = datax;
1988
1989         *ret = iommu_domain_identity_map(si_domain,
1990                                          (uint64_t)start_pfn << PAGE_SHIFT,
1991                                          (uint64_t)end_pfn << PAGE_SHIFT);
1992         return *ret;
1993
1994 }
1995
1996 static int si_domain_init(void)
1997 {
1998         struct dmar_drhd_unit *drhd;
1999         struct intel_iommu *iommu;
2000         int nid, ret = 0;
2001
2002         si_domain = alloc_domain();
2003         if (!si_domain)
2004                 return -EFAULT;
2005
2006         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2007
2008         for_each_active_iommu(iommu, drhd) {
2009                 ret = iommu_attach_domain(si_domain, iommu);
2010                 if (ret) {
2011                         domain_exit(si_domain);
2012                         return -EFAULT;
2013                 }
2014         }
2015
2016         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2017                 domain_exit(si_domain);
2018                 return -EFAULT;
2019         }
2020
2021         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2022
2023         for_each_online_node(nid) {
2024                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2025                 if (ret)
2026                         return ret;
2027         }
2028
2029         return 0;
2030 }
2031
2032 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2033                                           struct pci_dev *pdev);
2034 static int identity_mapping(struct pci_dev *pdev)
2035 {
2036         struct device_domain_info *info;
2037
2038         if (likely(!iommu_identity_mapping))
2039                 return 0;
2040
2041
2042         list_for_each_entry(info, &si_domain->devices, link)
2043                 if (info->dev == pdev)
2044                         return 1;
2045         return 0;
2046 }
2047
2048 static int domain_add_dev_info(struct dmar_domain *domain,
2049                                   struct pci_dev *pdev)
2050 {
2051         struct device_domain_info *info;
2052         unsigned long flags;
2053
2054         info = alloc_devinfo_mem();
2055         if (!info)
2056                 return -ENOMEM;
2057
2058         info->segment = pci_domain_nr(pdev->bus);
2059         info->bus = pdev->bus->number;
2060         info->devfn = pdev->devfn;
2061         info->dev = pdev;
2062         info->domain = domain;
2063
2064         spin_lock_irqsave(&device_domain_lock, flags);
2065         list_add(&info->link, &domain->devices);
2066         list_add(&info->global, &device_domain_list);
2067         pdev->dev.archdata.iommu = info;
2068         spin_unlock_irqrestore(&device_domain_lock, flags);
2069
2070         return 0;
2071 }
2072
2073 static int iommu_prepare_static_identity_mapping(void)
2074 {
2075         struct pci_dev *pdev = NULL;
2076         int ret;
2077
2078         ret = si_domain_init();
2079         if (ret)
2080                 return -EFAULT;
2081
2082         for_each_pci_dev(pdev) {
2083                 printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2084                        pci_name(pdev));
2085
2086                 ret = domain_context_mapping(si_domain, pdev,
2087                                              CONTEXT_TT_MULTI_LEVEL);
2088                 if (ret)
2089                         return ret;
2090                 ret = domain_add_dev_info(si_domain, pdev);
2091                 if (ret)
2092                         return ret;
2093         }
2094
2095         return 0;
2096 }
2097
2098 int __init init_dmars(void)
2099 {
2100         struct dmar_drhd_unit *drhd;
2101         struct dmar_rmrr_unit *rmrr;
2102         struct pci_dev *pdev;
2103         struct intel_iommu *iommu;
2104         int i, ret;
2105         int pass_through = 1;
2106
2107         /*
2108          * In case pass through can not be enabled, iommu tries to use identity
2109          * mapping.
2110          */
2111         if (iommu_pass_through)
2112                 iommu_identity_mapping = 1;
2113
2114         /*
2115          * for each drhd
2116          *    allocate root
2117          *    initialize and program root entry to not present
2118          * endfor
2119          */
2120         for_each_drhd_unit(drhd) {
2121                 g_num_of_iommus++;
2122                 /*
2123                  * lock not needed as this is only incremented in the single
2124                  * threaded kernel __init code path all other access are read
2125                  * only
2126                  */
2127         }
2128
2129         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2130                         GFP_KERNEL);
2131         if (!g_iommus) {
2132                 printk(KERN_ERR "Allocating global iommu array failed\n");
2133                 ret = -ENOMEM;
2134                 goto error;
2135         }
2136
2137         deferred_flush = kzalloc(g_num_of_iommus *
2138                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2139         if (!deferred_flush) {
2140                 kfree(g_iommus);
2141                 ret = -ENOMEM;
2142                 goto error;
2143         }
2144
2145         for_each_drhd_unit(drhd) {
2146                 if (drhd->ignored)
2147                         continue;
2148
2149                 iommu = drhd->iommu;
2150                 g_iommus[iommu->seq_id] = iommu;
2151
2152                 ret = iommu_init_domains(iommu);
2153                 if (ret)
2154                         goto error;
2155
2156                 /*
2157                  * TBD:
2158                  * we could share the same root & context tables
2159                  * amoung all IOMMU's. Need to Split it later.
2160                  */
2161                 ret = iommu_alloc_root_entry(iommu);
2162                 if (ret) {
2163                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2164                         goto error;
2165                 }
2166                 if (!ecap_pass_through(iommu->ecap))
2167                         pass_through = 0;
2168         }
2169         if (iommu_pass_through)
2170                 if (!pass_through) {
2171                         printk(KERN_INFO
2172                                "Pass Through is not supported by hardware.\n");
2173                         iommu_pass_through = 0;
2174                 }
2175
2176         /*
2177          * Start from the sane iommu hardware state.
2178          */
2179         for_each_drhd_unit(drhd) {
2180                 if (drhd->ignored)
2181                         continue;
2182
2183                 iommu = drhd->iommu;
2184
2185                 /*
2186                  * If the queued invalidation is already initialized by us
2187                  * (for example, while enabling interrupt-remapping) then
2188                  * we got the things already rolling from a sane state.
2189                  */
2190                 if (iommu->qi)
2191                         continue;
2192
2193                 /*
2194                  * Clear any previous faults.
2195                  */
2196                 dmar_fault(-1, iommu);
2197                 /*
2198                  * Disable queued invalidation if supported and already enabled
2199                  * before OS handover.
2200                  */
2201                 dmar_disable_qi(iommu);
2202         }
2203
2204         for_each_drhd_unit(drhd) {
2205                 if (drhd->ignored)
2206                         continue;
2207
2208                 iommu = drhd->iommu;
2209
2210                 if (dmar_enable_qi(iommu)) {
2211                         /*
2212                          * Queued Invalidate not enabled, use Register Based
2213                          * Invalidate
2214                          */
2215                         iommu->flush.flush_context = __iommu_flush_context;
2216                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2217                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2218                                "invalidation\n",
2219                                (unsigned long long)drhd->reg_base_addr);
2220                 } else {
2221                         iommu->flush.flush_context = qi_flush_context;
2222                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2223                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2224                                "invalidation\n",
2225                                (unsigned long long)drhd->reg_base_addr);
2226                 }
2227         }
2228
2229         /*
2230          * If pass through is set and enabled, context entries of all pci
2231          * devices are intialized by pass through translation type.
2232          */
2233         if (iommu_pass_through) {
2234                 ret = init_context_pass_through();
2235                 if (ret) {
2236                         printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2237                         iommu_pass_through = 0;
2238                 }
2239         }
2240
2241         /*
2242          * If pass through is not set or not enabled, setup context entries for
2243          * identity mappings for rmrr, gfx, and isa and may fall back to static
2244          * identity mapping if iommu_identity_mapping is set.
2245          */
2246         if (!iommu_pass_through) {
2247                 if (iommu_identity_mapping)
2248                         iommu_prepare_static_identity_mapping();
2249                 /*
2250                  * For each rmrr
2251                  *   for each dev attached to rmrr
2252                  *   do
2253                  *     locate drhd for dev, alloc domain for dev
2254                  *     allocate free domain
2255                  *     allocate page table entries for rmrr
2256                  *     if context not allocated for bus
2257                  *           allocate and init context
2258                  *           set present in root table for this bus
2259                  *     init context with domain, translation etc
2260                  *    endfor
2261                  * endfor
2262                  */
2263                 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2264                 for_each_rmrr_units(rmrr) {
2265                         for (i = 0; i < rmrr->devices_cnt; i++) {
2266                                 pdev = rmrr->devices[i];
2267                                 /*
2268                                  * some BIOS lists non-exist devices in DMAR
2269                                  * table.
2270                                  */
2271                                 if (!pdev)
2272                                         continue;
2273                                 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2274                                 if (ret)
2275                                         printk(KERN_ERR
2276                                  "IOMMU: mapping reserved region failed\n");
2277                         }
2278                 }
2279
2280                 iommu_prepare_isa();
2281         }
2282
2283         /*
2284          * for each drhd
2285          *   enable fault log
2286          *   global invalidate context cache
2287          *   global invalidate iotlb
2288          *   enable translation
2289          */
2290         for_each_drhd_unit(drhd) {
2291                 if (drhd->ignored)
2292                         continue;
2293                 iommu = drhd->iommu;
2294
2295                 iommu_flush_write_buffer(iommu);
2296
2297                 ret = dmar_set_interrupt(iommu);
2298                 if (ret)
2299                         goto error;
2300
2301                 iommu_set_root_entry(iommu);
2302
2303                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2304                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2305                 iommu_disable_protect_mem_regions(iommu);
2306
2307                 ret = iommu_enable_translation(iommu);
2308                 if (ret)
2309                         goto error;
2310         }
2311
2312         return 0;
2313 error:
2314         for_each_drhd_unit(drhd) {
2315                 if (drhd->ignored)
2316                         continue;
2317                 iommu = drhd->iommu;
2318                 free_iommu(iommu);
2319         }
2320         kfree(g_iommus);
2321         return ret;
2322 }
2323
2324 static inline u64 aligned_size(u64 host_addr, size_t size)
2325 {
2326         u64 addr;
2327         addr = (host_addr & (~PAGE_MASK)) + size;
2328         return PAGE_ALIGN(addr);
2329 }
2330
2331 struct iova *
2332 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2333 {
2334         struct iova *piova;
2335
2336         /* Make sure it's in range */
2337         end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2338         if (!size || (IOVA_START_ADDR + size > end))
2339                 return NULL;
2340
2341         piova = alloc_iova(&domain->iovad,
2342                         size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2343         return piova;
2344 }
2345
2346 static struct iova *
2347 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2348                    size_t size, u64 dma_mask)
2349 {
2350         struct pci_dev *pdev = to_pci_dev(dev);
2351         struct iova *iova = NULL;
2352
2353         if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
2354                 iova = iommu_alloc_iova(domain, size, dma_mask);
2355         else {
2356                 /*
2357                  * First try to allocate an io virtual address in
2358                  * DMA_BIT_MASK(32) and if that fails then try allocating
2359                  * from higher range
2360                  */
2361                 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
2362                 if (!iova)
2363                         iova = iommu_alloc_iova(domain, size, dma_mask);
2364         }
2365
2366         if (!iova) {
2367                 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2368                 return NULL;
2369         }
2370
2371         return iova;
2372 }
2373
2374 static struct dmar_domain *
2375 get_valid_domain_for_dev(struct pci_dev *pdev)
2376 {
2377         struct dmar_domain *domain;
2378         int ret;
2379
2380         domain = get_domain_for_dev(pdev,
2381                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2382         if (!domain) {
2383                 printk(KERN_ERR
2384                         "Allocating domain for %s failed", pci_name(pdev));
2385                 return NULL;
2386         }
2387
2388         /* make sure context mapping is ok */
2389         if (unlikely(!domain_context_mapped(pdev))) {
2390                 ret = domain_context_mapping(domain, pdev,
2391                                              CONTEXT_TT_MULTI_LEVEL);
2392                 if (ret) {
2393                         printk(KERN_ERR
2394                                 "Domain context map for %s failed",
2395                                 pci_name(pdev));
2396                         return NULL;
2397                 }
2398         }
2399
2400         return domain;
2401 }
2402
2403 static int iommu_dummy(struct pci_dev *pdev)
2404 {
2405         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2406 }
2407
2408 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2409 static int iommu_no_mapping(struct pci_dev *pdev)
2410 {
2411         int found;
2412
2413         if (!iommu_identity_mapping)
2414                 return iommu_dummy(pdev);
2415
2416         found = identity_mapping(pdev);
2417         if (found) {
2418                 if (pdev->dma_mask > DMA_BIT_MASK(32))
2419                         return 1;
2420                 else {
2421                         /*
2422                          * 32 bit DMA is removed from si_domain and fall back
2423                          * to non-identity mapping.
2424                          */
2425                         domain_remove_one_dev_info(si_domain, pdev);
2426                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2427                                pci_name(pdev));
2428                         return 0;
2429                 }
2430         } else {
2431                 /*
2432                  * In case of a detached 64 bit DMA device from vm, the device
2433                  * is put into si_domain for identity mapping.
2434                  */
2435                 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2436                         int ret;
2437                         ret = domain_add_dev_info(si_domain, pdev);
2438                         if (!ret) {
2439                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2440                                        pci_name(pdev));
2441                                 return 1;
2442                         }
2443                 }
2444         }
2445
2446         return iommu_dummy(pdev);
2447 }
2448
2449 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2450                                      size_t size, int dir, u64 dma_mask)
2451 {
2452         struct pci_dev *pdev = to_pci_dev(hwdev);
2453         struct dmar_domain *domain;
2454         phys_addr_t start_paddr;
2455         struct iova *iova;
2456         int prot = 0;
2457         int ret;
2458         struct intel_iommu *iommu;
2459
2460         BUG_ON(dir == DMA_NONE);
2461
2462         if (iommu_no_mapping(pdev))
2463                 return paddr;
2464
2465         domain = get_valid_domain_for_dev(pdev);
2466         if (!domain)
2467                 return 0;
2468
2469         iommu = domain_get_iommu(domain);
2470         size = aligned_size((u64)paddr, size);
2471
2472         iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2473         if (!iova)
2474                 goto error;
2475
2476         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2477
2478         /*
2479          * Check if DMAR supports zero-length reads on write only
2480          * mappings..
2481          */
2482         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2483                         !cap_zlr(iommu->cap))
2484                 prot |= DMA_PTE_READ;
2485         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2486                 prot |= DMA_PTE_WRITE;
2487         /*
2488          * paddr - (paddr + size) might be partial page, we should map the whole
2489          * page.  Note: if two part of one page are separately mapped, we
2490          * might have two guest_addr mapping to the same host paddr, but this
2491          * is not a big problem
2492          */
2493         ret = domain_page_mapping(domain, start_paddr,
2494                                   ((u64)paddr) & PHYSICAL_PAGE_MASK,
2495                                   size, prot);
2496         if (ret)
2497                 goto error;
2498
2499         /* it's a non-present to present mapping. Only flush if caching mode */
2500         if (cap_caching_mode(iommu->cap))
2501                 iommu_flush_iotlb_psi(iommu, 0, start_paddr,
2502                                       size >> VTD_PAGE_SHIFT);
2503         else
2504                 iommu_flush_write_buffer(iommu);
2505
2506         return start_paddr + ((u64)paddr & (~PAGE_MASK));
2507
2508 error:
2509         if (iova)
2510                 __free_iova(&domain->iovad, iova);
2511         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2512                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2513         return 0;
2514 }
2515
2516 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2517                                  unsigned long offset, size_t size,
2518                                  enum dma_data_direction dir,
2519                                  struct dma_attrs *attrs)
2520 {
2521         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2522                                   dir, to_pci_dev(dev)->dma_mask);
2523 }
2524
2525 static void flush_unmaps(void)
2526 {
2527         int i, j;
2528
2529         timer_on = 0;
2530
2531         /* just flush them all */
2532         for (i = 0; i < g_num_of_iommus; i++) {
2533                 struct intel_iommu *iommu = g_iommus[i];
2534                 if (!iommu)
2535                         continue;
2536
2537                 if (!deferred_flush[i].next)
2538                         continue;
2539
2540                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2541                                          DMA_TLB_GLOBAL_FLUSH);
2542                 for (j = 0; j < deferred_flush[i].next; j++) {
2543                         unsigned long mask;
2544                         struct iova *iova = deferred_flush[i].iova[j];
2545
2546                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2547                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2548                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2549                                         iova->pfn_lo << PAGE_SHIFT, mask);
2550                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2551                 }
2552                 deferred_flush[i].next = 0;
2553         }
2554
2555         list_size = 0;
2556 }
2557
2558 static void flush_unmaps_timeout(unsigned long data)
2559 {
2560         unsigned long flags;
2561
2562         spin_lock_irqsave(&async_umap_flush_lock, flags);
2563         flush_unmaps();
2564         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2565 }
2566
2567 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2568 {
2569         unsigned long flags;
2570         int next, iommu_id;
2571         struct intel_iommu *iommu;
2572
2573         spin_lock_irqsave(&async_umap_flush_lock, flags);
2574         if (list_size == HIGH_WATER_MARK)
2575                 flush_unmaps();
2576
2577         iommu = domain_get_iommu(dom);
2578         iommu_id = iommu->seq_id;
2579
2580         next = deferred_flush[iommu_id].next;
2581         deferred_flush[iommu_id].domain[next] = dom;
2582         deferred_flush[iommu_id].iova[next] = iova;
2583         deferred_flush[iommu_id].next++;
2584
2585         if (!timer_on) {
2586                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2587                 timer_on = 1;
2588         }
2589         list_size++;
2590         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2591 }
2592
2593 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2594                              size_t size, enum dma_data_direction dir,
2595                              struct dma_attrs *attrs)
2596 {
2597         struct pci_dev *pdev = to_pci_dev(dev);
2598         struct dmar_domain *domain;
2599         unsigned long start_pfn, last_pfn;
2600         struct iova *iova;
2601         struct intel_iommu *iommu;
2602
2603         if (iommu_no_mapping(pdev))
2604                 return;
2605
2606         domain = find_domain(pdev);
2607         BUG_ON(!domain);
2608
2609         iommu = domain_get_iommu(domain);
2610
2611         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2612         if (!iova)
2613                 return;
2614
2615         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2616         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2617
2618         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2619                  pci_name(pdev), start_pfn, last_pfn);
2620
2621         /*  clear the whole page */
2622         dma_pte_clear_range(domain, start_pfn, last_pfn);
2623
2624         /* free page tables */
2625         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2626
2627         if (intel_iommu_strict) {
2628                 iommu_flush_iotlb_psi(iommu, domain->id,
2629                                       start_pfn << VTD_PAGE_SHIFT,
2630                                       last_pfn - start_pfn + 1);
2631                 /* free iova */
2632                 __free_iova(&domain->iovad, iova);
2633         } else {
2634                 add_unmap(domain, iova);
2635                 /*
2636                  * queue up the release of the unmap to save the 1/6th of the
2637                  * cpu used up by the iotlb flush operation...
2638                  */
2639         }
2640 }
2641
2642 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2643                                int dir)
2644 {
2645         intel_unmap_page(dev, dev_addr, size, dir, NULL);
2646 }
2647
2648 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2649                                   dma_addr_t *dma_handle, gfp_t flags)
2650 {
2651         void *vaddr;
2652         int order;
2653
2654         size = PAGE_ALIGN(size);
2655         order = get_order(size);
2656         flags &= ~(GFP_DMA | GFP_DMA32);
2657
2658         vaddr = (void *)__get_free_pages(flags, order);
2659         if (!vaddr)
2660                 return NULL;
2661         memset(vaddr, 0, size);
2662
2663         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2664                                          DMA_BIDIRECTIONAL,
2665                                          hwdev->coherent_dma_mask);
2666         if (*dma_handle)
2667                 return vaddr;
2668         free_pages((unsigned long)vaddr, order);
2669         return NULL;
2670 }
2671
2672 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2673                                 dma_addr_t dma_handle)
2674 {
2675         int order;
2676
2677         size = PAGE_ALIGN(size);
2678         order = get_order(size);
2679
2680         intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2681         free_pages((unsigned long)vaddr, order);
2682 }
2683
2684 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2685                            int nelems, enum dma_data_direction dir,
2686                            struct dma_attrs *attrs)
2687 {
2688         struct pci_dev *pdev = to_pci_dev(hwdev);
2689         struct dmar_domain *domain;
2690         unsigned long start_pfn, last_pfn;
2691         struct iova *iova;
2692         struct intel_iommu *iommu;
2693
2694         if (iommu_no_mapping(pdev))
2695                 return;
2696
2697         domain = find_domain(pdev);
2698         BUG_ON(!domain);
2699
2700         iommu = domain_get_iommu(domain);
2701
2702         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2703         if (!iova)
2704                 return;
2705
2706         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2707         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2708
2709         /*  clear the whole page */
2710         dma_pte_clear_range(domain, start_pfn, last_pfn);
2711
2712         /* free page tables */
2713         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2714
2715         iommu_flush_iotlb_psi(iommu, domain->id,
2716                               start_pfn << VTD_PAGE_SHIFT,
2717                               (last_pfn - start_pfn + 1));
2718
2719         /* free iova */
2720         __free_iova(&domain->iovad, iova);
2721 }
2722
2723 static int intel_nontranslate_map_sg(struct device *hddev,
2724         struct scatterlist *sglist, int nelems, int dir)
2725 {
2726         int i;
2727         struct scatterlist *sg;
2728
2729         for_each_sg(sglist, sg, nelems, i) {
2730                 BUG_ON(!sg_page(sg));
2731                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2732                 sg->dma_length = sg->length;
2733         }
2734         return nelems;
2735 }
2736
2737 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2738                         enum dma_data_direction dir, struct dma_attrs *attrs)
2739 {
2740         phys_addr_t addr;
2741         int i;
2742         struct pci_dev *pdev = to_pci_dev(hwdev);
2743         struct dmar_domain *domain;
2744         size_t size = 0;
2745         int prot = 0;
2746         size_t offset = 0;
2747         struct iova *iova = NULL;
2748         int ret;
2749         struct scatterlist *sg;
2750         unsigned long start_addr;
2751         struct intel_iommu *iommu;
2752
2753         BUG_ON(dir == DMA_NONE);
2754         if (iommu_no_mapping(pdev))
2755                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2756
2757         domain = get_valid_domain_for_dev(pdev);
2758         if (!domain)
2759                 return 0;
2760
2761         iommu = domain_get_iommu(domain);
2762
2763         for_each_sg(sglist, sg, nelems, i) {
2764                 addr = page_to_phys(sg_page(sg)) + sg->offset;
2765                 size += aligned_size((u64)addr, sg->length);
2766         }
2767
2768         iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2769         if (!iova) {
2770                 sglist->dma_length = 0;
2771                 return 0;
2772         }
2773
2774         /*
2775          * Check if DMAR supports zero-length reads on write only
2776          * mappings..
2777          */
2778         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2779                         !cap_zlr(iommu->cap))
2780                 prot |= DMA_PTE_READ;
2781         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2782                 prot |= DMA_PTE_WRITE;
2783
2784         start_addr = iova->pfn_lo << PAGE_SHIFT;
2785         offset = 0;
2786         for_each_sg(sglist, sg, nelems, i) {
2787                 addr = page_to_phys(sg_page(sg)) + sg->offset;
2788                 size = aligned_size((u64)addr, sg->length);
2789                 ret = domain_page_mapping(domain, start_addr + offset,
2790                                           ((u64)addr) & PHYSICAL_PAGE_MASK,
2791                                           size, prot);
2792                 if (ret) {
2793                         /*  clear the page */
2794                         dma_pte_clear_range(domain,
2795                                             start_addr >> VTD_PAGE_SHIFT,
2796                                             (start_addr + offset - 1) >> VTD_PAGE_SHIFT);
2797                         /* free page tables */
2798                         dma_pte_free_pagetable(domain, start_addr >> VTD_PAGE_SHIFT,
2799                                                (start_addr + offset - 1) >> VTD_PAGE_SHIFT);
2800                         /* free iova */
2801                         __free_iova(&domain->iovad, iova);
2802                         return 0;
2803                 }
2804                 sg->dma_address = start_addr + offset +
2805                                 ((u64)addr & (~PAGE_MASK));
2806                 sg->dma_length = sg->length;
2807                 offset += size;
2808         }
2809
2810         /* it's a non-present to present mapping. Only flush if caching mode */
2811         if (cap_caching_mode(iommu->cap))
2812                 iommu_flush_iotlb_psi(iommu, 0, start_addr,
2813                                       offset >> VTD_PAGE_SHIFT);
2814         else
2815                 iommu_flush_write_buffer(iommu);
2816
2817         return nelems;
2818 }
2819
2820 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2821 {
2822         return !dma_addr;
2823 }
2824
2825 struct dma_map_ops intel_dma_ops = {
2826         .alloc_coherent = intel_alloc_coherent,
2827         .free_coherent = intel_free_coherent,
2828         .map_sg = intel_map_sg,
2829         .unmap_sg = intel_unmap_sg,
2830         .map_page = intel_map_page,
2831         .unmap_page = intel_unmap_page,
2832         .mapping_error = intel_mapping_error,
2833 };
2834
2835 static inline int iommu_domain_cache_init(void)
2836 {
2837         int ret = 0;
2838
2839         iommu_domain_cache = kmem_cache_create("iommu_domain",
2840                                          sizeof(struct dmar_domain),
2841                                          0,
2842                                          SLAB_HWCACHE_ALIGN,
2843
2844                                          NULL);
2845         if (!iommu_domain_cache) {
2846                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2847                 ret = -ENOMEM;
2848         }
2849
2850         return ret;
2851 }
2852
2853 static inline int iommu_devinfo_cache_init(void)
2854 {
2855         int ret = 0;
2856
2857         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2858                                          sizeof(struct device_domain_info),
2859                                          0,
2860                                          SLAB_HWCACHE_ALIGN,
2861                                          NULL);
2862         if (!iommu_devinfo_cache) {
2863                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2864                 ret = -ENOMEM;
2865         }
2866
2867         return ret;
2868 }
2869
2870 static inline int iommu_iova_cache_init(void)
2871 {
2872         int ret = 0;
2873
2874         iommu_iova_cache = kmem_cache_create("iommu_iova",
2875                                          sizeof(struct iova),
2876                                          0,
2877                                          SLAB_HWCACHE_ALIGN,
2878                                          NULL);
2879         if (!iommu_iova_cache) {
2880                 printk(KERN_ERR "Couldn't create iova cache\n");
2881                 ret = -ENOMEM;
2882         }
2883
2884         return ret;
2885 }
2886
2887 static int __init iommu_init_mempool(void)
2888 {
2889         int ret;
2890         ret = iommu_iova_cache_init();
2891         if (ret)
2892                 return ret;
2893
2894         ret = iommu_domain_cache_init();
2895         if (ret)
2896                 goto domain_error;
2897
2898         ret = iommu_devinfo_cache_init();
2899         if (!ret)
2900                 return ret;
2901
2902         kmem_cache_destroy(iommu_domain_cache);
2903 domain_error:
2904         kmem_cache_destroy(iommu_iova_cache);
2905
2906         return -ENOMEM;
2907 }
2908
2909 static void __init iommu_exit_mempool(void)
2910 {
2911         kmem_cache_destroy(iommu_devinfo_cache);
2912         kmem_cache_destroy(iommu_domain_cache);
2913         kmem_cache_destroy(iommu_iova_cache);
2914
2915 }
2916
2917 static void __init init_no_remapping_devices(void)
2918 {
2919         struct dmar_drhd_unit *drhd;
2920
2921         for_each_drhd_unit(drhd) {
2922                 if (!drhd->include_all) {
2923                         int i;
2924                         for (i = 0; i < drhd->devices_cnt; i++)
2925                                 if (drhd->devices[i] != NULL)
2926                                         break;
2927                         /* ignore DMAR unit if no pci devices exist */
2928                         if (i == drhd->devices_cnt)
2929                                 drhd->ignored = 1;
2930                 }
2931         }
2932
2933         if (dmar_map_gfx)
2934                 return;
2935
2936         for_each_drhd_unit(drhd) {
2937                 int i;
2938                 if (drhd->ignored || drhd->include_all)
2939                         continue;
2940
2941                 for (i = 0; i < drhd->devices_cnt; i++)
2942                         if (drhd->devices[i] &&
2943                                 !IS_GFX_DEVICE(drhd->devices[i]))
2944                                 break;
2945
2946                 if (i < drhd->devices_cnt)
2947                         continue;
2948
2949                 /* bypass IOMMU if it is just for gfx devices */
2950                 drhd->ignored = 1;
2951                 for (i = 0; i < drhd->devices_cnt; i++) {
2952                         if (!drhd->devices[i])
2953                                 continue;
2954                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2955                 }
2956         }
2957 }
2958
2959 #ifdef CONFIG_SUSPEND
2960 static int init_iommu_hw(void)
2961 {
2962         struct dmar_drhd_unit *drhd;
2963         struct intel_iommu *iommu = NULL;
2964
2965         for_each_active_iommu(iommu, drhd)
2966                 if (iommu->qi)
2967                         dmar_reenable_qi(iommu);
2968
2969         for_each_active_iommu(iommu, drhd) {
2970                 iommu_flush_write_buffer(iommu);
2971
2972                 iommu_set_root_entry(iommu);
2973
2974                 iommu->flush.flush_context(iommu, 0, 0, 0,
2975                                            DMA_CCMD_GLOBAL_INVL);
2976                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2977                                          DMA_TLB_GLOBAL_FLUSH);
2978                 iommu_disable_protect_mem_regions(iommu);
2979                 iommu_enable_translation(iommu);
2980         }
2981
2982         return 0;
2983 }
2984
2985 static void iommu_flush_all(void)
2986 {
2987         struct dmar_drhd_unit *drhd;
2988         struct intel_iommu *iommu;
2989
2990         for_each_active_iommu(iommu, drhd) {
2991                 iommu->flush.flush_context(iommu, 0, 0, 0,
2992                                            DMA_CCMD_GLOBAL_INVL);
2993                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2994                                          DMA_TLB_GLOBAL_FLUSH);
2995         }
2996 }
2997
2998 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
2999 {
3000         struct dmar_drhd_unit *drhd;
3001         struct intel_iommu *iommu = NULL;
3002         unsigned long flag;
3003
3004         for_each_active_iommu(iommu, drhd) {
3005                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3006                                                  GFP_ATOMIC);
3007                 if (!iommu->iommu_state)
3008                         goto nomem;
3009         }
3010
3011         iommu_flush_all();
3012
3013         for_each_active_iommu(iommu, drhd) {
3014                 iommu_disable_translation(iommu);
3015
3016                 spin_lock_irqsave(&iommu->register_lock, flag);
3017
3018                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3019                         readl(iommu->reg + DMAR_FECTL_REG);
3020                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3021                         readl(iommu->reg + DMAR_FEDATA_REG);
3022                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3023                         readl(iommu->reg + DMAR_FEADDR_REG);
3024                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3025                         readl(iommu->reg + DMAR_FEUADDR_REG);
3026
3027                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3028         }
3029         return 0;
3030
3031 nomem:
3032         for_each_active_iommu(iommu, drhd)
3033                 kfree(iommu->iommu_state);
3034
3035         return -ENOMEM;
3036 }
3037
3038 static int iommu_resume(struct sys_device *dev)
3039 {
3040         struct dmar_drhd_unit *drhd;
3041         struct intel_iommu *iommu = NULL;
3042         unsigned long flag;
3043
3044         if (init_iommu_hw()) {
3045                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3046                 return -EIO;
3047         }
3048
3049         for_each_active_iommu(iommu, drhd) {
3050
3051                 spin_lock_irqsave(&iommu->register_lock, flag);
3052
3053                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3054                         iommu->reg + DMAR_FECTL_REG);
3055                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3056                         iommu->reg + DMAR_FEDATA_REG);
3057                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3058                         iommu->reg + DMAR_FEADDR_REG);
3059                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3060                         iommu->reg + DMAR_FEUADDR_REG);
3061
3062                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3063         }
3064
3065         for_each_active_iommu(iommu, drhd)
3066                 kfree(iommu->iommu_state);
3067
3068         return 0;
3069 }
3070
3071 static struct sysdev_class iommu_sysclass = {
3072         .name           = "iommu",
3073         .resume         = iommu_resume,
3074         .suspend        = iommu_suspend,
3075 };
3076
3077 static struct sys_device device_iommu = {
3078         .cls    = &iommu_sysclass,
3079 };
3080
3081 static int __init init_iommu_sysfs(void)
3082 {
3083         int error;
3084
3085         error = sysdev_class_register(&iommu_sysclass);
3086         if (error)
3087                 return error;
3088
3089         error = sysdev_register(&device_iommu);
3090         if (error)
3091                 sysdev_class_unregister(&iommu_sysclass);
3092
3093         return error;
3094 }
3095
3096 #else
3097 static int __init init_iommu_sysfs(void)
3098 {
3099         return 0;
3100 }
3101 #endif  /* CONFIG_PM */
3102
3103 int __init intel_iommu_init(void)
3104 {
3105         int ret = 0;
3106
3107         if (dmar_table_init())
3108                 return  -ENODEV;
3109
3110         if (dmar_dev_scope_init())
3111                 return  -ENODEV;
3112
3113         /*
3114          * Check the need for DMA-remapping initialization now.
3115          * Above initialization will also be used by Interrupt-remapping.
3116          */
3117         if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3118                 return -ENODEV;
3119
3120         iommu_init_mempool();
3121         dmar_init_reserved_ranges();
3122
3123         init_no_remapping_devices();
3124
3125         ret = init_dmars();
3126         if (ret) {
3127                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3128                 put_iova_domain(&reserved_iova_list);
3129                 iommu_exit_mempool();
3130                 return ret;
3131         }
3132         printk(KERN_INFO
3133         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3134
3135         init_timer(&unmap_timer);
3136         force_iommu = 1;
3137
3138         if (!iommu_pass_through) {
3139                 printk(KERN_INFO
3140                        "Multi-level page-table translation for DMAR.\n");
3141                 dma_ops = &intel_dma_ops;
3142         } else
3143                 printk(KERN_INFO
3144                        "DMAR: Pass through translation for DMAR.\n");
3145
3146         init_iommu_sysfs();
3147
3148         register_iommu(&intel_iommu_ops);
3149
3150         return 0;
3151 }
3152
3153 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3154                                            struct pci_dev *pdev)
3155 {
3156         struct pci_dev *tmp, *parent;
3157
3158         if (!iommu || !pdev)
3159                 return;
3160
3161         /* dependent device detach */
3162         tmp = pci_find_upstream_pcie_bridge(pdev);
3163         /* Secondary interface's bus number and devfn 0 */
3164         if (tmp) {
3165                 parent = pdev->bus->self;
3166                 while (parent != tmp) {
3167                         iommu_detach_dev(iommu, parent->bus->number,
3168                                          parent->devfn);
3169                         parent = parent->bus->self;
3170                 }
3171                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3172                         iommu_detach_dev(iommu,
3173                                 tmp->subordinate->number, 0);
3174                 else /* this is a legacy PCI bridge */
3175                         iommu_detach_dev(iommu, tmp->bus->number,
3176                                          tmp->devfn);
3177         }
3178 }
3179
3180 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3181                                           struct pci_dev *pdev)
3182 {
3183         struct device_domain_info *info;
3184         struct intel_iommu *iommu;
3185         unsigned long flags;
3186         int found = 0;
3187         struct list_head *entry, *tmp;
3188
3189         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3190                                 pdev->devfn);
3191         if (!iommu)
3192                 return;
3193
3194         spin_lock_irqsave(&device_domain_lock, flags);
3195         list_for_each_safe(entry, tmp, &domain->devices) {
3196                 info = list_entry(entry, struct device_domain_info, link);
3197                 /* No need to compare PCI domain; it has to be the same */
3198                 if (info->bus == pdev->bus->number &&
3199                     info->devfn == pdev->devfn) {
3200                         list_del(&info->link);
3201                         list_del(&info->global);
3202                         if (info->dev)
3203                                 info->dev->dev.archdata.iommu = NULL;
3204                         spin_unlock_irqrestore(&device_domain_lock, flags);
3205
3206                         iommu_disable_dev_iotlb(info);
3207                         iommu_detach_dev(iommu, info->bus, info->devfn);
3208                         iommu_detach_dependent_devices(iommu, pdev);
3209                         free_devinfo_mem(info);
3210
3211                         spin_lock_irqsave(&device_domain_lock, flags);
3212
3213                         if (found)
3214                                 break;
3215                         else
3216                                 continue;
3217                 }
3218
3219                 /* if there is no other devices under the same iommu
3220                  * owned by this domain, clear this iommu in iommu_bmp
3221                  * update iommu count and coherency
3222                  */
3223                 if (iommu == device_to_iommu(info->segment, info->bus,
3224                                             info->devfn))
3225                         found = 1;
3226         }
3227
3228         if (found == 0) {
3229                 unsigned long tmp_flags;
3230                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3231                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3232                 domain->iommu_count--;
3233                 domain_update_iommu_cap(domain);
3234                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3235         }
3236
3237         spin_unlock_irqrestore(&device_domain_lock, flags);
3238 }
3239
3240 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3241 {
3242         struct device_domain_info *info;
3243         struct intel_iommu *iommu;
3244         unsigned long flags1, flags2;
3245
3246         spin_lock_irqsave(&device_domain_lock, flags1);
3247         while (!list_empty(&domain->devices)) {
3248                 info = list_entry(domain->devices.next,
3249                         struct device_domain_info, link);
3250                 list_del(&info->link);
3251                 list_del(&info->global);
3252                 if (info->dev)
3253                         info->dev->dev.archdata.iommu = NULL;
3254
3255                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3256
3257                 iommu_disable_dev_iotlb(info);
3258                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3259                 iommu_detach_dev(iommu, info->bus, info->devfn);
3260                 iommu_detach_dependent_devices(iommu, info->dev);
3261
3262                 /* clear this iommu in iommu_bmp, update iommu count
3263                  * and capabilities
3264                  */
3265                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3266                 if (test_and_clear_bit(iommu->seq_id,
3267                                        &domain->iommu_bmp)) {
3268                         domain->iommu_count--;
3269                         domain_update_iommu_cap(domain);
3270                 }
3271                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3272
3273                 free_devinfo_mem(info);
3274                 spin_lock_irqsave(&device_domain_lock, flags1);
3275         }
3276         spin_unlock_irqrestore(&device_domain_lock, flags1);
3277 }
3278
3279 /* domain id for virtual machine, it won't be set in context */
3280 static unsigned long vm_domid;
3281
3282 static int vm_domain_min_agaw(struct dmar_domain *domain)
3283 {
3284         int i;
3285         int min_agaw = domain->agaw;
3286
3287         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3288         for (; i < g_num_of_iommus; ) {
3289                 if (min_agaw > g_iommus[i]->agaw)
3290                         min_agaw = g_iommus[i]->agaw;
3291
3292                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3293         }
3294
3295         return min_agaw;
3296 }
3297
3298 static struct dmar_domain *iommu_alloc_vm_domain(void)
3299 {
3300         struct dmar_domain *domain;
3301
3302         domain = alloc_domain_mem();
3303         if (!domain)
3304                 return NULL;
3305
3306         domain->id = vm_domid++;
3307         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3308         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3309
3310         return domain;
3311 }
3312
3313 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3314 {
3315         int adjust_width;
3316
3317         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3318         spin_lock_init(&domain->mapping_lock);
3319         spin_lock_init(&domain->iommu_lock);
3320
3321         domain_reserve_special_ranges(domain);
3322
3323         /* calculate AGAW */
3324         domain->gaw = guest_width;
3325         adjust_width = guestwidth_to_adjustwidth(guest_width);
3326         domain->agaw = width_to_agaw(adjust_width);
3327
3328         INIT_LIST_HEAD(&domain->devices);
3329
3330         domain->iommu_count = 0;
3331         domain->iommu_coherency = 0;
3332         domain->max_addr = 0;
3333
3334         /* always allocate the top pgd */
3335         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3336         if (!domain->pgd)
3337                 return -ENOMEM;
3338         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3339         return 0;
3340 }
3341
3342 static void iommu_free_vm_domain(struct dmar_domain *domain)
3343 {
3344         unsigned long flags;
3345         struct dmar_drhd_unit *drhd;
3346         struct intel_iommu *iommu;
3347         unsigned long i;
3348         unsigned long ndomains;
3349
3350         for_each_drhd_unit(drhd) {
3351                 if (drhd->ignored)
3352                         continue;
3353                 iommu = drhd->iommu;
3354
3355                 ndomains = cap_ndoms(iommu->cap);
3356                 i = find_first_bit(iommu->domain_ids, ndomains);
3357                 for (; i < ndomains; ) {
3358                         if (iommu->domains[i] == domain) {
3359                                 spin_lock_irqsave(&iommu->lock, flags);
3360                                 clear_bit(i, iommu->domain_ids);
3361                                 iommu->domains[i] = NULL;
3362                                 spin_unlock_irqrestore(&iommu->lock, flags);
3363                                 break;
3364                         }
3365                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3366                 }
3367         }
3368 }
3369
3370 static void vm_domain_exit(struct dmar_domain *domain)
3371 {
3372         /* Domain 0 is reserved, so dont process it */
3373         if (!domain)
3374                 return;
3375
3376         vm_domain_remove_all_dev_info(domain);
3377         /* destroy iovas */
3378         put_iova_domain(&domain->iovad);
3379
3380         /* clear ptes */
3381         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3382
3383         /* free page tables */
3384         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3385
3386         iommu_free_vm_domain(domain);
3387         free_domain_mem(domain);
3388 }
3389
3390 static int intel_iommu_domain_init(struct iommu_domain *domain)
3391 {
3392         struct dmar_domain *dmar_domain;
3393
3394         dmar_domain = iommu_alloc_vm_domain();
3395         if (!dmar_domain) {
3396                 printk(KERN_ERR
3397                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3398                 return -ENOMEM;
3399         }
3400         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3401                 printk(KERN_ERR
3402                         "intel_iommu_domain_init() failed\n");
3403                 vm_domain_exit(dmar_domain);
3404                 return -ENOMEM;
3405         }
3406         domain->priv = dmar_domain;
3407
3408         return 0;
3409 }
3410
3411 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3412 {
3413         struct dmar_domain *dmar_domain = domain->priv;
3414
3415         domain->priv = NULL;
3416         vm_domain_exit(dmar_domain);
3417 }
3418
3419 static int intel_iommu_attach_device(struct iommu_domain *domain,
3420                                      struct device *dev)
3421 {
3422         struct dmar_domain *dmar_domain = domain->priv;
3423         struct pci_dev *pdev = to_pci_dev(dev);
3424         struct intel_iommu *iommu;
3425         int addr_width;
3426         u64 end;
3427         int ret;
3428
3429         /* normally pdev is not mapped */
3430         if (unlikely(domain_context_mapped(pdev))) {
3431                 struct dmar_domain *old_domain;
3432
3433                 old_domain = find_domain(pdev);
3434                 if (old_domain) {
3435                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3436                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3437                                 domain_remove_one_dev_info(old_domain, pdev);
3438                         else
3439                                 domain_remove_dev_info(old_domain);
3440                 }
3441         }
3442
3443         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3444                                 pdev->devfn);
3445         if (!iommu)
3446                 return -ENODEV;
3447
3448         /* check if this iommu agaw is sufficient for max mapped address */
3449         addr_width = agaw_to_width(iommu->agaw);
3450         end = DOMAIN_MAX_ADDR(addr_width);
3451         end = end & VTD_PAGE_MASK;
3452         if (end < dmar_domain->max_addr) {
3453                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3454                        "sufficient for the mapped address (%llx)\n",
3455                        __func__, iommu->agaw, dmar_domain->max_addr);
3456                 return -EFAULT;
3457         }
3458
3459         ret = domain_add_dev_info(dmar_domain, pdev);
3460         if (ret)
3461                 return ret;
3462
3463         ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3464         return ret;
3465 }
3466
3467 static void intel_iommu_detach_device(struct iommu_domain *domain,
3468                                       struct device *dev)
3469 {
3470         struct dmar_domain *dmar_domain = domain->priv;
3471         struct pci_dev *pdev = to_pci_dev(dev);
3472
3473         domain_remove_one_dev_info(dmar_domain, pdev);
3474 }
3475
3476 static int intel_iommu_map_range(struct iommu_domain *domain,
3477                                  unsigned long iova, phys_addr_t hpa,
3478                                  size_t size, int iommu_prot)
3479 {
3480         struct dmar_domain *dmar_domain = domain->priv;
3481         u64 max_addr;
3482         int addr_width;
3483         int prot = 0;
3484         int ret;
3485
3486         if (iommu_prot & IOMMU_READ)
3487                 prot |= DMA_PTE_READ;
3488         if (iommu_prot & IOMMU_WRITE)
3489                 prot |= DMA_PTE_WRITE;
3490         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3491                 prot |= DMA_PTE_SNP;
3492
3493         max_addr = iova + size;
3494         if (dmar_domain->max_addr < max_addr) {
3495                 int min_agaw;
3496                 u64 end;
3497
3498                 /* check if minimum agaw is sufficient for mapped address */
3499                 min_agaw = vm_domain_min_agaw(dmar_domain);
3500                 addr_width = agaw_to_width(min_agaw);
3501                 end = DOMAIN_MAX_ADDR(addr_width);
3502                 end = end & VTD_PAGE_MASK;
3503                 if (end < max_addr) {
3504                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3505                                "sufficient for the mapped address (%llx)\n",
3506                                __func__, min_agaw, max_addr);
3507                         return -EFAULT;
3508                 }
3509                 dmar_domain->max_addr = max_addr;
3510         }
3511
3512         ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot);
3513         return ret;
3514 }
3515
3516 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3517                                     unsigned long iova, size_t size)
3518 {
3519         struct dmar_domain *dmar_domain = domain->priv;
3520
3521         dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3522                             (iova + size - 1) >> VTD_PAGE_SHIFT);
3523
3524         if (dmar_domain->max_addr == iova + size)
3525                 dmar_domain->max_addr = iova;
3526 }
3527
3528 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3529                                             unsigned long iova)
3530 {
3531         struct dmar_domain *dmar_domain = domain->priv;
3532         struct dma_pte *pte;
3533         u64 phys = 0;
3534
3535         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3536         if (pte)
3537                 phys = dma_pte_addr(pte);
3538
3539         return phys;
3540 }
3541
3542 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3543                                       unsigned long cap)
3544 {
3545         struct dmar_domain *dmar_domain = domain->priv;
3546
3547         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3548                 return dmar_domain->iommu_snooping;
3549
3550         return 0;
3551 }
3552
3553 static struct iommu_ops intel_iommu_ops = {
3554         .domain_init    = intel_iommu_domain_init,
3555         .domain_destroy = intel_iommu_domain_destroy,
3556         .attach_dev     = intel_iommu_attach_device,
3557         .detach_dev     = intel_iommu_detach_device,
3558         .map            = intel_iommu_map_range,
3559         .unmap          = intel_iommu_unmap_range,
3560         .iova_to_phys   = intel_iommu_iova_to_phys,
3561         .domain_has_cap = intel_iommu_domain_has_cap,
3562 };
3563
3564 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3565 {
3566         /*
3567          * Mobile 4 Series Chipset neglects to set RWBF capability,
3568          * but needs it:
3569          */
3570         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3571         rwbf_quirk = 1;
3572 }
3573
3574 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);