wl1251: rename reg.h to wl1251_reg.h
[linux-2.6.git] / drivers / net / wireless / wl12xx / wl1251_boot.c
1 /*
2  * This file is part of wl1251
3  *
4  * Copyright (C) 2008 Nokia Corporation
5  *
6  * Contact: Kalle Valo <kalle.valo@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/gpio.h>
25
26 #include "wl1251_reg.h"
27 #include "wl1251_boot.h"
28 #include "wl1251_io.h"
29 #include "wl1251_spi.h"
30 #include "wl1251_event.h"
31 #include "wl1251_acx.h"
32
33 void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
34 {
35         wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
36         wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
37 }
38
39 int wl1251_boot_soft_reset(struct wl1251 *wl)
40 {
41         unsigned long timeout;
42         u32 boot_data;
43
44         /* perform soft reset */
45         wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
46
47         /* SOFT_RESET is self clearing */
48         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
49         while (1) {
50                 boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
51                 wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
52                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
53                         break;
54
55                 if (time_after(jiffies, timeout)) {
56                         /* 1.2 check pWhalBus->uSelfClearTime if the
57                          * timeout was reached */
58                         wl1251_error("soft reset timeout");
59                         return -1;
60                 }
61
62                 udelay(SOFT_RESET_STALL_TIME);
63         }
64
65         /* disable Rx/Tx */
66         wl1251_reg_write32(wl, ENABLE, 0x0);
67
68         /* disable auto calibration on start*/
69         wl1251_reg_write32(wl, SPARE_A2, 0xffff);
70
71         return 0;
72 }
73
74 int wl1251_boot_init_seq(struct wl1251 *wl)
75 {
76         u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
77
78         /*
79          * col #1: INTEGER_DIVIDER
80          * col #2: FRACTIONAL_DIVIDER
81          * col #3: ATTN_BB
82          * col #4: ALPHA_BB
83          * col #5: STOP_TIME_BB
84          * col #6: BB_PLL_LOOP_FILTER
85          */
86         static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {
87
88                 {   83, 87381,  0xB, 5, 0xF00,  3}, /* REF_FREQ_19_2*/
89                 {   61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
90                 {   41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
91                 {   40, 0,      0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
92                 {   47, 162280, 0xC, 6, 0x2760, 1}  /* REF_FREQ_33_6        */
93         };
94
95         /* read NVS params */
96         scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
97         wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
98
99         /* read ELP_CMD */
100         elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
101         wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
102
103         /* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
104         ref_freq = scr_pad6 & 0x000000FF;
105         wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
106
107         wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
108
109         /*
110          * PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
111          */
112         wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);
113
114         /*
115          * set the clock detect feature to work in the restart wu procedure
116          * (ELP_CFG_MODE[14]) and Select the clock source type
117          * (ELP_CFG_MODE[13:12])
118          */
119         tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
120         wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
121
122         /* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
123         elp_cmd |= 0x00000040;
124         wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
125
126         /* PG 1.2: Set the BB PLL stable time to be 1000usec
127          * (PLL_STABLE_TIME) */
128         wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
129
130         /* PG 1.2: read clock request time */
131         init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
132
133         /*
134          * PG 1.2: set the clock request time to be ref_clk_settling_time -
135          * 1ms = 4ms
136          */
137         if (init_data > 0x21)
138                 tmp = init_data - 0x21;
139         else
140                 tmp = 0;
141         wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
142
143         /* set BB PLL configurations in RF AFE */
144         wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
145
146         /* set RF_AFE_REG_5 */
147         wl1251_reg_write32(wl, 0x003058d4, 0x50);
148
149         /* set RF_AFE_CTRL_REG_2 */
150         wl1251_reg_write32(wl, 0x00305948, 0x11c001);
151
152         /*
153          * change RF PLL and BB PLL divider for VCO clock and adjust VCO
154          * bais current(RF_AFE_REG_13)
155          */
156         wl1251_reg_write32(wl, 0x003058f4, 0x1e);
157
158         /* set BB PLL configurations */
159         tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
160         wl1251_reg_write32(wl, 0x00305840, tmp);
161
162         /* set fractional divider according to Appendix C-BB PLL
163          * Calculations
164          */
165         tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
166         wl1251_reg_write32(wl, 0x00305844, tmp);
167
168         /* set the initial data for the sigma delta */
169         wl1251_reg_write32(wl, 0x00305848, 0x3039);
170
171         /*
172          * set the accumulator attenuation value, calibration loop1
173          * (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
174          * the VCO gain
175          */
176         tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
177                 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
178         wl1251_reg_write32(wl, 0x00305854, tmp);
179
180         /*
181          * set the calibration stop time after holdoff time expires and set
182          * settling time HOLD_OFF_TIME_BB
183          */
184         tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
185         wl1251_reg_write32(wl, 0x00305858, tmp);
186
187         /*
188          * set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
189          * constant leakage current to linearize PFD to 0uA -
190          * BB_ILOOPF[7:3]
191          */
192         tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
193         wl1251_reg_write32(wl, 0x003058f8, tmp);
194
195         /*
196          * set regulator output voltage for n divider to
197          * 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
198          * set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
199          * PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
200          */
201         wl1251_reg_write32(wl, 0x003058f0, 0x29);
202
203         /* enable restart wakeup sequence (ELP_CMD[0]) */
204         wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
205
206         /* restart sequence completed */
207         udelay(2000);
208
209         return 0;
210 }
211
212 static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
213 {
214         u32 cpu_ctrl;
215
216         /* 10.5.0 run the firmware (I) */
217         cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
218
219         /* 10.5.1 run the firmware (II) */
220         cpu_ctrl &= ~flag;
221         wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
222 }
223
224 int wl1251_boot_run_firmware(struct wl1251 *wl)
225 {
226         int loop, ret;
227         u32 chip_id, interrupt;
228
229         wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
230
231         chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
232
233         wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
234
235         if (chip_id != wl->chip_id) {
236                 wl1251_error("chip id doesn't match after firmware boot");
237                 return -EIO;
238         }
239
240         /* wait for init to complete */
241         loop = 0;
242         while (loop++ < INIT_LOOP) {
243                 udelay(INIT_LOOP_DELAY);
244                 interrupt = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
245
246                 if (interrupt == 0xffffffff) {
247                         wl1251_error("error reading hardware complete "
248                                      "init indication");
249                         return -EIO;
250                 }
251                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
252                 else if (interrupt & WL1251_ACX_INTR_INIT_COMPLETE) {
253                         wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
254                                            WL1251_ACX_INTR_INIT_COMPLETE);
255                         break;
256                 }
257         }
258
259         if (loop >= INIT_LOOP) {
260                 wl1251_error("timeout waiting for the hardware to "
261                              "complete initialization");
262                 return -EIO;
263         }
264
265         /* get hardware config command mail box */
266         wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
267
268         /* get hardware config event mail box */
269         wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
270
271         /* set the working partition to its "running" mode offset */
272         wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
273                              WL1251_PART_WORK_MEM_SIZE,
274                              WL1251_PART_WORK_REG_START,
275                              WL1251_PART_WORK_REG_SIZE);
276
277         wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
278                      wl->cmd_box_addr, wl->event_box_addr);
279
280         wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));
281
282         /*
283          * in case of full asynchronous mode the firmware event must be
284          * ready to receive event from the command mailbox
285          */
286
287         /* enable gpio interrupts */
288         wl1251_enable_interrupts(wl);
289
290         /* Enable target's interrupts */
291         wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
292                 WL1251_ACX_INTR_RX1_DATA |
293                 WL1251_ACX_INTR_TX_RESULT |
294                 WL1251_ACX_INTR_EVENT_A |
295                 WL1251_ACX_INTR_EVENT_B |
296                 WL1251_ACX_INTR_INIT_COMPLETE;
297         wl1251_boot_target_enable_interrupts(wl);
298
299         /* unmask all mbox events  */
300         wl->event_mask = 0xffffffff;
301
302         ret = wl1251_event_unmask(wl);
303         if (ret < 0) {
304                 wl1251_error("EVENT mask setting failed");
305                 return ret;
306         }
307
308         wl1251_event_mbox_config(wl);
309
310         /* firmware startup completed */
311         return 0;
312 }
313
314 static int wl1251_boot_upload_firmware(struct wl1251 *wl)
315 {
316         int addr, chunk_num, partition_limit;
317         size_t fw_data_len;
318         u8 *p;
319
320         /* whal_FwCtrl_LoadFwImageSm() */
321
322         wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
323                      wl1251_reg_read32(wl, CHIP_ID_B));
324
325         /* 10.0 check firmware length and set partition */
326         fw_data_len =  (wl->fw[4] << 24) | (wl->fw[5] << 16) |
327                 (wl->fw[6] << 8) | (wl->fw[7]);
328
329         wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
330                 CHUNK_SIZE);
331
332         if ((fw_data_len % 4) != 0) {
333                 wl1251_error("firmware length not multiple of four");
334                 return -EIO;
335         }
336
337         wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
338                              WL1251_PART_DOWN_MEM_SIZE,
339                              WL1251_PART_DOWN_REG_START,
340                              WL1251_PART_DOWN_REG_SIZE);
341
342         /* 10.1 set partition limit and chunk num */
343         chunk_num = 0;
344         partition_limit = WL1251_PART_DOWN_MEM_SIZE;
345
346         while (chunk_num < fw_data_len / CHUNK_SIZE) {
347                 /* 10.2 update partition, if needed */
348                 addr = WL1251_PART_DOWN_MEM_START +
349                         (chunk_num + 2) * CHUNK_SIZE;
350                 if (addr > partition_limit) {
351                         addr = WL1251_PART_DOWN_MEM_START +
352                                 chunk_num * CHUNK_SIZE;
353                         partition_limit = chunk_num * CHUNK_SIZE +
354                                 WL1251_PART_DOWN_MEM_SIZE;
355                         wl1251_set_partition(wl,
356                                              addr,
357                                              WL1251_PART_DOWN_MEM_SIZE,
358                                              WL1251_PART_DOWN_REG_START,
359                                              WL1251_PART_DOWN_REG_SIZE);
360                 }
361
362                 /* 10.3 upload the chunk */
363                 addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
364                 p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
365                 wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
366                              p, addr);
367                 wl1251_mem_write(wl, addr, p, CHUNK_SIZE);
368
369                 chunk_num++;
370         }
371
372         /* 10.4 upload the last chunk */
373         addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
374         p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
375         wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
376                      fw_data_len % CHUNK_SIZE, p, addr);
377         wl1251_mem_write(wl, addr, p, fw_data_len % CHUNK_SIZE);
378
379         return 0;
380 }
381
382 static int wl1251_boot_upload_nvs(struct wl1251 *wl)
383 {
384         size_t nvs_len, nvs_bytes_written, burst_len;
385         int nvs_start, i;
386         u32 dest_addr, val;
387         u8 *nvs_ptr, *nvs;
388
389         nvs = wl->nvs;
390         if (nvs == NULL)
391                 return -ENODEV;
392
393         nvs_ptr = nvs;
394
395         nvs_len = wl->nvs_len;
396         nvs_start = wl->fw_len;
397
398         /*
399          * Layout before the actual NVS tables:
400          * 1 byte : burst length.
401          * 2 bytes: destination address.
402          * n bytes: data to burst copy.
403          *
404          * This is ended by a 0 length, then the NVS tables.
405          */
406
407         while (nvs_ptr[0]) {
408                 burst_len = nvs_ptr[0];
409                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
410
411                 /* We move our pointer to the data */
412                 nvs_ptr += 3;
413
414                 for (i = 0; i < burst_len; i++) {
415                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
416                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
417
418                         wl1251_debug(DEBUG_BOOT,
419                                      "nvs burst write 0x%x: 0x%x",
420                                      dest_addr, val);
421                         wl1251_mem_write32(wl, dest_addr, val);
422
423                         nvs_ptr += 4;
424                         dest_addr += 4;
425                 }
426         }
427
428         /*
429          * We've reached the first zero length, the first NVS table
430          * is 7 bytes further.
431          */
432         nvs_ptr += 7;
433         nvs_len -= nvs_ptr - nvs;
434         nvs_len = ALIGN(nvs_len, 4);
435
436         /* Now we must set the partition correctly */
437         wl1251_set_partition(wl, nvs_start,
438                              WL1251_PART_DOWN_MEM_SIZE,
439                              WL1251_PART_DOWN_REG_START,
440                              WL1251_PART_DOWN_REG_SIZE);
441
442         /* And finally we upload the NVS tables */
443         nvs_bytes_written = 0;
444         while (nvs_bytes_written < nvs_len) {
445                 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
446                        | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
447
448                 val = cpu_to_le32(val);
449
450                 wl1251_debug(DEBUG_BOOT,
451                              "nvs write table 0x%x: 0x%x",
452                              nvs_start, val);
453                 wl1251_mem_write32(wl, nvs_start, val);
454
455                 nvs_ptr += 4;
456                 nvs_bytes_written += 4;
457                 nvs_start += 4;
458         }
459
460         return 0;
461 }
462
463 int wl1251_boot(struct wl1251 *wl)
464 {
465         int ret = 0, minor_minor_e2_ver;
466         u32 tmp, boot_data;
467
468         ret = wl1251_boot_soft_reset(wl);
469         if (ret < 0)
470                 goto out;
471
472         /* 2. start processing NVS file */
473         ret = wl1251_boot_upload_nvs(wl);
474         if (ret < 0)
475                 goto out;
476
477         /* write firmware's last address (ie. it's length) to
478          * ACX_EEPROMLESS_IND_REG */
479         wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
480
481         /* 6. read the EEPROM parameters */
482         tmp = wl1251_reg_read32(wl, SCR_PAD2);
483
484         /* 7. read bootdata */
485         wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
486         wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
487         tmp = wl1251_reg_read32(wl, SCR_PAD3);
488
489         /* 8. check bootdata and call restart sequence */
490         wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
491         minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
492
493         wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
494                      "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
495                      wl->boot_attr.radio_type, wl->boot_attr.major,
496                      wl->boot_attr.minor, minor_minor_e2_ver);
497
498         ret = wl1251_boot_init_seq(wl);
499         if (ret < 0)
500                 goto out;
501
502         /* 9. NVS processing done */
503         boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
504
505         wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
506
507         /* 10. check that ECPU_CONTROL_HALT bits are set in
508          * pWhalBus->uBootData and start uploading firmware
509          */
510         if ((boot_data & ECPU_CONTROL_HALT) == 0) {
511                 wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
512                 ret = -EIO;
513                 goto out;
514         }
515
516         ret = wl1251_boot_upload_firmware(wl);
517         if (ret < 0)
518                 goto out;
519
520         /* 10.5 start firmware */
521         ret = wl1251_boot_run_firmware(wl);
522         if (ret < 0)
523                 goto out;
524
525 out:
526         return ret;
527 }