Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / wireless / wl12xx / wl1251_boot.c
1 /*
2  * This file is part of wl1251
3  *
4  * Copyright (C) 2008 Nokia Corporation
5  *
6  * Contact: Kalle Valo <kalle.valo@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but
13  * WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20  * 02110-1301 USA
21  *
22  */
23
24 #include <linux/gpio.h>
25 #include <linux/slab.h>
26
27 #include "wl1251_reg.h"
28 #include "wl1251_boot.h"
29 #include "wl1251_io.h"
30 #include "wl1251_spi.h"
31 #include "wl1251_event.h"
32 #include "wl1251_acx.h"
33
34 void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
35 {
36         wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
37         wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
38 }
39
40 int wl1251_boot_soft_reset(struct wl1251 *wl)
41 {
42         unsigned long timeout;
43         u32 boot_data;
44
45         /* perform soft reset */
46         wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
47
48         /* SOFT_RESET is self clearing */
49         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
50         while (1) {
51                 boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
52                 wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
53                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
54                         break;
55
56                 if (time_after(jiffies, timeout)) {
57                         /* 1.2 check pWhalBus->uSelfClearTime if the
58                          * timeout was reached */
59                         wl1251_error("soft reset timeout");
60                         return -1;
61                 }
62
63                 udelay(SOFT_RESET_STALL_TIME);
64         }
65
66         /* disable Rx/Tx */
67         wl1251_reg_write32(wl, ENABLE, 0x0);
68
69         /* disable auto calibration on start*/
70         wl1251_reg_write32(wl, SPARE_A2, 0xffff);
71
72         return 0;
73 }
74
75 int wl1251_boot_init_seq(struct wl1251 *wl)
76 {
77         u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
78
79         /*
80          * col #1: INTEGER_DIVIDER
81          * col #2: FRACTIONAL_DIVIDER
82          * col #3: ATTN_BB
83          * col #4: ALPHA_BB
84          * col #5: STOP_TIME_BB
85          * col #6: BB_PLL_LOOP_FILTER
86          */
87         static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {
88
89                 {   83, 87381,  0xB, 5, 0xF00,  3}, /* REF_FREQ_19_2*/
90                 {   61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
91                 {   41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
92                 {   40, 0,      0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
93                 {   47, 162280, 0xC, 6, 0x2760, 1}  /* REF_FREQ_33_6        */
94         };
95
96         /* read NVS params */
97         scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
98         wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
99
100         /* read ELP_CMD */
101         elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
102         wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
103
104         /* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
105         ref_freq = scr_pad6 & 0x000000FF;
106         wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
107
108         wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
109
110         /*
111          * PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
112          */
113         wl1251_reg_write32(wl, CLK_BUF_TIME, 0x6);
114
115         /*
116          * set the clock detect feature to work in the restart wu procedure
117          * (ELP_CFG_MODE[14]) and Select the clock source type
118          * (ELP_CFG_MODE[13:12])
119          */
120         tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
121         wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
122
123         /* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
124         elp_cmd |= 0x00000040;
125         wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
126
127         /* PG 1.2: Set the BB PLL stable time to be 1000usec
128          * (PLL_STABLE_TIME) */
129         wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
130
131         /* PG 1.2: read clock request time */
132         init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
133
134         /*
135          * PG 1.2: set the clock request time to be ref_clk_settling_time -
136          * 1ms = 4ms
137          */
138         if (init_data > 0x21)
139                 tmp = init_data - 0x21;
140         else
141                 tmp = 0;
142         wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
143
144         /* set BB PLL configurations in RF AFE */
145         wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
146
147         /* set RF_AFE_REG_5 */
148         wl1251_reg_write32(wl, 0x003058d4, 0x50);
149
150         /* set RF_AFE_CTRL_REG_2 */
151         wl1251_reg_write32(wl, 0x00305948, 0x11c001);
152
153         /*
154          * change RF PLL and BB PLL divider for VCO clock and adjust VCO
155          * bais current(RF_AFE_REG_13)
156          */
157         wl1251_reg_write32(wl, 0x003058f4, 0x1e);
158
159         /* set BB PLL configurations */
160         tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
161         wl1251_reg_write32(wl, 0x00305840, tmp);
162
163         /* set fractional divider according to Appendix C-BB PLL
164          * Calculations
165          */
166         tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
167         wl1251_reg_write32(wl, 0x00305844, tmp);
168
169         /* set the initial data for the sigma delta */
170         wl1251_reg_write32(wl, 0x00305848, 0x3039);
171
172         /*
173          * set the accumulator attenuation value, calibration loop1
174          * (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
175          * the VCO gain
176          */
177         tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
178                 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
179         wl1251_reg_write32(wl, 0x00305854, tmp);
180
181         /*
182          * set the calibration stop time after holdoff time expires and set
183          * settling time HOLD_OFF_TIME_BB
184          */
185         tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
186         wl1251_reg_write32(wl, 0x00305858, tmp);
187
188         /*
189          * set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
190          * constant leakage current to linearize PFD to 0uA -
191          * BB_ILOOPF[7:3]
192          */
193         tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
194         wl1251_reg_write32(wl, 0x003058f8, tmp);
195
196         /*
197          * set regulator output voltage for n divider to
198          * 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
199          * set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
200          * PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
201          */
202         wl1251_reg_write32(wl, 0x003058f0, 0x29);
203
204         /* enable restart wakeup sequence (ELP_CMD[0]) */
205         wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
206
207         /* restart sequence completed */
208         udelay(2000);
209
210         return 0;
211 }
212
213 static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
214 {
215         u32 cpu_ctrl;
216
217         /* 10.5.0 run the firmware (I) */
218         cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
219
220         /* 10.5.1 run the firmware (II) */
221         cpu_ctrl &= ~flag;
222         wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
223 }
224
225 int wl1251_boot_run_firmware(struct wl1251 *wl)
226 {
227         int loop, ret;
228         u32 chip_id, interrupt;
229
230         wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
231
232         chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
233
234         wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
235
236         if (chip_id != wl->chip_id) {
237                 wl1251_error("chip id doesn't match after firmware boot");
238                 return -EIO;
239         }
240
241         /* wait for init to complete */
242         loop = 0;
243         while (loop++ < INIT_LOOP) {
244                 udelay(INIT_LOOP_DELAY);
245                 interrupt = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
246
247                 if (interrupt == 0xffffffff) {
248                         wl1251_error("error reading hardware complete "
249                                      "init indication");
250                         return -EIO;
251                 }
252                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
253                 else if (interrupt & WL1251_ACX_INTR_INIT_COMPLETE) {
254                         wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
255                                            WL1251_ACX_INTR_INIT_COMPLETE);
256                         break;
257                 }
258         }
259
260         if (loop > INIT_LOOP) {
261                 wl1251_error("timeout waiting for the hardware to "
262                              "complete initialization");
263                 return -EIO;
264         }
265
266         /* get hardware config command mail box */
267         wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
268
269         /* get hardware config event mail box */
270         wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
271
272         /* set the working partition to its "running" mode offset */
273         wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
274                              WL1251_PART_WORK_MEM_SIZE,
275                              WL1251_PART_WORK_REG_START,
276                              WL1251_PART_WORK_REG_SIZE);
277
278         wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
279                      wl->cmd_box_addr, wl->event_box_addr);
280
281         wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));
282
283         /*
284          * in case of full asynchronous mode the firmware event must be
285          * ready to receive event from the command mailbox
286          */
287
288         /* enable gpio interrupts */
289         wl1251_enable_interrupts(wl);
290
291         /* Enable target's interrupts */
292         wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
293                 WL1251_ACX_INTR_RX1_DATA |
294                 WL1251_ACX_INTR_TX_RESULT |
295                 WL1251_ACX_INTR_EVENT_A |
296                 WL1251_ACX_INTR_EVENT_B |
297                 WL1251_ACX_INTR_INIT_COMPLETE;
298         wl1251_boot_target_enable_interrupts(wl);
299
300         wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID |
301                 SYNCHRONIZATION_TIMEOUT_EVENT_ID |
302                 ROAMING_TRIGGER_LOW_RSSI_EVENT_ID |
303                 ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID |
304                 REGAINED_BSS_EVENT_ID | BT_PTA_SENSE_EVENT_ID |
305                 BT_PTA_PREDICTION_EVENT_ID;
306
307         ret = wl1251_event_unmask(wl);
308         if (ret < 0) {
309                 wl1251_error("EVENT mask setting failed");
310                 return ret;
311         }
312
313         wl1251_event_mbox_config(wl);
314
315         /* firmware startup completed */
316         return 0;
317 }
318
319 static int wl1251_boot_upload_firmware(struct wl1251 *wl)
320 {
321         int addr, chunk_num, partition_limit;
322         size_t fw_data_len, len;
323         u8 *p, *buf;
324
325         /* whal_FwCtrl_LoadFwImageSm() */
326
327         wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
328                      wl1251_reg_read32(wl, CHIP_ID_B));
329
330         /* 10.0 check firmware length and set partition */
331         fw_data_len =  (wl->fw[4] << 24) | (wl->fw[5] << 16) |
332                 (wl->fw[6] << 8) | (wl->fw[7]);
333
334         wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
335                 CHUNK_SIZE);
336
337         if ((fw_data_len % 4) != 0) {
338                 wl1251_error("firmware length not multiple of four");
339                 return -EIO;
340         }
341
342         buf = kmalloc(CHUNK_SIZE, GFP_KERNEL);
343         if (!buf) {
344                 wl1251_error("allocation for firmware upload chunk failed");
345                 return -ENOMEM;
346         }
347
348         wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
349                              WL1251_PART_DOWN_MEM_SIZE,
350                              WL1251_PART_DOWN_REG_START,
351                              WL1251_PART_DOWN_REG_SIZE);
352
353         /* 10.1 set partition limit and chunk num */
354         chunk_num = 0;
355         partition_limit = WL1251_PART_DOWN_MEM_SIZE;
356
357         while (chunk_num < fw_data_len / CHUNK_SIZE) {
358                 /* 10.2 update partition, if needed */
359                 addr = WL1251_PART_DOWN_MEM_START +
360                         (chunk_num + 2) * CHUNK_SIZE;
361                 if (addr > partition_limit) {
362                         addr = WL1251_PART_DOWN_MEM_START +
363                                 chunk_num * CHUNK_SIZE;
364                         partition_limit = chunk_num * CHUNK_SIZE +
365                                 WL1251_PART_DOWN_MEM_SIZE;
366                         wl1251_set_partition(wl,
367                                              addr,
368                                              WL1251_PART_DOWN_MEM_SIZE,
369                                              WL1251_PART_DOWN_REG_START,
370                                              WL1251_PART_DOWN_REG_SIZE);
371                 }
372
373                 /* 10.3 upload the chunk */
374                 addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
375                 p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
376                 wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
377                              p, addr);
378
379                 /* need to copy the chunk for dma */
380                 len = CHUNK_SIZE;
381                 memcpy(buf, p, len);
382                 wl1251_mem_write(wl, addr, buf, len);
383
384                 chunk_num++;
385         }
386
387         /* 10.4 upload the last chunk */
388         addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
389         p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
390
391         /* need to copy the chunk for dma */
392         len = fw_data_len % CHUNK_SIZE;
393         memcpy(buf, p, len);
394
395         wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
396                      len, p, addr);
397         wl1251_mem_write(wl, addr, buf, len);
398
399         kfree(buf);
400
401         return 0;
402 }
403
404 static int wl1251_boot_upload_nvs(struct wl1251 *wl)
405 {
406         size_t nvs_len, nvs_bytes_written, burst_len;
407         int nvs_start, i;
408         u32 dest_addr, val;
409         u8 *nvs_ptr, *nvs;
410
411         nvs = wl->nvs;
412         if (nvs == NULL)
413                 return -ENODEV;
414
415         nvs_ptr = nvs;
416
417         nvs_len = wl->nvs_len;
418         nvs_start = wl->fw_len;
419
420         /*
421          * Layout before the actual NVS tables:
422          * 1 byte : burst length.
423          * 2 bytes: destination address.
424          * n bytes: data to burst copy.
425          *
426          * This is ended by a 0 length, then the NVS tables.
427          */
428
429         while (nvs_ptr[0]) {
430                 burst_len = nvs_ptr[0];
431                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
432
433                 /* We move our pointer to the data */
434                 nvs_ptr += 3;
435
436                 for (i = 0; i < burst_len; i++) {
437                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
438                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
439
440                         wl1251_debug(DEBUG_BOOT,
441                                      "nvs burst write 0x%x: 0x%x",
442                                      dest_addr, val);
443                         wl1251_mem_write32(wl, dest_addr, val);
444
445                         nvs_ptr += 4;
446                         dest_addr += 4;
447                 }
448         }
449
450         /*
451          * We've reached the first zero length, the first NVS table
452          * is 7 bytes further.
453          */
454         nvs_ptr += 7;
455         nvs_len -= nvs_ptr - nvs;
456         nvs_len = ALIGN(nvs_len, 4);
457
458         /* Now we must set the partition correctly */
459         wl1251_set_partition(wl, nvs_start,
460                              WL1251_PART_DOWN_MEM_SIZE,
461                              WL1251_PART_DOWN_REG_START,
462                              WL1251_PART_DOWN_REG_SIZE);
463
464         /* And finally we upload the NVS tables */
465         nvs_bytes_written = 0;
466         while (nvs_bytes_written < nvs_len) {
467                 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
468                        | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
469
470                 val = cpu_to_le32(val);
471
472                 wl1251_debug(DEBUG_BOOT,
473                              "nvs write table 0x%x: 0x%x",
474                              nvs_start, val);
475                 wl1251_mem_write32(wl, nvs_start, val);
476
477                 nvs_ptr += 4;
478                 nvs_bytes_written += 4;
479                 nvs_start += 4;
480         }
481
482         return 0;
483 }
484
485 int wl1251_boot(struct wl1251 *wl)
486 {
487         int ret = 0, minor_minor_e2_ver;
488         u32 tmp, boot_data;
489
490         /* halt embedded ARM CPU while loading firmware */
491         wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);
492
493         ret = wl1251_boot_soft_reset(wl);
494         if (ret < 0)
495                 goto out;
496
497         /* 2. start processing NVS file */
498         if (wl->use_eeprom) {
499                 wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR);
500                 /* Wait for EEPROM NVS burst read to complete */
501                 msleep(40);
502                 wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM);
503         } else {
504                 ret = wl1251_boot_upload_nvs(wl);
505                 if (ret < 0)
506                         goto out;
507
508                 /* write firmware's last address (ie. it's length) to
509                  * ACX_EEPROMLESS_IND_REG */
510                 wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
511         }
512
513         /* 6. read the EEPROM parameters */
514         tmp = wl1251_reg_read32(wl, SCR_PAD2);
515
516         /* 7. read bootdata */
517         wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
518         wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
519         tmp = wl1251_reg_read32(wl, SCR_PAD3);
520
521         /* 8. check bootdata and call restart sequence */
522         wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
523         minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
524
525         wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
526                      "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
527                      wl->boot_attr.radio_type, wl->boot_attr.major,
528                      wl->boot_attr.minor, minor_minor_e2_ver);
529
530         ret = wl1251_boot_init_seq(wl);
531         if (ret < 0)
532                 goto out;
533
534         /* 9. NVS processing done */
535         boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
536
537         wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
538
539         /* 10. check that ECPU_CONTROL_HALT bits are set in
540          * pWhalBus->uBootData and start uploading firmware
541          */
542         if ((boot_data & ECPU_CONTROL_HALT) == 0) {
543                 wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
544                 ret = -EIO;
545                 goto out;
546         }
547
548         ret = wl1251_boot_upload_firmware(wl);
549         if (ret < 0)
550                 goto out;
551
552         /* 10.5 start firmware */
553         ret = wl1251_boot_run_firmware(wl);
554         if (ret < 0)
555                 goto out;
556
557 out:
558         return ret;
559 }