1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
33 #include <linux/sched.h>
34 #include <linux/firmware.h>
35 #include <linux/version.h>
36 #include <linux/etherdevice.h>
37 #include <linux/usb.h>
38 #include <net/mac80211.h>
41 #define RF_CHANGE_BY_INIT 0
42 #define RF_CHANGE_BY_IPS BIT(28)
43 #define RF_CHANGE_BY_PS BIT(29)
44 #define RF_CHANGE_BY_HW BIT(30)
45 #define RF_CHANGE_BY_SW BIT(31)
47 #define IQK_ADDA_REG_NUM 16
48 #define IQK_MAC_REG_NUM 4
50 #define MAX_KEY_LEN 61
51 #define KEY_BUF_SIZE 5
54 /*aci: 0x00 Best Effort*/
55 /*aci: 0x01 Background*/
58 /*Max: define total number.*/
64 #define QOS_QUEUE_NUM 4
65 #define RTL_MAC80211_NUM_QUEUE 5
67 #define QBSS_LOAD_SIZE 5
68 #define MAX_WMMELE_LENGTH 64
70 /*slot time for 11g. */
71 #define RTL_SLOT_TIME_9 9
72 #define RTL_SLOT_TIME_20 20
74 /*related with tcp/ip. */
76 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
77 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
78 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
80 #define PROTOC_TYPE_SIZE 2
82 /*related with 802.11 frame*/
83 #define MAC80211_3ADDR_LEN 24
84 #define MAC80211_4ADDR_LEN 30
86 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
87 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
88 #define MAX_PG_GROUP 13
89 #define CHANNEL_GROUP_MAX_2G 3
90 #define CHANNEL_GROUP_IDX_5GL 3
91 #define CHANNEL_GROUP_IDX_5GM 6
92 #define CHANNEL_GROUP_IDX_5GH 9
93 #define CHANNEL_GROUP_MAX_5G 9
94 #define CHANNEL_MAX_NUMBER_2G 14
95 #define AVG_THERMAL_NUM 8
111 enum rt_eeprom_type {
118 RTL_STATUS_INTERFACE_START = 0,
122 HARDWARE_TYPE_RTL8192E,
123 HARDWARE_TYPE_RTL8192U,
124 HARDWARE_TYPE_RTL8192SE,
125 HARDWARE_TYPE_RTL8192SU,
126 HARDWARE_TYPE_RTL8192CE,
127 HARDWARE_TYPE_RTL8192CU,
128 HARDWARE_TYPE_RTL8192DE,
129 HARDWARE_TYPE_RTL8192DU,
130 HARDWARE_TYPE_RTL8723E,
131 HARDWARE_TYPE_RTL8723U,
137 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
138 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
139 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
140 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
141 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
142 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
143 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
144 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
145 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
146 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
147 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
148 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
149 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
150 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
151 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
152 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
153 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
154 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
155 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
156 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
157 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
158 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
159 #define IS_HARDWARE_TYPE_8723(rtlhal) \
160 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
162 enum scan_operation_backup_opt {
185 u32 rfswitch_control;
188 u32 rfrxiq_imbalance;
190 u32 rftxiq_imbalance;
193 u32 rflssi_readbackpi;
197 IO_CMD_PAUSE_DM_BY_SCAN = 0,
198 IO_CMD_RESUME_DM_BY_SCAN = 1,
203 HW_VAR_MULTICAST_REG,
207 HW_VAR_SECURITY_CONF,
208 HW_VAR_BEACON_INTERVAL,
210 HW_VAR_LISTEN_INTERVAL,
223 HW_VAR_RATE_FALLBACK_CONTROL,
224 HW_VAR_CONTENTION_WINDOW,
229 HW_VAR_AMPDU_MIN_SPACE,
230 HW_VAR_SHORTGI_DENSITY,
232 HW_VAR_MCS_RATE_AVAILABLE,
235 HW_VAR_DIS_Req_Qsize,
236 HW_VAR_CCX_CHNL_LOAD,
237 HW_VAR_CCX_NOISE_HISTOGRAM,
244 HW_VAR_SET_DEV_POWER,
254 HW_VAR_USER_CONTROL_TURBO_MODE,
260 HW_VAR_AUTOLOAD_STATUS,
261 HW_VAR_RF_2R_DISABLE,
263 HW_VAR_H2C_FW_PWRMODE,
264 HW_VAR_H2C_FW_JOINBSSRPT,
265 HW_VAR_FW_PSMODE_STATUS,
266 HW_VAR_1X1_RECV_COMBINE,
267 HW_VAR_STOP_SEND_BEACON,
272 HW_VAR_H2C_FW_UPDATE_GTK,
275 HW_VAR_WF_IS_MAC_ADDR,
276 HW_VAR_H2C_FW_OFFLOAD,
279 HW_VAR_HANDLE_FW_C2H,
280 HW_VAR_DL_FW_RSVD_PAGE,
282 HW_VAR_HW_SEQ_ENABLE,
287 HW_VAR_SWITCH_EPHY_WoWLAN,
288 HW_VAR_INT_MIGRATION,
299 enum _RT_MEDIA_STATUS {
300 RT_MEDIA_DISCONNECT = 0,
306 RT_CID_8187_ALPHA0 = 1,
307 RT_CID_8187_SERCOMM_PS = 2,
308 RT_CID_8187_HW_LED = 3,
309 RT_CID_8187_NETGEAR = 4,
311 RT_CID_819x_CAMEO = 6,
312 RT_CID_819x_RUNTOP = 7,
313 RT_CID_819x_Senao = 8,
315 RT_CID_819x_Netcore = 10,
316 RT_CID_Nettronix = 11,
320 RT_CID_819x_ALPHA = 15,
321 RT_CID_819x_Sitecom = 16,
323 RT_CID_819x_Lenovo = 18,
324 RT_CID_819x_QMI = 19,
325 RT_CID_819x_Edimax_Belkin = 20,
326 RT_CID_819x_Sercomm_Belkin = 21,
327 RT_CID_819x_CAMEO1 = 22,
328 RT_CID_819x_MSI = 23,
329 RT_CID_819x_Acer = 24,
331 RT_CID_819x_CLEVO = 28,
332 RT_CID_819x_Arcadyan_Belkin = 29,
333 RT_CID_819x_SAMSUNG = 30,
334 RT_CID_819x_WNC_COREGA = 31,
335 RT_CID_819x_Foxcoon = 32,
336 RT_CID_819x_DELL = 33,
342 HW_DESC_TX_NEXTDESC_ADDR,
350 PRIME_CHNL_OFFSET_DONT_CARE = 0,
351 PRIME_CHNL_OFFSET_LOWER = 1,
352 PRIME_CHNL_OFFSET_UPPER = 2,
362 enum ht_channel_width {
363 HT_CHANNEL_WIDTH_20 = 0,
364 HT_CHANNEL_WIDTH_20_40 = 1,
367 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
368 Cipher Suites Encryption Algorithms */
371 WEP40_ENCRYPTION = 1,
373 RSERVED_ENCRYPTION = 3,
374 AESCCMP_ENCRYPTION = 4,
375 WEP104_ENCRYPTION = 5,
380 _HAL_STATE_START = 1,
403 EFUSE_HWSET_MAX_SIZE,
404 EFUSE_MAX_SECTION_MAP,
405 EFUSE_REAL_CONTENT_SIZE,
420 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
421 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
422 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
423 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
424 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
425 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
426 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
427 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
428 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
429 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
430 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
431 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
432 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
433 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
434 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
435 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
436 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
437 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
438 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
439 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
440 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
441 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
442 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
443 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
444 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
445 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
446 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
447 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
448 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
449 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
450 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
451 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
452 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
453 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
456 /*CCK Rates, TxHT = 0 */
462 /*OFDM Rates, TxHT = 0 */
479 /*Firmware PS mode for control LPS.*/
481 FW_PS_ACTIVE_MODE = 0,
486 FW_PS_UAPSD_WMM_MODE = 5,
487 FW_PS_UAPSD_MODE = 6,
489 FW_PS_WWLAN_MODE = 8,
490 FW_PS_PM_Radio_Off = 9,
491 FW_PS_PM_Card_Disable = 10,
495 EACTIVE, /*Active/Continuous access. */
496 EMAXPS, /*Max power save mode. */
497 EFASTPS, /*Fast power save mode. */
498 EAUTOPS, /*Auto power save mode. */
503 LED_CTL_POWER_ON = 1,
508 LED_CTL_SITE_SURVEY = 6,
509 LED_CTL_POWER_OFF = 7,
510 LED_CTL_START_TO_LINK = 8,
511 LED_CTL_START_WPS = 9,
512 LED_CTL_STOP_WPS = 10,
523 /*acm implementation method.*/
525 eAcmWay0_SwAndHw = 0,
531 SINGLEMAC_SINGLEPHY = 0,
544 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
558 WIRELESS_MODE_UNKNOWN = 0x00,
559 WIRELESS_MODE_A = 0x01,
560 WIRELESS_MODE_B = 0x02,
561 WIRELESS_MODE_G = 0x04,
562 WIRELESS_MODE_AUTO = 0x08,
563 WIRELESS_MODE_N_24G = 0x10,
564 WIRELESS_MODE_N_5G = 0x20
567 #define IS_WIRELESS_MODE_A(wirelessmode) \
568 (wirelessmode == WIRELESS_MODE_A)
569 #define IS_WIRELESS_MODE_B(wirelessmode) \
570 (wirelessmode == WIRELESS_MODE_B)
571 #define IS_WIRELESS_MODE_G(wirelessmode) \
572 (wirelessmode == WIRELESS_MODE_G)
573 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
574 (wirelessmode == WIRELESS_MODE_N_24G)
575 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
576 (wirelessmode == WIRELESS_MODE_N_5G)
578 enum ratr_table_mode {
579 RATR_INX_WIRELESS_NGB = 0,
580 RATR_INX_WIRELESS_NG = 1,
581 RATR_INX_WIRELESS_NB = 2,
582 RATR_INX_WIRELESS_N = 3,
583 RATR_INX_WIRELESS_GB = 4,
584 RATR_INX_WIRELESS_G = 5,
585 RATR_INX_WIRELESS_B = 6,
586 RATR_INX_WIRELESS_MC = 7,
587 RATR_INX_WIRELESS_A = 8,
590 enum rtl_link_state {
592 MAC80211_LINKING = 1,
594 MAC80211_LINKED_SCANNING = 3,
611 struct octet_string {
616 struct rtl_hdr_3addr {
626 struct rtl_info_element {
632 struct rtl_probe_rsp {
633 struct rtl_hdr_3addr header;
635 __le16 beacon_interval;
637 /*SSID, supported rates, FH params, DS params,
638 CF params, IBSS params, TIM (if beacon), RSN */
639 struct rtl_info_element info_element[0];
643 /*ledpin Identify how to implement this SW led.*/
646 enum rtl_led_pin ledpin;
652 struct rtl_led sw_led0;
653 struct rtl_led sw_led1;
656 struct rtl_qos_parameters {
664 struct rt_smooth_data {
665 u32 elements[100]; /*array to store values */
666 u32 index; /*index to current array to store */
667 u32 total_num; /*num of valid elements */
668 u32 total_val; /*sum of valid elements */
671 struct false_alarm_statistics {
673 u32 cnt_rate_illegal;
676 u32 cnt_fast_fsync_fail;
677 u32 cnt_sb_search_fail;
692 struct wireless_stats {
693 unsigned long txbytesunicast;
694 unsigned long txbytesmulticast;
695 unsigned long txbytesbroadcast;
696 unsigned long rxbytesunicast;
699 /*Correct smoothed ss in Dbm, only used
700 in driver to report real power now. */
701 long recv_signal_power;
703 long last_sigstrength_inpercent;
705 u32 rssi_calculate_cnt;
707 /*Transformed, in dbm. Beautified signal
708 strength for UI, not correct. */
709 long signal_strength;
711 u8 rx_rssi_percentage[4];
712 u8 rx_evm_percentage[2];
714 struct rt_smooth_data ui_rssi;
715 struct rt_smooth_data ui_link_quality;
718 struct rate_adaptive {
719 u8 rate_adaptive_disabled;
723 u32 high_rssi_thresh_for_ra;
724 u32 high2low_rssi_thresh_for_ra;
725 u8 low2high_rssi_thresh_for_ra40m;
726 u32 low_rssi_thresh_for_ra40M;
727 u8 low2high_rssi_thresh_for_ra20m;
728 u32 low_rssi_thresh_for_ra20M;
729 u32 upper_rssi_threshold_ratr;
730 u32 middleupper_rssi_threshold_ratr;
731 u32 middle_rssi_threshold_ratr;
732 u32 middlelow_rssi_threshold_ratr;
733 u32 low_rssi_threshold_ratr;
734 u32 ultralow_rssi_threshold_ratr;
735 u32 low_rssi_threshold_ratr_40m;
736 u32 low_rssi_threshold_ratr_20m;
739 u32 ping_rssi_thresh_for_ra;
744 struct regd_pair_mapping {
750 struct rtl_regulatory {
758 struct regd_pair_mapping *regpair;
762 bool rfkill_state; /*0 is off, 1 is on */
765 #define IQK_MATRIX_REG_NUM 8
766 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
767 struct iqk_matrix_regs {
769 long value[1][IQK_MATRIX_REG_NUM];
772 struct phy_parameters {
777 enum hw_param_tab_index {
792 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
793 struct init_gain initgain_backup;
794 enum io_type current_io_type;
799 u8 set_bwmode_inprogress;
800 u8 sw_chnl_inprogress;
805 u8 set_io_inprogress;
808 /* record for power tracking */
820 u32 reg_c04, reg_c08, reg_874;
822 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
823 u32 iqk_bb_backup[10];
827 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
833 /* MAX_PG_GROUP groups of pwr diff by rates */
834 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
835 u8 default_initialgain[4];
837 /* the current Tx power level */
839 u8 cur_ofdm24g_txpwridx;
841 u32 rfreg_chnlval[2];
843 u32 reg_rf3c[2]; /* pathA / pathB */
849 struct phy_parameters hwparam_tables[MAX_TAB];
853 #define MAX_TID_COUNT 9
854 #define RTL_AGG_OFF 0
856 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
857 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
868 struct rtl_tid_data {
870 struct rtl_ht_agg agg;
876 struct mutex bb_mutex;
879 unsigned long pci_mem_end; /*shared mem end */
880 unsigned long pci_mem_start; /*shared mem start */
883 unsigned long pci_base_addr; /*device I/O address */
885 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
886 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
887 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
888 int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
891 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
892 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
893 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
894 int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
899 u8 mac_addr[ETH_ALEN];
900 u8 mac80211_registered;
906 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
907 struct ieee80211_hw *hw;
908 struct ieee80211_vif *vif;
909 enum nl80211_iftype opmode;
911 /*Probe Beacon management */
912 struct rtl_tid_data tids[MAX_TID_COUNT];
913 enum rtl_link_state link_state;
929 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
930 u8 earlymode_threshold;
938 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
939 u32 basic_rates; /* b/g rates */
944 u8 mode; /* wireless mode */
949 u8 cur_40_prime_sc_bk;
959 u8 min_space_cfg; /*For Min spacing configurations */
961 u8 current_ampdu_factor;
962 u8 current_ampdu_density;
965 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
966 struct rtl_qos_parameters ac[AC_MAX];
970 struct ieee80211_hw *hw;
972 enum intf_type interface;
973 u16 hw_type; /*92c or 92d or 92s and so on */
976 u32 version; /*version of chip */
977 u8 state; /*stop 0, start 1 */
984 bool h2c_setinprogress;
987 /*Reserve page start offset except beacon in TxQ. */
988 u8 fw_rsvdpage_startoffset;
991 /* FW Cmd IO related */
994 bool set_fwcmd_inprogress;
998 bool driver_going2unload;
1000 /*AMPDU init min space*/
1001 u8 minspace_cfg; /*For Min spacing configurations */
1004 enum macphy_mode macphymode;
1005 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1006 enum band_type current_bandtypebackup;
1007 enum band_type bandset;
1008 /* dual MAC 0--Mac0 1--Mac1 */
1010 /* just for DualMac S3S4 */
1012 bool earlymode_enable;
1014 bool during_mac0init_radiob;
1015 bool during_mac1init_radioa;
1016 bool reloadtxpowerindex;
1017 /* True if IMR or IQK have done
1018 for 2.4G in scan progress */
1019 bool load_imrandiqk_setting_for2g;
1021 bool disable_amsdu_8k;
1024 struct rtl_security {
1029 bool use_defaultkey;
1030 /*Encryption Algorithm for Unicast Packet */
1031 enum rt_enc_alg pairwise_enc_algorithm;
1032 /*Encryption Algorithm for Brocast/Multicast */
1033 enum rt_enc_alg group_enc_algorithm;
1035 /*local Key buffer, indx 0 is for
1036 pairwise key 1-4 is for agoup key. */
1037 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1038 u8 key_len[KEY_BUF_SIZE];
1040 /*The pointer of Pairwise Key,
1041 it always points to KeyBuf[4] */
1046 /*PHY status for Dynamic Management */
1047 long entry_min_undecoratedsmoothed_pwdb;
1048 long undecorated_smoothed_pwdb; /*out dm */
1049 long entry_max_undecoratedsmoothed_pwdb;
1050 bool dm_initialgain_enable;
1051 bool dynamic_txpower_enable;
1052 bool current_turbo_edca;
1053 bool is_any_nonbepkts; /*out dm */
1054 bool is_cur_rdlstate;
1055 bool txpower_trackingInit;
1056 bool disable_framebursting;
1058 bool txpower_tracking;
1060 bool rfpath_rxenable[4];
1061 bool inform_fw_driverctrldm;
1062 bool current_mrc_switch;
1065 u8 thermalvalue_rxgain;
1066 u8 thermalvalue_iqk;
1067 u8 thermalvalue_lck;
1070 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1071 u8 thermalvalue_avg_index;
1073 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1074 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1076 u8 txpower_track_control;
1077 bool interrupt_migration;
1078 bool disable_tx_int;
1081 u8 power_index_backup[6];
1084 #define EFUSE_MAX_LOGICAL_SIZE 256
1089 u16 max_physical_size;
1091 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1092 u16 efuse_usedbytes;
1093 u8 efuse_usedpercentage;
1094 #ifdef EFUSE_REPG_WORKAROUND
1095 bool efuse_re_pg_sec1flag;
1096 u8 efuse_re_pg_data[8];
1099 u8 autoload_failflag;
1108 u16 eeprom_channelplan;
1115 bool txpwr_fromeprom;
1116 u8 eeprom_crystalcap;
1118 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1119 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1120 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1121 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1122 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1123 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
1124 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1125 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1126 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1128 u8 internal_pa_5g[2]; /* pathA / pathB */
1132 /*For power group */
1133 u8 eeprom_pwrgroup[2][3];
1134 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1135 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1137 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1138 /*For HT<->legacy pwr diff*/
1139 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1140 u8 txpwr_safetyflag; /* Band edge enable flag */
1141 u16 eeprom_txpowerdiff;
1142 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1143 u8 antenna_txpwdiff[3];
1145 u8 eeprom_regulatory;
1146 u8 eeprom_thermalmeter;
1147 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1149 u8 crystalcap; /* CrystalCap. */
1153 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1154 bool apk_thermalmeterignore;
1156 bool b1x1_recvcombine;
1164 bool pwrdomain_protect;
1165 bool set_rfpowerstate_inprogress;
1166 bool in_powersavemode;
1167 bool rfchange_inprogress;
1168 bool swrf_processing;
1172 * just for PCIE ASPM
1173 * If it supports ASPM, Offset[560h] = 0x40,
1174 * otherwise Offset[560h] = 0x00.
1177 bool support_backdoor;
1180 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1185 /*For Fw control LPS mode */
1187 /*Record Fw PS mode status. */
1188 bool fw_current_inpsmode;
1189 u8 reg_max_lps_awakeintvl;
1201 /*just for PCIE ASPM */
1202 u8 const_amdpci_aspm;
1206 enum rf_pwrstate inactive_pwrstate;
1207 enum rf_pwrstate rfpwr_state; /*cur power state */
1213 bool multi_buffered;
1215 unsigned int dtim_counter;
1216 unsigned int sleep_ms;
1217 unsigned long last_sleep_jiffies;
1218 unsigned long last_awake_jiffies;
1219 unsigned long last_delaylps_stamp_jiffies;
1220 unsigned long last_dtim;
1221 unsigned long last_beacon;
1222 unsigned long last_action;
1223 unsigned long last_slept;
1231 u16 rate; /*in 100 kbps */
1232 u8 received_channel;
1241 u8 signalquality; /*in 0-100 index. */
1243 * Real power in dBm for this packet,
1244 * no beautification and aggregation.
1246 s32 recvsignalpower;
1247 s8 rxpower; /*in dBm Translate from PWdB */
1248 u8 signalstrength; /*in 0-100 index. */
1252 u16 shortpreamble:1;
1263 bool rx_is40Mhzpacket;
1265 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1266 s8 rx_mimo_signalquality[2];
1267 bool packet_matchbssid;
1270 bool packet_beacon; /*for rssi */
1271 char cck_adc_pwdb[4]; /*for rx path selection */
1274 struct rt_link_detect {
1275 u32 num_tx_in4period[4];
1276 u32 num_rx_in4period[4];
1278 u32 num_tx_inperiod;
1279 u32 num_rx_inperiod;
1282 bool higher_busytraffic;
1283 bool higher_busyrxtraffic;
1286 struct rtl_tcb_desc {
1294 u8 rts_use_shortpreamble:1;
1295 u8 rts_use_shortgi:1;
1301 u8 use_shortpreamble:1;
1302 u8 use_driver_rate:1;
1303 u8 disable_ratefallback:1;
1315 /* The max value by HW */
1319 struct rtl_hal_ops {
1320 int (*init_sw_vars) (struct ieee80211_hw *hw);
1321 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1322 void (*read_chip_version)(struct ieee80211_hw *hw);
1323 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1324 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1325 u32 *p_inta, u32 *p_intb);
1326 int (*hw_init) (struct ieee80211_hw *hw);
1327 void (*hw_disable) (struct ieee80211_hw *hw);
1328 void (*hw_suspend) (struct ieee80211_hw *hw);
1329 void (*hw_resume) (struct ieee80211_hw *hw);
1330 void (*enable_interrupt) (struct ieee80211_hw *hw);
1331 void (*disable_interrupt) (struct ieee80211_hw *hw);
1332 int (*set_network_type) (struct ieee80211_hw *hw,
1333 enum nl80211_iftype type);
1334 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1336 void (*set_bw_mode) (struct ieee80211_hw *hw,
1337 enum nl80211_channel_type ch_type);
1338 u8(*switch_channel) (struct ieee80211_hw *hw);
1339 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1340 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1341 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1342 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1343 u32 add_msr, u32 rm_msr);
1344 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1345 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1346 void (*update_rate_table) (struct ieee80211_hw *hw);
1347 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1348 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1349 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1350 struct ieee80211_tx_info *info,
1351 struct sk_buff *skb, unsigned int queue_index);
1352 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 * pDesc,
1353 u32 buffer_len, bool bIsPsPoll);
1354 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1355 bool firstseg, bool lastseg,
1356 struct sk_buff *skb);
1357 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1358 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1359 struct rtl_stats *stats,
1360 struct ieee80211_rx_status *rx_status,
1361 u8 *pdesc, struct sk_buff *skb);
1362 void (*set_channel_access) (struct ieee80211_hw *hw);
1363 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1364 void (*dm_watchdog) (struct ieee80211_hw *hw);
1365 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1366 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1367 enum rf_pwrstate rfpwr_state);
1368 void (*led_control) (struct ieee80211_hw *hw,
1369 enum led_ctl_mode ledaction);
1370 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1371 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1372 void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue);
1373 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1374 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1375 u8 *p_macaddr, bool is_group, u8 enc_algo,
1376 bool is_wepkey, bool clear_all);
1377 void (*init_sw_leds) (struct ieee80211_hw *hw);
1378 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1379 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1380 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1382 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1383 u32 regaddr, u32 bitmask);
1384 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1385 u32 regaddr, u32 bitmask, u32 data);
1388 struct rtl_intf_ops {
1390 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1391 int (*adapter_start) (struct ieee80211_hw *hw);
1392 void (*adapter_stop) (struct ieee80211_hw *hw);
1394 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb);
1395 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1396 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1399 void (*disable_aspm) (struct ieee80211_hw *hw);
1400 void (*enable_aspm) (struct ieee80211_hw *hw);
1405 struct rtl_mod_params {
1406 /* default: 0 = using hardware encryption */
1410 struct rtl_hal_usbint_cfg {
1417 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1418 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1419 struct sk_buff_head *);
1422 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1423 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1425 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1426 struct sk_buff_head *);
1428 /* endpoint mapping */
1429 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1430 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1433 struct rtl_hal_cfg {
1437 struct rtl_hal_ops *ops;
1438 struct rtl_mod_params *mod_params;
1439 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1441 /*this map used for some registers or vars
1442 defined int HAL but used in MAIN */
1443 u32 maps[RTL_VAR_MAP_MAX];
1449 struct mutex conf_mutex;
1452 spinlock_t ips_lock;
1453 spinlock_t irq_th_lock;
1454 spinlock_t h2c_lock;
1455 spinlock_t rf_ps_lock;
1457 spinlock_t lps_lock;
1458 spinlock_t waitq_lock;
1459 spinlock_t tx_urb_lock;
1462 spinlock_t cck_and_rw_pagea_lock;
1466 struct ieee80211_hw *hw;
1469 struct timer_list watchdog_timer;
1472 struct tasklet_struct irq_tasklet;
1473 struct tasklet_struct irq_prepare_bcn_tasklet;
1476 struct workqueue_struct *rtl_wq;
1477 struct delayed_work watchdog_wq;
1478 struct delayed_work ips_nic_off_wq;
1481 struct delayed_work ps_work;
1482 struct delayed_work ps_rfon_wq;
1486 u32 dbgp_type[DBGP_TYPE_MAX];
1487 u32 global_debuglevel;
1488 u64 global_debugcomponents;
1490 /* add for proc debug */
1491 struct proc_dir_entry *proc_dir;
1496 struct rtl_locks locks;
1497 struct rtl_works works;
1498 struct rtl_mac mac80211;
1499 struct rtl_hal rtlhal;
1500 struct rtl_regulatory regd;
1501 struct rtl_rfkill rfkill;
1505 struct rtl_security sec;
1506 struct rtl_efuse efuse;
1508 struct rtl_ps_ctl psc;
1509 struct rate_adaptive ra;
1510 struct wireless_stats stats;
1511 struct rt_link_detect link_info;
1512 struct false_alarm_statistics falsealm_cnt;
1514 struct rtl_rate_priv *rate_priv;
1516 struct rtl_debug dbg;
1519 *hal_cfg : for diff cards
1520 *intf_ops : for diff interrface usb/pcie
1522 struct rtl_hal_cfg *cfg;
1523 struct rtl_intf_ops *intf_ops;
1525 /*this var will be set by set_bit,
1526 and was used to indicate status of
1527 interface or hardware */
1528 unsigned long status;
1530 /*This must be the last item so
1531 that it points to the data allocated
1532 beyond this structure like:
1533 rtl_pci_priv or rtl_usb_priv */
1537 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1538 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1539 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1540 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1541 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1544 /***************************************
1545 Bluetooth Co-existance Related
1546 ****************************************/
1567 enum bt_service_type {
1574 BT_OTHER_ACTION = 6,
1580 enum bt_radio_shared {
1581 BT_RADIO_SHARED = 0,
1582 BT_RADIO_INDIVIDUAL = 1,
1585 struct bt_coexist_info {
1587 /* EEPROM BT info. */
1588 u8 eeprom_bt_coexist;
1590 u8 eeprom_bt_ant_num;
1591 u8 eeprom_bt_ant_isolation;
1592 u8 eeprom_bt_radio_shared;
1598 u8 bt_cur_state; /* 0:on, 1:off */
1599 u8 bt_ant_isolation; /* 0:good, 1:bad */
1600 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1602 u8 bt_radio_shared_type;
1603 u8 bt_rfreg_origin_1e;
1604 u8 bt_rfreg_origin_1f;
1612 bool b_bt_busy_traffic;
1613 bool b_bt_traffic_mode_set;
1614 bool b_bt_non_traffic_mode_set;
1616 bool b_fw_coexist_all_off;
1617 bool b_sw_coexist_all_off;
1620 u8 bt_pre_rssi_state;
1628 /****************************************
1629 mem access macro define start
1630 Call endian free function when
1631 1. Read/write packet content.
1632 2. Before write integer to IO.
1633 3. After read integer from IO.
1634 ****************************************/
1635 /* Convert little data endian to host */
1636 #define EF1BYTE(_val) \
1638 #define EF2BYTE(_val) \
1640 #define EF4BYTE(_val) \
1643 /* Read data from memory */
1644 #define READEF1BYTE(_ptr) \
1645 EF1BYTE(*((u8 *)(_ptr)))
1646 #define READEF2BYTE(_ptr) \
1647 EF2BYTE(*((u16 *)(_ptr)))
1648 #define READEF4BYTE(_ptr) \
1649 EF4BYTE(*((__le32 *)(_ptr)))
1651 /* Write data to memory */
1652 #define WRITEEF1BYTE(_ptr, _val) \
1653 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1654 #define WRITEEF2BYTE(_ptr, _val) \
1655 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1656 #define WRITEEF4BYTE(_ptr, _val) \
1657 (*((u32 *)(_ptr))) = EF4BYTE(_val)
1660 BIT_LEN_MASK_32(0) => 0x00000000
1661 BIT_LEN_MASK_32(1) => 0x00000001
1662 BIT_LEN_MASK_32(2) => 0x00000003
1663 BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
1664 #define BIT_LEN_MASK_32(__bitlen) \
1665 (0xFFFFFFFF >> (32 - (__bitlen)))
1666 #define BIT_LEN_MASK_16(__bitlen) \
1667 (0xFFFF >> (16 - (__bitlen)))
1668 #define BIT_LEN_MASK_8(__bitlen) \
1669 (0xFF >> (8 - (__bitlen)))
1672 BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1673 BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
1674 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1675 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1676 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1677 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1678 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1679 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1682 Return 4-byte value in host byte ordering from
1683 4-byte pointer in little-endian system.*/
1684 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1685 (EF4BYTE(*((u32 *)(__pstart))))
1686 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1687 (EF2BYTE(*((u16 *)(__pstart))))
1688 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1689 (EF1BYTE(*((u8 *)(__pstart))))
1692 Translate subfield (continuous bits in little-endian) of 4-byte
1693 value to host byte ordering.*/
1694 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1696 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1697 BIT_LEN_MASK_32(__bitlen) \
1699 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1701 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1702 BIT_LEN_MASK_16(__bitlen) \
1704 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1706 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1707 BIT_LEN_MASK_8(__bitlen) \
1711 Mask subfield (continuous bits in little-endian) of 4-byte value
1712 and return the result in 4-byte value in host byte ordering.*/
1713 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1715 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1716 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1718 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1720 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1721 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1723 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1725 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1726 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1730 Set subfield of little-endian 4-byte value to specified value. */
1731 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1732 *((u32 *)(__pstart)) = EF4BYTE \
1734 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1735 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1737 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1738 *((u16 *)(__pstart)) = EF2BYTE \
1740 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1741 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1743 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1744 *((u8 *)(__pstart)) = EF1BYTE \
1746 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1747 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1750 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
1751 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
1753 /****************************************
1754 mem access macro define end
1755 ****************************************/
1757 #define byte(x, n) ((x >> (8 * n)) & 0xff)
1759 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1760 #define RTL_WATCH_DOG_TIME 2000
1761 #define MSECS(t) msecs_to_jiffies(t)
1762 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1763 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1764 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1765 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1766 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1767 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1768 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1770 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1771 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1772 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1773 /*NIC halt, re-initialize hw parameters*/
1774 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1775 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1776 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1777 /*Always enable ASPM and Clock Req in initialization.*/
1778 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1779 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1780 #define RT_PS_LEVEL_ASPM BIT(7)
1781 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1782 #define RT_RF_LPS_DISALBE_2R BIT(30)
1783 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1784 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1785 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1786 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1787 (ppsc->cur_ps_level &= (~(_ps_flg)))
1788 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1789 (ppsc->cur_ps_level |= _ps_flg)
1791 #define container_of_dwork_rtl(x, y, z) \
1792 container_of(container_of(x, struct delayed_work, work), y, z)
1794 #define FILL_OCTET_STRING(_os, _octet, _len) \
1796 (_os). octet = (u8 *)(_octet); \
1797 (_os). length = (_len); \
1800 #define CP_MACADDR(des, src) \
1801 memcpy((des), (src), ETH_ALEN)
1803 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1805 return rtlpriv->io.read8_sync(rtlpriv, addr);
1808 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1810 return rtlpriv->io.read16_sync(rtlpriv, addr);
1813 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1815 return rtlpriv->io.read32_sync(rtlpriv, addr);
1818 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1820 rtlpriv->io.write8_async(rtlpriv, addr, val8);
1823 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1825 rtlpriv->io.write16_async(rtlpriv, addr, val16);
1828 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1829 u32 addr, u32 val32)
1831 rtlpriv->io.write32_async(rtlpriv, addr, val32);
1834 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1835 u32 regaddr, u32 bitmask)
1837 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1842 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1843 u32 bitmask, u32 data)
1845 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1851 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1852 enum radio_path rfpath, u32 regaddr,
1855 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1861 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1862 enum radio_path rfpath, u32 regaddr,
1863 u32 bitmask, u32 data)
1865 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1870 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1872 return (_HAL_STATE_STOP == rtlhal->state);
1875 static inline void set_hal_start(struct rtl_hal *rtlhal)
1877 rtlhal->state = _HAL_STATE_START;
1880 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1882 rtlhal->state = _HAL_STATE_STOP;
1885 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1887 return rtlphy->rf_type;