Merge branch 'core-rcu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / drivers / net / wireless / rtlwifi / rtl8192cu / hw.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2010  Realtek Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <wlanfae@realtek.com>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
25  *
26  * Larry Finger <Larry.Finger@lwfinger.net>
27  *
28  *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../cam.h"
34 #include "../ps.h"
35 #include "../usb.h"
36 #include "reg.h"
37 #include "def.h"
38 #include "phy.h"
39 #include "mac.h"
40 #include "dm.h"
41 #include "hw.h"
42 #include "../rtl8192ce/hw.h"
43 #include "trx.h"
44 #include "led.h"
45 #include "table.h"
46
47 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
48 {
49         struct rtl_priv *rtlpriv = rtl_priv(hw);
50         struct rtl_phy *rtlphy = &(rtlpriv->phy);
51         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
52
53         rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
54         rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
55         if (IS_HIGHT_PA(rtlefuse->board_type)) {
56                 rtlphy->hwparam_tables[PHY_REG_PG].length =
57                         RTL8192CUPHY_REG_Array_PG_HPLength;
58                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
59                         RTL8192CUPHY_REG_Array_PG_HP;
60         } else {
61                 rtlphy->hwparam_tables[PHY_REG_PG].length =
62                         RTL8192CUPHY_REG_ARRAY_PGLENGTH;
63                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
64                         RTL8192CUPHY_REG_ARRAY_PG;
65         }
66         /* 2T */
67         rtlphy->hwparam_tables[PHY_REG_2T].length =
68                         RTL8192CUPHY_REG_2TARRAY_LENGTH;
69         rtlphy->hwparam_tables[PHY_REG_2T].pdata =
70                         RTL8192CUPHY_REG_2TARRAY;
71         rtlphy->hwparam_tables[RADIOA_2T].length =
72                         RTL8192CURADIOA_2TARRAYLENGTH;
73         rtlphy->hwparam_tables[RADIOA_2T].pdata =
74                         RTL8192CURADIOA_2TARRAY;
75         rtlphy->hwparam_tables[RADIOB_2T].length =
76                         RTL8192CURADIOB_2TARRAYLENGTH;
77         rtlphy->hwparam_tables[RADIOB_2T].pdata =
78                         RTL8192CU_RADIOB_2TARRAY;
79         rtlphy->hwparam_tables[AGCTAB_2T].length =
80                         RTL8192CUAGCTAB_2TARRAYLENGTH;
81         rtlphy->hwparam_tables[AGCTAB_2T].pdata =
82                         RTL8192CUAGCTAB_2TARRAY;
83         /* 1T */
84         if (IS_HIGHT_PA(rtlefuse->board_type)) {
85                 rtlphy->hwparam_tables[PHY_REG_1T].length =
86                         RTL8192CUPHY_REG_1T_HPArrayLength;
87                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
88                         RTL8192CUPHY_REG_1T_HPArray;
89                 rtlphy->hwparam_tables[RADIOA_1T].length =
90                         RTL8192CURadioA_1T_HPArrayLength;
91                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
92                         RTL8192CURadioA_1T_HPArray;
93                 rtlphy->hwparam_tables[RADIOB_1T].length =
94                         RTL8192CURADIOB_1TARRAYLENGTH;
95                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
96                         RTL8192CU_RADIOB_1TARRAY;
97                 rtlphy->hwparam_tables[AGCTAB_1T].length =
98                         RTL8192CUAGCTAB_1T_HPArrayLength;
99                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
100                         Rtl8192CUAGCTAB_1T_HPArray;
101         } else {
102                 rtlphy->hwparam_tables[PHY_REG_1T].length =
103                          RTL8192CUPHY_REG_1TARRAY_LENGTH;
104                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
105                         RTL8192CUPHY_REG_1TARRAY;
106                 rtlphy->hwparam_tables[RADIOA_1T].length =
107                         RTL8192CURADIOA_1TARRAYLENGTH;
108                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
109                         RTL8192CU_RADIOA_1TARRAY;
110                 rtlphy->hwparam_tables[RADIOB_1T].length =
111                         RTL8192CURADIOB_1TARRAYLENGTH;
112                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
113                         RTL8192CU_RADIOB_1TARRAY;
114                 rtlphy->hwparam_tables[AGCTAB_1T].length =
115                         RTL8192CUAGCTAB_1TARRAYLENGTH;
116                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
117                         RTL8192CUAGCTAB_1TARRAY;
118         }
119 }
120
121 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
122                                                  bool autoload_fail,
123                                                  u8 *hwinfo)
124 {
125         struct rtl_priv *rtlpriv = rtl_priv(hw);
126         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
127         u8 rf_path, index, tempval;
128         u16 i;
129
130         for (rf_path = 0; rf_path < 2; rf_path++) {
131                 for (i = 0; i < 3; i++) {
132                         if (!autoload_fail) {
133                                 rtlefuse->
134                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
135                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
136                                 rtlefuse->
137                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
138                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
139                                            i];
140                         } else {
141                                 rtlefuse->
142                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
143                                     EEPROM_DEFAULT_TXPOWERLEVEL;
144                                 rtlefuse->
145                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
146                                     EEPROM_DEFAULT_TXPOWERLEVEL;
147                         }
148                 }
149         }
150         for (i = 0; i < 3; i++) {
151                 if (!autoload_fail)
152                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
153                 else
154                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
155                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
156                     (tempval & 0xf);
157                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
158                     ((tempval & 0xf0) >> 4);
159         }
160         for (rf_path = 0; rf_path < 2; rf_path++)
161                 for (i = 0; i < 3; i++)
162                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
163                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
164                                  i, rtlefuse->
165                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
166         for (rf_path = 0; rf_path < 2; rf_path++)
167                 for (i = 0; i < 3; i++)
168                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
169                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
170                                  rf_path, i,
171                                  rtlefuse->
172                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
173         for (rf_path = 0; rf_path < 2; rf_path++)
174                 for (i = 0; i < 3; i++)
175                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
176                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
177                                  rf_path, i,
178                                  rtlefuse->
179                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
180                                  [i]));
181         for (rf_path = 0; rf_path < 2; rf_path++) {
182                 for (i = 0; i < 14; i++) {
183                         index = _rtl92c_get_chnl_group((u8) i);
184                         rtlefuse->txpwrlevel_cck[rf_path][i] =
185                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
186                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
187                             rtlefuse->
188                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
189                         if ((rtlefuse->
190                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
191                              rtlefuse->
192                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
193                             > 0) {
194                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
195                                     rtlefuse->
196                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
197                                     [index] - rtlefuse->
198                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
199                                     [index];
200                         } else {
201                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
202                         }
203                 }
204                 for (i = 0; i < 14; i++) {
205                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
206                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
207                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
208                                  rtlefuse->txpwrlevel_cck[rf_path][i],
209                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
210                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
211                 }
212         }
213         for (i = 0; i < 3; i++) {
214                 if (!autoload_fail) {
215                         rtlefuse->eeprom_pwrlimit_ht40[i] =
216                             hwinfo[EEPROM_TXPWR_GROUP + i];
217                         rtlefuse->eeprom_pwrlimit_ht20[i] =
218                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
219                 } else {
220                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
221                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
222                 }
223         }
224         for (rf_path = 0; rf_path < 2; rf_path++) {
225                 for (i = 0; i < 14; i++) {
226                         index = _rtl92c_get_chnl_group((u8) i);
227                         if (rf_path == RF90_PATH_A) {
228                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
229                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
230                                      & 0xf);
231                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
232                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
233                                      & 0xf);
234                         } else if (rf_path == RF90_PATH_B) {
235                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
236                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
237                                       & 0xf0) >> 4);
238                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
239                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
240                                       & 0xf0) >> 4);
241                         }
242                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
243                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
244                                  rf_path, i,
245                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
246                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
247                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
248                                  rf_path, i,
249                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
250                 }
251         }
252         for (i = 0; i < 14; i++) {
253                 index = _rtl92c_get_chnl_group((u8) i);
254                 if (!autoload_fail)
255                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
256                 else
257                         tempval = EEPROM_DEFAULT_HT20_DIFF;
258                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
259                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
260                     ((tempval >> 4) & 0xF);
261                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
262                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
263                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
264                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
265                 index = _rtl92c_get_chnl_group((u8) i);
266                 if (!autoload_fail)
267                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
268                 else
269                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
270                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
271                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
272                     ((tempval >> 4) & 0xF);
273         }
274         rtlefuse->legacy_ht_txpowerdiff =
275             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
276         for (i = 0; i < 14; i++)
277                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
278                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
279                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
280         for (i = 0; i < 14; i++)
281                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
282                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
283                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
284         for (i = 0; i < 14; i++)
285                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
286                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
287                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
288         for (i = 0; i < 14; i++)
289                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
290                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
291                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
292         if (!autoload_fail)
293                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
294         else
295                 rtlefuse->eeprom_regulatory = 0;
296         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
297                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
298         if (!autoload_fail) {
299                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
300                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
301         } else {
302                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
303                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
304         }
305         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
306                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
307                  rtlefuse->eeprom_tssi[RF90_PATH_A],
308                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
309         if (!autoload_fail)
310                 tempval = hwinfo[EEPROM_THERMAL_METER];
311         else
312                 tempval = EEPROM_DEFAULT_THERMALMETER;
313         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
314         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
315             rtlefuse->eeprom_thermalmeter > 0x1c)
316                 rtlefuse->eeprom_thermalmeter = 0x12;
317         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
318                 rtlefuse->apk_thermalmeterignore = true;
319         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
320         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
321                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
322 }
323
324 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
325 {
326         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
327         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
328         u8 boardType;
329
330         if (IS_NORMAL_CHIP(rtlhal->version)) {
331                 boardType = ((contents[EEPROM_RF_OPT1]) &
332                             BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
333         } else {
334                 boardType = contents[EEPROM_RF_OPT4];
335                 boardType &= BOARD_TYPE_TEST_MASK;
336         }
337         rtlefuse->board_type = boardType;
338         if (IS_HIGHT_PA(rtlefuse->board_type))
339                 rtlefuse->external_pa = 1;
340         printk(KERN_INFO "rtl8192cu: Board Type %x\n", rtlefuse->board_type);
341
342 #ifdef CONFIG_ANTENNA_DIVERSITY
343         /* Antenna Diversity setting. */
344         if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
345                 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
346         else
347                 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
348
349         printk(KERN_INFO "rtl8192cu: Antenna Config %x\n",
350                rtl_efuse->antenna_cfg);
351 #endif
352 }
353
354 #ifdef CONFIG_BT_COEXIST
355 static void _update_bt_param(_adapter *padapter)
356 {
357         struct btcoexist_priv    *pbtpriv = &(padapter->halpriv.bt_coexist);
358         struct registry_priv    *registry_par = &padapter->registrypriv;
359         if (2 != registry_par->bt_iso) {
360                 /* 0:Low, 1:High, 2:From Efuse */
361                 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
362         }
363         if (registry_par->bt_sco == 1) {
364                 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
365                  * 5.OtherBusy */
366                 pbtpriv->BT_Service = BT_OtherAction;
367         } else if (registry_par->bt_sco == 2) {
368                 pbtpriv->BT_Service = BT_SCO;
369         } else if (registry_par->bt_sco == 4) {
370                 pbtpriv->BT_Service = BT_Busy;
371         } else if (registry_par->bt_sco == 5) {
372                 pbtpriv->BT_Service = BT_OtherBusy;
373         } else {
374                 pbtpriv->BT_Service = BT_Idle;
375         }
376         pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
377         pbtpriv->bCOBT = _TRUE;
378         pbtpriv->BtEdcaUL = 0;
379         pbtpriv->BtEdcaDL = 0;
380         pbtpriv->BtRssiState = 0xff;
381         pbtpriv->bInitSet = _FALSE;
382         pbtpriv->bBTBusyTraffic = _FALSE;
383         pbtpriv->bBTTrafficModeSet = _FALSE;
384         pbtpriv->bBTNonTrafficModeSet = _FALSE;
385         pbtpriv->CurrentState = 0;
386         pbtpriv->PreviousState = 0;
387         printk(KERN_INFO "rtl8192cu: BT Coexistance = %s\n",
388                (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
389         if (pbtpriv->BT_Coexist) {
390                 if (pbtpriv->BT_Ant_Num == Ant_x2)
391                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
392                                "Ant_Num = Antx2\n");
393                 else if (pbtpriv->BT_Ant_Num == Ant_x1)
394                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
395                                "Ant_Num = Antx1\n");
396                 switch (pbtpriv->BT_CoexistType) {
397                 case BT_2Wire:
398                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
399                                "CoexistType = BT_2Wire\n");
400                         break;
401                 case BT_ISSC_3Wire:
402                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
403                                "CoexistType = BT_ISSC_3Wire\n");
404                         break;
405                 case BT_Accel:
406                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
407                                "CoexistType = BT_Accel\n");
408                         break;
409                 case BT_CSR_BC4:
410                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
411                                "CoexistType = BT_CSR_BC4\n");
412                         break;
413                 case BT_CSR_BC8:
414                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
415                                "CoexistType = BT_CSR_BC8\n");
416                         break;
417                 case BT_RTL8756:
418                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
419                                "CoexistType = BT_RTL8756\n");
420                         break;
421                 default:
422                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
423                                "CoexistType = Unknown\n");
424                         break;
425                 }
426                 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Ant_isolation = %d\n",
427                        pbtpriv->BT_Ant_isolation);
428                 switch (pbtpriv->BT_Service) {
429                 case BT_OtherAction:
430                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
431                                "BT_OtherAction\n");
432                         break;
433                 case BT_SCO:
434                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
435                                "BT_SCO\n");
436                         break;
437                 case BT_Busy:
438                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
439                                "BT_Busy\n");
440                         break;
441                 case BT_OtherBusy:
442                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
443                                "BT_OtherBusy\n");
444                         break;
445                 default:
446                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
447                                "BT_Idle\n");
448                         break;
449                 }
450                 printk(KERN_INFO "rtl8192cu: BT_RadioSharedType = 0x%x\n",
451                        pbtpriv->BT_RadioSharedType);
452         }
453 }
454
455 #define GET_BT_COEXIST(priv) (&priv->bt_coexist)
456
457 static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
458                                                 u8 *contents,
459                                                 bool bautoloadfailed);
460 {
461         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
462         bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
463         struct btcoexist_priv    *pbtpriv = &pHalData->bt_coexist;
464         u8      rf_opt4;
465
466         _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
467         if (AutoloadFail) {
468                 pbtpriv->BT_Coexist = _FALSE;
469                 pbtpriv->BT_CoexistType = BT_2Wire;
470                 pbtpriv->BT_Ant_Num = Ant_x2;
471                 pbtpriv->BT_Ant_isolation = 0;
472                 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
473                 return;
474         }
475         if (isNormal) {
476                 if (pHalData->BoardType == BOARD_USB_COMBO)
477                         pbtpriv->BT_Coexist = _TRUE;
478                 else
479                         pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
480                                               0x20) >> 5); /* bit[5] */
481                 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
482                 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
483                 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
484                 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
485                 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
486         } else {
487                 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
488                                        _TRUE : _FALSE;
489         }
490         _update_bt_param(Adapter);
491 }
492 #endif
493
494 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
495 {
496         struct rtl_priv *rtlpriv = rtl_priv(hw);
497         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
498         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
499         u16 i, usvalue;
500         u8 hwinfo[HWSET_MAX_SIZE] = {0};
501         u16 eeprom_id;
502
503         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
504                 rtl_efuse_shadow_map_update(hw);
505                 memcpy((void *)hwinfo,
506                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
507                        HWSET_MAX_SIZE);
508         } else if (rtlefuse->epromtype == EEPROM_93C46) {
509                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
510                          ("RTL819X Not boot from eeprom, check it !!"));
511         }
512         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
513                       hwinfo, HWSET_MAX_SIZE);
514         eeprom_id = *((u16 *)&hwinfo[0]);
515         if (eeprom_id != RTL8190_EEPROM_ID) {
516                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
517                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
518                 rtlefuse->autoload_failflag = true;
519         } else {
520                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
521                 rtlefuse->autoload_failflag = false;
522         }
523         if (rtlefuse->autoload_failflag)
524                 return;
525         for (i = 0; i < 6; i += 2) {
526                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
527                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
528         }
529         printk(KERN_INFO "rtl8192cu: MAC address: %pM\n", rtlefuse->dev_addr);
530         _rtl92cu_read_txpower_info_from_hwpg(hw,
531                                            rtlefuse->autoload_failflag, hwinfo);
532         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
533         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
534         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
535                  (" VID = 0x%02x PID = 0x%02x\n",
536                  rtlefuse->eeprom_vid, rtlefuse->eeprom_did));
537         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
538         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
539         rtlefuse->txpwr_fromeprom = true;
540         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
541         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
542                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
543         if (rtlhal->oem_id == RT_CID_DEFAULT) {
544                 switch (rtlefuse->eeprom_oemid) {
545                 case EEPROM_CID_DEFAULT:
546                         if (rtlefuse->eeprom_did == 0x8176) {
547                                 if ((rtlefuse->eeprom_svid == 0x103C &&
548                                      rtlefuse->eeprom_smid == 0x1629))
549                                         rtlhal->oem_id = RT_CID_819x_HP;
550                                 else
551                                         rtlhal->oem_id = RT_CID_DEFAULT;
552                         } else {
553                                 rtlhal->oem_id = RT_CID_DEFAULT;
554                         }
555                         break;
556                 case EEPROM_CID_TOSHIBA:
557                         rtlhal->oem_id = RT_CID_TOSHIBA;
558                         break;
559                 case EEPROM_CID_QMI:
560                         rtlhal->oem_id = RT_CID_819x_QMI;
561                         break;
562                 case EEPROM_CID_WHQL:
563                 default:
564                         rtlhal->oem_id = RT_CID_DEFAULT;
565                         break;
566                 }
567         }
568         _rtl92cu_read_board_type(hw, hwinfo);
569 #ifdef CONFIG_BT_COEXIST
570         _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
571                                             rtlefuse->autoload_failflag);
572 #endif
573 }
574
575 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
576 {
577         struct rtl_priv *rtlpriv = rtl_priv(hw);
578         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
579         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
580
581         switch (rtlhal->oem_id) {
582         case RT_CID_819x_HP:
583                 usb_priv->ledctl.led_opendrain = true;
584                 break;
585         case RT_CID_819x_Lenovo:
586         case RT_CID_DEFAULT:
587         case RT_CID_TOSHIBA:
588         case RT_CID_CCX:
589         case RT_CID_819x_Acer:
590         case RT_CID_WHQL:
591         default:
592                 break;
593         }
594         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
595                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
596 }
597
598 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
599 {
600
601         struct rtl_priv *rtlpriv = rtl_priv(hw);
602         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
603         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
604         u8 tmp_u1b;
605
606         if (!IS_NORMAL_CHIP(rtlhal->version))
607                 return;
608         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
609         rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
610                                EEPROM_93C46 : EEPROM_BOOT_EFUSE;
611         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from %s\n",
612                  (tmp_u1b & BOOT_FROM_EEPROM) ? "EERROM" : "EFUSE"));
613         rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
614         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload %s\n",
615                  (tmp_u1b & EEPROM_EN) ? "OK!!" : "ERR!!"));
616         _rtl92cu_read_adapter_info(hw);
617         _rtl92cu_hal_customized_behavior(hw);
618         return;
619 }
620
621 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
622 {
623         struct rtl_priv *rtlpriv = rtl_priv(hw);
624         int             status = 0;
625         u16             value16;
626         u8              value8;
627         /*  polling autoload done. */
628         u32     pollingCount = 0;
629
630         do {
631                 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
632                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
633                                  ("Autoload Done!\n"));
634                         break;
635                 }
636                 if (pollingCount++ > 100) {
637                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
638                                  ("Failed to polling REG_APS_FSMCO[PFM_ALDN]"
639                                  " done!\n"));
640                         return -ENODEV;
641                 }
642         } while (true);
643         /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
644         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
645         /* Power on when re-enter from IPS/Radio off/card disable */
646         /* enable SPS into PWM mode */
647         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
648         udelay(100);
649         value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
650         if (0 == (value8 & LDV12_EN)) {
651                 value8 |= LDV12_EN;
652                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
653                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
654                          (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",
655                          value8));
656                 udelay(100);
657                 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
658                 value8 &= ~ISO_MD2PP;
659                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
660         }
661         /*  auto enable WLAN */
662         pollingCount = 0;
663         value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
664         value16 |= APFM_ONMAC;
665         rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
666         do {
667                 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
668                         printk(KERN_INFO "rtl8192cu: MAC auto ON okay!\n");
669                         break;
670                 }
671                 if (pollingCount++ > 100) {
672                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
673                                  ("Failed to polling REG_APS_FSMCO[APFM_ONMAC]"
674                                  " done!\n"));
675                         return -ENODEV;
676                 }
677         } while (true);
678         /* Enable Radio ,GPIO ,and LED function */
679         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
680         /* release RF digital isolation */
681         value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
682         value16 &= ~ISO_DIOR;
683         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
684         /* Reconsider when to do this operation after asking HWSD. */
685         pollingCount = 0;
686         rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
687                                                 REG_APSD_CTRL) & ~BIT(6)));
688         do {
689                 pollingCount++;
690         } while ((pollingCount < 200) &&
691                  (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
692         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
693         value16 = rtl_read_word(rtlpriv,  REG_CR);
694         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
695                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
696         rtl_write_word(rtlpriv, REG_CR, value16);
697         return status;
698 }
699
700 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
701                                               bool wmm_enable,
702                                               u8 out_ep_num,
703                                               u8 queue_sel)
704 {
705         struct rtl_priv *rtlpriv = rtl_priv(hw);
706         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
707         bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
708         u32 outEPNum = (u32)out_ep_num;
709         u32 numHQ = 0;
710         u32 numLQ = 0;
711         u32 numNQ = 0;
712         u32 numPubQ;
713         u32 value32;
714         u8 value8;
715         u32 txQPageNum, txQPageUnit, txQRemainPage;
716
717         if (!wmm_enable) {
718                 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
719                           CHIP_A_PAGE_NUM_PUBQ;
720                 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
721
722                 txQPageUnit = txQPageNum/outEPNum;
723                 txQRemainPage = txQPageNum % outEPNum;
724                 if (queue_sel & TX_SELE_HQ)
725                         numHQ = txQPageUnit;
726                 if (queue_sel & TX_SELE_LQ)
727                         numLQ = txQPageUnit;
728                 /* HIGH priority queue always present in the configuration of
729                  * 2 out-ep. Remainder pages have assigned to High queue */
730                 if ((outEPNum > 1) && (txQRemainPage))
731                         numHQ += txQRemainPage;
732                 /* NOTE: This step done before writting REG_RQPN. */
733                 if (isChipN) {
734                         if (queue_sel & TX_SELE_NQ)
735                                 numNQ = txQPageUnit;
736                         value8 = (u8)_NPQ(numNQ);
737                         rtl_write_byte(rtlpriv,  REG_RQPN_NPQ, value8);
738                 }
739         } else {
740                 /* for WMM ,number of out-ep must more than or equal to 2! */
741                 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
742                           WMM_CHIP_A_PAGE_NUM_PUBQ;
743                 if (queue_sel & TX_SELE_HQ) {
744                         numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
745                                 WMM_CHIP_A_PAGE_NUM_HPQ;
746                 }
747                 if (queue_sel & TX_SELE_LQ) {
748                         numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
749                                 WMM_CHIP_A_PAGE_NUM_LPQ;
750                 }
751                 /* NOTE: This step done before writting REG_RQPN. */
752                 if (isChipN) {
753                         if (queue_sel & TX_SELE_NQ)
754                                 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
755                         value8 = (u8)_NPQ(numNQ);
756                         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
757                 }
758         }
759         /* TX DMA */
760         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
761         rtl_write_dword(rtlpriv, REG_RQPN, value32);
762 }
763
764 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
765 {
766         struct rtl_priv *rtlpriv = rtl_priv(hw);
767         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
768         u8      txpktbuf_bndy;
769         u8      value8;
770
771         if (!wmm_enable)
772                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
773         else /* for WMM */
774                 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
775                                                 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
776                                                 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
777         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
778         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
779         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
780         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
781         rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
782         rtl_write_word(rtlpriv,  (REG_TRXFF_BNDY + 2), 0x27FF);
783         value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
784         rtl_write_byte(rtlpriv, REG_PBP, value8);
785 }
786
787 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
788                                             u16 bkQ, u16 viQ, u16 voQ,
789                                             u16 mgtQ, u16 hiQ)
790 {
791         struct rtl_priv *rtlpriv = rtl_priv(hw);
792         u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
793
794         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
795                    _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
796                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
797         rtl_write_word(rtlpriv,  REG_TRXDMA_CTRL, value16);
798 }
799
800 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
801                                                     bool wmm_enable,
802                                                     u8 queue_sel)
803 {
804         u16 uninitialized_var(value);
805
806         switch (queue_sel) {
807         case TX_SELE_HQ:
808                 value = QUEUE_HIGH;
809                 break;
810         case TX_SELE_LQ:
811                 value = QUEUE_LOW;
812                 break;
813         case TX_SELE_NQ:
814                 value = QUEUE_NORMAL;
815                 break;
816         default:
817                 WARN_ON(1); /* Shall not reach here! */
818                 break;
819         }
820         _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
821                                         value, value);
822         printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
823 }
824
825 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
826                                                                 bool wmm_enable,
827                                                                 u8 queue_sel)
828 {
829         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
830         u16 uninitialized_var(valueHi);
831         u16 uninitialized_var(valueLow);
832
833         switch (queue_sel) {
834         case (TX_SELE_HQ | TX_SELE_LQ):
835                 valueHi = QUEUE_HIGH;
836                 valueLow = QUEUE_LOW;
837                 break;
838         case (TX_SELE_NQ | TX_SELE_LQ):
839                 valueHi = QUEUE_NORMAL;
840                 valueLow = QUEUE_LOW;
841                 break;
842         case (TX_SELE_HQ | TX_SELE_NQ):
843                 valueHi = QUEUE_HIGH;
844                 valueLow = QUEUE_NORMAL;
845                 break;
846         default:
847                 WARN_ON(1);
848                 break;
849         }
850         if (!wmm_enable) {
851                 beQ = valueLow;
852                 bkQ = valueLow;
853                 viQ = valueHi;
854                 voQ = valueHi;
855                 mgtQ = valueHi;
856                 hiQ = valueHi;
857         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
858                 beQ = valueHi;
859                 bkQ = valueLow;
860                 viQ = valueLow;
861                 voQ = valueHi;
862                 mgtQ = valueHi;
863                 hiQ = valueHi;
864         }
865         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
866         printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
867 }
868
869 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
870                                                       bool wmm_enable,
871                                                       u8 queue_sel)
872 {
873         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
874         struct rtl_priv *rtlpriv = rtl_priv(hw);
875
876         if (!wmm_enable) { /* typical setting */
877                 beQ     = QUEUE_LOW;
878                 bkQ     = QUEUE_LOW;
879                 viQ     = QUEUE_NORMAL;
880                 voQ     = QUEUE_HIGH;
881                 mgtQ    = QUEUE_HIGH;
882                 hiQ     = QUEUE_HIGH;
883         } else { /* for WMM */
884                 beQ     = QUEUE_LOW;
885                 bkQ     = QUEUE_NORMAL;
886                 viQ     = QUEUE_NORMAL;
887                 voQ     = QUEUE_HIGH;
888                 mgtQ    = QUEUE_HIGH;
889                 hiQ     = QUEUE_HIGH;
890         }
891         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
892         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
893                  ("Tx queue select :0x%02x..\n", queue_sel));
894 }
895
896 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
897                                                bool wmm_enable,
898                                                u8 out_ep_num,
899                                                u8 queue_sel)
900 {
901         switch (out_ep_num) {
902         case 1:
903                 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
904                                                         queue_sel);
905                 break;
906         case 2:
907                 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
908                                                         queue_sel);
909                 break;
910         case 3:
911                 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
912                                                           queue_sel);
913                 break;
914         default:
915                 WARN_ON(1); /* Shall not reach here! */
916                 break;
917         }
918 }
919
920 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
921                                                bool wmm_enable,
922                                                u8 out_ep_num,
923                                                u8 queue_sel)
924 {
925         u8 hq_sele = 0;
926         struct rtl_priv *rtlpriv = rtl_priv(hw);
927
928         switch (out_ep_num) {
929         case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
930                 if (!wmm_enable) /* typical setting */
931                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
932                                    HQSEL_HIQ;
933                 else    /* for WMM */
934                         hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
935                                   HQSEL_HIQ;
936                 break;
937         case 1:
938                 if (TX_SELE_LQ == queue_sel) {
939                         /* map all endpoint to Low queue */
940                         hq_sele = 0;
941                 } else if (TX_SELE_HQ == queue_sel) {
942                         /* map all endpoint to High queue */
943                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
944                                    HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
945                 }
946                 break;
947         default:
948                 WARN_ON(1); /* Shall not reach here! */
949                 break;
950         }
951         rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
952         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
953                  ("Tx queue select :0x%02x..\n", hq_sele));
954 }
955
956 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
957                                                 bool wmm_enable,
958                                                 u8 out_ep_num,
959                                                 u8 queue_sel)
960 {
961         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
962         if (IS_NORMAL_CHIP(rtlhal->version))
963                 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
964                                                    queue_sel);
965         else
966                 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
967                                                    queue_sel);
968 }
969
970 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
971 {
972 }
973
974 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
975 {
976         u16                     value16;
977
978         struct rtl_priv *rtlpriv = rtl_priv(hw);
979         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
980
981         mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
982                       RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
983                       RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
984         rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
985         /* Accept all multicast address */
986         rtl_write_dword(rtlpriv,  REG_MAR, 0xFFFFFFFF);
987         rtl_write_dword(rtlpriv,  REG_MAR + 4, 0xFFFFFFFF);
988         /* Accept all management frames */
989         value16 = 0xFFFF;
990         rtl92c_set_mgt_filter(hw, value16);
991         /* Reject all control frame - default value is 0 */
992         rtl92c_set_ctrl_filter(hw, 0x0);
993         /* Accept all data frames */
994         value16 = 0xFFFF;
995         rtl92c_set_data_filter(hw, value16);
996 }
997
998 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
999 {
1000         struct rtl_priv *rtlpriv = rtl_priv(hw);
1001         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1002         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
1003         struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
1004         int err = 0;
1005         u32     boundary = 0;
1006         u8 wmm_enable = false; /* TODO */
1007         u8 out_ep_nums = rtlusb->out_ep_nums;
1008         u8 queue_sel = rtlusb->out_queue_sel;
1009         err = _rtl92cu_init_power_on(hw);
1010
1011         if (err) {
1012                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1013                         ("Failed to init power on!\n"));
1014                 return err;
1015         }
1016         if (!wmm_enable) {
1017                 boundary = TX_PAGE_BOUNDARY;
1018         } else { /* for WMM */
1019                 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1020                                         ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1021                                         : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1022         }
1023         if (false == rtl92c_init_llt_table(hw, boundary)) {
1024                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1025                         ("Failed to init LLT Table!\n"));
1026                 return -EINVAL;
1027         }
1028         _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1029                                           queue_sel);
1030         _rtl92c_init_trx_buffer(hw, wmm_enable);
1031         _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1032                                      queue_sel);
1033         /* Get Rx PHY status in order to report RSSI and others. */
1034         rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1035         rtl92c_init_interrupt(hw);
1036         rtl92c_init_network_type(hw);
1037         _rtl92cu_init_wmac_setting(hw);
1038         rtl92c_init_adaptive_ctrl(hw);
1039         rtl92c_init_edca(hw);
1040         rtl92c_init_rate_fallback(hw);
1041         rtl92c_init_retry_function(hw);
1042         _rtl92cu_init_usb_aggregation(hw);
1043         rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1044         rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1045         rtl92c_init_beacon_parameters(hw, rtlhal->version);
1046         rtl92c_init_ampdu_aggregation(hw);
1047         rtl92c_init_beacon_max_error(hw, true);
1048         return err;
1049 }
1050
1051 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1052 {
1053         struct rtl_priv *rtlpriv = rtl_priv(hw);
1054         u8 sec_reg_value = 0x0;
1055         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1056
1057         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1058                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1059                   rtlpriv->sec.pairwise_enc_algorithm,
1060                   rtlpriv->sec.group_enc_algorithm));
1061         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1062                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1063                          ("not open sw encryption\n"));
1064                 return;
1065         }
1066         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1067         if (rtlpriv->sec.use_defaultkey) {
1068                 sec_reg_value |= SCR_TxUseDK;
1069                 sec_reg_value |= SCR_RxUseDK;
1070         }
1071         if (IS_NORMAL_CHIP(rtlhal->version))
1072                 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1073         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1074         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
1075                  ("The SECR-value %x\n", sec_reg_value));
1076         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1077 }
1078
1079 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1080 {
1081         struct rtl_priv *rtlpriv = rtl_priv(hw);
1082         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1083
1084         /* To Fix MAC loopback mode fail. */
1085         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1086         rtl_write_byte(rtlpriv, 0x15, 0xe9);
1087         /* HW SEQ CTRL */
1088         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1089         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1090         /* fixed USB interface interference issue */
1091         rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1092         rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1093         rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1094         rtlusb->reg_bcn_ctrl_val = 0x18;
1095         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1096 }
1097
1098 static void _InitPABias(struct ieee80211_hw *hw)
1099 {
1100         struct rtl_priv *rtlpriv = rtl_priv(hw);
1101         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1102         u8 pa_setting;
1103
1104         /* FIXED PA current issue */
1105         pa_setting = efuse_read_1byte(hw, 0x1FA);
1106         if (!(pa_setting & BIT(0))) {
1107                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1108                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1109                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1110                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1111         }
1112         if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1113             IS_92C_SERIAL(rtlhal->version)) {
1114                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1115                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1116                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1117                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1118         }
1119         if (!(pa_setting & BIT(4))) {
1120                 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1121                 pa_setting &= 0x0F;
1122                 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1123         }
1124 }
1125
1126 static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1127 {
1128 #ifdef CONFIG_ANTENNA_DIVERSITY
1129         struct rtl_priv *rtlpriv = rtl_priv(hw);
1130         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1131         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1132
1133         if (pHalData->AntDivCfg == 0)
1134                 return;
1135
1136         if (rtlphy->rf_type == RF_1T1R) {
1137                 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1138                                 rtl_read_dword(rtlpriv,
1139                                 REG_LEDCFG0)|BIT(23));
1140                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1141                 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1142                     Antenna_A)
1143                         pHalData->CurAntenna = Antenna_A;
1144                 else
1145                         pHalData->CurAntenna = Antenna_B;
1146         }
1147 #endif
1148 }
1149
1150 static void _dump_registers(struct ieee80211_hw *hw)
1151 {
1152 }
1153
1154 static void _update_mac_setting(struct ieee80211_hw *hw)
1155 {
1156         struct rtl_priv *rtlpriv = rtl_priv(hw);
1157         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1158
1159         mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1160         mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1161         mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1162         mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1163 }
1164
1165 int rtl92cu_hw_init(struct ieee80211_hw *hw)
1166 {
1167         struct rtl_priv *rtlpriv = rtl_priv(hw);
1168         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1169         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1170         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1171         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1172         int err = 0;
1173         static bool iqk_initialized;
1174
1175         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1176         err = _rtl92cu_init_mac(hw);
1177         if (err) {
1178                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("init mac failed!\n"));
1179                 return err;
1180         }
1181         err = rtl92c_download_fw(hw);
1182         if (err) {
1183                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1184                          ("Failed to download FW. Init HW without FW now..\n"));
1185                 err = 1;
1186                 rtlhal->fw_ready = false;
1187                 return err;
1188         } else {
1189                 rtlhal->fw_ready = true;
1190         }
1191         rtlhal->last_hmeboxnum = 0; /* h2c */
1192         _rtl92cu_phy_param_tab_init(hw);
1193         rtl92cu_phy_mac_config(hw);
1194         rtl92cu_phy_bb_config(hw);
1195         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1196         rtl92c_phy_rf_config(hw);
1197         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1198             !IS_92C_SERIAL(rtlhal->version)) {
1199                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1200                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1201         }
1202         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1203                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1204         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1205                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1206         rtl92cu_bb_block_on(hw);
1207         rtl_cam_reset_all_entry(hw);
1208         rtl92cu_enable_hw_security_config(hw);
1209         ppsc->rfpwr_state = ERFON;
1210         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1211         if (ppsc->rfpwr_state == ERFON) {
1212                 rtl92c_phy_set_rfpath_switch(hw, 1);
1213                 if (iqk_initialized) {
1214                         rtl92c_phy_iq_calibrate(hw, false);
1215                 } else {
1216                         rtl92c_phy_iq_calibrate(hw, false);
1217                         iqk_initialized = true;
1218                 }
1219                 rtl92c_dm_check_txpower_tracking(hw);
1220                 rtl92c_phy_lc_calibrate(hw);
1221         }
1222         _rtl92cu_hw_configure(hw);
1223         _InitPABias(hw);
1224         _InitAntenna_Selection(hw);
1225         _update_mac_setting(hw);
1226         rtl92c_dm_init(hw);
1227         _dump_registers(hw);
1228         return err;
1229 }
1230
1231 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1232 {
1233         struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 /**************************************
1235 a.      TXPAUSE 0x522[7:0] = 0xFF       Pause MAC TX queue
1236 b.      RF path 0 offset 0x00 = 0x00    disable RF
1237 c.      APSD_CTRL 0x600[7:0] = 0x40
1238 d.      SYS_FUNC_EN 0x02[7:0] = 0x16    reset BB state machine
1239 e.      SYS_FUNC_EN 0x02[7:0] = 0x14    reset BB state machine
1240 ***************************************/
1241         u8 eRFPath = 0, value8 = 0;
1242         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1243         rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1244
1245         value8 |= APSDOFF;
1246         rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1247         value8 = 0;
1248         value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1249         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1250         value8 &= (~FEN_BB_GLB_RSTn);
1251         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1252 }
1253
1254 static void  _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1255 {
1256         struct rtl_priv *rtlpriv = rtl_priv(hw);
1257         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1258
1259         if (rtlhal->fw_version <=  0x20) {
1260                 /*****************************
1261                 f. MCUFWDL 0x80[7:0]=0          reset MCU ready status
1262                 g. SYS_FUNC_EN 0x02[10]= 0      reset MCU reg, (8051 reset)
1263                 h. SYS_FUNC_EN 0x02[15-12]= 5   reset MAC reg, DCORE
1264                 i. SYS_FUNC_EN 0x02[10]= 1      enable MCU reg, (8051 enable)
1265                 ******************************/
1266                 u16 valu16 = 0;
1267
1268                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1269                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1270                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1271                                (~FEN_CPUEN))); /* reset MCU ,8051 */
1272                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1273                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1274                               (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1275                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1276                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1277                                FEN_CPUEN)); /* enable MCU ,8051 */
1278         } else {
1279                 u8 retry_cnts = 0;
1280
1281                 /* IF fw in RAM code, do reset */
1282                 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1283                         /* reset MCU ready status */
1284                         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1285                         if (rtlhal->fw_ready) {
1286                                 /* 8051 reset by self */
1287                                 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1288                                 while ((retry_cnts++ < 100) &&
1289                                        (FEN_CPUEN & rtl_read_word(rtlpriv,
1290                                        REG_SYS_FUNC_EN))) {
1291                                         udelay(50);
1292                                 }
1293                                 if (retry_cnts >= 100) {
1294                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1295                                                 ("#####=> 8051 reset failed!.."
1296                                                 ".......................\n"););
1297                                         /* if 8051 reset fail, reset MAC. */
1298                                         rtl_write_byte(rtlpriv,
1299                                                        REG_SYS_FUNC_EN + 1,
1300                                                        0x50);
1301                                         udelay(100);
1302                                 }
1303                         }
1304                 }
1305                 /* Reset MAC and Enable 8051 */
1306                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1307                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1308         }
1309         if (bWithoutHWSM) {
1310                 /*****************************
1311                   Without HW auto state machine
1312                 g.SYS_CLKR 0x08[15:0] = 0x30A3          disable MAC clock
1313                 h.AFE_PLL_CTRL 0x28[7:0] = 0x80         disable AFE PLL
1314                 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F     gated AFE DIG_CLOCK
1315                 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9         isolated digital to PON
1316                 ******************************/
1317                 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1318                 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1319                 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1320                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1321         }
1322 }
1323
1324 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1325 {
1326         struct rtl_priv *rtlpriv = rtl_priv(hw);
1327 /*****************************
1328 k. SYS_FUNC_EN 0x03[7:0] = 0x44         disable ELDR runction
1329 l. SYS_CLKR 0x08[15:0] = 0x3083         disable ELDR clock
1330 m. SYS_ISO_CTRL 0x01[7:0] = 0x83        isolated ELDR to PON
1331 ******************************/
1332         rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1333         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1334 }
1335
1336 static void _DisableGPIO(struct ieee80211_hw *hw)
1337 {
1338         struct rtl_priv *rtlpriv = rtl_priv(hw);
1339 /***************************************
1340 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1341 k. Value = GPIO_PIN_CTRL[7:0]
1342 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1343 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1344 n. LEDCFG 0x4C[15:0] = 0x8080
1345 ***************************************/
1346         u8      value8;
1347         u16     value16;
1348         u32     value32;
1349
1350         /* 1. Disable GPIO[7:0] */
1351         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1352         value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1353         value8 = (u8) (value32&0x000000FF);
1354         value32 |= ((value8<<8) | 0x00FF0000);
1355         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1356         /* 2. Disable GPIO[10:8] */
1357         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1358         value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1359         value8 = (u8) (value16&0x000F);
1360         value16 |= ((value8<<4) | 0x0780);
1361         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1362         /* 3. Disable LED0 & 1 */
1363         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1364 }
1365
1366 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1367 {
1368         struct rtl_priv *rtlpriv = rtl_priv(hw);
1369         u16 value16 = 0;
1370         u8 value8 = 0;
1371
1372         if (bWithoutHWSM) {
1373                 /*****************************
1374                 n. LDOA15_CTRL 0x20[7:0] = 0x04  disable A15 power
1375                 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1376                 r. When driver call disable, the ASIC will turn off remaining
1377                    clock automatically
1378                 ******************************/
1379                 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1380                 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1381                 value8 &= (~LDV12_EN);
1382                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1383         }
1384
1385 /*****************************
1386 h. SPS0_CTRL 0x11[7:0] = 0x23           enter PFM mode
1387 i. APS_FSMCO 0x04[15:0] = 0x4802        set USB suspend
1388 ******************************/
1389         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1390         value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1391         rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1392         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1393 }
1394
1395 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1396 {
1397         /* ==== RF Off Sequence ==== */
1398         _DisableRFAFEAndResetBB(hw);
1399         /* ==== Reset digital sequence   ====== */
1400         _ResetDigitalProcedure1(hw, false);
1401         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1402         _DisableGPIO(hw);
1403         /* ==== Disable analog sequence === */
1404         _DisableAnalog(hw, false);
1405 }
1406
1407 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1408 {
1409         /*==== RF Off Sequence ==== */
1410         _DisableRFAFEAndResetBB(hw);
1411         /*  ==== Reset digital sequence   ====== */
1412         _ResetDigitalProcedure1(hw, true);
1413         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1414         _DisableGPIO(hw);
1415         /*  ==== Reset digital sequence   ====== */
1416         _ResetDigitalProcedure2(hw);
1417         /*  ==== Disable analog sequence === */
1418         _DisableAnalog(hw, true);
1419 }
1420
1421 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1422                                       u8 set_bits, u8 clear_bits)
1423 {
1424         struct rtl_priv *rtlpriv = rtl_priv(hw);
1425         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1426
1427         rtlusb->reg_bcn_ctrl_val |= set_bits;
1428         rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1429         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1430 }
1431
1432 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1433 {
1434         struct rtl_priv *rtlpriv = rtl_priv(hw);
1435         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1436         u8 tmp1byte = 0;
1437         if (IS_NORMAL_CHIP(rtlhal->version)) {
1438                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1439                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1440                                tmp1byte & (~BIT(6)));
1441                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1442                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1443                 tmp1byte &= ~(BIT(0));
1444                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1445         } else {
1446                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1447                                rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1448         }
1449 }
1450
1451 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1452 {
1453         struct rtl_priv *rtlpriv = rtl_priv(hw);
1454         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1455         u8 tmp1byte = 0;
1456
1457         if (IS_NORMAL_CHIP(rtlhal->version)) {
1458                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1459                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1460                                tmp1byte | BIT(6));
1461                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1462                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1463                 tmp1byte |= BIT(0);
1464                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1465         } else {
1466                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1467                                rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1468         }
1469 }
1470
1471 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1472 {
1473         struct rtl_priv *rtlpriv = rtl_priv(hw);
1474         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1475
1476         if (IS_NORMAL_CHIP(rtlhal->version))
1477                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1478         else
1479                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1480 }
1481
1482 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1483 {
1484         struct rtl_priv *rtlpriv = rtl_priv(hw);
1485         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1486
1487         if (IS_NORMAL_CHIP(rtlhal->version))
1488                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1489         else
1490                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1491 }
1492
1493 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1494                                      enum nl80211_iftype type)
1495 {
1496         struct rtl_priv *rtlpriv = rtl_priv(hw);
1497         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1498         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1499
1500         bt_msr &= 0xfc;
1501         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1502         if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1503             NL80211_IFTYPE_STATION) {
1504                 _rtl92cu_stop_tx_beacon(hw);
1505                 _rtl92cu_enable_bcn_sub_func(hw);
1506         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1507                 _rtl92cu_resume_tx_beacon(hw);
1508                 _rtl92cu_disable_bcn_sub_func(hw);
1509         } else {
1510                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("Set HW_VAR_MEDIA_"
1511                          "STATUS:No such media status(%x).\n", type));
1512         }
1513         switch (type) {
1514         case NL80211_IFTYPE_UNSPECIFIED:
1515                 bt_msr |= MSR_NOLINK;
1516                 ledaction = LED_CTL_LINK;
1517                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1518                          ("Set Network type to NO LINK!\n"));
1519                 break;
1520         case NL80211_IFTYPE_ADHOC:
1521                 bt_msr |= MSR_ADHOC;
1522                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1523                          ("Set Network type to Ad Hoc!\n"));
1524                 break;
1525         case NL80211_IFTYPE_STATION:
1526                 bt_msr |= MSR_INFRA;
1527                 ledaction = LED_CTL_LINK;
1528                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1529                          ("Set Network type to STA!\n"));
1530                 break;
1531         case NL80211_IFTYPE_AP:
1532                 bt_msr |= MSR_AP;
1533                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1534                          ("Set Network type to AP!\n"));
1535                 break;
1536         default:
1537                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1538                          ("Network type %d not support!\n", type));
1539                 goto error_out;
1540         }
1541         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1542         rtlpriv->cfg->ops->led_control(hw, ledaction);
1543         if ((bt_msr & 0xfc) == MSR_AP)
1544                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1545         else
1546                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1547         return 0;
1548 error_out:
1549         return 1;
1550 }
1551
1552 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1553 {
1554         struct rtl_priv *rtlpriv = rtl_priv(hw);
1555         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1556         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1557         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1558         enum nl80211_iftype opmode;
1559
1560         mac->link_state = MAC80211_NOLINK;
1561         opmode = NL80211_IFTYPE_UNSPECIFIED;
1562         _rtl92cu_set_media_status(hw, opmode);
1563         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1564         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1565         if (rtlusb->disableHWSM)
1566                 _CardDisableHWSM(hw);
1567         else
1568                 _CardDisableWithoutHWSM(hw);
1569 }
1570
1571 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1572 {
1573         /* dummy routine needed for callback from rtl_op_configure_filter() */
1574 }
1575
1576 /*========================================================================== */
1577
1578 static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1579                               enum nl80211_iftype type)
1580 {
1581         struct rtl_priv *rtlpriv = rtl_priv(hw);
1582         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1583         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1584         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1585         u8 filterout_non_associated_bssid = false;
1586
1587         switch (type) {
1588         case NL80211_IFTYPE_ADHOC:
1589         case NL80211_IFTYPE_STATION:
1590                 filterout_non_associated_bssid = true;
1591                 break;
1592         case NL80211_IFTYPE_UNSPECIFIED:
1593         case NL80211_IFTYPE_AP:
1594         default:
1595                 break;
1596         }
1597         if (filterout_non_associated_bssid) {
1598                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1599                         switch (rtlphy->current_io_type) {
1600                         case IO_CMD_RESUME_DM_BY_SCAN:
1601                                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1602                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1603                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1604                                 /* enable update TSF */
1605                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1606                                 break;
1607                         case IO_CMD_PAUSE_DM_BY_SCAN:
1608                                 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1609                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1610                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1611                                 /* disable update TSF */
1612                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1613                                 break;
1614                         }
1615                 } else {
1616                         reg_rcr |= (RCR_CBSSID);
1617                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1618                                                       (u8 *)(&reg_rcr));
1619                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1620                 }
1621         } else if (filterout_non_associated_bssid == false) {
1622                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1623                         reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1624                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1625                                                       (u8 *)(&reg_rcr));
1626                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1627                 } else {
1628                         reg_rcr &= (~RCR_CBSSID);
1629                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1630                                                       (u8 *)(&reg_rcr));
1631                         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1632                 }
1633         }
1634 }
1635
1636 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1637 {
1638         if (_rtl92cu_set_media_status(hw, type))
1639                 return -EOPNOTSUPP;
1640         _rtl92cu_set_check_bssid(hw, type);
1641         return 0;
1642 }
1643
1644 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1645 {
1646         struct rtl_priv *rtlpriv = rtl_priv(hw);
1647         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1648
1649         rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1650
1651         /* TODO: Remove these magic number */
1652         rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1653         rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1654         rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1655         /* Change beacon AIFS to the largest number
1656          * beacause test chip does not contension before sending beacon. */
1657         if (IS_NORMAL_CHIP(rtlhal->version))
1658                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1659         else
1660                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1661 }
1662
1663 static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1664                                     bool Linked)
1665 {
1666         struct rtl_priv *rtlpriv = rtl_priv(hw);
1667
1668         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1669         rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1670 }
1671
1672 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1673 {
1674
1675         struct rtl_priv *rtlpriv = rtl_priv(hw);
1676         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1677         u16 bcn_interval, atim_window;
1678         u32 value32;
1679
1680         bcn_interval = mac->beacon_interval;
1681         atim_window = 2;        /*FIX MERGE */
1682         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1683         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1684         _InitBeaconParameters(hw);
1685         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1686         /*
1687          * Force beacon frame transmission even after receiving beacon frame
1688          * from other ad hoc STA
1689          *
1690          *
1691          * Reset TSF Timer to zero, added by Roger. 2008.06.24
1692          */
1693         value32 = rtl_read_dword(rtlpriv, REG_TCR);
1694         value32 &= ~TSFRST;
1695         rtl_write_dword(rtlpriv, REG_TCR, value32);
1696         value32 |= TSFRST;
1697         rtl_write_dword(rtlpriv, REG_TCR, value32);
1698         RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1699                  ("SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1700                  value32));
1701         /* TODO: Modify later (Find the right parameters)
1702          * NOTE: Fix test chip's bug (about contention windows's randomness) */
1703         if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1704             (mac->opmode == NL80211_IFTYPE_AP)) {
1705                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1706                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1707         }
1708         _beacon_function_enable(hw, true, true);
1709 }
1710
1711 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1712 {
1713         struct rtl_priv *rtlpriv = rtl_priv(hw);
1714         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1715         u16 bcn_interval = mac->beacon_interval;
1716
1717         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1718                  ("beacon_interval:%d\n", bcn_interval));
1719         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1720 }
1721
1722 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1723                                    u32 add_msr, u32 rm_msr)
1724 {
1725 }
1726
1727 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1728 {
1729         struct rtl_priv *rtlpriv = rtl_priv(hw);
1730         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1731         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1732
1733         switch (variable) {
1734         case HW_VAR_RCR:
1735                 *((u32 *)(val)) = mac->rx_conf;
1736                 break;
1737         case HW_VAR_RF_STATE:
1738                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1739                 break;
1740         case HW_VAR_FWLPS_RF_ON:{
1741                         enum rf_pwrstate rfState;
1742                         u32 val_rcr;
1743
1744                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1745                                                       (u8 *)(&rfState));
1746                         if (rfState == ERFOFF) {
1747                                 *((bool *) (val)) = true;
1748                         } else {
1749                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1750                                 val_rcr &= 0x00070000;
1751                                 if (val_rcr)
1752                                         *((bool *) (val)) = false;
1753                                 else
1754                                         *((bool *) (val)) = true;
1755                         }
1756                         break;
1757                 }
1758         case HW_VAR_FW_PSMODE_STATUS:
1759                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1760                 break;
1761         case HW_VAR_CORRECT_TSF:{
1762                         u64 tsf;
1763                         u32 *ptsf_low = (u32 *)&tsf;
1764                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
1765
1766                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1767                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1768                         *((u64 *)(val)) = tsf;
1769                         break;
1770                 }
1771         case HW_VAR_MGT_FILTER:
1772                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1773                 break;
1774         case HW_VAR_CTRL_FILTER:
1775                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1776                 break;
1777         case HW_VAR_DATA_FILTER:
1778                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1779                 break;
1780         default:
1781                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1782                          ("switch case not process\n"));
1783                 break;
1784         }
1785 }
1786
1787 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1788 {
1789         struct rtl_priv *rtlpriv = rtl_priv(hw);
1790         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1791         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1792         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1793         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1794         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1795         enum wireless_mode wirelessmode = mac->mode;
1796         u8 idx = 0;
1797
1798         switch (variable) {
1799         case HW_VAR_ETHER_ADDR:{
1800                         for (idx = 0; idx < ETH_ALEN; idx++) {
1801                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1802                                                val[idx]);
1803                         }
1804                         break;
1805                 }
1806         case HW_VAR_BASIC_RATE:{
1807                         u16 rate_cfg = ((u16 *) val)[0];
1808                         u8 rate_index = 0;
1809
1810                         rate_cfg &= 0x15f;
1811                         /* TODO */
1812                         /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1813                          *     && ((rate_cfg & 0x150) == 0)) {
1814                          *        rate_cfg |= 0x010;
1815                          * } */
1816                         rate_cfg |= 0x01;
1817                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1818                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
1819                                        (rate_cfg >> 8) & 0xff);
1820                         while (rate_cfg > 0x1) {
1821                                 rate_cfg >>= 1;
1822                                 rate_index++;
1823                         }
1824                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1825                                        rate_index);
1826                         break;
1827                 }
1828         case HW_VAR_BSSID:{
1829                         for (idx = 0; idx < ETH_ALEN; idx++) {
1830                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1831                                                val[idx]);
1832                         }
1833                         break;
1834                 }
1835         case HW_VAR_SIFS:{
1836                         rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1837                         rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1838                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1839                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1840                         rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1841                         rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1842                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1843                                  ("HW_VAR_SIFS\n"));
1844                         break;
1845                 }
1846         case HW_VAR_SLOT_TIME:{
1847                         u8 e_aci;
1848                         u8 QOS_MODE = 1;
1849
1850                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1851                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1852                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
1853                         if (QOS_MODE) {
1854                                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1855                                         rtlpriv->cfg->ops->set_hw_reg(hw,
1856                                                                 HW_VAR_AC_PARAM,
1857                                                                 (u8 *)(&e_aci));
1858                         } else {
1859                                 u8 sifstime = 0;
1860                                 u8      u1bAIFS;
1861
1862                                 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1863                                     IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1864                                     IS_WIRELESS_MODE_N_5G(wirelessmode))
1865                                         sifstime = 16;
1866                                 else
1867                                         sifstime = 10;
1868                                 u1bAIFS = sifstime + (2 *  val[0]);
1869                                 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1870                                                u1bAIFS);
1871                                 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1872                                                u1bAIFS);
1873                                 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1874                                                u1bAIFS);
1875                                 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1876                                                u1bAIFS);
1877                         }
1878                         break;
1879                 }
1880         case HW_VAR_ACK_PREAMBLE:{
1881                         u8 reg_tmp;
1882                         u8 short_preamble = (bool) (*(u8 *) val);
1883                         reg_tmp = 0;
1884                         if (short_preamble)
1885                                 reg_tmp |= 0x80;
1886                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1887                         break;
1888                 }
1889         case HW_VAR_AMPDU_MIN_SPACE:{
1890                         u8 min_spacing_to_set;
1891                         u8 sec_min_space;
1892
1893                         min_spacing_to_set = *((u8 *) val);
1894                         if (min_spacing_to_set <= 7) {
1895                                 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1896                                 case NO_ENCRYPTION:
1897                                 case AESCCMP_ENCRYPTION:
1898                                         sec_min_space = 0;
1899                                         break;
1900                                 case WEP40_ENCRYPTION:
1901                                 case WEP104_ENCRYPTION:
1902                                 case TKIP_ENCRYPTION:
1903                                         sec_min_space = 6;
1904                                         break;
1905                                 default:
1906                                         sec_min_space = 7;
1907                                         break;
1908                                 }
1909                                 if (min_spacing_to_set < sec_min_space)
1910                                         min_spacing_to_set = sec_min_space;
1911                                 mac->min_space_cfg = ((mac->min_space_cfg &
1912                                                      0xf8) |
1913                                                      min_spacing_to_set);
1914                                 *val = min_spacing_to_set;
1915                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1916                                         ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1917                                         mac->min_space_cfg));
1918                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1919                                                mac->min_space_cfg);
1920                         }
1921                         break;
1922                 }
1923         case HW_VAR_SHORTGI_DENSITY:{
1924                         u8 density_to_set;
1925
1926                         density_to_set = *((u8 *) val);
1927                         density_to_set &= 0x1f;
1928                         mac->min_space_cfg &= 0x07;
1929                         mac->min_space_cfg |= (density_to_set << 3);
1930                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1931                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1932                                   mac->min_space_cfg));
1933                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1934                                        mac->min_space_cfg);
1935                         break;
1936                 }
1937         case HW_VAR_AMPDU_FACTOR:{
1938                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1939                         u8 factor_toset;
1940                         u8 *p_regtoset = NULL;
1941                         u8 index = 0;
1942
1943                         p_regtoset = regtoset_normal;
1944                         factor_toset = *((u8 *) val);
1945                         if (factor_toset <= 3) {
1946                                 factor_toset = (1 << (factor_toset + 2));
1947                                 if (factor_toset > 0xf)
1948                                         factor_toset = 0xf;
1949                                 for (index = 0; index < 4; index++) {
1950                                         if ((p_regtoset[index] & 0xf0) >
1951                                             (factor_toset << 4))
1952                                                 p_regtoset[index] =
1953                                                      (p_regtoset[index] & 0x0f)
1954                                                      | (factor_toset << 4);
1955                                         if ((p_regtoset[index] & 0x0f) >
1956                                              factor_toset)
1957                                                 p_regtoset[index] =
1958                                                      (p_regtoset[index] & 0xf0)
1959                                                      | (factor_toset);
1960                                         rtl_write_byte(rtlpriv,
1961                                                        (REG_AGGLEN_LMT + index),
1962                                                        p_regtoset[index]);
1963                                 }
1964                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1965                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
1966                                           factor_toset));
1967                         }
1968                         break;
1969                 }
1970         case HW_VAR_AC_PARAM:{
1971                         u8 e_aci = *((u8 *) val);
1972                         u32 u4b_ac_param;
1973                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1974                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1975                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1976
1977                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1978                         u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1979                                          AC_PARAM_ECW_MIN_OFFSET);
1980                         u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1981                                          AC_PARAM_ECW_MAX_OFFSET);
1982                         u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1983                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1984                                  ("queue:%x, ac_param:%x\n", e_aci,
1985                                   u4b_ac_param));
1986                         switch (e_aci) {
1987                         case AC1_BK:
1988                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1989                                                 u4b_ac_param);
1990                                 break;
1991                         case AC0_BE:
1992                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1993                                                 u4b_ac_param);
1994                                 break;
1995                         case AC2_VI:
1996                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1997                                                 u4b_ac_param);
1998                                 break;
1999                         case AC3_VO:
2000                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
2001                                                 u4b_ac_param);
2002                                 break;
2003                         default:
2004                                 RT_ASSERT(false, ("SetHwReg8185(): invalid"
2005                                           " aci: %d !\n", e_aci));
2006                                 break;
2007                         }
2008                         if (rtlusb->acm_method != eAcmWay2_SW)
2009                                 rtlpriv->cfg->ops->set_hw_reg(hw,
2010                                          HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
2011                         break;
2012                 }
2013         case HW_VAR_ACM_CTRL:{
2014                         u8 e_aci = *((u8 *) val);
2015                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
2016                                                         (&(mac->ac[0].aifs));
2017                         u8 acm = p_aci_aifsn->f.acm;
2018                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2019
2020                         acm_ctrl =
2021                             acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2022                         if (acm) {
2023                                 switch (e_aci) {
2024                                 case AC0_BE:
2025                                         acm_ctrl |= AcmHw_BeqEn;
2026                                         break;
2027                                 case AC2_VI:
2028                                         acm_ctrl |= AcmHw_ViqEn;
2029                                         break;
2030                                 case AC3_VO:
2031                                         acm_ctrl |= AcmHw_VoqEn;
2032                                         break;
2033                                 default:
2034                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2035                                                  ("HW_VAR_ACM_CTRL acm set "
2036                                                   "failed: eACI is %d\n", acm));
2037                                         break;
2038                                 }
2039                         } else {
2040                                 switch (e_aci) {
2041                                 case AC0_BE:
2042                                         acm_ctrl &= (~AcmHw_BeqEn);
2043                                         break;
2044                                 case AC2_VI:
2045                                         acm_ctrl &= (~AcmHw_ViqEn);
2046                                         break;
2047                                 case AC3_VO:
2048                                         acm_ctrl &= (~AcmHw_BeqEn);
2049                                         break;
2050                                 default:
2051                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2052                                                  ("switch case not process\n"));
2053                                         break;
2054                                 }
2055                         }
2056                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2057                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
2058                                   "Write 0x%X\n", acm_ctrl));
2059                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2060                         break;
2061                 }
2062         case HW_VAR_RCR:{
2063                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2064                         mac->rx_conf = ((u32 *) (val))[0];
2065                         RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2066                                  ("### Set RCR(0x%08x) ###\n", mac->rx_conf));
2067                         break;
2068                 }
2069         case HW_VAR_RETRY_LIMIT:{
2070                         u8 retry_limit = ((u8 *) (val))[0];
2071
2072                         rtl_write_word(rtlpriv, REG_RL,
2073                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2074                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
2075                         RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, ("Set HW_VAR_R"
2076                                  "ETRY_LIMIT(0x%08x)\n", retry_limit));
2077                         break;
2078                 }
2079         case HW_VAR_DUAL_TSF_RST:
2080                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2081                 break;
2082         case HW_VAR_EFUSE_BYTES:
2083                 rtlefuse->efuse_usedbytes = *((u16 *) val);
2084                 break;
2085         case HW_VAR_EFUSE_USAGE:
2086                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2087                 break;
2088         case HW_VAR_IO_CMD:
2089                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2090                 break;
2091         case HW_VAR_WPA_CONFIG:
2092                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2093                 break;
2094         case HW_VAR_SET_RPWM:{
2095                         u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2096
2097                         if (rpwm_val & BIT(7))
2098                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2099                                                (*(u8 *)val));
2100                         else
2101                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2102                                                ((*(u8 *)val) | BIT(7)));
2103                         break;
2104                 }
2105         case HW_VAR_H2C_FW_PWRMODE:{
2106                         u8 psmode = (*(u8 *) val);
2107
2108                         if ((psmode != FW_PS_ACTIVE_MODE) &&
2109                            (!IS_92C_SERIAL(rtlhal->version)))
2110                                 rtl92c_dm_rf_saving(hw, true);
2111                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2112                         break;
2113                 }
2114         case HW_VAR_FW_PSMODE_STATUS:
2115                 ppsc->fw_current_inpsmode = *((bool *) val);
2116                 break;
2117         case HW_VAR_H2C_FW_JOINBSSRPT:{
2118                         u8 mstatus = (*(u8 *) val);
2119                         u8 tmp_reg422;
2120                         bool recover = false;
2121
2122                         if (mstatus == RT_MEDIA_CONNECT) {
2123                                 rtlpriv->cfg->ops->set_hw_reg(hw,
2124                                                          HW_VAR_AID, NULL);
2125                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2126                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2127                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2128                                 tmp_reg422 = rtl_read_byte(rtlpriv,
2129                                                         REG_FWHW_TXQ_CTRL + 2);
2130                                 if (tmp_reg422 & BIT(6))
2131                                         recover = true;
2132                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2133                                                tmp_reg422 & (~BIT(6)));
2134                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2135                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2136                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2137                                 if (recover)
2138                                         rtl_write_byte(rtlpriv,
2139                                                  REG_FWHW_TXQ_CTRL + 2,
2140                                                 tmp_reg422 | BIT(6));
2141                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2142                         }
2143                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2144                         break;
2145                 }
2146         case HW_VAR_AID:{
2147                         u16 u2btmp;
2148
2149                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2150                         u2btmp &= 0xC000;
2151                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2152                                        (u2btmp | mac->assoc_id));
2153                         break;
2154                 }
2155         case HW_VAR_CORRECT_TSF:{
2156                         u8 btype_ibss = ((u8 *) (val))[0];
2157
2158                         if (btype_ibss)
2159                                 _rtl92cu_stop_tx_beacon(hw);
2160                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2161                         rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2162                                         0xffffffff));
2163                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2164                                         (u32)((mac->tsf >> 32) & 0xffffffff));
2165                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2166                         if (btype_ibss)
2167                                 _rtl92cu_resume_tx_beacon(hw);
2168                         break;
2169                 }
2170         case HW_VAR_MGT_FILTER:
2171                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2172                 break;
2173         case HW_VAR_CTRL_FILTER:
2174                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2175                 break;
2176         case HW_VAR_DATA_FILTER:
2177                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2178                 break;
2179         default:
2180                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2181                                                         "not process\n"));
2182                 break;
2183         }
2184 }
2185
2186 void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
2187                                    struct ieee80211_sta *sta,
2188                                    u8 rssi_level)
2189 {
2190         struct rtl_priv *rtlpriv = rtl_priv(hw);
2191         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2192         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2193         u32 ratr_value = (u32) mac->basic_rates;
2194         u8 *mcsrate = mac->mcs;
2195         u8 ratr_index = 0;
2196         u8 nmode = mac->ht_enable;
2197         u8 mimo_ps = 1;
2198         u16 shortgi_rate = 0;
2199         u32 tmp_ratr_value = 0;
2200         u8 curtxbw_40mhz = mac->bw_40;
2201         u8 curshortgi_40mhz = mac->sgi_40;
2202         u8 curshortgi_20mhz = mac->sgi_20;
2203         enum wireless_mode wirelessmode = mac->mode;
2204
2205         ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2206         switch (wirelessmode) {
2207         case WIRELESS_MODE_B:
2208                 if (ratr_value & 0x0000000c)
2209                         ratr_value &= 0x0000000d;
2210                 else
2211                         ratr_value &= 0x0000000f;
2212                 break;
2213         case WIRELESS_MODE_G:
2214                 ratr_value &= 0x00000FF5;
2215                 break;
2216         case WIRELESS_MODE_N_24G:
2217         case WIRELESS_MODE_N_5G:
2218                 nmode = 1;
2219                 if (mimo_ps == 0) {
2220                         ratr_value &= 0x0007F005;
2221                 } else {
2222                         u32 ratr_mask;
2223
2224                         if (get_rf_type(rtlphy) == RF_1T2R ||
2225                             get_rf_type(rtlphy) == RF_1T1R)
2226                                 ratr_mask = 0x000ff005;
2227                         else
2228                                 ratr_mask = 0x0f0ff005;
2229                         if (curtxbw_40mhz)
2230                                 ratr_mask |= 0x00000010;
2231                         ratr_value &= ratr_mask;
2232                 }
2233                 break;
2234         default:
2235                 if (rtlphy->rf_type == RF_1T2R)
2236                         ratr_value &= 0x000ff0ff;
2237                 else
2238                         ratr_value &= 0x0f0ff0ff;
2239                 break;
2240         }
2241         ratr_value &= 0x0FFFFFFF;
2242         if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2243             (!curtxbw_40mhz && curshortgi_20mhz))) {
2244                 ratr_value |= 0x10000000;
2245                 tmp_ratr_value = (ratr_value >> 12);
2246                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2247                         if ((1 << shortgi_rate) & tmp_ratr_value)
2248                                 break;
2249                 }
2250                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2251                                (shortgi_rate << 4) | (shortgi_rate);
2252         }
2253         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2254         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("%x\n", rtl_read_dword(rtlpriv,
2255                  REG_ARFR0)));
2256 }
2257
2258 void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2259 {
2260         struct rtl_priv *rtlpriv = rtl_priv(hw);
2261         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2262         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2263         u32 ratr_bitmap = (u32) mac->basic_rates;
2264         u8 *p_mcsrate = mac->mcs;
2265         u8 ratr_index = 0;
2266         u8 curtxbw_40mhz = mac->bw_40;
2267         u8 curshortgi_40mhz = mac->sgi_40;
2268         u8 curshortgi_20mhz = mac->sgi_20;
2269         enum wireless_mode wirelessmode = mac->mode;
2270         bool shortgi = false;
2271         u8 rate_mask[5];
2272         u8 macid = 0;
2273         u8 mimops = 1;
2274
2275         ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2276         switch (wirelessmode) {
2277         case WIRELESS_MODE_B:
2278                 ratr_index = RATR_INX_WIRELESS_B;
2279                 if (ratr_bitmap & 0x0000000c)
2280                         ratr_bitmap &= 0x0000000d;
2281                 else
2282                         ratr_bitmap &= 0x0000000f;
2283                 break;
2284         case WIRELESS_MODE_G:
2285                 ratr_index = RATR_INX_WIRELESS_GB;
2286                 if (rssi_level == 1)
2287                         ratr_bitmap &= 0x00000f00;
2288                 else if (rssi_level == 2)
2289                         ratr_bitmap &= 0x00000ff0;
2290                 else
2291                         ratr_bitmap &= 0x00000ff5;
2292                 break;
2293         case WIRELESS_MODE_A:
2294                 ratr_index = RATR_INX_WIRELESS_A;
2295                 ratr_bitmap &= 0x00000ff0;
2296                 break;
2297         case WIRELESS_MODE_N_24G:
2298         case WIRELESS_MODE_N_5G:
2299                 ratr_index = RATR_INX_WIRELESS_NGB;
2300                 if (mimops == 0) {
2301                         if (rssi_level == 1)
2302                                 ratr_bitmap &= 0x00070000;
2303                         else if (rssi_level == 2)
2304                                 ratr_bitmap &= 0x0007f000;
2305                         else
2306                                 ratr_bitmap &= 0x0007f005;
2307                 } else {
2308                         if (rtlphy->rf_type == RF_1T2R ||
2309                             rtlphy->rf_type == RF_1T1R) {
2310                                 if (curtxbw_40mhz) {
2311                                         if (rssi_level == 1)
2312                                                 ratr_bitmap &= 0x000f0000;
2313                                         else if (rssi_level == 2)
2314                                                 ratr_bitmap &= 0x000ff000;
2315                                         else
2316                                                 ratr_bitmap &= 0x000ff015;
2317                                 } else {
2318                                         if (rssi_level == 1)
2319                                                 ratr_bitmap &= 0x000f0000;
2320                                         else if (rssi_level == 2)
2321                                                 ratr_bitmap &= 0x000ff000;
2322                                         else
2323                                                 ratr_bitmap &= 0x000ff005;
2324                                 }
2325                         } else {
2326                                 if (curtxbw_40mhz) {
2327                                         if (rssi_level == 1)
2328                                                 ratr_bitmap &= 0x0f0f0000;
2329                                         else if (rssi_level == 2)
2330                                                 ratr_bitmap &= 0x0f0ff000;
2331                                         else
2332                                                 ratr_bitmap &= 0x0f0ff015;
2333                                 } else {
2334                                         if (rssi_level == 1)
2335                                                 ratr_bitmap &= 0x0f0f0000;
2336                                         else if (rssi_level == 2)
2337                                                 ratr_bitmap &= 0x0f0ff000;
2338                                         else
2339                                                 ratr_bitmap &= 0x0f0ff005;
2340                                 }
2341                         }
2342                 }
2343                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2344                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2345                         if (macid == 0)
2346                                 shortgi = true;
2347                         else if (macid == 1)
2348                                 shortgi = false;
2349                 }
2350                 break;
2351         default:
2352                 ratr_index = RATR_INX_WIRELESS_NGB;
2353                 if (rtlphy->rf_type == RF_1T2R)
2354                         ratr_bitmap &= 0x000ff0ff;
2355                 else
2356                         ratr_bitmap &= 0x0f0ff0ff;
2357                 break;
2358         }
2359         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("ratr_bitmap :%x\n",
2360                  ratr_bitmap));
2361         *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2362                                       ratr_index << 28);
2363         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2364         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
2365                                                 "ratr_val:%x, %x:%x:%x:%x:%x\n",
2366                                                 ratr_index, ratr_bitmap,
2367                                                 rate_mask[0], rate_mask[1],
2368                                                 rate_mask[2], rate_mask[3],
2369                                                 rate_mask[4]));
2370         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2371 }
2372
2373 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2374 {
2375         struct rtl_priv *rtlpriv = rtl_priv(hw);
2376         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2377         u16 sifs_timer;
2378
2379         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2380                                       (u8 *)&mac->slot_time);
2381         if (!mac->ht_enable)
2382                 sifs_timer = 0x0a0a;
2383         else
2384                 sifs_timer = 0x0e0e;
2385         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2386 }
2387
2388 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2389 {
2390         struct rtl_priv *rtlpriv = rtl_priv(hw);
2391         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2392         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2393         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2394         u8 u1tmp = 0;
2395         bool actuallyset = false;
2396         unsigned long flag = 0;
2397         /* to do - usb autosuspend */
2398         u8 usb_autosuspend = 0;
2399
2400         if (ppsc->swrf_processing)
2401                 return false;
2402         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2403         if (ppsc->rfchange_inprogress) {
2404                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2405                 return false;
2406         } else {
2407                 ppsc->rfchange_inprogress = true;
2408                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2409         }
2410         cur_rfstate = ppsc->rfpwr_state;
2411         if (usb_autosuspend) {
2412                 /* to do................... */
2413         } else {
2414                 if (ppsc->pwrdown_mode) {
2415                         u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2416                         e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2417                                                ERFOFF : ERFON;
2418                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2419                                  ("pwrdown, 0x5c(BIT7)=%02x\n", u1tmp));
2420                 } else {
2421                         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2422                                        rtl_read_byte(rtlpriv,
2423                                        REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2424                         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2425                         e_rfpowerstate_toset  = (u1tmp & BIT(3)) ?
2426                                                  ERFON : ERFOFF;
2427                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2428                                 ("GPIO_IN=%02x\n", u1tmp));
2429                 }
2430                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("N-SS RF =%x\n",
2431                          e_rfpowerstate_toset));
2432         }
2433         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2434                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF  - HW "
2435                          "Radio ON, RF ON\n"));
2436                 ppsc->hwradiooff = false;
2437                 actuallyset = true;
2438         } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset  ==
2439                     ERFOFF)) {
2440                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF  - HW"
2441                          " Radio OFF\n"));
2442                 ppsc->hwradiooff = true;
2443                 actuallyset = true;
2444         } else {
2445                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
2446                          ("pHalData->bHwRadioOff and eRfPowerStateToSet do not"
2447                          " match: pHalData->bHwRadioOff %x, eRfPowerStateToSet "
2448                          "%x\n", ppsc->hwradiooff, e_rfpowerstate_toset));
2449         }
2450         if (actuallyset) {
2451                 ppsc->hwradiooff = 1;
2452                 if (e_rfpowerstate_toset == ERFON) {
2453                         if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM) &&
2454                              RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2455                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2456                         else if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2457                                  && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2458                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2459                 }
2460                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2461                 ppsc->rfchange_inprogress = false;
2462                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2463                 /* For power down module, we need to enable register block
2464                  * contrl reg at 0x1c. Then enable power down control bit
2465                  * of register 0x04 BIT4 and BIT15 as 1.
2466                  */
2467                 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2468                         /* Enable register area 0x0-0xc. */
2469                         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2470                         if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2471                                 /*
2472                                  * We should configure HW PDn source for WiFi
2473                                  * ONLY, and then our HW will be set in
2474                                  * power-down mode if PDn source from all
2475                                  * functions are configured.
2476                                  */
2477                                 u1tmp = rtl_read_byte(rtlpriv,
2478                                                       REG_MULTI_FUNC_CTRL);
2479                                 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2480                                                (u1tmp|WL_HWPDN_EN));
2481                         } else {
2482                                 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2483                         }
2484                 }
2485                 if (e_rfpowerstate_toset == ERFOFF) {
2486                         if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2487                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2488                         else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2489                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2490                 }
2491         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2492                 /* Enter D3 or ASPM after GPIO had been done. */
2493                 if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2494                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2495                 else if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2496                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2497                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2498                 ppsc->rfchange_inprogress = false;
2499                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2500         } else {
2501                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2502                 ppsc->rfchange_inprogress = false;
2503                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2504         }
2505         *valid = 1;
2506         return !ppsc->hwradiooff;
2507 }