rt2x00: Introduce 3 queue commands in drivers (start, kick, stop).
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt73usb.c
1 /*
2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt73usb
23         Abstract: rt73usb device specific routines.
24         Supported chipsets: rt2571W & rt2671.
25  */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/usb.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00usb.h"
38 #include "rt73usb.h"
39
40 /*
41  * Allow hardware encryption to be disabled.
42  */
43 static int modparam_nohwcrypt;
44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
47 /*
48  * Register access.
49  * All access to the CSR registers will go through the methods
50  * rt2x00usb_register_read and rt2x00usb_register_write.
51  * BBP and RF register require indirect register access,
52  * and use the CSR registers BBPCSR and RFCSR to achieve this.
53  * These indirect registers work with busy bits,
54  * and we will try maximal REGISTER_BUSY_COUNT times to access
55  * the register while taking a REGISTER_BUSY_DELAY us delay
56  * between each attampt. When the busy bit is still set at that time,
57  * the access attempt is considered to have failed,
58  * and we will print an error.
59  * The _lock versions must be used if you already hold the csr_mutex
60  */
61 #define WAIT_FOR_BBP(__dev, __reg) \
62         rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
63 #define WAIT_FOR_RF(__dev, __reg) \
64         rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
65
66 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
67                               const unsigned int word, const u8 value)
68 {
69         u32 reg;
70
71         mutex_lock(&rt2x00dev->csr_mutex);
72
73         /*
74          * Wait until the BBP becomes available, afterwards we
75          * can safely write the new data into the register.
76          */
77         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78                 reg = 0;
79                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
84                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
85         }
86
87         mutex_unlock(&rt2x00dev->csr_mutex);
88 }
89
90 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
91                              const unsigned int word, u8 *value)
92 {
93         u32 reg;
94
95         mutex_lock(&rt2x00dev->csr_mutex);
96
97         /*
98          * Wait until the BBP becomes available, afterwards we
99          * can safely write the read request into the register.
100          * After the data has been written, we wait until hardware
101          * returns the correct value, if at any time the register
102          * doesn't become available in time, reg will be 0xffffffff
103          * which means we return 0xff to the caller.
104          */
105         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106                 reg = 0;
107                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
110
111                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
112
113                 WAIT_FOR_BBP(rt2x00dev, &reg);
114         }
115
116         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
117
118         mutex_unlock(&rt2x00dev->csr_mutex);
119 }
120
121 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
122                              const unsigned int word, const u32 value)
123 {
124         u32 reg;
125
126         mutex_lock(&rt2x00dev->csr_mutex);
127
128         /*
129          * Wait until the RF becomes available, afterwards we
130          * can safely write the new data into the register.
131          */
132         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133                 reg = 0;
134                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135                 /*
136                  * RF5225 and RF2527 contain 21 bits per RF register value,
137                  * all others contain 20 bits.
138                  */
139                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
140                                    20 + (rt2x00_rf(rt2x00dev, RF5225) ||
141                                          rt2x00_rf(rt2x00dev, RF2527)));
142                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
143                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
144
145                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
146                 rt2x00_rf_write(rt2x00dev, word, value);
147         }
148
149         mutex_unlock(&rt2x00dev->csr_mutex);
150 }
151
152 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
153 static const struct rt2x00debug rt73usb_rt2x00debug = {
154         .owner  = THIS_MODULE,
155         .csr    = {
156                 .read           = rt2x00usb_register_read,
157                 .write          = rt2x00usb_register_write,
158                 .flags          = RT2X00DEBUGFS_OFFSET,
159                 .word_base      = CSR_REG_BASE,
160                 .word_size      = sizeof(u32),
161                 .word_count     = CSR_REG_SIZE / sizeof(u32),
162         },
163         .eeprom = {
164                 .read           = rt2x00_eeprom_read,
165                 .write          = rt2x00_eeprom_write,
166                 .word_base      = EEPROM_BASE,
167                 .word_size      = sizeof(u16),
168                 .word_count     = EEPROM_SIZE / sizeof(u16),
169         },
170         .bbp    = {
171                 .read           = rt73usb_bbp_read,
172                 .write          = rt73usb_bbp_write,
173                 .word_base      = BBP_BASE,
174                 .word_size      = sizeof(u8),
175                 .word_count     = BBP_SIZE / sizeof(u8),
176         },
177         .rf     = {
178                 .read           = rt2x00_rf_read,
179                 .write          = rt73usb_rf_write,
180                 .word_base      = RF_BASE,
181                 .word_size      = sizeof(u32),
182                 .word_count     = RF_SIZE / sizeof(u32),
183         },
184 };
185 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
186
187 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188 {
189         u32 reg;
190
191         rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
192         return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
193 }
194
195 #ifdef CONFIG_RT2X00_LIB_LEDS
196 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
197                                    enum led_brightness brightness)
198 {
199         struct rt2x00_led *led =
200            container_of(led_cdev, struct rt2x00_led, led_dev);
201         unsigned int enabled = brightness != LED_OFF;
202         unsigned int a_mode =
203             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
204         unsigned int bg_mode =
205             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
206
207         if (led->type == LED_TYPE_RADIO) {
208                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
209                                    MCU_LEDCS_RADIO_STATUS, enabled);
210
211                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
212                                             0, led->rt2x00dev->led_mcu_reg,
213                                             REGISTER_TIMEOUT);
214         } else if (led->type == LED_TYPE_ASSOC) {
215                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
216                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
217                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
218                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
219
220                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
221                                             0, led->rt2x00dev->led_mcu_reg,
222                                             REGISTER_TIMEOUT);
223         } else if (led->type == LED_TYPE_QUALITY) {
224                 /*
225                  * The brightness is divided into 6 levels (0 - 5),
226                  * this means we need to convert the brightness
227                  * argument into the matching level within that range.
228                  */
229                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
230                                             brightness / (LED_FULL / 6),
231                                             led->rt2x00dev->led_mcu_reg,
232                                             REGISTER_TIMEOUT);
233         }
234 }
235
236 static int rt73usb_blink_set(struct led_classdev *led_cdev,
237                              unsigned long *delay_on,
238                              unsigned long *delay_off)
239 {
240         struct rt2x00_led *led =
241             container_of(led_cdev, struct rt2x00_led, led_dev);
242         u32 reg;
243
244         rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
245         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
246         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
247         rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
248
249         return 0;
250 }
251
252 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
253                              struct rt2x00_led *led,
254                              enum led_type type)
255 {
256         led->rt2x00dev = rt2x00dev;
257         led->type = type;
258         led->led_dev.brightness_set = rt73usb_brightness_set;
259         led->led_dev.blink_set = rt73usb_blink_set;
260         led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263
264 /*
265  * Configuration handlers.
266  */
267 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
268                                      struct rt2x00lib_crypto *crypto,
269                                      struct ieee80211_key_conf *key)
270 {
271         struct hw_key_entry key_entry;
272         struct rt2x00_field32 field;
273         u32 mask;
274         u32 reg;
275
276         if (crypto->cmd == SET_KEY) {
277                 /*
278                  * rt2x00lib can't determine the correct free
279                  * key_idx for shared keys. We have 1 register
280                  * with key valid bits. The goal is simple, read
281                  * the register, if that is full we have no slots
282                  * left.
283                  * Note that each BSS is allowed to have up to 4
284                  * shared keys, so put a mask over the allowed
285                  * entries.
286                  */
287                 mask = (0xf << crypto->bssidx);
288
289                 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
290                 reg &= mask;
291
292                 if (reg && reg == mask)
293                         return -ENOSPC;
294
295                 key->hw_key_idx += reg ? ffz(reg) : 0;
296
297                 /*
298                  * Upload key to hardware
299                  */
300                 memcpy(key_entry.key, crypto->key,
301                        sizeof(key_entry.key));
302                 memcpy(key_entry.tx_mic, crypto->tx_mic,
303                        sizeof(key_entry.tx_mic));
304                 memcpy(key_entry.rx_mic, crypto->rx_mic,
305                        sizeof(key_entry.rx_mic));
306
307                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
308                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
309                                               &key_entry, sizeof(key_entry));
310
311                 /*
312                  * The cipher types are stored over 2 registers.
313                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
314                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
315                  * Using the correct defines correctly will cause overhead,
316                  * so just calculate the correct offset.
317                  */
318                 if (key->hw_key_idx < 8) {
319                         field.bit_offset = (3 * key->hw_key_idx);
320                         field.bit_mask = 0x7 << field.bit_offset;
321
322                         rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
323                         rt2x00_set_field32(&reg, field, crypto->cipher);
324                         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
325                 } else {
326                         field.bit_offset = (3 * (key->hw_key_idx - 8));
327                         field.bit_mask = 0x7 << field.bit_offset;
328
329                         rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
330                         rt2x00_set_field32(&reg, field, crypto->cipher);
331                         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
332                 }
333
334                 /*
335                  * The driver does not support the IV/EIV generation
336                  * in hardware. However it doesn't support the IV/EIV
337                  * inside the ieee80211 frame either, but requires it
338                  * to be provided separately for the descriptor.
339                  * rt2x00lib will cut the IV/EIV data out of all frames
340                  * given to us by mac80211, but we must tell mac80211
341                  * to generate the IV/EIV data.
342                  */
343                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
344         }
345
346         /*
347          * SEC_CSR0 contains only single-bit fields to indicate
348          * a particular key is valid. Because using the FIELD32()
349          * defines directly will cause a lot of overhead we use
350          * a calculation to determine the correct bit directly.
351          */
352         mask = 1 << key->hw_key_idx;
353
354         rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
355         if (crypto->cmd == SET_KEY)
356                 reg |= mask;
357         else if (crypto->cmd == DISABLE_KEY)
358                 reg &= ~mask;
359         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
360
361         return 0;
362 }
363
364 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
365                                        struct rt2x00lib_crypto *crypto,
366                                        struct ieee80211_key_conf *key)
367 {
368         struct hw_pairwise_ta_entry addr_entry;
369         struct hw_key_entry key_entry;
370         u32 mask;
371         u32 reg;
372
373         if (crypto->cmd == SET_KEY) {
374                 /*
375                  * rt2x00lib can't determine the correct free
376                  * key_idx for pairwise keys. We have 2 registers
377                  * with key valid bits. The goal is simple, read
378                  * the first register, if that is full move to
379                  * the next register.
380                  * When both registers are full, we drop the key,
381                  * otherwise we use the first invalid entry.
382                  */
383                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
384                 if (reg && reg == ~0) {
385                         key->hw_key_idx = 32;
386                         rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
387                         if (reg && reg == ~0)
388                                 return -ENOSPC;
389                 }
390
391                 key->hw_key_idx += reg ? ffz(reg) : 0;
392
393                 /*
394                  * Upload key to hardware
395                  */
396                 memcpy(key_entry.key, crypto->key,
397                        sizeof(key_entry.key));
398                 memcpy(key_entry.tx_mic, crypto->tx_mic,
399                        sizeof(key_entry.tx_mic));
400                 memcpy(key_entry.rx_mic, crypto->rx_mic,
401                        sizeof(key_entry.rx_mic));
402
403                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
404                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
405                                               &key_entry, sizeof(key_entry));
406
407                 /*
408                  * Send the address and cipher type to the hardware register.
409                  */
410                 memset(&addr_entry, 0, sizeof(addr_entry));
411                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
412                 addr_entry.cipher = crypto->cipher;
413
414                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
415                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
416                                             &addr_entry, sizeof(addr_entry));
417
418                 /*
419                  * Enable pairwise lookup table for given BSS idx,
420                  * without this received frames will not be decrypted
421                  * by the hardware.
422                  */
423                 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
424                 reg |= (1 << crypto->bssidx);
425                 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
426
427                 /*
428                  * The driver does not support the IV/EIV generation
429                  * in hardware. However it doesn't support the IV/EIV
430                  * inside the ieee80211 frame either, but requires it
431                  * to be provided separately for the descriptor.
432                  * rt2x00lib will cut the IV/EIV data out of all frames
433                  * given to us by mac80211, but we must tell mac80211
434                  * to generate the IV/EIV data.
435                  */
436                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
437         }
438
439         /*
440          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
441          * a particular key is valid. Because using the FIELD32()
442          * defines directly will cause a lot of overhead we use
443          * a calculation to determine the correct bit directly.
444          */
445         if (key->hw_key_idx < 32) {
446                 mask = 1 << key->hw_key_idx;
447
448                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
449                 if (crypto->cmd == SET_KEY)
450                         reg |= mask;
451                 else if (crypto->cmd == DISABLE_KEY)
452                         reg &= ~mask;
453                 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
454         } else {
455                 mask = 1 << (key->hw_key_idx - 32);
456
457                 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
458                 if (crypto->cmd == SET_KEY)
459                         reg |= mask;
460                 else if (crypto->cmd == DISABLE_KEY)
461                         reg &= ~mask;
462                 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
463         }
464
465         return 0;
466 }
467
468 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
469                                   const unsigned int filter_flags)
470 {
471         u32 reg;
472
473         /*
474          * Start configuration steps.
475          * Note that the version error will always be dropped
476          * and broadcast frames will always be accepted since
477          * there is no filter for it at this time.
478          */
479         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
480         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
481                            !(filter_flags & FIF_FCSFAIL));
482         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
483                            !(filter_flags & FIF_PLCPFAIL));
484         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
485                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
486         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
487                            !(filter_flags & FIF_PROMISC_IN_BSS));
488         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
489                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
490                            !rt2x00dev->intf_ap_count);
491         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
492         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
493                            !(filter_flags & FIF_ALLMULTI));
494         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
495         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
496                            !(filter_flags & FIF_CONTROL));
497         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
498 }
499
500 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
501                                 struct rt2x00_intf *intf,
502                                 struct rt2x00intf_conf *conf,
503                                 const unsigned int flags)
504 {
505         unsigned int beacon_base;
506         u32 reg;
507
508         if (flags & CONFIG_UPDATE_TYPE) {
509                 /*
510                  * Clear current synchronisation setup.
511                  * For the Beacon base registers we only need to clear
512                  * the first byte since that byte contains the VALID and OWNER
513                  * bits which (when set to 0) will invalidate the entire beacon.
514                  */
515                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
516                 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
517
518                 /*
519                  * Enable synchronisation.
520                  */
521                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
522                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
523                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
524                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
525                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
526         }
527
528         if (flags & CONFIG_UPDATE_MAC) {
529                 reg = le32_to_cpu(conf->mac[1]);
530                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
531                 conf->mac[1] = cpu_to_le32(reg);
532
533                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
534                                             conf->mac, sizeof(conf->mac));
535         }
536
537         if (flags & CONFIG_UPDATE_BSSID) {
538                 reg = le32_to_cpu(conf->bssid[1]);
539                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
540                 conf->bssid[1] = cpu_to_le32(reg);
541
542                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
543                                             conf->bssid, sizeof(conf->bssid));
544         }
545 }
546
547 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
548                                struct rt2x00lib_erp *erp,
549                                u32 changed)
550 {
551         u32 reg;
552
553         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
554         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
555         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
556         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
557
558         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
559                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
560                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
561                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
562                                    !!erp->short_preamble);
563                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
564         }
565
566         if (changed & BSS_CHANGED_BASIC_RATES)
567                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
568                                          erp->basic_rates);
569
570         if (changed & BSS_CHANGED_BEACON_INT) {
571                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
572                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
573                                    erp->beacon_int * 16);
574                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
575         }
576
577         if (changed & BSS_CHANGED_ERP_SLOT) {
578                 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
579                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
580                 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
581
582                 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
583                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
584                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
585                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
586                 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
587         }
588 }
589
590 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
591                                       struct antenna_setup *ant)
592 {
593         u8 r3;
594         u8 r4;
595         u8 r77;
596         u8 temp;
597
598         rt73usb_bbp_read(rt2x00dev, 3, &r3);
599         rt73usb_bbp_read(rt2x00dev, 4, &r4);
600         rt73usb_bbp_read(rt2x00dev, 77, &r77);
601
602         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
603
604         /*
605          * Configure the RX antenna.
606          */
607         switch (ant->rx) {
608         case ANTENNA_HW_DIVERSITY:
609                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
610                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
611                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
612                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
613                 break;
614         case ANTENNA_A:
615                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
616                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
617                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
618                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
619                 else
620                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
621                 break;
622         case ANTENNA_B:
623         default:
624                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
625                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
626                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
627                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
628                 else
629                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
630                 break;
631         }
632
633         rt73usb_bbp_write(rt2x00dev, 77, r77);
634         rt73usb_bbp_write(rt2x00dev, 3, r3);
635         rt73usb_bbp_write(rt2x00dev, 4, r4);
636 }
637
638 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
639                                       struct antenna_setup *ant)
640 {
641         u8 r3;
642         u8 r4;
643         u8 r77;
644
645         rt73usb_bbp_read(rt2x00dev, 3, &r3);
646         rt73usb_bbp_read(rt2x00dev, 4, &r4);
647         rt73usb_bbp_read(rt2x00dev, 77, &r77);
648
649         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
650         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
651                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
652
653         /*
654          * Configure the RX antenna.
655          */
656         switch (ant->rx) {
657         case ANTENNA_HW_DIVERSITY:
658                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
659                 break;
660         case ANTENNA_A:
661                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
662                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
663                 break;
664         case ANTENNA_B:
665         default:
666                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
667                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
668                 break;
669         }
670
671         rt73usb_bbp_write(rt2x00dev, 77, r77);
672         rt73usb_bbp_write(rt2x00dev, 3, r3);
673         rt73usb_bbp_write(rt2x00dev, 4, r4);
674 }
675
676 struct antenna_sel {
677         u8 word;
678         /*
679          * value[0] -> non-LNA
680          * value[1] -> LNA
681          */
682         u8 value[2];
683 };
684
685 static const struct antenna_sel antenna_sel_a[] = {
686         { 96,  { 0x58, 0x78 } },
687         { 104, { 0x38, 0x48 } },
688         { 75,  { 0xfe, 0x80 } },
689         { 86,  { 0xfe, 0x80 } },
690         { 88,  { 0xfe, 0x80 } },
691         { 35,  { 0x60, 0x60 } },
692         { 97,  { 0x58, 0x58 } },
693         { 98,  { 0x58, 0x58 } },
694 };
695
696 static const struct antenna_sel antenna_sel_bg[] = {
697         { 96,  { 0x48, 0x68 } },
698         { 104, { 0x2c, 0x3c } },
699         { 75,  { 0xfe, 0x80 } },
700         { 86,  { 0xfe, 0x80 } },
701         { 88,  { 0xfe, 0x80 } },
702         { 35,  { 0x50, 0x50 } },
703         { 97,  { 0x48, 0x48 } },
704         { 98,  { 0x48, 0x48 } },
705 };
706
707 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
708                                struct antenna_setup *ant)
709 {
710         const struct antenna_sel *sel;
711         unsigned int lna;
712         unsigned int i;
713         u32 reg;
714
715         /*
716          * We should never come here because rt2x00lib is supposed
717          * to catch this and send us the correct antenna explicitely.
718          */
719         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
720                ant->tx == ANTENNA_SW_DIVERSITY);
721
722         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
723                 sel = antenna_sel_a;
724                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
725         } else {
726                 sel = antenna_sel_bg;
727                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
728         }
729
730         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
731                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
732
733         rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
734
735         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
736                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
737         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
738                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
739
740         rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
741
742         if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
743                 rt73usb_config_antenna_5x(rt2x00dev, ant);
744         else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
745                 rt73usb_config_antenna_2x(rt2x00dev, ant);
746 }
747
748 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
749                                     struct rt2x00lib_conf *libconf)
750 {
751         u16 eeprom;
752         short lna_gain = 0;
753
754         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
755                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
756                         lna_gain += 14;
757
758                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
759                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
760         } else {
761                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
762                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
763         }
764
765         rt2x00dev->lna_gain = lna_gain;
766 }
767
768 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
769                                    struct rf_channel *rf, const int txpower)
770 {
771         u8 r3;
772         u8 r94;
773         u8 smart;
774
775         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
776         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
777
778         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
779
780         rt73usb_bbp_read(rt2x00dev, 3, &r3);
781         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
782         rt73usb_bbp_write(rt2x00dev, 3, r3);
783
784         r94 = 6;
785         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
786                 r94 += txpower - MAX_TXPOWER;
787         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
788                 r94 += txpower;
789         rt73usb_bbp_write(rt2x00dev, 94, r94);
790
791         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
792         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
793         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
794         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
795
796         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
797         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
798         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
799         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
800
801         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
802         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
803         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
804         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
805
806         udelay(10);
807 }
808
809 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
810                                    const int txpower)
811 {
812         struct rf_channel rf;
813
814         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
815         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
816         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
817         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
818
819         rt73usb_config_channel(rt2x00dev, &rf, txpower);
820 }
821
822 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
823                                        struct rt2x00lib_conf *libconf)
824 {
825         u32 reg;
826
827         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
828         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
829         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
830         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
831         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
832                            libconf->conf->long_frame_max_tx_count);
833         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
834                            libconf->conf->short_frame_max_tx_count);
835         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
836 }
837
838 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
839                                 struct rt2x00lib_conf *libconf)
840 {
841         enum dev_state state =
842             (libconf->conf->flags & IEEE80211_CONF_PS) ?
843                 STATE_SLEEP : STATE_AWAKE;
844         u32 reg;
845
846         if (state == STATE_SLEEP) {
847                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
848                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
849                                    rt2x00dev->beacon_int - 10);
850                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
851                                    libconf->conf->listen_interval - 1);
852                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
853
854                 /* We must first disable autowake before it can be enabled */
855                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
856                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
857
858                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
859                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
860
861                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
862                                             USB_MODE_SLEEP, REGISTER_TIMEOUT);
863         } else {
864                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
865                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
866                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
867                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
868                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
869                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
870
871                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
872                                             USB_MODE_WAKEUP, REGISTER_TIMEOUT);
873         }
874 }
875
876 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
877                            struct rt2x00lib_conf *libconf,
878                            const unsigned int flags)
879 {
880         /* Always recalculate LNA gain before changing configuration */
881         rt73usb_config_lna_gain(rt2x00dev, libconf);
882
883         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
884                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
885                                        libconf->conf->power_level);
886         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
887             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
888                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
889         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
890                 rt73usb_config_retry_limit(rt2x00dev, libconf);
891         if (flags & IEEE80211_CONF_CHANGE_PS)
892                 rt73usb_config_ps(rt2x00dev, libconf);
893 }
894
895 /*
896  * Link tuning
897  */
898 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
899                                struct link_qual *qual)
900 {
901         u32 reg;
902
903         /*
904          * Update FCS error count from register.
905          */
906         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
907         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
908
909         /*
910          * Update False CCA count from register.
911          */
912         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
913         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
914 }
915
916 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
917                                    struct link_qual *qual, u8 vgc_level)
918 {
919         if (qual->vgc_level != vgc_level) {
920                 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
921                 qual->vgc_level = vgc_level;
922                 qual->vgc_level_reg = vgc_level;
923         }
924 }
925
926 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
927                                 struct link_qual *qual)
928 {
929         rt73usb_set_vgc(rt2x00dev, qual, 0x20);
930 }
931
932 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
933                                struct link_qual *qual, const u32 count)
934 {
935         u8 up_bound;
936         u8 low_bound;
937
938         /*
939          * Determine r17 bounds.
940          */
941         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
942                 low_bound = 0x28;
943                 up_bound = 0x48;
944
945                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
946                         low_bound += 0x10;
947                         up_bound += 0x10;
948                 }
949         } else {
950                 if (qual->rssi > -82) {
951                         low_bound = 0x1c;
952                         up_bound = 0x40;
953                 } else if (qual->rssi > -84) {
954                         low_bound = 0x1c;
955                         up_bound = 0x20;
956                 } else {
957                         low_bound = 0x1c;
958                         up_bound = 0x1c;
959                 }
960
961                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
962                         low_bound += 0x14;
963                         up_bound += 0x10;
964                 }
965         }
966
967         /*
968          * If we are not associated, we should go straight to the
969          * dynamic CCA tuning.
970          */
971         if (!rt2x00dev->intf_associated)
972                 goto dynamic_cca_tune;
973
974         /*
975          * Special big-R17 for very short distance
976          */
977         if (qual->rssi > -35) {
978                 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
979                 return;
980         }
981
982         /*
983          * Special big-R17 for short distance
984          */
985         if (qual->rssi >= -58) {
986                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
987                 return;
988         }
989
990         /*
991          * Special big-R17 for middle-short distance
992          */
993         if (qual->rssi >= -66) {
994                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
995                 return;
996         }
997
998         /*
999          * Special mid-R17 for middle distance
1000          */
1001         if (qual->rssi >= -74) {
1002                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1003                 return;
1004         }
1005
1006         /*
1007          * Special case: Change up_bound based on the rssi.
1008          * Lower up_bound when rssi is weaker then -74 dBm.
1009          */
1010         up_bound -= 2 * (-74 - qual->rssi);
1011         if (low_bound > up_bound)
1012                 up_bound = low_bound;
1013
1014         if (qual->vgc_level > up_bound) {
1015                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1016                 return;
1017         }
1018
1019 dynamic_cca_tune:
1020
1021         /*
1022          * r17 does not yet exceed upper limit, continue and base
1023          * the r17 tuning on the false CCA count.
1024          */
1025         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1026                 rt73usb_set_vgc(rt2x00dev, qual,
1027                                 min_t(u8, qual->vgc_level + 4, up_bound));
1028         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1029                 rt73usb_set_vgc(rt2x00dev, qual,
1030                                 max_t(u8, qual->vgc_level - 4, low_bound));
1031 }
1032
1033 /*
1034  * Queue handlers.
1035  */
1036 static void rt73usb_start_queue(struct data_queue *queue)
1037 {
1038         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1039         u32 reg;
1040
1041         switch (queue->qid) {
1042         case QID_RX:
1043                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1044                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1045                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1046                 break;
1047         case QID_BEACON:
1048                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1049                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1050                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1051                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1052                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1053                 break;
1054         default:
1055                 break;
1056         }
1057 }
1058
1059 static void rt73usb_stop_queue(struct data_queue *queue)
1060 {
1061         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1062         u32 reg;
1063
1064         switch (queue->qid) {
1065         case QID_RX:
1066                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1067                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1068                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1069                 break;
1070         case QID_BEACON:
1071                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1072                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1073                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1074                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1075                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1076                 break;
1077         default:
1078                 break;
1079         }
1080
1081         rt2x00usb_stop_queue(queue);
1082 }
1083
1084 /*
1085  * Firmware functions
1086  */
1087 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1088 {
1089         return FIRMWARE_RT2571;
1090 }
1091
1092 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1093                                   const u8 *data, const size_t len)
1094 {
1095         u16 fw_crc;
1096         u16 crc;
1097
1098         /*
1099          * Only support 2kb firmware files.
1100          */
1101         if (len != 2048)
1102                 return FW_BAD_LENGTH;
1103
1104         /*
1105          * The last 2 bytes in the firmware array are the crc checksum itself,
1106          * this means that we should never pass those 2 bytes to the crc
1107          * algorithm.
1108          */
1109         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1110
1111         /*
1112          * Use the crc itu-t algorithm.
1113          */
1114         crc = crc_itu_t(0, data, len - 2);
1115         crc = crc_itu_t_byte(crc, 0);
1116         crc = crc_itu_t_byte(crc, 0);
1117
1118         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1119 }
1120
1121 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1122                                  const u8 *data, const size_t len)
1123 {
1124         unsigned int i;
1125         int status;
1126         u32 reg;
1127
1128         /*
1129          * Wait for stable hardware.
1130          */
1131         for (i = 0; i < 100; i++) {
1132                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1133                 if (reg)
1134                         break;
1135                 msleep(1);
1136         }
1137
1138         if (!reg) {
1139                 ERROR(rt2x00dev, "Unstable hardware.\n");
1140                 return -EBUSY;
1141         }
1142
1143         /*
1144          * Write firmware to device.
1145          */
1146         rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1147
1148         /*
1149          * Send firmware request to device to load firmware,
1150          * we need to specify a long timeout time.
1151          */
1152         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1153                                              0, USB_MODE_FIRMWARE,
1154                                              REGISTER_TIMEOUT_FIRMWARE);
1155         if (status < 0) {
1156                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1157                 return status;
1158         }
1159
1160         return 0;
1161 }
1162
1163 /*
1164  * Initialization functions.
1165  */
1166 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1167 {
1168         u32 reg;
1169
1170         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1171         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1172         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1173         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1174         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1175
1176         rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1177         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1178         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1179         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1180         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1181         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1182         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1183         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1184         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1185         rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1186
1187         /*
1188          * CCK TXD BBP registers
1189          */
1190         rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1191         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1192         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1193         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1194         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1195         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1196         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1197         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1198         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1199         rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1200
1201         /*
1202          * OFDM TXD BBP registers
1203          */
1204         rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1205         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1206         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1207         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1208         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1209         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1210         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1211         rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1212
1213         rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1214         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1215         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1216         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1217         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1218         rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1219
1220         rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1221         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1222         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1223         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1224         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1225         rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1226
1227         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1228         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1229         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1230         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1231         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1232         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1233         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1234         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1235
1236         rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1237
1238         rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1239         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1240         rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1241
1242         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1243
1244         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1245                 return -EBUSY;
1246
1247         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1248
1249         /*
1250          * Invalidate all Shared Keys (SEC_CSR0),
1251          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1252          */
1253         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1254         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1255         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1256
1257         reg = 0x000023b0;
1258         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1259                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1260         rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1261
1262         rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1263         rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1264         rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1265
1266         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1267         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1268         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1269
1270         /*
1271          * Clear all beacons
1272          * For the Beacon base registers we only need to clear
1273          * the first byte since that byte contains the VALID and OWNER
1274          * bits which (when set to 0) will invalidate the entire beacon.
1275          */
1276         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1277         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1278         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1279         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1280
1281         /*
1282          * We must clear the error counters.
1283          * These registers are cleared on read,
1284          * so we may pass a useless variable to store the value.
1285          */
1286         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1287         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1288         rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1289
1290         /*
1291          * Reset MAC and BBP registers.
1292          */
1293         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1294         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1295         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1296         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1297
1298         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1299         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1300         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1301         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1302
1303         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1304         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1305         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1306
1307         return 0;
1308 }
1309
1310 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1311 {
1312         unsigned int i;
1313         u8 value;
1314
1315         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1316                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1317                 if ((value != 0xff) && (value != 0x00))
1318                         return 0;
1319                 udelay(REGISTER_BUSY_DELAY);
1320         }
1321
1322         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1323         return -EACCES;
1324 }
1325
1326 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1327 {
1328         unsigned int i;
1329         u16 eeprom;
1330         u8 reg_id;
1331         u8 value;
1332
1333         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1334                 return -EACCES;
1335
1336         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1337         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1338         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1339         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1340         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1341         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1342         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1343         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1344         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1345         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1346         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1347         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1348         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1349         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1350         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1351         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1352         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1353         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1354         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1355         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1356         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1357         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1358         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1359         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1360         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1361
1362         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1363                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1364
1365                 if (eeprom != 0xffff && eeprom != 0x0000) {
1366                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1367                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1368                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1369                 }
1370         }
1371
1372         return 0;
1373 }
1374
1375 /*
1376  * Device state switch handlers.
1377  */
1378 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1379 {
1380         /*
1381          * Initialize all registers.
1382          */
1383         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1384                      rt73usb_init_bbp(rt2x00dev)))
1385                 return -EIO;
1386
1387         return 0;
1388 }
1389
1390 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1391 {
1392         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1393
1394         /*
1395          * Disable synchronisation.
1396          */
1397         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1398
1399         rt2x00usb_disable_radio(rt2x00dev);
1400 }
1401
1402 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1403 {
1404         u32 reg, reg2;
1405         unsigned int i;
1406         char put_to_sleep;
1407
1408         put_to_sleep = (state != STATE_AWAKE);
1409
1410         rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1411         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1412         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1413         rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1414
1415         /*
1416          * Device is not guaranteed to be in the requested state yet.
1417          * We must wait until the register indicates that the
1418          * device has entered the correct state.
1419          */
1420         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1421                 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg2);
1422                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1423                 if (state == !put_to_sleep)
1424                         return 0;
1425                 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1426                 msleep(10);
1427         }
1428
1429         return -EBUSY;
1430 }
1431
1432 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1433                                     enum dev_state state)
1434 {
1435         int retval = 0;
1436
1437         switch (state) {
1438         case STATE_RADIO_ON:
1439                 retval = rt73usb_enable_radio(rt2x00dev);
1440                 break;
1441         case STATE_RADIO_OFF:
1442                 rt73usb_disable_radio(rt2x00dev);
1443                 break;
1444         case STATE_RADIO_RX_ON:
1445                 rt73usb_start_queue(rt2x00dev->rx);
1446                 break;
1447         case STATE_RADIO_RX_OFF:
1448                 rt73usb_stop_queue(rt2x00dev->rx);
1449                 break;
1450         case STATE_RADIO_IRQ_ON:
1451         case STATE_RADIO_IRQ_ON_ISR:
1452         case STATE_RADIO_IRQ_OFF:
1453         case STATE_RADIO_IRQ_OFF_ISR:
1454                 /* No support, but no error either */
1455                 break;
1456         case STATE_DEEP_SLEEP:
1457         case STATE_SLEEP:
1458         case STATE_STANDBY:
1459         case STATE_AWAKE:
1460                 retval = rt73usb_set_state(rt2x00dev, state);
1461                 break;
1462         default:
1463                 retval = -ENOTSUPP;
1464                 break;
1465         }
1466
1467         if (unlikely(retval))
1468                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1469                       state, retval);
1470
1471         return retval;
1472 }
1473
1474 /*
1475  * TX descriptor initialization
1476  */
1477 static void rt73usb_write_tx_desc(struct queue_entry *entry,
1478                                   struct txentry_desc *txdesc)
1479 {
1480         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1481         __le32 *txd = (__le32 *) entry->skb->data;
1482         u32 word;
1483
1484         /*
1485          * Start writing the descriptor words.
1486          */
1487         rt2x00_desc_read(txd, 0, &word);
1488         rt2x00_set_field32(&word, TXD_W0_BURST,
1489                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1490         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1491         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1492                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1493         rt2x00_set_field32(&word, TXD_W0_ACK,
1494                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1495         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1496                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1497         rt2x00_set_field32(&word, TXD_W0_OFDM,
1498                            (txdesc->rate_mode == RATE_MODE_OFDM));
1499         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1500         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1501                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1502         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1503                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1504         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1505                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1506         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1507         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1508         rt2x00_set_field32(&word, TXD_W0_BURST2,
1509                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1510         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1511         rt2x00_desc_write(txd, 0, word);
1512
1513         rt2x00_desc_read(txd, 1, &word);
1514         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1515         rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1516         rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1517         rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1518         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1519         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1520                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1521         rt2x00_desc_write(txd, 1, word);
1522
1523         rt2x00_desc_read(txd, 2, &word);
1524         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1525         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1526         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1527         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1528         rt2x00_desc_write(txd, 2, word);
1529
1530         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1531                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1532                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1533         }
1534
1535         rt2x00_desc_read(txd, 5, &word);
1536         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1537                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1538         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1539         rt2x00_desc_write(txd, 5, word);
1540
1541         /*
1542          * Register descriptor details in skb frame descriptor.
1543          */
1544         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1545         skbdesc->desc = txd;
1546         skbdesc->desc_len = TXD_DESC_SIZE;
1547 }
1548
1549 /*
1550  * TX data initialization
1551  */
1552 static void rt73usb_write_beacon(struct queue_entry *entry,
1553                                  struct txentry_desc *txdesc)
1554 {
1555         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1556         unsigned int beacon_base;
1557         u32 reg;
1558
1559         /*
1560          * Disable beaconing while we are reloading the beacon data,
1561          * otherwise we might be sending out invalid data.
1562          */
1563         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1564         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1565         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1566
1567         /*
1568          * Add space for the descriptor in front of the skb.
1569          */
1570         skb_push(entry->skb, TXD_DESC_SIZE);
1571         memset(entry->skb->data, 0, TXD_DESC_SIZE);
1572
1573         /*
1574          * Write the TX descriptor for the beacon.
1575          */
1576         rt73usb_write_tx_desc(entry, txdesc);
1577
1578         /*
1579          * Dump beacon to userspace through debugfs.
1580          */
1581         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1582
1583         /*
1584          * Write entire beacon with descriptor to register.
1585          */
1586         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1587         rt2x00usb_register_multiwrite(rt2x00dev, beacon_base,
1588                                       entry->skb->data, entry->skb->len);
1589
1590         /*
1591          * Enable beaconing again.
1592          *
1593          * For Wi-Fi faily generated beacons between participating stations.
1594          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1595          */
1596         rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1597
1598         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1599         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1600         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1601         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1602
1603         /*
1604          * Clean up the beacon skb.
1605          */
1606         dev_kfree_skb(entry->skb);
1607         entry->skb = NULL;
1608 }
1609
1610 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1611 {
1612         int length;
1613
1614         /*
1615          * The length _must_ be a multiple of 4,
1616          * but it must _not_ be a multiple of the USB packet size.
1617          */
1618         length = roundup(entry->skb->len, 4);
1619         length += (4 * !(length % entry->queue->usb_maxpacket));
1620
1621         return length;
1622 }
1623
1624 /*
1625  * RX control handlers
1626  */
1627 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1628 {
1629         u8 offset = rt2x00dev->lna_gain;
1630         u8 lna;
1631
1632         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1633         switch (lna) {
1634         case 3:
1635                 offset += 90;
1636                 break;
1637         case 2:
1638                 offset += 74;
1639                 break;
1640         case 1:
1641                 offset += 64;
1642                 break;
1643         default:
1644                 return 0;
1645         }
1646
1647         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1648                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1649                         if (lna == 3 || lna == 2)
1650                                 offset += 10;
1651                 } else {
1652                         if (lna == 3)
1653                                 offset += 6;
1654                         else if (lna == 2)
1655                                 offset += 8;
1656                 }
1657         }
1658
1659         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1660 }
1661
1662 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1663                                 struct rxdone_entry_desc *rxdesc)
1664 {
1665         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1666         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1667         __le32 *rxd = (__le32 *)entry->skb->data;
1668         u32 word0;
1669         u32 word1;
1670
1671         /*
1672          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1673          * frame data in rt2x00usb.
1674          */
1675         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1676         rxd = (__le32 *)skbdesc->desc;
1677
1678         /*
1679          * It is now safe to read the descriptor on all architectures.
1680          */
1681         rt2x00_desc_read(rxd, 0, &word0);
1682         rt2x00_desc_read(rxd, 1, &word1);
1683
1684         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1685                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1686
1687         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1688         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1689
1690         if (rxdesc->cipher != CIPHER_NONE) {
1691                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1692                 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1693                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1694
1695                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1696                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1697
1698                 /*
1699                  * Hardware has stripped IV/EIV data from 802.11 frame during
1700                  * decryption. It has provided the data separately but rt2x00lib
1701                  * should decide if it should be reinserted.
1702                  */
1703                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1704
1705                 /*
1706                  * FIXME: Legacy driver indicates that the frame does
1707                  * contain the Michael Mic. Unfortunately, in rt2x00
1708                  * the MIC seems to be missing completely...
1709                  */
1710                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1711
1712                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1713                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1714                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1715                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1716         }
1717
1718         /*
1719          * Obtain the status about this packet.
1720          * When frame was received with an OFDM bitrate,
1721          * the signal is the PLCP value. If it was received with
1722          * a CCK bitrate the signal is the rate in 100kbit/s.
1723          */
1724         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1725         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1726         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1727
1728         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1729                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1730         else
1731                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1732         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1733                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1734
1735         /*
1736          * Set skb pointers, and update frame information.
1737          */
1738         skb_pull(entry->skb, entry->queue->desc_size);
1739         skb_trim(entry->skb, rxdesc->size);
1740 }
1741
1742 /*
1743  * Device probe functions.
1744  */
1745 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1746 {
1747         u16 word;
1748         u8 *mac;
1749         s8 value;
1750
1751         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1752
1753         /*
1754          * Start validation of the data that has been read.
1755          */
1756         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1757         if (!is_valid_ether_addr(mac)) {
1758                 random_ether_addr(mac);
1759                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1760         }
1761
1762         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1763         if (word == 0xffff) {
1764                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1765                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1766                                    ANTENNA_B);
1767                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1768                                    ANTENNA_B);
1769                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1770                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1771                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1772                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1773                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1774                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1775         }
1776
1777         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1778         if (word == 0xffff) {
1779                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1780                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1781                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1782         }
1783
1784         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1785         if (word == 0xffff) {
1786                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1787                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1788                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1789                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1790                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1791                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1792                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1793                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1794                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1795                                    LED_MODE_DEFAULT);
1796                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1797                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1798         }
1799
1800         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1801         if (word == 0xffff) {
1802                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1803                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1804                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1805                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1806         }
1807
1808         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1809         if (word == 0xffff) {
1810                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1811                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1812                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1813                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1814         } else {
1815                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1816                 if (value < -10 || value > 10)
1817                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1818                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1819                 if (value < -10 || value > 10)
1820                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1821                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1822         }
1823
1824         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1825         if (word == 0xffff) {
1826                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1827                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1828                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1829                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1830         } else {
1831                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1832                 if (value < -10 || value > 10)
1833                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1834                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1835                 if (value < -10 || value > 10)
1836                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1837                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1838         }
1839
1840         return 0;
1841 }
1842
1843 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1844 {
1845         u32 reg;
1846         u16 value;
1847         u16 eeprom;
1848
1849         /*
1850          * Read EEPROM word for configuration.
1851          */
1852         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1853
1854         /*
1855          * Identify RF chipset.
1856          */
1857         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1858         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1859         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1860                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1861
1862         if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1863                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1864                 return -ENODEV;
1865         }
1866
1867         if (!rt2x00_rf(rt2x00dev, RF5226) &&
1868             !rt2x00_rf(rt2x00dev, RF2528) &&
1869             !rt2x00_rf(rt2x00dev, RF5225) &&
1870             !rt2x00_rf(rt2x00dev, RF2527)) {
1871                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1872                 return -ENODEV;
1873         }
1874
1875         /*
1876          * Identify default antenna configuration.
1877          */
1878         rt2x00dev->default_ant.tx =
1879             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1880         rt2x00dev->default_ant.rx =
1881             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1882
1883         /*
1884          * Read the Frame type.
1885          */
1886         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1887                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1888
1889         /*
1890          * Detect if this device has an hardware controlled radio.
1891          */
1892         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1893                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1894
1895         /*
1896          * Read frequency offset.
1897          */
1898         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1899         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1900
1901         /*
1902          * Read external LNA informations.
1903          */
1904         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1905
1906         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1907                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1908                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1909         }
1910
1911         /*
1912          * Store led settings, for correct led behaviour.
1913          */
1914 #ifdef CONFIG_RT2X00_LIB_LEDS
1915         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1916
1917         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1918         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1919         if (value == LED_MODE_SIGNAL_STRENGTH)
1920                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1921                                  LED_TYPE_QUALITY);
1922
1923         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1924         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1925                            rt2x00_get_field16(eeprom,
1926                                               EEPROM_LED_POLARITY_GPIO_0));
1927         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1928                            rt2x00_get_field16(eeprom,
1929                                               EEPROM_LED_POLARITY_GPIO_1));
1930         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1931                            rt2x00_get_field16(eeprom,
1932                                               EEPROM_LED_POLARITY_GPIO_2));
1933         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1934                            rt2x00_get_field16(eeprom,
1935                                               EEPROM_LED_POLARITY_GPIO_3));
1936         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1937                            rt2x00_get_field16(eeprom,
1938                                               EEPROM_LED_POLARITY_GPIO_4));
1939         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1940                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1941         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1942                            rt2x00_get_field16(eeprom,
1943                                               EEPROM_LED_POLARITY_RDY_G));
1944         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1945                            rt2x00_get_field16(eeprom,
1946                                               EEPROM_LED_POLARITY_RDY_A));
1947 #endif /* CONFIG_RT2X00_LIB_LEDS */
1948
1949         return 0;
1950 }
1951
1952 /*
1953  * RF value list for RF2528
1954  * Supports: 2.4 GHz
1955  */
1956 static const struct rf_channel rf_vals_bg_2528[] = {
1957         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1958         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1959         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1960         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1961         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1962         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1963         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1964         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1965         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1966         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1967         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1968         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1969         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1970         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1971 };
1972
1973 /*
1974  * RF value list for RF5226
1975  * Supports: 2.4 GHz & 5.2 GHz
1976  */
1977 static const struct rf_channel rf_vals_5226[] = {
1978         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1979         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1980         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1981         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1982         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1983         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1984         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1985         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1986         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1987         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1988         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1989         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1990         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1991         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1992
1993         /* 802.11 UNI / HyperLan 2 */
1994         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1995         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1996         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1997         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1998         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1999         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2000         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2001         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2002
2003         /* 802.11 HyperLan 2 */
2004         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2005         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2006         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2007         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2008         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2009         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2010         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2011         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2012         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2013         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2014
2015         /* 802.11 UNII */
2016         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2017         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2018         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2019         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2020         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2021         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2022
2023         /* MMAC(Japan)J52 ch 34,38,42,46 */
2024         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2025         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2026         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2027         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2028 };
2029
2030 /*
2031  * RF value list for RF5225 & RF2527
2032  * Supports: 2.4 GHz & 5.2 GHz
2033  */
2034 static const struct rf_channel rf_vals_5225_2527[] = {
2035         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2036         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2037         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2038         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2039         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2040         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2041         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2042         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2043         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2044         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2045         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2046         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2047         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2048         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2049
2050         /* 802.11 UNI / HyperLan 2 */
2051         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2052         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2053         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2054         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2055         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2056         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2057         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2058         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2059
2060         /* 802.11 HyperLan 2 */
2061         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2062         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2063         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2064         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2065         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2066         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2067         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2068         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2069         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2070         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2071
2072         /* 802.11 UNII */
2073         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2074         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2075         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2076         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2077         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2078         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2079
2080         /* MMAC(Japan)J52 ch 34,38,42,46 */
2081         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2082         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2083         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2084         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2085 };
2086
2087
2088 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2089 {
2090         struct hw_mode_spec *spec = &rt2x00dev->spec;
2091         struct channel_info *info;
2092         char *tx_power;
2093         unsigned int i;
2094
2095         /*
2096          * Initialize all hw fields.
2097          *
2098          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
2099          * capable of sending the buffered frames out after the DTIM
2100          * transmission using rt2x00lib_beacondone. This will send out
2101          * multicast and broadcast traffic immediately instead of buffering it
2102          * infinitly and thus dropping it after some time.
2103          */
2104         rt2x00dev->hw->flags =
2105             IEEE80211_HW_SIGNAL_DBM |
2106             IEEE80211_HW_SUPPORTS_PS |
2107             IEEE80211_HW_PS_NULLFUNC_STACK;
2108
2109         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2110         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2111                                 rt2x00_eeprom_addr(rt2x00dev,
2112                                                    EEPROM_MAC_ADDR_0));
2113
2114         /*
2115          * Initialize hw_mode information.
2116          */
2117         spec->supported_bands = SUPPORT_BAND_2GHZ;
2118         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2119
2120         if (rt2x00_rf(rt2x00dev, RF2528)) {
2121                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2122                 spec->channels = rf_vals_bg_2528;
2123         } else if (rt2x00_rf(rt2x00dev, RF5226)) {
2124                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2125                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2126                 spec->channels = rf_vals_5226;
2127         } else if (rt2x00_rf(rt2x00dev, RF2527)) {
2128                 spec->num_channels = 14;
2129                 spec->channels = rf_vals_5225_2527;
2130         } else if (rt2x00_rf(rt2x00dev, RF5225)) {
2131                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2132                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2133                 spec->channels = rf_vals_5225_2527;
2134         }
2135
2136         /*
2137          * Create channel information array
2138          */
2139         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2140         if (!info)
2141                 return -ENOMEM;
2142
2143         spec->channels_info = info;
2144
2145         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2146         for (i = 0; i < 14; i++) {
2147                 info[i].max_power = MAX_TXPOWER;
2148                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2149         }
2150
2151         if (spec->num_channels > 14) {
2152                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2153                 for (i = 14; i < spec->num_channels; i++) {
2154                         info[i].max_power = MAX_TXPOWER;
2155                         info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2156                 }
2157         }
2158
2159         return 0;
2160 }
2161
2162 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2163 {
2164         int retval;
2165
2166         /*
2167          * Allocate eeprom data.
2168          */
2169         retval = rt73usb_validate_eeprom(rt2x00dev);
2170         if (retval)
2171                 return retval;
2172
2173         retval = rt73usb_init_eeprom(rt2x00dev);
2174         if (retval)
2175                 return retval;
2176
2177         /*
2178          * Initialize hw specifications.
2179          */
2180         retval = rt73usb_probe_hw_mode(rt2x00dev);
2181         if (retval)
2182                 return retval;
2183
2184         /*
2185          * This device has multiple filters for control frames,
2186          * but has no a separate filter for PS Poll frames.
2187          */
2188         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2189
2190         /*
2191          * This device requires firmware.
2192          */
2193         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2194         if (!modparam_nohwcrypt)
2195                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2196         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
2197         __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags);
2198
2199         /*
2200          * Set the rssi offset.
2201          */
2202         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2203
2204         return 0;
2205 }
2206
2207 /*
2208  * IEEE80211 stack callback functions.
2209  */
2210 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2211                            const struct ieee80211_tx_queue_params *params)
2212 {
2213         struct rt2x00_dev *rt2x00dev = hw->priv;
2214         struct data_queue *queue;
2215         struct rt2x00_field32 field;
2216         int retval;
2217         u32 reg;
2218         u32 offset;
2219
2220         /*
2221          * First pass the configuration through rt2x00lib, that will
2222          * update the queue settings and validate the input. After that
2223          * we are free to update the registers based on the value
2224          * in the queue parameter.
2225          */
2226         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2227         if (retval)
2228                 return retval;
2229
2230         /*
2231          * We only need to perform additional register initialization
2232          * for WMM queues/
2233          */
2234         if (queue_idx >= 4)
2235                 return 0;
2236
2237         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2238
2239         /* Update WMM TXOP register */
2240         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2241         field.bit_offset = (queue_idx & 1) * 16;
2242         field.bit_mask = 0xffff << field.bit_offset;
2243
2244         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2245         rt2x00_set_field32(&reg, field, queue->txop);
2246         rt2x00usb_register_write(rt2x00dev, offset, reg);
2247
2248         /* Update WMM registers */
2249         field.bit_offset = queue_idx * 4;
2250         field.bit_mask = 0xf << field.bit_offset;
2251
2252         rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2253         rt2x00_set_field32(&reg, field, queue->aifs);
2254         rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2255
2256         rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2257         rt2x00_set_field32(&reg, field, queue->cw_min);
2258         rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2259
2260         rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2261         rt2x00_set_field32(&reg, field, queue->cw_max);
2262         rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2263
2264         return 0;
2265 }
2266
2267 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2268 {
2269         struct rt2x00_dev *rt2x00dev = hw->priv;
2270         u64 tsf;
2271         u32 reg;
2272
2273         rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2274         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2275         rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2276         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2277
2278         return tsf;
2279 }
2280
2281 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2282         .tx                     = rt2x00mac_tx,
2283         .start                  = rt2x00mac_start,
2284         .stop                   = rt2x00mac_stop,
2285         .add_interface          = rt2x00mac_add_interface,
2286         .remove_interface       = rt2x00mac_remove_interface,
2287         .config                 = rt2x00mac_config,
2288         .configure_filter       = rt2x00mac_configure_filter,
2289         .set_tim                = rt2x00mac_set_tim,
2290         .set_key                = rt2x00mac_set_key,
2291         .sw_scan_start          = rt2x00mac_sw_scan_start,
2292         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2293         .get_stats              = rt2x00mac_get_stats,
2294         .bss_info_changed       = rt2x00mac_bss_info_changed,
2295         .conf_tx                = rt73usb_conf_tx,
2296         .get_tsf                = rt73usb_get_tsf,
2297         .rfkill_poll            = rt2x00mac_rfkill_poll,
2298         .flush                  = rt2x00mac_flush,
2299 };
2300
2301 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2302         .probe_hw               = rt73usb_probe_hw,
2303         .get_firmware_name      = rt73usb_get_firmware_name,
2304         .check_firmware         = rt73usb_check_firmware,
2305         .load_firmware          = rt73usb_load_firmware,
2306         .initialize             = rt2x00usb_initialize,
2307         .uninitialize           = rt2x00usb_uninitialize,
2308         .clear_entry            = rt2x00usb_clear_entry,
2309         .set_device_state       = rt73usb_set_device_state,
2310         .rfkill_poll            = rt73usb_rfkill_poll,
2311         .link_stats             = rt73usb_link_stats,
2312         .reset_tuner            = rt73usb_reset_tuner,
2313         .link_tuner             = rt73usb_link_tuner,
2314         .watchdog               = rt2x00usb_watchdog,
2315         .write_tx_desc          = rt73usb_write_tx_desc,
2316         .write_beacon           = rt73usb_write_beacon,
2317         .get_tx_data_len        = rt73usb_get_tx_data_len,
2318         .kick_tx_queue          = rt2x00usb_kick_tx_queue,
2319         .kill_tx_queue          = rt73usb_stop_queue,
2320         .fill_rxdone            = rt73usb_fill_rxdone,
2321         .config_shared_key      = rt73usb_config_shared_key,
2322         .config_pairwise_key    = rt73usb_config_pairwise_key,
2323         .config_filter          = rt73usb_config_filter,
2324         .config_intf            = rt73usb_config_intf,
2325         .config_erp             = rt73usb_config_erp,
2326         .config_ant             = rt73usb_config_ant,
2327         .config                 = rt73usb_config,
2328 };
2329
2330 static const struct data_queue_desc rt73usb_queue_rx = {
2331         .entry_num              = 32,
2332         .data_size              = DATA_FRAME_SIZE,
2333         .desc_size              = RXD_DESC_SIZE,
2334         .priv_size              = sizeof(struct queue_entry_priv_usb),
2335 };
2336
2337 static const struct data_queue_desc rt73usb_queue_tx = {
2338         .entry_num              = 32,
2339         .data_size              = DATA_FRAME_SIZE,
2340         .desc_size              = TXD_DESC_SIZE,
2341         .priv_size              = sizeof(struct queue_entry_priv_usb),
2342 };
2343
2344 static const struct data_queue_desc rt73usb_queue_bcn = {
2345         .entry_num              = 4,
2346         .data_size              = MGMT_FRAME_SIZE,
2347         .desc_size              = TXINFO_SIZE,
2348         .priv_size              = sizeof(struct queue_entry_priv_usb),
2349 };
2350
2351 static const struct rt2x00_ops rt73usb_ops = {
2352         .name                   = KBUILD_MODNAME,
2353         .max_sta_intf           = 1,
2354         .max_ap_intf            = 4,
2355         .eeprom_size            = EEPROM_SIZE,
2356         .rf_size                = RF_SIZE,
2357         .tx_queues              = NUM_TX_QUEUES,
2358         .extra_tx_headroom      = TXD_DESC_SIZE,
2359         .rx                     = &rt73usb_queue_rx,
2360         .tx                     = &rt73usb_queue_tx,
2361         .bcn                    = &rt73usb_queue_bcn,
2362         .lib                    = &rt73usb_rt2x00_ops,
2363         .hw                     = &rt73usb_mac80211_ops,
2364 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2365         .debugfs                = &rt73usb_rt2x00debug,
2366 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2367 };
2368
2369 /*
2370  * rt73usb module information.
2371  */
2372 static struct usb_device_id rt73usb_device_table[] = {
2373         /* AboCom */
2374         { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2375         { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
2376         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2377         { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2378         { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2379         /* AL */
2380         { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
2381         /* Amigo */
2382         { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2383         { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2384         /* AMIT  */
2385         { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
2386         /* Askey */
2387         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2388         /* ASUS */
2389         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2390         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2391         /* Belkin */
2392         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2393         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2394         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2395         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2396         /* Billionton */
2397         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2398         { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
2399         /* Buffalo */
2400         { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2401         { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
2402         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2403         { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2404         { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
2405         { USB_DEVICE(0x0411, 0x0137), USB_DEVICE_DATA(&rt73usb_ops) },
2406         /* CEIVA */
2407         { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
2408         /* CNet */
2409         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2410         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2411         /* Conceptronic */
2412         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2413         /* Corega */
2414         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2415         /* D-Link */
2416         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2417         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2418         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2419         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2420         /* Edimax */
2421         { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2422         { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2423         /* EnGenius */
2424         { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
2425         /* Gemtek */
2426         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2427         /* Gigabyte */
2428         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2429         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2430         /* Huawei-3Com */
2431         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2432         /* Hercules */
2433         { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
2434         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2435         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2436         /* Linksys */
2437         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2438         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2439         { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2440         /* MSI */
2441         { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
2442         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2443         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2444         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2445         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2446         /* Ovislink */
2447         { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2448         /* Ralink */
2449         { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
2450         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2451         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2452         /* Qcom */
2453         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2454         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2455         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2456         /* Samsung */
2457         { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
2458         /* Senao */
2459         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2460         /* Sitecom */
2461         { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2462         { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2463         { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
2464         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2465         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2466         /* Surecom */
2467         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2468         /* Tilgin */
2469         { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
2470         /* Philips */
2471         { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
2472         /* Planex */
2473         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2474         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2475         /* WideTell */
2476         { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
2477         /* Zcom */
2478         { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
2479         /* ZyXEL */
2480         { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
2481         { 0, }
2482 };
2483
2484 MODULE_AUTHOR(DRV_PROJECT);
2485 MODULE_VERSION(DRV_VERSION);
2486 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2487 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2488 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2489 MODULE_FIRMWARE(FIRMWARE_RT2571);
2490 MODULE_LICENSE("GPL");
2491
2492 static struct usb_driver rt73usb_driver = {
2493         .name           = KBUILD_MODNAME,
2494         .id_table       = rt73usb_device_table,
2495         .probe          = rt2x00usb_probe,
2496         .disconnect     = rt2x00usb_disconnect,
2497         .suspend        = rt2x00usb_suspend,
2498         .resume         = rt2x00usb_resume,
2499 };
2500
2501 static int __init rt73usb_init(void)
2502 {
2503         return usb_register(&rt73usb_driver);
2504 }
2505
2506 static void __exit rt73usb_exit(void)
2507 {
2508         usb_deregister(&rt73usb_driver);
2509 }
2510
2511 module_init(rt73usb_init);
2512 module_exit(rt73usb_exit);